Display panel and display device

Abstract

The application discloses a display panel and a display device, and relates to the technical field of display panels, and specifically discloses a display panel and a display device, which comprises a driving circuit, a plurality of scanning lines and a plurality of pixels arranged in an array, the gate of the switching transistor of at least part of the pixels in the same row is electrically connected with the same scanning line, in the driving circuit, the i-th stage shift register unit is cascaded with the i+n-th stage shift register unit, each stage shift register unit provides a gate driving signal to each scanning line, and the effective pulse of the gate driving signal received by each scanning line is shifted in turn, wherein the width of the effective pulse of the gate driving signal is T0>(Th+k*Th), 0 The application can increase the charging time of the effective pulse of the gate driving signal on the switching transistor of the pixel, so that each pixel can accurately display light emission.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular, to a display panel and a display device. Background Art

[0002] With the development of display technology, electronic products with display functions are widely used in various fields. For example, televisions, mobile phones, computers, personal digital assistants, etc. are all electronic products with display functions, and have become an indispensable part of people's life and work. Among them, a display panel is a core structure for implementing a display function in an electronic product.

[0003] A display panel is usually provided with a pixel array and a driving circuit for driving the pixel array. The driving circuit can perform line-by-line scanning on the pixel array to enable the pixel array to display images. However, limited by the function and structure of the driving circuit in the prior art, the driving circuit in the prior art cannot accurately drive a row of pixels, thereby resulting in inaccurate display luminance of the pixels and affecting the overall display effect of the display panel. Summary of the Invention

[0004] The present invention provides a display panel and a display device, so that a driving circuit can accurately drive pixels in the display panel, thereby improving the display effect of the display panel.

[0005] According to one aspect of the present invention, there is provided a display panel, comprising: a driving circuit, a plurality of scanning lines, and a plurality of pixels arranged in an array;

[0006] the pixel comprises at least one switching transistor; gates of the switching transistors of at least some of the pixels located in the same row are electrically connected to the same scanning line;

[0007] the driving circuit comprises a plurality of stages of shift register units; an i-th stage of the shift register unit is cascaded with an (i+n)-th stage of the shift register unit; n is a positive integer greater than or equal to 2, and i is a positive integer;

[0008] each stage of the shift register units is also electrically connected to each of the scanning lines respectively; each stage of the shift register units respectively provides a gate driving signal to each of the scanning lines, and effective pulses of the gate driving signals received by the scanning lines are shifted sequentially;

[0009] wherein the width T0 of the effective pulse of the gate driving signal satisfies T0>(Th+k*Th); 0<k≤(n-1), Th=1 / (F*L), F is a refresh frequency of the display panel, and L is the number of rows of the pixels; a shift amount of effective pulses of the gate driving signals output by any two adjacent stages of the shift register units is greater than or equal to Th.

[0010] According to another aspect of the present invention, a display device is provided, comprising: the above-described display panel.

[0011] The technical solution of this invention electrically connects the shift output terminal of the i-th stage shift register unit to the first input terminal of the (i+n)-th stage shift register unit, controlling each stage shift register unit to output a gate drive signal with an effective pulse width greater than the row drive time. Furthermore, the shift amount of the effective pulses of the gate drive signals of two adjacent stages is greater than or equal to the row drive time. This allows the gate of the switching transistor in a row of pixels to be pre-charged during the first k*Th time period of the effective pulse of the gate drive signal. This transitions the switching transistor of the row of pixels from a closed state to a turned-on state, ensuring that the switching transistor remains in a normally turned-on state at least during the last Th time period of the effective pulse of the gate drive signal. This enables the data signal to be accurately written into the pixel, thereby improving the display effect of the display panel.

[0012] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a schematic diagram of the structure of a display panel based on related technologies;

[0015] Figure 2 This is a timing diagram of the driver for a display panel based on related technologies;

[0016] Figure 3 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0017] Figure 4 This is a driving timing diagram of a display panel provided in an embodiment of the present invention;

[0018] Figure 5 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0019] Figure 6 This is a schematic diagram of a driving circuit provided in an embodiment of the present invention;

[0020] Figure 7 This is a schematic diagram of the structure of a shift register unit provided in an embodiment of the present invention;

[0021] Figure 8 This is a schematic diagram of the circuit structure of a shift register unit provided in an embodiment of the present invention;

[0022] Figure 9 This is a timing diagram of the drive of a shift register unit provided in an embodiment of the present invention;

[0023] Figure 10 This is a driving timing diagram of a driving circuit provided in an embodiment of the present invention;

[0024] Figure 11 This is a schematic diagram of another driving circuit provided in an embodiment of the present invention;

[0025] Figure 12 This is a driving timing diagram of another driving circuit provided in an embodiment of the present invention;

[0026] Figure 13 This is a schematic diagram of another driving circuit provided in an embodiment of the present invention;

[0027] Figure 14 This is a schematic diagram of another driving circuit provided in an embodiment of the present invention;

[0028] Figure 15 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention;

[0029] Figure 16 This is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of the present invention;

[0030] Figure 17 This is a timing diagram of another shift register unit provided in an embodiment of the present invention;

[0031] Figure 18 This is a driving timing diagram of another driving circuit provided in an embodiment of the present invention;

[0032] Figure 19 This is a schematic diagram of another driving circuit provided in an embodiment of the present invention;

[0033] Figure 20 This is a driving timing diagram of another driving circuit provided in an embodiment of the present invention;

[0034] Figure 21 This is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of the present invention;

[0035] Figure 22This is a schematic diagram of another driving circuit provided in an embodiment of the present invention;

[0036] Figure 23 This is a driving timing diagram of another driving circuit provided in an embodiment of the present invention;

[0037] Figure 24 This is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of the present invention;

[0038] Figure 25 This is a schematic diagram of another driving circuit provided in an embodiment of the present invention;

[0039] Figure 26 This is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of the present invention;

[0040] Figure 27 This is a schematic diagram of another driving circuit provided in an embodiment of the present invention;

[0041] Figure 28 This is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of the present invention;

[0042] Figure 29 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0043] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0044] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0045] As described in the background section, Figure 1This is a schematic diagram of the structure of a display panel based on related technologies. Figure 2 This is a timing diagram of a display panel driver based on related technologies, in conjunction with reference. Figure 1 and Figure 2 The display panel 01 includes an array of pixels 010 and a driving circuit 030. The driving circuit 030 includes multiple cascaded shift register units 031, where each subsequent shift register unit 031 is electrically connected to the preceding shift register unit 031. Each shift register unit 031 sequentially outputs valid pulses of gate driving signals G′ (G1′, G2′, G3′, G4′, G5′, G6′, ...). Each shift register unit 031 is also connected to a sensor located in the same row via a scan line 020. The gates of the switching transistors M′ of each pixel 010 are electrically connected so that the gate drive signals G′ output by each shift register unit 031 can control the switching transistors M′ of each row of pixels 010 to be turned on row by row. When the gate drive signal G′ controls the switching transistors M′ to be turned on, the switching transistors M′ can transmit the corresponding signals (e.g., data signals controlling the brightness of the pixel display) to the nodes electrically connected to them, so as to refresh the signals at the nodes and realize the driving of the pixels 010. In this way, by making each shift register unit 031 output effective pulses of the gate drive signals in sequence, each pixel 010 can be driven row by row in a timely manner.

[0046] When the display panel 01 includes L rows of pixels 010 and the refresh frequency of the display panel is F, the driving time Th for each row of pixels 010 is 1 / (F*L), so that the signal refresh time of each row of pixels 010 shall be less than or equal to Th, so as to ensure that the driving of L rows of pixels 010 can be completed within the one-frame time 1 / F of the display panel. To meet the driving requirements of pixels 010 in each row, in the prior art, the width of the effective pulse of the gate drive signal G' output by each stage of shift register units 031 in the driving circuit 030 is Th. When the shift register unit 031 starts outputting the effective pulse of the gate drive signal G' and transmits it to the gate of the switching transistor M' of each pixel 010 located in the same row through the scan line 020, the effective pulse of the gate drive signal G' first charges the gate of the switching transistor M' of the row of pixels 010, and the switching transistor M' can only be turned on when the voltage difference Vgs between the gate and the source of the switching transistor M' satisfies |Vgs|>|Vth| (Vth is the threshold voltage of the switching transistor M'). When the size of the display panel 01 is relatively large, the number of pixels 010 in one row in the display panel 01 is relatively large, and the number of pixels 010 electrically connected to each scan line 020 is relatively large, so that the load at the signal output end of the shift register unit 031 is relatively large, and a longer charging time is required to enable all switching transistors of pixels 010 in the same row to be in a normal conducting state. As a result, within the time of the effective pulse of the gate drive signal G' output by the shift register unit 031, the charging duration requirement for one row of pixels 010 cannot be met, which leads to a short conducting duration or even failure to conduct for the switching transistor M' in the pixel 010, thereby causing insufficient signal writing at the node electrically connected to the switching transistor M', affecting the display luminous brightness of the pixel 010, and further affecting the overall display effect of the display panel 01.

[0047] To solve the above technical problem, embodiments of the present invention provide a display panel, the display panel comprising: a driving circuit, a plurality of scan lines, and a plurality of pixels arranged in an array; the pixel comprises at least one switching transistor; gates of switching transistors of at least some pixels located in the same row are electrically connected to the same scan line; the driving circuit comprises a plurality of stages of shift register units; an i-th stage shift register unit is cascaded with an (i+n)-th stage shift register unit; n is a positive integer greater than or equal to 2, and i is a positive integer; each stage of shift register unit is also electrically connected to each scan line respectively; each stage of shift register unit provides a gate drive signal to each scan line respectively, and effective pulses of the gate drive signals received by each scan line are shifted sequentially; wherein the width T0 of the effective pulse of the gate drive signal satisfies T0>(Th+k*Th); 0<k≤(n-1), Th=1 / (F*L), F is the refresh frequency of the display panel, and L is the number of rows of pixels; the shift amount of effective pulses of gate drive signals output by any two adjacent stages of shift register units is greater than or equal to Th.

[0048] By cascading the i-th shift register unit with the (i+n)-th shift register unit, it is ensured that while the gate drive signals output by each shift register unit are shifted sequentially, the effective pulse width of the gate drive signals output by each shift register unit is Th+k*Th. The effective pulse width of the gate drive signals output by each shift register unit is greater than the driving time Th of a row of pixels. This ensures that when the gate drive signals output by the shift register units control the switching transistors of pixels located in the same row to be turned on or off, the time for each row of pixels' switching transistors to receive the effective pulse of the gate drive signal is greater than the driving time Th of a row of pixels. In other words, the charging time for charging the gate of the pixel's switching transistor is greater than... Compared to existing technologies, the driving time Th for a row of pixels increases the charging time for charging the gates of the switching transistors in the pixel. This ensures that the switching transistors of each row of pixels have a sufficiently long conduction time. Especially for display panels with large size and high resolution, even if the number of pixels connected to each scan line is large and the load carried by each shift register unit is large, the longer charging time can ensure that the gates of the switching transistors of each pixel are charged to meet their conduction conditions. This ensures that when the signal is refreshed at the node electrically connected to the switching transistor, the corresponding signal can be accurately written to that node, which is beneficial to improving the display illumination accuracy of the pixels and thus improving the display illumination effect of the display panel. Furthermore, since the shift amount of the effective pulse of the gate drive signal of two adjacent shift register units is greater than or equal to the driving time Th of one row of pixels, the gate of the switching transistor of one row of pixels is pre-charged during the first k*Th time period of the effective pulse of the gate drive signal output by the shift register unit. This causes the switching transistor of that row of pixels to tend from the off state to the normal on state. During the last Th time period of the effective pulse of the gate drive signal output by the shift register unit, the switching transistor of the pixel can quickly enter the normal on state. This ensures that the switching transistor of the pixel can be in the normal on state for at least one row of pixels' driving time Th. This ensures that the time for providing the corresponding signal to the node electrically connected to the switching transistor is at least one row of pixels' driving time Th. This allows the corresponding signal to be accurately written into the pixel, enabling the pixel to accurately display and emit light, thereby improving the display effect of the display panel.

[0049] The above is the core idea of ​​this invention. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention. The technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings.

[0050] Figure 3This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Figure 4 This is a driving timing diagram of a display panel provided in an embodiment of the present invention, in conjunction with reference to [reference needed]. Figure 3 and Figure 4 The display panel 100 includes a driving circuit 30, multiple scan lines 20, and multiple pixels 10 arranged in an array. Each pixel 10 includes at least one switching transistor M0, meaning that a pixel 10 may include one or more switching transistors M0, which can be designed according to actual needs. This embodiment of the invention does not specifically limit this. The gates of the switching transistors M0 of at least a portion of the pixels 10 located in the same row are electrically connected to the same scan line 20. That is, the gates of the switching transistors of all pixels 10 located in the same row are electrically connected to the same scan line 20, or the gates of the switching transistors of some pixels 10 located in the same row are electrically connected to the same scan line 20. For ease of description, unless otherwise specified, this embodiment of the invention uses the example of all pixels 10 located in the same row being electrically connected to the same scan line 20 for illustrative purposes.

[0051] The display panel 100 can be a self-emissive display panel or a non-self-emissive display panel. When the display panel 100 is a non-self-emissive display panel, it may include, but is not limited to, a liquid crystal display panel. In this case, the pixel 10 may also include a pixel electrode and a common electrode. When the switching transistor M0 is turned on, it can transmit a data signal to the pixel electrode to generate an electric field between the pixel electrode and the common electrode. Under the action of this electric field, the light transmittance of the pixel 10 can be controlled, thereby controlling the display brightness of the pixel 10. When the display panel 100 is a self-emissive display panel, it may include, but is not limited to, an organic light-emitting display panel or a micro / mini LED display panel. In this case, the pixel may include a pixel circuit and a light-emitting element. The pixel circuit may include a driving transistor and at least one switching transistor M0. The switching transistor M0 can control the data signal provided to the gate of the driving transistor so that the driving transistor can provide a driving current to the light-emitting element according to the data signal at its gate, thereby controlling the display brightness of the light-emitting element, that is, controlling the display brightness of the pixel 10.

[0052] It should be noted that the above-described example only uses the switching transistor M0 as the transistor for controlling the writing of data signals into pixel 10. However, in this embodiment of the invention, the switching transistor M0 can also control the writing of other signals, and this embodiment of the invention does not specifically limit this. For ease of description, this embodiment of the invention uses the example of the switching transistor M0 controlling the writing of data signals to illustrate the technical solution of this embodiment of the invention.

[0053] In an alternative embodiment, such as Figure 3As shown, the display panel 100 may further include a plurality of data lines 40, the first poles of the switching transistors M0 of at least part of the pixels 10 located in the same column are electrically connected to the same data line 40, that is, the first poles of the switching transistors M0 of each pixel 10 located in the same column are all electrically connected to the same data line 40, or the first poles of the switching transistors M0 of part of the pixels 10 located in the same column are electrically connected to the same data line 40. For ease of description, the embodiments of the present invention all take that the first poles of the switching transistors M0 of each of the pixels 10 located in the same column are all electrically connected to the same data line 40 as an example to exemplarily describe the technical solution of the embodiments of the present invention. Wherein, the data line 40 can transmit data signals of each pixel 10 located in the same column in a time-division manner, so that when the switching transistor M0 is in a conducting state, the data signal can be written into the pixel 10 to perform data refreshing on the pixel 10.

[0054] With continued reference to Figure 3 and Figure 4 , the driving circuit 30 includes a plurality of stages of shift register units 31; the i-th stage shift register unit 31i is cascaded with the (i+n)-th stage shift register unit 31i+n; n is a positive integer greater than or equal to 2, and i is a positive integer; each stage of shift register units 31 are also electrically connected to each of the scanning lines 20 respectively; each stage of shift register units 31 respectively provide a gate driving signal G to each of the scanning lines 20, and the effective pulses of the gate driving signal G received by each of the scanning lines 20 shift sequentially; wherein, the width T0 of the effective pulse of the gate driving signal G is greater than (Th + k*Th); 0 < k ≤ (n-1), Th = 1 / (F*L), F is the refresh frequency of the display panel 100, and L is the number of rows of the pixels 10; the shift amount of the effective pulse of the gate driving signals output by any two adjacent stages of shift register units 31 is greater than or equal to Th.

[0055] For example, taking n=2, the first-stage shift register unit 311 is cascaded with the third-stage shift register unit 313, the second-stage shift register unit 312 is cascaded with the fourth-stage shift register unit 314, the third-stage shift register unit 313 is cascaded with the fifth-stage shift register unit 315, and the fourth-stage shift register unit 314 is cascaded with the sixth-stage shift register unit 316. In this way, any two adjacent shift register units 31 in the driving circuit 30 are not connected to each other, so that the gate drive signal Gi output by the previous-stage shift register unit 31i will not affect the gate drive signal Gi+1 output by the next-stage shift register unit 31i+1. At this time, in the previous... During the effective pulse period of the gate drive signal Gi output by the first-level shift register unit 31i, the gate drive signal Gi+1 output by the next-level shift register unit 31i+1 can also be an effective pulse. That is, the effective pulse time of the gate drive Gi output by the previous-level shift register unit 31i can overlap with the effective pulse time of the gate drive signal G output by the next-level shift register unit 31i+1, so that the effective pulse width of the gate drive signal G output by each level of shift register unit 31 can be greater than the driving time Th of one row of pixels. In other words, the effective pulse width of the gate drive signal G transmitted by each scan line 20 is greater than the driving time Th of one row of pixels.

[0056] Since the gates of the switching transistors M0 of each pixel 10 located in the same row are electrically connected to the same scan line 20, the gate drive signal G transmitted by the scan line 20 can control the switching transistors M0 of each pixel 10 located in the same row to be turned on or off. Specifically, when the gate drive signal G is at an active level, it can control the switching transistors M0 to be in the on state, and when the gate drive signal G is at an inactive level, it can control the switching transistors M0 to be in the off state.

[0057] It is understood that the width of the effective pulse of the gate drive signal G is the length of time that the gate drive signal G remains at an effective level. The switching transistor M0 can be an N-type transistor or a P-type transistor. When the switching transistor M0 is an N-type transistor, the effective level of the gate drive signal G is high, and the ineffective level is low; when the switching transistor M0 is a P-type transistor, the effective level of the gate drive signal G is low, and the ineffective level is high. For ease of description, unless otherwise specified, the embodiments of the present invention use an N-type transistor as an example to illustrate the technical solutions of the embodiments of the present invention.

[0058] Wherein, when the scanning line 20 is used to transmit the gate drive signal G, the voltage drop of the gate drive signal G becomes more obvious as the transmission distance of the gate drive signal G increases, so that the voltages of the gate drive signals received by the pixels 10 at different positions in the same row are different. When the effective pulse of the gate drive signal G is used to charge the gate of the switching transistor M0 of the pixels 10 in the same row, the switching transistors M0 of the pixels 10 at different positions require different charging durations. When the effective pulse duration of the gate drive signal G transmitted by the scanning line 20 is sufficiently long, it can be ensured that all the switching transistors M0 of the pixels 10 in the same row are in a normal conducting state.

[0059] Specifically, the effective pulse width M0 of the gate drive signal output by each stage of shift register units 31 is Th+k*Th, that is, the duration for which the gate drive signal G output by each stage of shift register units 31 remains an effective pulse is Th+k*Th, and since 0<k≤(n-1), the effective pulse width M0 of the gate drive signal G output by each stage of shift register units 31 is greater than the driving time Th of one row of pixels 10; when the gate drive signal G output by the shift register unit 31 is used to control the switching transistors M0 of the pixels 10 in the same row to turn on or off, the effective pulse duration of the gate drive signal G received by the switching transistors M0 of one row of pixels 10 is greater than the driving time Th of one row of pixels 10, that is, the charging time for charging the gate of the switching transistor M0 of the pixel 10 is greater than the driving time Th of one row of pixels 10, so that the gates of the switching transistors M0 of the pixels 10 in the same row have a sufficiently long charging time, enabling all the switching transistors M0 of the pixels 10 in this row to be in a normal conducting state, thereby allowing the data signal to be accurately written into the corresponding pixel 10 through the conducting switching transistor M0, which improves the accuracy of the display luminance of the pixels 10 when the pixels 10 perform display and light emission according to the data signal written therein, and further improves the overall display effect of the display panel 100.

[0060] For example, taking the gate drive signal G1 output by the first-stage shift register unit 311 as an example, which is transmitted through the scan line 20 to the gate of the switching transistor M0 of the first row pixel 10, and the gate drive signal G2 output by the second-stage shift register unit 312 as an example, since the gate drive signals G output by each stage of the shift register unit 31 are shifted sequentially, and the effective pulse shift amount T14 of the gate drive signals G output by two adjacent stages of the shift register unit 31 is greater than or equal to Th, the gate drive signal G1 output by the first-stage shift register unit 311 is... The effective pulse start time of signal G1 is located before the effective pulse start time of gate drive signal G2 output by the second-stage shift register unit 312. The overlap time T13 between the effective pulse of gate drive signal G1 output by the first-stage shift register unit 311 and the effective pulse of gate drive signal G2 output by the second-stage shift register unit 312 can be less than or equal to k*Th. Moreover, compared with the effective pulse of gate drive signal G1 output by the first-stage shift register unit 311, the shift amount T14 of the effective pulse of gate drive signal G2 output by the second-stage shift register unit 312 is greater than or equal to Th.

[0061] During time period T11, the effective level of the gate drive signal G1 output by the first-stage shift register unit 311 is transmitted to the gate of the switching transistor M0 of the first row pixel 10 through the scan line 20 to charge the gate of the switching transistor M0 of the first row pixel 10, causing the gate voltage of the switching transistor M0 of the first row pixel 10 to tend from the ineffective level of the gate drive signal G1 to the effective level, and the switching transistor M0 of the first row pixel 10 can tend from the off state to the on state; during time period T12, the gate drive signal G1 output by the first-stage shift register unit 311 continues to remain at the effective level, so that the voltage charged to the gate of the switching transistor M0 of the first row pixel 10 during time period T11 continues to increase. The gate of the switching transistor M0 of the first row of pixels 10 is charged so that the gate voltage of the switching transistor M0 of the first row of pixels 10 can be charged quickly to meet the conduction condition of the switching transistor M0. That is, during the time period T12, the switching transistor M0 of the first row of pixels 10 can be turned on quickly. At this time, the data signal of the first row of pixels 10 transmitted by the data line 40 is written into the first row of pixels 10 through the turned-on switching transistor M0, so that the writing time of the data signal can approach the total duration of the time period T12. This ensures that the data signal of the first row of pixels 10 has a sufficiently long writing time, ensuring the accuracy of the data signal written into the first row of pixels 10, so that the first row of pixels 10 can accurately display and emit light.

[0062] During time period T13 within time period T12, the second-stage shift register unit 312 also outputs an effective level of the gate drive signal G2. This effective level of the gate drive signal G2 can be transmitted through the scan line 20 to the gate of the switching transistor M0 of the second row pixel 10 to charge the gate of the switching transistor M0 of the second row pixel 10. This causes the gate voltage of the switching transistor M0 of the second row pixel 10 to tend towards an effective level from an ineffective level of the gate drive signal G2, and the switching transistor M0 of the second row pixel 10 will tend towards a normal conducting state. During time period T14, the first-stage shift register unit 311 outputs an ineffective level of the gate drive signal G1, and the switching transistor M0 of the first row pixel 10 tends to turn off. The gate drive signal G2 output by the second-stage shift register unit G2 continues to remain at an effective level, so that the second row pixel 10 is charged during time period T13. Based on the gate voltage of the switching transistor M0 of pixel 10, the gate of the switching transistor M0 of the second row of pixels 10 continues to be charged, so that the gate voltage of the switching transistor M0 of the second row of pixels 10 can be quickly charged to meet the conduction condition of the switching transistor M0. That is, during the time period T14, the switching transistor M0 of the second row of pixels 10 can be quickly turned on. At this time, the data line 40 transmits the data signal of the second row of pixels 10, so that the writing time of the data signal of the second row of pixels 10 can also approach the total duration of the time period T14. That is, the writing time of the data signal of the second row of pixels 10 can be greater than or equal to the driving time Th of one row of pixels. The data signal of the second row of pixels 10 can also have a sufficiently long writing time to ensure the accuracy of the data signal written to the second row of pixels 10, so that the second row of pixels 10 can accurately display and emit light.

[0063] If the switching transistor M0 of the second row of pixels 10 is already in the conducting state during the T13 time period, the data signal of the first row of pixels 10 transmitted by the data line 40 will also be written into the second row of pixels 10. At this time, the data signal of the first row of pixels 10 can be used to precharge the node electrically connected to the switching transistor M0 in the second row of pixels 10, so that when entering the T14 time period, the data signal of the second row of pixels 10 can continue to be written to the node electrically connected to the switching transistor M0 of the second row of pixels based on the signal written to the node electrically connected to the switching transistor M0 during the T13 time period, so that the signal at the node electrically connected to the switching transistor M0 in the second row of pixels 10 can still be consistent with the data signal of the second row of pixels 10.

[0064] Thus, by making any two adjacent shift register units disconnected from each other, the effective pulse width of the gate drive signal output by any two adjacent shift register units can be greater than Th. This ensures that when the shift register unit outputs the effective level of the gate drive signal, the charging time for charging the gate of the switching transistor in the pixel is long enough. Especially for large-size, high-resolution display panels, even if the number of pixels electrically connected to each scan line is large and the load carried by each shift register unit is large, the gate of the switching transistor in a row of pixels can be charged to meet its conduction condition during the effective level of the gate drive signal output by the shift register unit. This ensures that the switching transistor in a row of pixels can be in a normal conducting state, allowing the corresponding signal to be accurately written into the pixel, ensuring that the pixel can accurately display and emit light, thereby improving the display effect of the display panel.

[0065] Furthermore, since the shift amount of the effective pulse of the gate drive signal of two adjacent shift register units is greater than or equal to the driving time Th of one row of pixels, the gate of the switching transistor of one row of pixels is pre-charged during the first k*Th time period of the effective pulse of the gate drive signal output by the shift register unit. This causes the switching transistor of that row of pixels to tend from the off state to the normal on state. During the last Th time period of the effective pulse of the gate drive signal output by the shift register unit, the switching transistor of the pixel can quickly enter the normal on state. This ensures that the switching transistor of the pixel can be in the normal on state for at least one row of pixels' driving time Th. The time for providing the corresponding signal to the node electrically connected to the switching transistor is at least one row of pixels' driving time Th. This allows the corresponding signal to be accurately written into the pixel, enabling the pixel to accurately display and emit light, thereby improving the display effect of the display panel.

[0066] It is understood that the width T10 of the effective pulse of the gate drive signal output by each shift register unit is Th+k*Th, where k is a positive integer greater than 0 and less than or equal to n-1. This allows the width of the effective pulse of the gate drive signal output by each shift register unit to be greater than Th and less than or equal to n*Th. For example, when n equals 2, the width T10 of the effective pulse of the gate drive signal can be (4 / 3)*Th, (3 / 2)*Th, or 2Th, etc., which can be designed according to actual needs. This embodiment of the invention does not impose specific limitations on this.

[0067] Optional, continue to refer to the references Figure 3 and Figure 4Since the i-th stage shift register unit 31i and the (i+n)-th stage shift register unit 31i+n are cascaded, the gate drive signal Gi output by the i-th stage shift register unit 31i can control the gate drive signal Gi+n output by the (i+n)-th stage shift register unit 31i+n. At this time, by ensuring that the effective pulse time of the gate drive signal Gi output by the i-th stage shift register unit 31i does not overlap with the effective pulse time of the gate drive signal Gi+n output by the (i+n)-th stage shift register unit 31i+n, it is ensured that the gate drive signal output by the (i+n)-th stage shift register unit 31i+n is more effective than the effective pulse time of the gate drive signal Gi output by the i-th stage shift register unit 31i+n. The effective pulse shift amount of the moving signal Gi+n is greater than or equal to T10, that is, the effective pulse of the gate driving signal Gi+n output by the i+n-th stage shift register unit 31i+n and the effective pulse of the gate driving signal Gi output by the i-th stage shift register unit 31i do not overlap for a period of time greater than or equal to T10. During this period, the data line 40 can transmit the data signals of each pixel 10 corresponding to the i+n-th stage shift register unit 31i+n, ensuring that each pixel 10 corresponding to the i+n-th stage shift register unit 31i+n has a sufficiently long data signal writing time, thereby improving the display light emission accuracy of each pixel 10 corresponding to the i+n-th stage shift register unit 31i+n.

[0068] It should be noted that the above description of the technical solution of the present invention is only exemplarily illustrated using n=2 as an example. In the embodiments of the present invention, n can be any positive integer greater than or equal to 2, for example... Figure 5 As shown, n can also be equal to 3. Under the premise of being able to realize the core inventive point of the present invention, the present invention does not specifically limit the value of n.

[0069] In an alternative embodiment, Figure 6 This is a schematic diagram of a driving circuit provided in an embodiment of the present invention, such as... Figure 6 As shown, the shift register unit 31 includes at least a first input terminal IN1, a clock signal terminal A, a shift output terminal Next, at least one drive output terminal OUT, and at least one output control terminal B corresponding to at least one drive output terminal OUT. The shift register unit 31 is used to control the shift signal Vnext output by the shift output terminal Next and the gate drive signal G output by the drive output terminal OUT in response to the clock signal CKA received by the clock signal terminal A, the first input signal Vin1 received by the first input terminal IN1, and the output control signal CKB received by the output control terminal B.

[0070] In this system, the shift output terminal Next of the i-th level shift register unit 31i is electrically connected to the first input terminal IN1 of the (i+n)-th level shift register unit 31i+n; each drive output terminal OUT of each level shift register unit 31 is electrically connected to each scan line 20. For example, when n equals 2, the shift output terminal Next of the first level shift register unit 311 is electrically connected to the first input terminal IN1 of the third level shift register unit 313, and the shift output terminal Next of the second shift extreme unit 312 is electrically connected to the first input terminal of the fourth level shift register unit 314.

[0071] It is understood that the clock signal CKA received by clock signal terminal A and the output control signal CKB received by output control terminal B can both be pulse signals composed of high and low levels. The clock periods of clock signal CKA and output control signal CKB can be the same or different, and this embodiment does not specifically limit this. The effective levels of clock signal CKA and output control signal CKB can be high or low, and can be set according to actual needs. This embodiment does not specifically limit this; for ease of description, this embodiment uses the example of both clock signal CKA and output control signal CKB being at a high level to illustrate the technical solution of this embodiment.

[0072] Specifically, since the shift output terminal Next of the i-th stage shift register unit 31i is electrically connected to the first input terminal IN1 of the (i+n)-th stage shift register unit 31i+n, the shift signal Vnexti output by the shift output terminal of the i-th stage shift register unit 31i can be used as the first input signal Vin1i+n received by the first input terminal IN1 of the (i+n)-th stage shift register unit 31i+n. This allows the (i+n)-th stage shift register unit 31i+n to control the shift signal Vnexti+n output by its shift output terminal Next and the gate drive signal Gi+n output by its drive output terminal OUT, based on the shift signal Vnexti output by the shift output terminal Next of the i-th stage shift register unit 31i. At this time, the first input terminal IN1 of each shift register unit from the first-stage shift register unit 311 to the nth-stage shift register unit 31n can receive the start signals STV1, ..., STVn respectively, and the effective pulses of the start signals STV1, ..., STVn should be shifted sequentially so as to sequentially start each shift register unit from the first-stage shift register unit 311 to the nth-stage shift register unit 31n. This allows the shift signal Vnext output from the shift output terminal Next of each shift register unit from the first-stage shift register unit 311 to the nth-stage shift register unit 31n to be shifted sequentially, and the gate drive signal G output from the drive output terminal OUT of each shift register unit to be shifted sequentially. This prevents signal crosstalk and improves the accuracy of the shift signal Vnext and the gate drive signal G output by each shift register unit 31.

[0073] It is understandable that, based on the fact that each shift register unit includes a first input terminal, a clock signal terminal A, a shift output terminal, a drive output terminal, and an output control terminal, each shift register unit may also include other signal terminals and modules, so that the signals of each signal terminal and each module cooperate with each other to output corresponding shift signals and gate drive signals.

[0074] In an alternative embodiment, Figure 7 This is a schematic diagram of the structure of a shift register unit provided in an embodiment of the present invention, as shown below. Figure 7As shown, the shift register unit 31 further includes a latch module 310A, at least one level conversion module 320A corresponding to at least one drive output terminal OUT, and at least one output module 330A corresponding to at least one level conversion module 320A; in the same shift register unit 31: the latch module 310A is electrically connected to the clock signal terminal A, the first input terminal IN1, and the shift output terminal Next respectively; the latch module 310A is used to latch the first input signal Vin1 of the first input terminal IN1 in response to the clock signal CKA of the clock signal terminal A. The system stores and controls the shift signal Vnext output from the shift output terminal OUT; the level conversion module 320A is electrically connected to the output control terminal B, the shift output terminal Next, and the output module 330A respectively; the level conversion module 320A is used to respond to the output control signal CKB and the shift signal Vnext from the output control terminal B, and control the voltage of the gate drive signal G provided to the output module 330A; the output module 330A is also electrically connected to the drive output terminal OUT; the output module 330A is used to control the polarity of the gate drive signal G output from the drive output terminal OUT.

[0075] The latch module 310A may include latches, etc. When the clock signal A is active, the latch module 310A latches the first output signal Vin1 of the first input terminal IN1 and controls the shift output terminal Next to output the active level of the shift signal Vnext. When the clock signal A is inactive, the latching of the first input signal Vin1 of the first input terminal IN1 is stopped. After the latch module 310A stops latching the first input signal Vin1 of the first input terminal IN1, it can continue to control the shift output terminal Next to output the active level of the shift signal Vnext. When the clock signal CKA jumps to active level again, the shift output terminal Next starts outputting the inactive level of the shift signal Vnext. Thus, the latch module 310A can output the active or inactive level of the shift signal Vnext under the control of the clock signal CKA and the first input signal Vin1.

[0076] In one exemplary embodiment, such as Figure 8As shown, the latch module 310A may include a first inverter U11, a second inverter U12, a first tri-state gate U13, and a second tri-state gate U14; wherein, the input terminal of the first inverter U11 is electrically connected to the clock signal terminal A, and the input terminal of the first inverter U11 is also electrically connected to the negative signal control terminal of the first tri-state gate U13 and the positive signal control terminal of the second tri-state gate U14, respectively; the output terminal of the first inverter U11 is connected to the positive signal control terminal of the first tri-state gate U13 and the second tri-state gate U14, respectively. The negative signal control terminal of U14 is electrically connected; the input terminal of the first tri-state gate U13 is electrically connected to the first input terminal IN1; the input terminal of the second tri-state gate U14 is electrically connected to the shift output terminal Next; the output terminals of the first tri-state gate U13 and the second tri-state gate U14 are both electrically connected to the input terminal of the second inverter U12; the output terminal of the second inverter U12 is electrically connected to the input terminal of the second tri-state gate U14; and the output terminal of the second tri-state gate U14 is electrically connected to the input terminal of the second inverter U12.

[0077] The first inverter U11 and the second inverter U12 can both be composed of an N-type transistor and a P-type transistor. When the input terminal of the first inverter U11 receives a high level of the clock signal CKA, it can control the N-type transistor to conduct, so that the N-type transistor can transmit the low-level signal VGL to the output terminal of the first inverter U11, and the first inverter U11 outputs a low-level signal. When the input terminal of the first inverter U11 receives a low level of the clock signal CKA, it can control the P-type transistor to conduct, so that the P-type transistor can transmit the high-level signal VGH to the output terminal of the first inverter U11, and the first inverter U11 outputs a high-level signal. Similarly, when the input terminal of the second inverter U12 is high, it can control its N-type transistor to conduct, and when the input terminal of the second inverter U12 is low, it can control its P-type transistor to conduct, so that the polarity of the signal at the input terminal of the second inverter U12 is opposite to that of the signal at its output terminal.

[0078] Both the first tri-state gate U13 and the second tri-state gate U14 can be constructed from two P-type transistors and two N-type transistors connected in series. When the first tri-state gate U13 receives a high level of the first input signal Vin1 at its input terminal, a high level of the clock signal CKA at its negative signal control terminal, and a low level signal from the first inverter U11 at its positive signal control terminal, the two N-type transistors of the first tri-state gate U13 can transmit the low-level signal VGL to the output terminal of the first tri-state gate U13, causing the first tri-state gate U13 to output a low-level signal. Meanwhile, in the first tri-state gate U13... When the input terminal of the first tri-state gate U13 receives a low level of the first input signal Vin1, the negative signal control terminal receives a high level of the clock signal CKA, and the positive signal control terminal receives a low level signal output from the first inverter U11, the two P-type transistors of the first tri-state gate U13 can transmit the high level signal VGH to the output terminal of the first tri-state gate U13, so that the first tri-state gate U13 outputs a high level signal. Correspondingly, the working principle of the second tri-state gate U14 is similar to that of the first tri-state gate U13, and will not be repeated again. For the similarities, please refer to the description of the working process of the first tri-state gate U13.

[0079] Continue to refer to Figure 7 The level conversion module 320A, under the control of the output control signal CKB of the output control terminal B, can convert the level and pulse width of the received shift signal Vnext and output a corresponding gate drive signal G. The effective level of the gate drive signal G is such that the amplitude of the effective level is such that it can control the switching transistor M0 to turn on, and the amplitude of the ineffective level of the gate drive signal G is such that it can control the switching transistor M0 to turn off. That is, the amplitudes of the effective and ineffective levels of the gate drive signal G are related to the threshold voltage of the switching transistor M0. Under the premise of ensuring that the gate drive signal G can control the switching transistor M0 to turn on or off, the specific structure of the level conversion module 320A is not limited in this embodiment of the invention.

[0080] In an alternative embodiment, reference continues. Figure 7 The shift register unit 31 may also include a set signal terminal GAS, which can be electrically connected to the level conversion module 320A so that before each shift register unit 31 in the driving circuit starts to output an effective pulse of the gate drive signal G, the level conversion module 30 can respond to the set signal Vgas of the set signal terminal GAS, so that each shift register unit 31 can output an invalid level of the gate drive signal G, thereby controlling the switching transistor M0 of each pixel to be in the off state.

[0081] In one exemplary embodiment, such as Figure 8As shown, the level conversion module 320A can consist of multiple N-type transistors (M2, M3, M6) and multiple P-type transistors (M1, M4, M5). The gates of transistors M1 and M2 are electrically connected to the shift output terminal Next; the gates of transistors M5 and M3 are electrically connected to the output control terminal B; and the gates of transistors M4 and M6 are electrically connected to the set signal terminal GAS. The first terminal of transistor M4 receives a high-level signal VGH, and its second terminal is electrically connected to the first terminals of transistors M1 and M5. The second terminals of transistors M1 and M5 are both electrically connected to the second terminal of transistor M3. The first terminal of transistor M3 is electrically connected to the first terminal of transistor M2, and the first terminal of transistor M2 receives a low-level signal VGL. The first terminal of transistor M6 receives a low-level signal VGL, and its second terminal is electrically connected to the second terminal of transistor M3, serving as the output terminal of the level conversion module 320A and electrically connected to the input terminal of the output module 330A.

[0082] Since transistors M1 and M2 are different types of transistors, they can be turned on in a time-sharing manner. That is, when the shift output terminal Next is high, transistor M2 can be turned on, and when Next is low, transistor M1 is turned on. Similarly, transistors M5 and M3, and transistors M4 and M6, are turned on in a time-sharing manner. Thus, when the set signal Vgas at the set signal terminal GAS is high, transistor M6 can be turned on and transistor M4 can be turned off, allowing the low-level signal VGL to be transmitted to the output of the level conversion module 320A through transistor M6, resulting in a low-level output gate drive signal G from the level conversion module 320A. Conversely, when the set signal Vgas is low, transistor M6 can be turned off and transistor M4 can be turned off. When the transistor is turned on, the high-level signal VGH can be transmitted through transistor M4 to the first terminals of transistors M1 and M5. If at least one of the shift signal Vnext at the shift output terminal Next and the output control signal CKB at the output control terminal B is low, transistors M1 and M5 can be turned on, and the high-level signal VGH can be transmitted to the output terminal of level conversion module 320A through transistors M1 and M5 respectively, enabling level conversion module 330A to continue outputting the low level of gate drive signal G. When both the output control signal B and the shift signal Vnext are high, transistors M2 and M3 are turned on, allowing the low-level signal to be transmitted sequentially through transistors M2 and M3 to the output terminal of level conversion module 30, causing level conversion module 30 to output the low level of gate drive signal. Thus, level conversion module 30 can provide the output module 330A with a high or low level of gate drive signal G under the control of shift signal Vnext, output control signal CKB, and set signal Vgas.

[0083] Continue to refer to Figure 8The output module 330A can convert the polarity of the gate drive signal G output by the level conversion module 320A according to the polarity of the switching transistor. For example, when the switching transistor is an N-type transistor, if the effective level of the gate drive signal G output by the level conversion module 320A is low, the output module 330A can convert the low-level gate drive signal G output by the level conversion module 320A into a high-level gate drive signal G, so that when the gate drive signal G is effective, it can control the switching transistor to be in the on state. Conversely, the output module 330A can also convert the ineffective level of the gate drive signal G output by the level conversion module 320A from high level to low level, so that the low-level gate drive signal G can control the switching transistor to be in the off state. Furthermore, when the switching transistor is a P-type transistor and the effective level of the gate drive signal G output by the level conversion module 320A is low, the output module 330A does not need to convert the polarity of the gate drive signal G output by the level conversion module 320A. At this time, the output module 330A can buffer the gate drive signal G output by the level conversion module 320A so that the gate drive signal G transmitted to the drive output terminal OUT has a high driving capability, so as to quickly and accurately control the switching transistor to turn on or off.

[0084] In one exemplary embodiment, the output module 330A may include at least one buffer, which may consist of one or more inverters. The number of inverters in the output module 330A may be odd or even. When the number of inverters in the output module 330A is odd, the output module 330A can both perform polarity conversion on the gate drive signal G output by the level conversion module 320A and improve the driving capability of the gate drive signal G; while when the number of inverters in the output module 330A is even, the output module 330A only needs to improve the driving capability of the gate drive signal G, without needing to perform polarity conversion on the gate drive signal G output by the level conversion module 320A.

[0085] For example, such as Figure 8As shown, the output module 330A includes three inverters U31, U32, and U33 connected in series. Each inverter U31, U32, and U33 can also be composed of N-type transistors and P-type transistors. When the level conversion module 320A outputs a high-level gate drive signal G, the N-type transistor in inverter U31 is turned on, transmitting a low-level signal VGL to the input of inverter U32. The P-type transistor in inverter U32 is turned on, transmitting a high-level signal VGH to the input of inverter U33. This causes the N-type transistor in inverter U33 to turn on, transmitting a low-level signal to the drive output terminal OUT, resulting in the drive output terminal OUT outputting a low-level gate drive signal G. Conversely, when the level conversion module 320A outputs a high-level gate drive signal G, the output module 330A outputs a high-level gate drive signal G. When the level conversion module 320A outputs a low level gate drive signal G, the P-type transistor in inverter U31 can transmit a high-level signal to the input terminal of inverter U32, so that the N-type transistor in inverter U32 can transmit a low-level signal VGL to the input terminal of inverter U33. The P-type transistor in inverter U33 transmits a high-level signal VGH to the drive output terminal OUT, so that the drive output terminal OUT outputs a high level gate drive signal G. In this way, by setting three inverters U31, U32 and U33 connected in series in the output module 330A, the polarity of the gate drive signal G output by the level conversion module 320A can be converted at the same time, and the driving capability of the gate drive signal G output by the drive output terminal OUT can also be improved.

[0086] For example, Figure 9 This is a timing diagram of a shift register unit provided in an embodiment of the present invention, taking an example where the effective pulse levels of the clock signal CKA, output control signal CKB, first input signal Vin1, shift signal Vnext, and gate drive signal G are all high. (Refer to the reference...) Figure 7 , Figure 8 and Figure 9Before stage t1, the first input signal Vin1 received by the first input terminal IN1 of the shift register unit 31 is at a low level, causing the signal latched by the latch module 310A of the shift register unit 31 to also be the low-level first input signal Vin1. The shift output terminal Next, which is electrically connected to the latch module 310A, outputs a low-level shift signal Vnext. Under the control of the low-level shift signal Vnext, the level conversion module 320A provides a high-level gate drive signal G to the output module 330A. After the output module 330A reverses the polarity of the high-level gate drive signal G, it outputs a low-level gate drive signal G through the drive output terminal OUT. In stage t1, the first input terminal IN1 The first input signal Vin1 becomes high, but since the clock signal CKA at clock signal terminal A is low, the latch module 310A of shift register unit 31 only latches the first input signal Vin1. The shift signal Vnext output by shift output terminal Next remains low, and correspondingly, the gate drive signal G output by drive output terminal OUT remains low. In stage t2, the first input signal Vin1 received by the first input terminal IN1 remains high, and the clock signal CKA at clock signal terminal A becomes high. This causes the latch module 310A of shift register unit 31 to respond to the high-level clock signal CKA and control the shift output terminal Next. At stage t3, the output control signal Vnext is high. At this time, because the output control signal CKB of the output control terminal B is low, the level conversion module 320A continues to provide a high-level gate drive signal G to the output module 330A. This high-level gate drive signal G is polarity-converted by the output module 330A, causing the drive output terminal OUT to continue outputting a low-level gate drive signal G. At stage t3, the first input signal Vin1 received by the first input terminal IN1 becomes low, the clock signal CKA of the clock signal terminal A becomes low, and the shift output signal Vnext output by the shift output terminal Next remains at the same high level as in stage t2. At this time, due to the output control signal of the output control terminal B... When signal CKB goes high, the gate drive signal G provided by level conversion module 320A to output module 330A goes low. After polarity conversion by output module 330A, the low-level gate drive signal G is output as a high-level gate drive signal G by drive output terminal OUT. After stage t3, the first input signal Vin1 of the first input terminal IN1 continues to be low, so that latch module 310A of shift register unit 31 continues to latch the low level of the first input signal Vin1. Drive output terminal OUT will also continue to output the low-level gate drive signal G until the first input signal Vin1 jumps to high level again, and then enters stage t1 of the next drive cycle again.

[0087] In an alternative embodiment, reference continues. Figure 8 The shift register unit 31 may also include a reset module 340A and a reset signal terminal Reset. The reset module 340A can respond to the reset signal Vreset of the reset signal terminal Reset to reset the signal latched by the latch module 310A, so that the shift signal Vnext output by the latch module 310A can be reset to an invalid level.

[0088] In one exemplary embodiment, such as Figure 8 As shown, the reset module 310A may include a reset transistor M7. The gate of the reset transistor M7 is electrically connected to the reset signal terminal Reset. The first terminal of the reset transistor M7 receives a high-level signal VGH, and the second terminal of the reset transistor M7 is electrically connected to the latch module 310A. Specifically, the second terminal of the reset transistor M7 is electrically connected to the input terminal of the inverter U12 in the latch module 310A. Thus, when the reset signal Vreset at the reset signal terminal Reset controls the reset transistor M7 to be turned on, the reset transistor M7 can transmit the high-level signal VGH to the input terminal of the inverter U12, causing the inverter U12 to output a low-level signal VGL to the shift output terminal Next, thereby making the shift signal Vnext output by the shift output terminal Next low. The reset transistor M7 can be an N-type transistor or a P-type transistor, which can be set according to actual needs. This embodiment of the invention does not specifically limit this.

[0089] Understandable Figure 8 The diagram only exemplarily illustrates the structure of the latch module 310A, level conversion module 320A, and output module 330A in the shift register unit 31. In this embodiment of the invention, the structure of the latch module 310A, level conversion module 320A, and output module 330A is not limited to this. They can be designed according to actual needs, and the devices set in each module can be added or removed. Under the premise of achieving the core inventive points of this embodiment of the invention, this embodiment of the invention does not limit the specific structure of the shift register unit 31.

[0090] Optional, refer to the reference Figure 7 and Figure 9 In the same shift register unit 31, the effective pulses of the clock signal CKA and the output control signal CKB are shifted sequentially, and the effective pulse times of the clock signal CKA and the output control signal CKB do not overlap.

[0091] In this system, since the first input signal Vin1 of the first input terminal IN1 of the current-stage shift register unit 31 is the shift signal Vnext output by another shift register unit cascaded with the current-stage shift register unit 31, and the clock signal CKA can control the shift register unit 31 to latch the first input signal Vin1 received at its first input terminal IN1, and control the shift signal Vnext output by the shift register unit 31; and the shift signal Vnext and the output control signal CKB output by the shift register unit 31 can control the gate drive signal G output by its drive output terminal OUT; thus, by shifting the clock signal CKA and the output control signal CKB of the same-stage shift register unit 31 sequentially and ensuring that their effective pulse times do not overlap, the effective pulse time of the first input signal Vin1 latched by the shift register unit 31 and the effective pulse time of the gate drive signal G output by the drive output terminal OUT can be kept separate. Simultaneously, since the effective pulse time of the gate drive signal G output by the drive output terminal OUT overlaps with the effective pulse time of the shift signal output by the shift output terminal Next, when the effective pulse time of the first input signal Vin1 of the same shift register unit 31 does not overlap with the effective pulse time of the gate drive signal G, the effective pulse times of the gate drive signal G output by the two cascaded shift register units 31 do not overlap. This ensures that the effective pulses of the gate drive signal G output by each shift register unit 31 do not interfere with each other, improving the accuracy of the gate drive signal G output by each shift register unit 31. This allows for accurate control of the state of the switching transistors in each row of pixels when each shift register unit 31 controls the switching transistors in each row of pixels to be turned on or off, thereby enabling the corresponding signals to be accurately written into each pixel. This improves the display light emission accuracy of the pixels and enhances the overall display effect of the display panel.

[0092] It is understandable that, since the clock signal CKA and the output control signal CKB are shifted sequentially in the same shift register unit and their effective pulse times do not overlap, when the clock signal CKA is at an active level, the output control signal CKB is at an inactive level, and when the output control signal CKB is at an active level, the clock signal CKA is at an inactive level. At this time, the clock periods of the clock signals CKA and CKB can be the same, and at the same time, the clock signal CKA and the output control signal CKB can be two signals with opposite polarities. Thus, it is only necessary to set up corresponding inverters between the terminals providing the clock signal CKA and the terminals providing the output control signal CKB, thereby eliminating the need to set up corresponding timing circuits for providing the clock signal CKA or the output control signal CKB. This helps to simplify the structure of the display panel and reduce the cost of the display panel.

[0093] Optional, continue to refer to the references Figure 7 and Figure 9The width of the effective pulse of the clock signal CKA and the width of the effective pulse of the output control signal CKB are both equal to the width of the effective pulse of the gate drive signal G.

[0094] Specifically, when the widths of the effective pulses of the clock signal CKA and the output control signal CKB are the same as the width of the effective pulse of the gate drive signal, the width of the effective pulse of the gate drive signal G output from the drive output terminal OUT of the shift register unit 31 can be controlled by controlling the widths of the effective pulses of the clock signal CKA and the output control signal CKB provided to the shift register unit 31. That is, the value of k can be selected according to actual needs, and the widths of the effective pulses of the clock signal CKA and the output control signal CKB can be set according to the value of k. This ensures that, under the premise that the width of the effective pulse of the gate drive signal G is greater than the driving time Th of a row of pixels, the normal conduction time of each row of pixels can be greater than or equal to the driving time Th of a row of pixels. This ensures that the time for writing signals to each row of pixels is greater than or equal to the driving time Th of a row of pixels, guaranteeing the accuracy of the signals written to each row of pixels, thereby improving the display light emission accuracy of each pixel and improving the display effect of the display panel.

[0095] Optionally, the effective pulse time of the clock signal received by the i-th stage shift register unit does not overlap with the effective pulse time of the clock signal received by the (i+n)-th stage shift register unit; the effective pulse time of the output control signal received by the i-th stage shift register unit does not overlap with the effective pulse time of the output control signal received by the (i+n)-th stage shift register unit.

[0096] Specifically, taking n=2 as an example, please refer to [link / reference]. Figure 7Since the clock signal CKA received by the shift register unit 31 can control the effective pulse time of the shift signal Vnext output by the shift output terminal Next of the shift register unit 31, when the effective pulse time of the clock signal cka1 received by the first-stage shift register unit 311 does not overlap with the effective pulse time of the clock signal cka3 received by the third-stage shift register unit 313, the effective pulses of the shift signal Vnext1 output by the first-stage shift register unit 311 and the effective pulses of the shift signal Vnext3 output by the third-stage shift register unit 313 can be shifted sequentially, and the shift amount of the effective pulse of the shift signal Vnext3 can be greater than or equal to the effective pulse width of the clock signal CKA (cka1, cka3) compared to the effective pulse of the shift signal Vnext1; similarly, when the clock signal CKA received by the second-stage shift register unit 312 does not overlap with the effective pulse time of the clock signal cka1 received by the first-stage shift register unit 311, the effective pulse time of the clock signal cka3 received by the third-stage shift register unit 313 can be shifted sequentially, and the shift amount of the effective pulse of the shift signal Vnext3 can be greater than or equal to the effective pulse width of the clock signal CKA (cka1, cka3); similarly, when the clock signal CKA received by the second-stage shift register unit 312 does not overlap with the effective pulse time of the clock signal cka1 received by the first-stage shift register unit 311, the effective pulse time of the clock signal cka1 received by the second-stage shift register unit 312 can be shifted sequentially, and the effective pulse time of the clock signal Vnext3 can be shifted sequentially, and the effective pulse time of the clock signal Vnext3 can be shifted sequentially, and the effective pulse time of the clock signal Vnext3 received by the second-stage shift register unit 312 can be shifted sequentially, and the effective pulse time of the clock signal Vnext3 received by the second-stage shift When the effective pulse time of clock signal cka2 does not overlap with the effective pulse time of clock signal cka4 received by the fourth-stage shift register unit 314, the effective pulses of shift signal Vnext2 output by the second-stage shift register unit 312 and the effective pulses of shift signal Vnext4 output by the fourth-stage shift register unit 314 can be shifted sequentially. Moreover, compared with the effective pulse of shift signal Vnext2, the shift amount of the effective pulse of shift signal Vnext4 can be greater than or equal to the effective pulse width of clock signal CKA (cka2, cka4). Similarly, by ensuring that the effective pulse times of clock signal CKA received by the two cascaded shift register units do not overlap, it can be ensured that the effective pulses of shift signal Vnext output by the two cascaded shift register units are shifted sequentially, and the shift amount can be greater than or equal to the effective pulse time of clock signal CKA.

[0097] Correspondingly, since the output control signal CKB received by the shift register unit 31 can control the effective pulse time of the gate drive signal G output by the drive output terminal OUT of the shift register unit 31, when the effective pulse time of the output control signal ckb1 received by the first-stage shift register unit 311 does not overlap with the effective pulse time of the output control signal ckb2 received by the third-stage shift register unit 313, the effective pulse time of the gate drive signal G1 output by the first-stage shift register unit 311 and the effective pulse time of the gate drive signal G1 output by the third-stage shift register unit 313 can be synchronized. The effective pulses of signal G3 are shifted sequentially, and the shift amount of the effective pulses of gate drive signal G3 can be greater than or equal to the effective pulse width of output control signals CKB (ckb1, ckb3) compared to the effective pulses of gate drive signal G1. Similarly, when the effective pulse time of output control signal ckb2 received by the second-stage shift register unit 312 does not overlap with the effective pulse time of output control signal ckb4 received by the fourth-stage shift register unit 314, the effective pulses of the gate drive signal G2 output by the second-stage shift register unit 312 and the fourth-stage shift register unit 314 can be made to overlap. The effective pulses of the gate drive signal G4 output by the bit register unit 314 are shifted sequentially, and the shift amount of the effective pulse of the gate drive signal G4 can be greater than or equal to the effective pulse width of the output control signal CKB (ckb2, ckb4) compared to the effective pulse of the gate drive signal G2. Similarly, by ensuring that the effective pulse times of the output control signal CKB received by the two cascaded shift register units do not overlap, it can be ensured that the effective pulses of the gate drive signal G output by the two cascaded shift register units are shifted sequentially, and the shift amount can be greater than or equal to the effective pulse width of the output control signal G4. The effective pulse time of CKB ensures that when the effective pulse width of the output control signal CKB is equal to the effective pulse width of the gate drive signal G, the shift amount of the effective pulse of the gate drive signal G output by the two cascaded shift register units is greater than the effective pulse width of the gate drive signal G. This ensures that the effective pulses of the gate drive signal G output by the two cascaded shift register units do not overlap, thus ensuring that the effective pulses of the gate drive signal G output by the two cascaded shift register units do not affect each other, thereby improving the accuracy of the gate drive signal G output by each shift register unit.

[0098] For example, with Figure 8 Taking the structure of the shift register shown as an example, Figure 10 This is a driving timing diagram of a driving circuit provided in an embodiment of the present invention, in conjunction with reference to [reference needed]. Figure 6 , Figure 8 and Figure 10Taking the operation of the first four shift register units when n equals 2 as an example, the driving process of the driving circuit is explained exemplarily. Specifically, the first input terminal IN1 of the first-stage shift register unit 131 receives the start signal STV1, and the first input terminal IN1 of the second-stage shift register unit 132 receives the start signal STV2. The effective level of the start signal STV1 and the effective pulse of the start signal STV2 are shifted sequentially. The shift output terminal Next of the first-stage shift register unit 311 is electrically connected to the first input terminal IN1 of the third-stage shift register unit 313, and the shift output terminal of the second-stage shift register unit 312 is electrically connected to the first input terminal IN1 of the fourth-stage shift register unit 314.

[0099] Before time T01, the start signal STV1 is invalid, causing the latch module 310A of the first-stage shift register unit 311 to latch the invalid level of the start signal STV1. The shift output terminal Next of the first-stage shift register unit 311 outputs the invalid level of the shift signal Vnext1, and the drive output terminal OUT of the first-stage shift register unit 311 outputs the invalid level of the gate drive signal G1. This causes the third-stage shift register unit 313, cascaded with the first-stage shift register unit 311, to output the invalid level of the shift signal Vnext3 and the invalid level of the gate drive signal G3. Similarly... Before time T01, the start signal STV2 is also invalid, causing the latch module 310A of the second-stage shift register unit 312 to latch the invalid level of the start signal STV2, the shift output terminal Next of the second-stage shift register unit 312 to output the invalid level of the shift signal Vnext2, and the drive output terminal OUT of the second-stage shift register unit 312 to output the invalid level of the gate drive signal G2, causing the fourth-stage shift register unit 314, which is cascaded with the second-stage shift register unit 312, to output the invalid level of the shift signal Vnext4 and the invalid level of the gate drive signal G4.

[0100] At time T0, the start signal STV1 jumps to an active level, and the latch module 310A of the first-stage shift register unit 311 latches the start signal STV1. However, since the clock signal cka1 received by the clock signal terminal A of the first-stage shift register unit 311 is at an invalid level at this time, the shift signal Vnext1 output by the shift output terminal Next of the first-stage shift register unit 311 remains at an invalid level; the start signal STV2 also remains at an invalid level, so that the second-stage shift register unit 311 remains in the state before time T01.

[0101] In phase T1, the start signal STV1 remains active, and the clock signal cka1 received by the clock signal terminal A of the first-stage shift register unit 311 becomes active. The first-stage shift register unit 311 begins to output the active level of the shift signal Vnext1. The active level of the shift signal Vnext1 is provided to the level conversion module 320A of the first-stage shift register unit 311 and the first input terminal IN1 of the third-stage shift register unit 313. Since the output control signal ckb1 received by the output control terminal B of the first-stage shift register unit 311 is inactive at this time, the gate drive signal G1 output by the level conversion module 320A of the first-stage shift register unit 311 is level-converted and provided to the drive output terminal OUT via the output module 330A. The drive output terminal OUT of the first-stage shift register unit 311 then outputs the inactive level of the gate drive signal G1 to the scan line 20 electrically connected to it. At the same time, the third-stage shift register unit 313 will... The effective level of the shift signal Vnext1 received at its first input terminal IN1 is latched. However, since the clock signal cka3 received at the clock signal terminal A of the third-stage shift register unit 313 is invalid, the shift signal Vnext3 output by the shift signal terminal Next of the third-stage shift register unit 313 remains invalid. Consequently, the drive output terminal OUT of the third-stage shift register unit 313 outputs an invalid level of the gate drive signal G3. Furthermore, since at least one of the start signal STV2 and the clock signal cka2 received by the second shift register unit 312 is invalid during the T1 stage, the second shift register unit 312 will continue to output an invalid level of the shift signal Vnext2 and an invalid level of the gate drive signal G2. Consequently, the fourth-stage shift register unit 314, which is cascaded with the second-stage shift register unit 312, will also continue to output an invalid level of the shift signal Vnext4 and an invalid level of the gate drive signal G4.

[0102] In stage T2, the clock signal cka1 and the start signal STV1 received by the first-stage shift register unit 311 remain at valid levels, while the output control signal ckb1 received by the first-stage shift register unit 311 remains at invalid levels. This causes the shift output terminal Next of the first-stage shift register unit 311 to continue outputting the valid level of the shift signal Vnext, and the drive output terminal OUT of the first-stage shift register unit 311 to continue outputting the invalid level of the gate drive signal G1. Correspondingly, the clock signal of the third-stage shift register unit 313, which is cascaded with the first-stage shift register unit 311, remains at a valid level. The clock signal cka3 received at terminal A remains invalid, causing the third-stage shift unit 313 to continue outputting the shift signal Vnext3 and the gate drive signal G3 at invalid levels. Simultaneously, in stage T2, the start signal STV2 is active, causing the latch module 310A of the second-stage shift register unit 312 to latch the active level of the start signal STV2. Since the clock signal cka2 received at terminal A of the second-stage shift register unit 312 is active at this time, the second-stage shift register unit 312 begins outputting the shift signal Vnext2. The effective level of the shift signal Vnext2 is provided to the level conversion module 320A of the second-stage shift register unit 312 and the first input terminal IN1 of the fourth-stage shift register unit 314, respectively. However, since the output control signal ckb2 received by the output control terminal B of the second-stage shift register unit 312 is invalid, the gate drive signal G2 output by the level conversion module 320A of the second-stage shift register unit 312 is provided to the drive output terminal OUT after polarity conversion via its output module 330A. The invalid level of the gate drive signal G1 output by UT is sent to the scan line 20 electrically connected to it; the fourth-stage shift register unit 314 latches the valid level of the shift signal Vnext2 received by its first input terminal IN1, but because the clock signal cka4 received by the clock signal terminal A of the fourth-stage shift register unit 314 is invalid, the shift signal Vnext4 output by the shift signal terminal Next of the fourth-stage shift register unit 314 remains invalid, thereby causing the gate drive signal G4 to be invalid at the drive output terminal OUT of the fourth-stage shift register unit 314.

[0103] In stage T3, the clock signal cka1 received by the first-stage shift register unit 311 becomes invalid, and the output control signal ckb1 received by the first-stage shift register unit 311 becomes valid. The shift output terminal Next of the first-stage shift register unit 311 continues to output the valid level of the shift signal Vnext1. Under the control of the valid level of the shift signal Vnext1 and the valid level of the output control signal ckb1, the level conversion module 320A of the first-stage shift register unit 311 provides a low level of the gate drive signal G1 to its output module 330A. The low level of the gate drive signal G1 is output by the drive output terminal OUT after polarity conversion by the output module 330A, so that the scan line 20 electrically connected to the first-stage shift register unit 311 can transmit the valid level of the gate drive signal G1 to the gate of the switching transistor of the first row pixel to charge the gate of the switching transistor of the first row pixel; the start signal STV2 and the clock signal cka2 received by the second-stage shift register unit 312 are both The clock signal cka3 of the third-stage shift register unit 313 becomes valid, making the output control signal ckb2 of the second-stage shift register unit 312 continue to output the gate drive signal G2. Correspondingly, since the clock signal cka3 of the third-stage shift register unit 313 becomes valid, the shift signal Vnext3 initially output by the third-stage shift register unit 313 becomes valid. At this time, the output control signal ckb3 of the third-stage shift register unit 313 becomes invalid, making the drive output terminal OUT of the third-stage shift register unit 313 continue to output the gate drive signal G3. Simultaneously, under the control of the invalid clock signal cka4 it receives, the fourth-stage shift register unit 314 continues to output the invalid shift signal Vnext4, making the drive output terminal OUT of the fourth-stage shift register unit 314 continue to output the gate drive signal G4.

[0104] During time interval T4, the clock signal cka1 received by the first-stage shift register unit 311 remains invalid, while the output control signal ckb1 received by the first-stage shift register unit 311 remains valid. The shift output terminal Next of the first-stage shift register unit 311 continues to output the valid level of the shift signal Vnext1. This allows the level conversion module 320A of the first-stage shift register unit 311 to continue providing the valid level of the gate drive signal G1 to the scan line 20 electrically connected to its drive output terminal OUT. This allows the gate of the switching transistor of the first row of pixels electrically connected to that scan line 20 to continue charging, ensuring that the gate of the switching transistor of the first row of pixels is charged to meet its normal conduction condition, thereby enabling the corresponding signal to be accurately written into the pixel through the switching transistor. Meanwhile, the clock signal cka2 received by the second-stage shift register unit 312 becomes invalid, and the output control signal ckb2 received by the second-stage shift register unit 312 becomes valid. This allows the second-stage shift register unit 312 to continue outputting the valid level of the shift signal Vnext2 while simultaneously... Register unit 312 begins to output an effective level of the gate drive signal G2. This effective level of the gate drive signal G2 can be transmitted through the scan line to the gate of the switching transistor of the second row of pixels to charge the gate of the switching transistor of the second row of pixels. The clock signal cka3 received by the clock signal terminal A of the third-stage shift register unit 313 remains at an effective level, and the output control signal ckb3 of the output control terminal B of the third-stage shift register unit 313 remains at an ineffective level, so that the third-stage shift unit 313 continues to output the shift signal Vnex. The effective level of t3 and the ineffective level of the gate drive signal G3; at the same time, since the clock signal cka4 received by the clock signal terminal A of the fourth-stage shift register unit 314 becomes effective, the shift signal terminal Next of the fourth-stage shift register unit 314 starts to output the effective level of the shift signal Vnext4. However, since the output control signal ckb4 of the output control terminal B of the fourth-stage shift register unit 314 is ineffective, the drive output terminal OUT of the fourth-stage shift register unit 314 continues to output the ineffective level of the gate drive signal G4.

[0105] During time interval T5, the clock signal cka1 received by the first-stage shift register unit 311 becomes active, and the output control signal ckb1 received by the first-stage shift register unit 311 becomes inactive. This causes the shift output terminal Next of the first-stage shift register unit 311 to start outputting the inactive level of the shift signal Vnext1. Simultaneously, the drive output terminal OUT of the first-stage shift register unit 311 starts outputting the inactive level G1 of the gate drive signal G1 to scan line 20, thereby controlling the switching transistor electrically connected to scan line 20 to be in the off state, stopping the input to scan line 20. The first row of pixels is written with a 0-connection signal, ensuring that the signal in the first row of pixels remains the same as the signal written in the previous stage. Meanwhile, because the clock signal cka2 received by the second-stage shift register unit 312 remains inactive, and the output control signal ckb2 received by the second-stage shift register unit 312 remains active, the second-stage shift register unit 312 continues to output the shift signal Vnext2 and the gate drive signal G2 at active levels. The active level of the gate drive signal G2 continues to charge the gate of the switching transistor in the second row of pixels, allowing the second row of pixels to... The gate of the switching transistor of the element can be charged to meet its normal conduction condition, so that the corresponding signal can be written into each pixel through the switching transistor of each pixel in the second row; accordingly, the clock signal cka3 received by the clock signal terminal A of the third-stage shift register unit 313 becomes invalid, and the output control signal ckb3 of the output control terminal B of the third-stage shift register unit 313 becomes valid, so that while the third-stage shift unit 313 continues to output the valid level of the shift signal Vnext3, the output control terminal of the third-stage shift register unit 313 starts to output the gate drive signal G. The effective level of the gate drive signal G3 can be transmitted through the scan line 20 to the gate of the switching transistor of the third row pixel to charge the gate of the switching transistor of the third row pixel; in addition, since the clock signal cka4 of the clock signal terminal A of the fourth-stage shift register unit 314 continues to be effective, the output control signal ckb2 of the output control terminal B of the fourth-stage shift register unit 314 continues to be ineffective, so that the fourth-stage shift register unit 314 continues to output the effective level of the shift signal Vnext4 and the ineffective level of the gate drive signal G4.

[0106] During time period T6, the clock signal cka1 received by the first-stage shift register unit 311 remains active, and the output control signal ckb1 received by the first-stage shift register unit 311 remains inactive, causing the first-stage shift register unit 311 to continue outputting inactive shift signals Vnext1 and G1. Simultaneously, because the clock signal cka2 of the second-stage shift register unit 312 becomes active, the output control signal ckb2 of the second-stage shift register unit 312 becomes inactive, causing the second-stage shift register unit 312 to start outputting inactive shift signals Vnext2 and G2. The inactive gate drive signal G2 can charge the gate of the switching transistor of the second row of pixels, controlling the switching transistor of the second row of pixels to be in the off state, stopping the writing of corresponding signals to the second row of pixels, so that the signal in the second row of pixels can remain the signal written in the previous stage. At this time, because the clock signal cka3 of the third-stage shift register unit 313 remains inactive, the third-stage shift register unit... The output control signal ckb3 of the third-stage shift unit 313 remains active, causing the third-stage shift unit 313 to continue outputting the active level of the shift signal Vnext3 and the active level of the gate drive signal G3. This allows the active level of the gate drive signal G3 to continue charging the gate of the switching transistor of the third row of pixels, ensuring that the switching transistor of the third row of pixels is in a normal conducting state. The corresponding signal can be accurately written into the third row of pixels through the conducting switching transistor. In addition, since the clock signal cka4 of the fourth-stage shift register unit 314 becomes inactive, the output control signal ckb2 of the fourth-stage shift register unit 314 becomes active. This allows the fourth-stage shift register unit 314 to continue outputting the active level of the shift signal Vnext4. At the same time, the drive output terminal OUT of the fourth-stage shift register unit 314 starts outputting the active level of the gate drive signal G4. This active level of the gate drive signal G4 can be transmitted to the gate of the switching transistor of the fourth row of pixels through the scan line 20 to charge the gate of the switching transistor of the fourth row of pixels.

[0107] During time interval T7, since the start signals STV1 and STV2 remain invalid, the first-stage shift register unit 311 continues to output invalid shift signals Vnext1 and gate drive signals G1, and the second-stage shift register unit 312 similarly outputs invalid shift signals Vnext2 and gate drive signals G2. The clock signal cka3 received by the third-stage shift register unit 313 becomes valid, and the output control signal ckb3 received by the third-stage shift register unit 314 becomes invalid, causing the third-stage shift register unit 314 to start outputting invalid shift signals Vnext3 and gate drive signals G3. This invalid gate drive signal G3 can be transmitted through scan line 20 to the switching transistor of the third row pixel, thereby enabling the third... When the switching transistor of the row pixel is in the off state, the corresponding signal is stopped from being written to the third row pixel, so that the signal in the third row pixel can remain the signal written in the previous stage. At this time, since the clock signal cka4 of the fourth-stage shift register unit 314 continues to remain at an invalid level, the output control signal ckb4 of the fourth-stage shift register unit 314 continues to remain at an effective level, so that the fourth-stage shift register unit 314 continues to output the effective level of the shift signal Vnext4 and the gate drive signal G4. The effective level of the gate drive signal G4 can continue to charge the gate of the switching transistor of the fourth row pixel, so that the switching transistor of the fourth row pixel can be in a normal conducting state, so that the corresponding signal can be accurately written to the fourth row pixel through the conducting switching transistor.

[0108] In stage T8, the shift signal Vnext1 and gate drive signal G1 output by the first-stage shift register unit 311, the shift signal Vnext2 and gate drive signal G2 output by the second-stage shift register unit 312, and the shift signal Vnext3 and gate drive signal G3 output by the third-stage shift register unit 313 remain at an invalid level. At this time, because the clock signal cka4 of the fourth-stage shift register unit 314 becomes an active level, the fourth-stage shift register unit 314 starts to output an invalid level of the shift signal Vnext4. At the same time, the output control signal ckb4 of the fourth-stage shift register unit 314 becomes an invalid level, causing the fourth-stage shift register unit 314 to start outputting an invalid level of the gate drive signal G4. The invalid level of the gate drive signal G4 is transmitted to the gate of the switching transistor of the fourth row pixel through the scan line 20, so that the switching transistor of the fourth row pixel is turned off, stopping the writing of the corresponding signal to the fourth row pixel, so that the signal in the fourth row pixel can remain the signal written in the previous stage.

[0109] In this way, the shift signals Vnext output by each shift register unit 31 are shifted sequentially, and the shift amount of the shift signals Vnext output by the two cascaded shift register units 31 is equal to the width of the effective pulse of the clock signal CKA received by each of them; at the same time, the gate drive signals G output by each shift register unit 31 can also be shifted sequentially, and the effective pulses of the gate drive signals G output by the two cascaded shift register units 31 do not overlap, so as to ensure that the switching transistors of each row of pixels are normally turned on, and also to ensure the accuracy of the signals written to each row of pixels, thereby improving the display light emission accuracy of each row of pixels and thus improving the display effect of the display panel.

[0110] It is understandable that, such as Figure 10 As shown, the clock signal cka1 of the first-stage shift register unit can be the same as the output control signal ckb3 of the third-stage shift register unit, and the output control signal ckb1 of the first-stage shift register unit can be the same as the clock signal cka3 of the third-stage shift register unit, so that the clock signal cka1 of the first-stage shift register unit can be multiplexed as the output control signal ckb3 of the third-stage shift register unit, and the output control signal ckb1 of the first-stage shift register unit can be multiplexed as the clock signal cka3 of the third-stage shift register unit; Similarly, the clock signal cka2 of the second-stage shift register unit can be the same as the output control signal ckb4 of the fourth-stage shift register unit, and the output control signal ckb2 of the second-stage shift register unit can be the same as the clock signal cka4 of the fourth-stage shift register unit. This allows the clock signal cka2 of the second-stage shift register unit to be multiplexed as the output control signal ckb4 of the fourth-stage shift register unit, and vice versa. At this time, as... Figure 11 and Figure 12 As shown, each four-stage shift register unit 31 of the driving circuit 30 is controlled by four control signals CK1, CK2, CK3 and CK4 to realize the sequential shifting of the shift signal Vnext and the gate drive signal G, thereby reducing the number of control signals provided to the driving circuit, reducing the number of signal lines used to transmit control signals, simplifying the structure of the display panel, and facilitating the narrow bezel of the display panel.

[0111] Optional, continue to refer to Figure 11 and Figure 12Multiple shift register units constitute multiple shift register unit groups 301; each shift register unit group 301 includes n unconnected and adjacent shift register units 31; the effective pulse times of the clock signal CKA received by each shift register unit 31 in the same shift register unit group 301 are shifted sequentially; and the effective pulse times of the output control signal CKB received by each shift register unit 301 in the same shift register unit group 301 are shifted sequentially.

[0112] Specifically, since the clock signal CKA of shift register unit 31 can control the effective pulse time of the shift signal Vnext output by its shift output terminal Next, and the output control signal CKB can control the effective pulse time of the gate drive signal G output by the controller drive output terminal OUT, by sequentially shifting the clock signals CKA received by each shift register unit 31 of the same shift register unit group 301, the shift signals Vnext output by each shift register unit 31 of the same shift register unit group 301 can be sequentially shifted, and by sequentially shifting the clock signals CKA received by each shift register unit 31 of the same shift register unit group 301, the shift signals Vnext output by each shift register unit 31 of the same shift register unit group 301 can be sequentially shifted. The output control signal CKB received by the stage shift register unit 31 is shifted sequentially, which enables the gate drive signal G output by each stage shift register unit 31 of the same shift register unit group 301 to be shifted sequentially. When the gate drive signal G output by each stage shift register unit 31 is transmitted to the gate of the switching transistor of each row pixel through each scan line 20, the row pixel can be scanned line by line, so that the switching transistor of each row pixel is turned on line by line. The data signal transmitted by the data line can be written into each row pixel in time-division, ensuring the accuracy of the data signal written to each row pixel and improving the display effect of the display panel.

[0113] In an optional embodiment, since in two adjacent shift register unit groups 301, each level of shift register unit 31 in the previous shift register unit is cascaded with each level of shift register unit 31 in the subsequent shift register unit group, for example, the first level shift register unit 311 in shift register unit group 3011 is cascaded with the third level shift register unit 313 in shift register unit group 3012, and the second level shift register unit 312 in shift register unit group 3011 is cascaded with the fourth level shift register unit 314 in shift register unit group 3012, the clock signal CKA received by each level of shift register unit 31 in the two adjacent shift register unit groups 301 is shifted sequentially. For example, control signal CK1 can be used as the clock signal CKA of the first level shift register unit 311, and control signal CK2 can be used as the clock signal of the second level shift register unit 312. CKA, control signal CK3 can be used as the clock signal CKA of the third-level shift register unit 313, control signal CK4 can be used as the clock signal CKA of the fourth-level shift register unit 314, and control signals CK1, CK2, CK3 and CK4 are shifted sequentially within one clock cycle t10; similarly, the output control signals CKB received by each level of shift register unit 31 in two adjacent shift register unit groups 301 are also shifted sequentially. For example, control signal CK3 can be used as the output control signal CKB of the first-level shift register unit 311, control signal CK4 can be used as the output control signal CKB of the second-level shift register unit 312, control signal CK1 can be used as the output control signal CKB of the third-level shift register unit 313, and control signal CK2 can be used as the output control signal CKB of the fourth-level shift register unit 314.

[0114] Optional, continue to refer to the references Figure 11 and Figure 12 When each shift register unit 31 includes a drive output terminal OUT, the effective pulse overlap time of the gate drive signal G output by any two adjacent shift register units 31 is k*Th. At this time, the effective pulse shift amount of the gate drive signal G output by any two adjacent shift register units 31 is Th.

[0115] Specifically, when the gate drive signal G output by the two adjacent shift register units 31 controls the switching transistors of the two adjacent rows of pixels to be turned on or off respectively, for example, the i-th shift register unit 31i can control the switching transistors of the i-th row of pixels to be turned on or off, and the (i+1)-th shift register unit 31i+1 can control the switching transistors of the (i+1)-th row of pixels to be turned on or off. At this time, during the effective pulse period of the gate drive signal Gi output by the i-th level shift register unit 31i, the (i+1)-th level shift register unit 31i+1 will also output the effective pulse of the gate drive signal Gi+1. The time for the i-th level shift register unit 31i and the (i+1)-th level shift register unit 31i to simultaneously output the effective pulses of the gate drive signals G(Gi, Gi+1) is k*Th. During this time period, the gate drive signal Gi output by the i-th level shift register unit 31i can control the switching transistor of the i-th row pixel to be in the normal conducting state, so that the data signal of the i-th row pixel can be written into each pixel of the i-th row one by one. Meanwhile, the gate drive signal Gi+1 output by the (i+1)-th level shift register unit 31i+1 can precharge the gate of the switching transistor of the (i+1)-th row pixel. This allows the switching transistor of the (i+1)th row of pixels to tend towards the on state. Simultaneously, when the gate drive signal Gi output by the i-th stage shift register unit 31i becomes invalid, the gate drive signal Gi+1 of the (i+1)th stage shift register unit 31i+1 can remain at an effective level for a duration of Th. Since the switching transistor of the (i+1)th row of pixels is already tending towards the on state, continuing to provide the gate drive signal Gi+1 to the gate of the (i+1)th row of pixel switching transistors allows the (i+1)th row of pixel switching transistors to quickly become on again. At this time, data signals can be provided to the (i+1)th row of pixels, enabling the data signals to be written into each pixel of the (i+1)th row, ensuring that the data signal writing time is consistent with the driving time Th of a row of pixels. Thus, by making the effective pulse overlap time of the gate drive signal G output by the two adjacent shift register units 31 equal to k*Th, it can be ensured that the shift amount of the effective pulse of the gate drive signal G output by the two adjacent shift register units 31 is Th, thereby making the writing time of the data signals of each row of pixels long enough to ensure the accuracy of the data signals written to each row of pixels, thereby improving the display light emission accuracy of the pixels and improving the display effect of the display panel.

[0116] Optional, continue to refer to the references Figure 11 and Figure 12Under the premise that the gate drive signals output by each level of shift register unit 31 in the same shift register unit group 301 are shifted sequentially and the shift amount is Th, the effective pulse times of the gate drive signals G output by each level of shift register unit 31 in the same shift register unit group 301 can overlap. At this time, the effective pulse time of the gate drive signals G output by each level of shift register unit 31 in the same shift register unit group 301 can be n*Th. In this way, under the premise of ensuring the accuracy of the gate drive signals G output by each level of shift register unit 31, the effective pulse of the gate drive signals G output by each level of shift register unit 31 can have a sufficiently long time so that when the gate drive signals G output by the shift register unit 31 control the switching transistor of the pixel to be turned on or off, the switching transistor of the pixel can have a sufficiently long conduction time so that the corresponding signal can be accurately written into each pixel.

[0117] Optional, continue to refer to the references Figure 11 and Figure 12 The effective pulse times of the output control signal CKB received by each level of shift register unit 31 in the same shift register unit group 301 overlap.

[0118] The output control signal CKB received by the shift register unit 31 is used to control the effective pulse time of the gate drive signal G output by its drive output terminal OUT. In the same shift register unit 31, the effective pulse time of the output control signal CKB usually overlaps with the effective pulse time of its gate drive signal G. Therefore, when the effective pulse times of the output control signals CKB of each shift register unit 31 in the same shift register unit group 301 overlap, the effective pulse times of the gate drive signal G output by each shift register unit 31 in the same shift register unit group 301 can overlap, thereby ensuring that the effective pulse time of the gate drive signal G output by each shift register unit 31 is long enough, so that the gate of the switching transistor of each row of pixels has a long enough charging time, ensuring that the data signal of each row of pixels can be accurately written to the corresponding node through its respective switching transistor. When each pixel displays light emission according to the data signal written therein, the display light emission accuracy of each pixel can be improved, which is conducive to improving the display effect of the display panel.

[0119] Optionally, the clock signal provided to the i-th stage shift register unit is multiplexed into the clock signal provided to the (i+2*n)-th stage shift register unit; the output control signal provided to the i-th stage shift register unit is multiplexed into the output control signal provided to the (i+2*n)-th stage shift register unit.

[0120] For example, taking n=2 as an example, Figure 13 This is a schematic diagram of another driving circuit provided in an embodiment of the present invention, such as... Figure 13As shown, the clock signal CK1 of the first-stage shift register unit 311 can be multiplexed as the clock signal of the fifth-stage shift register unit 315, the clock signal CK2 of the second-stage shift register unit 312 can be multiplexed as the clock signal of the sixth-stage shift register unit 316, the clock signal CK3 of the third-stage shift register unit 313 can be multiplexed as the clock signal of the seventh-stage shift register unit 317, and the clock signal CK4 of the fourth-stage shift register unit 314 can be multiplexed as the clock signal of the eighth-stage shift register unit 318. In this way, while ensuring that the shift signals Vnext output by each stage of the shift register unit 31 are shifted sequentially, the number of clock signals provided to the driving circuit can be reduced, thereby reducing the number of signal lines used to transmit clock signals. This is beneficial for reducing the size of the non-display area and for narrowing the bezel of the display panel.

[0121] Correspondingly, the output control signal CK3 of the first-stage shift register unit 311 can be reused as the output control signal of the fifth-stage shift register unit 315, the output control signal CK4 of the second-stage shift register unit 312 can be reused as the output control signal of the sixth-stage shift register unit 316, the output control signal CK1 of the third-stage shift register unit 313 can be reused as the output control signal of the seventh-stage shift register unit 317, and the output control signal CK2 of the fourth-stage shift register unit 314 can be reused as the output control signal of the eighth-stage shift register unit 318. In this way, while ensuring that the gate drive signals G output by each stage of the shift register unit 31 are shifted sequentially, the number of output control signals provided to the drive circuit can be reduced, thereby reducing the number of signal lines used to transmit the output control signals. This is beneficial for reducing the size of the non-display area and for narrowing the bezel of the display panel.

[0122] It should be noted that the above description is merely an exemplary illustration of the present invention, using the shift register units at each level including latch modules, level conversion modules, output modules, and reset modules as examples. However, the structure of the shift register units in the embodiments of the present invention is not limited to this.

[0123] In an alternative embodiment, Figure 14 This is a schematic diagram of another driving circuit provided in an embodiment of the present invention, such as... Figure 14As shown, in the same shift register unit, the drive output terminal OUT can be multiplexed as a shift output terminal. In this case, in the cascaded two-stage shift register units, the drive output terminal OUT of the i-th stage shift register unit 31i can be electrically connected to the scan line 20 and the first input terminal IN1 of the (i+n)-th stage shift register unit 31i+n, respectively. This allows the gate drive signal Gi output by the drive output terminal OUT of the i-th stage shift register unit 31i to be multiplexed as the first input signal Vin1i+n of the (i+n)-th stage shift register unit 31i+n. Thus, by multiplexing the drive output terminal OUT as a shift output terminal, the number of ports in the shift register unit 31 can be reduced, thereby simplifying the structure of the shift register unit, reducing its size, and consequently reducing the overall size of the drive circuit, which is beneficial for narrow bezels in the display panel.

[0124] For example, such as Figure 14As shown, taking n=4 as an example, the first input terminal IN1 of the first-stage shift register unit 311, the second-stage shift register unit 312, the third-stage shift register unit 313, and the fourth-stage shift register unit 314 respectively receive the start signals STV1, STV2, STV3, and STV1, and the effective pulses of the start signals STV1, STV2, STV3, and STV1 are shifted sequentially; while the drive output terminal OUT of the first-stage shift register unit 311 is electrically connected to the gate of the switching transistor of the first row pixel through the scan line 20, the drive output terminal OUT of the first-stage shift register unit 311 is also electrically connected to the first input terminal IN1 of the fifth-stage shift register unit 315; the drive output terminal OUT of the second-stage shift register unit 312 is connected to the gate of the second row pixel through the scan line 20. While the gate of the switching transistor of the third row pixel is electrically connected, the drive output terminal OUT of the second-stage shift register unit 312 is also electrically connected to the first input terminal IN1 of the sixth-stage shift register unit 316; while the drive output terminal OUT of the third-stage shift register unit 313 is electrically connected to the gate of the switching transistor of the third row pixel through the scan line 20, the drive output terminal OUT of the third-stage shift register unit 313 is also electrically connected to the first input terminal IN1 of the seventh-stage shift register unit 317; while the drive output terminal OUT of the fourth-stage shift register unit 314 is electrically connected to the gate of the switching transistor of the fourth row pixel through the scan line 20, the drive output terminal OUT of the fourth-stage shift register unit 314 is also electrically connected to the first input terminal IN1 of the eighth-stage shift register unit 318. Thus, the first-stage shift register unit 311, the second-stage shift register unit 312, the third-stage shift register unit 313, and the fourth-stage shift register unit 314 can sequentially output effective pulses of the gate drive signal under the start signals STV1, STV2, STV3, and STV1, respectively. Under the control of the gate drive signal output by the first-stage shift register unit 311, the sixth-stage shift register unit 316 under the control of the gate drive signal output by the second-stage shift register unit 312, the seventh-stage shift register unit 317 under the control of the gate drive signal output by the third-stage shift register unit 313, and the eighth-stage shift register unit 318 under the control of the gate drive signal output by the fourth-stage shift register unit 314, the fifth-stage shift register unit 315, the sixth-stage shift register unit 316, the seventh-stage shift register unit 317, and the eighth-stage shift register unit 318, respectively, can sequentially output effective pulses of the gate drive signal.

[0125] Optional, Figure 15 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention, as shown below. Figure 15As shown, when the drive output terminal OUT of the same shift register unit 31 is multiplexed as a shift output terminal, the shift register unit 31 may also include a first reset terminal C, a first voltage terminal V1, a second voltage terminal V2, a first control module 310B, a second control module 320B, a reset module 330B, and at least one output module 340B corresponding to at least one drive output terminal OUT.

[0126] The reset module 330B is electrically connected to the first reset terminal C, the first control module 310B, and the second control module 320B, respectively. The reset module 330B, the first control module 310B, and the second control module 320B are also electrically connected to the first node N1. The reset module 330B is used to control the signal of the first node N1 in response to the first reset signal CKC from the first reset terminal C. The first reset signal CKC can be a pulse signal including both high and low levels. The effective level of the first reset signal CKC can be either high or low. Thus, when the first reset signal CKC is active, the reset module 330B can control the signal of the first node N1 to be active, and when the first reset signal CKC is inactive, the reset module 330B can control the signal of the first node N1 to be inactive.

[0127] In one exemplary embodiment, Figure 16 This is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of the present invention, as shown below. Figure 16 As shown, the reset module 330B may include a first reset transistor M31. The gate of the first reset transistor M31 can receive a scan control signal U2D. The scan control signal U2D is continuously active during normal operation of the driving circuit, enabling the scan control signal U2D to control the first reset transistor M31 to remain continuously in an on state. The first terminal of the first reset transistor M31 is electrically connected to the first reset terminal C, and the second terminal of the first reset transistor M31 is electrically connected to the first node N1. Thus, the first reset signal CKC can be transmitted to the first node N1 through the on-state first reset transistor M31, ensuring that the signal at the first node N1 is consistent with the first reset signal CKC. The first reset transistor M31 can be an N-type transistor or a P-type transistor, which can be configured according to actual needs; this embodiment of the invention does not impose specific limitations on this.

[0128] Continue to refer to Figure 15The first control module 310B is electrically connected to the first input terminal IN1, the clock signal terminal A, and the output module 340B, respectively, and the first control module 310B and the output module 340B are electrically connected to the second node N2. The first control module 310B is used to control the signal of the second node N2 in response to the first input signal Vin1 of the first input terminal IN1, the clock signal CKA of the clock signal terminal A, and the signal of the first node N1. Wherein, the first input signal Vin1 of the first input terminal IN1 is the gate drive signal output by the shift register unit cascaded with it. The clock signal CKA and the signal of the first node N1 can control the transmission path of the first control module 310B to transmit the first input signal Vin1 to the second node N2. When the first input signal Vin1 is at an active level, the first control module 310B transmits the first input signal Vin1 to the second node N2 under the control of the clock signal CKA, so that the second node N2 is at an active level consistent with the first input signal Vin. When it is necessary to reset the signal at the second node N2 so that the signal at the second node N2 becomes inactive, the signal at the first node N1 can control the first control module 310B to transmit the inactive level of the first input signal Vin1 to the second node N2 to reset the second node N2.

[0129] In one exemplary embodiment, reference continues to... Figure 16The first control module 310B may include a first control transistor M11 and a second control transistor M12. The gate of the first control transistor M11 can be electrically connected to the clock signal terminal A, and the gate of the second control transistor M12 can be electrically connected to the first node N1. The first terminals of both the first control transistor M11 and the second control transistor M12 are electrically connected to the first input terminal IN1, and the second terminals of both the first control transistor M11 and the second control transistor M12 are electrically connected to the second node N2. At this time, the clock signal CKA of the clock signal terminal A can control the first control transistor M11 to be turned on or off, so as to control the clock signal... When the CKA controls the first control transistor M11 to be turned on, the first control transistor M11 can transmit the first input signal Vin1 from the first input terminal IN1 to the second node N2, so that the signal of the second node N2 can be kept consistent with the first input signal IN1; the signal of the first node N1 can control the second control transistor M21 to be turned on or off, so that when the signal of the first node N1 controls the second control transistor M21 to be turned on, the second control transistor M21 can transmit the first input signal Vin1 to the second node N2, so that the signal of the second node N2 can also be kept consistent with the first input signal Vin1. Thus, to allow the signal at the second node N2 to vary between valid and invalid levels, the first control transistor M11 and the second control transistor M12 can be time-division multiplexed. That is, when the first input signal Vin1 is valid, the clock signal CKA can also be valid. During the period when the first input signal Vin1 is invalid, the signal at the first node N1 can be controlled to be valid, so that the clock signal CKA can control the writing of the valid level of the first input signal Vin1 to the second node N2, and the signal at the first node N1 can control the writing of the invalid level of the first input signal Vin1 to the second node N2. Since the signal at the first node N1 is consistent with the first reset signal C, the first reset signal C can control the writing of the invalid level of the first input signal Vin1 to the second node N2. The first control transistor M11 and the second control transistor M12 can be N-type transistors or P-type transistors, and can be configured according to actual needs; this embodiment of the invention does not impose specific limitations on this.

[0130] Continue to refer to Figure 15The second control module 320B is electrically connected to the first voltage terminal V1, the second voltage terminal V2, the first node N1, the second node N2, and the output module 340B. The second control module 320B and the output module 340B are electrically connected to the third node N3. The second control module 320B is used to control the first voltage signal Vgl of the first voltage terminal V1 to be provided to the third node N3 when the signal of the first node N1 is at an effective level, and to control the second voltage signal Vgh of the second voltage terminal V2 to be provided to the third node N3 when the signal of the second node N2 is at an effective level. The first voltage signal Vgl of the first voltage terminal V1 and the second voltage signal Vgh of the second voltage terminal V2 can be fixed voltage levels with different values. The second voltage signal Vgh can be a signal that controls the third node N3 to be at an effective level, while the first voltage signal Vgl can be a signal that controls the third node N3 to be at an ineffective level. Thus, when the signal at the first node N1 is at an active level, the second control module 320B can transmit the second voltage signal Vgh to the third node N3, making the third node N3 active. When the signal at the second node N2 is at an active level, the second control module 320B can transmit the first voltage signal Vgl to the third node N3, making the signal at the third node N3 inactive. This ensures that when the signal at the second node N2 is active, the signal at the third node N3 can be inactive, and when the signal at the second node N2 is inactive, the signal at the third node N3 can be inactive.

[0131] In one exemplary embodiment, reference continues to... Figure 16The second control module 320B may include a third control transistor M21 and a fourth control transistor M22. The gate of the third control transistor M21 is electrically connected to the first node N1, the first terminal of the third control transistor M21 is electrically connected to the second voltage terminal V2, and the second terminal of the third control transistor M21 is electrically connected to the third node N3. The gate of the fourth control transistor M22 is electrically connected to the second node N2, the first terminal of the fourth control transistor M22 is electrically connected to the first voltage terminal V1, and the second terminal of the fourth control transistor M22 is electrically connected to the third node N3. Thus, the first node N1... The signal can control the third control transistor M21 to turn on or off. When the signal from the first node N1 controls the third control transistor M21 to turn on, the third control transistor M21 can transmit the second voltage signal Vgh to the third node N3, making the third node N3 an active level. The signal from the second node N2 can control the fourth control transistor M22 to turn on or off. When the signal from the second node N2 controls the fourth control transistor M22 to turn on, the fourth control transistor M22 can transmit the first voltage signal Vgl to the third node N3, making the third node N3 an inactive level. The third control transistor M21 and the fourth control transistor M22 can be N-type transistors or P-type transistors, and can be configured according to actual needs. This embodiment of the invention does not impose specific limitations on this.

[0132] Continue to refer to Figure 15The output module 340B is also electrically connected to the output control terminal B, the first voltage terminal V1, and the drive output terminal OUT. The output module 340B is used to control the gate drive signal G output by the drive output terminal OUT in response to the output control signal CKB from the output control terminal B, the first voltage signal Vgl from the first voltage terminal V1, the signal from the second node N2, and the signal from the third node N3. The output control signal B can be a pulse signal including both high and low levels, and its effective level can be either high or low, which can be set according to actual needs. This embodiment of the invention does not specifically limit this setting. Since the signals of the second node N2 and the third node N3 are opposite, the signal of the second node N2 can control the transmission path of the output control signal CKB to the drive output terminal OUT, while the signal of the third node N3 can control the transmission path of the first voltage signal Vgl to the drive output terminal OUT. When the output module 340B transmits the output control signal CKB to the drive output terminal OUT, the gate drive signal G output by the drive output terminal OUT remains consistent with the output control signal CKB. Similarly, when the output module 340B transmits the first voltage signal Vgl to the drive output terminal OUT, the gate drive signal G output by the drive output terminal OUT remains consistent with the first voltage signal Vgl. Furthermore, since the first voltage signal Vgl is a continuous invalid level, while the output control signal CKB includes both invalid and valid levels, when the output control signal CKB is valid, the gate drive signal G output by the drive output terminal OUT can be controlled to remain consistent with the output control signal CKB. Conversely, when the drive output terminal OUT needs to remain invalid for an extended period, the gate drive signal G output by the drive output terminal OUT can be controlled to remain consistent with the first voltage signal Vgl.

[0133] In one exemplary embodiment, reference continues to... Figure 16The output module 340B may include a first output transistor M41 and a second output transistor M42. The gate of the first output transistor M41 is electrically connected to the second node N2, the first terminal of the first output transistor M41 is electrically connected to the output control terminal B, and the second terminal of the first output transistor M41 is electrically connected to the drive output terminal OUT. The gate of the second output transistor M42 is electrically connected to the third node N3, the first terminal of the second output transistor M42 is electrically connected to the first voltage terminal V1, and the second terminal of the second output transistor M42 is electrically connected to the drive output terminal OUT. At this time, the signal of the second node N2 can control the first output transistor M41 to turn on or off, so that when the signal of the second node N2 is at an effective level, the first output transistor M41 is turned on, and the output control signal CKB can be transmitted to the drive output terminal OUT. The signal of the third node N3 can control the second output transistor M42 to turn on or off, so that when the signal of the third node N3 is at an effective level, the second output transistor M42 is turned on, and the first voltage signal V1 can be transmitted to the drive output terminal OUT. The first output transistor M41 and the second output transistor M42 can be N-type transistors or P-type transistors, and can be set according to actual needs. This embodiment of the invention does not make specific limitations on this.

[0134] In an alternative embodiment, Figure 17 This is a driving timing diagram of another shift register unit provided in an embodiment of the present invention, in conjunction with reference to [reference needed]. Figure 16 and Figure 17 In the same shift register unit 31, the effective pulses of the clock signal CKA, the output control signal CKB, and the first reset signal CKC are shifted sequentially, and the effective pulse times of the clock signal CKA, the output control signal CKB, and the first reset signal CKC do not overlap.

[0135] Specifically, since the first input signal Vin1 is the gate drive signal output by other shift register units cascaded with the current stage shift register unit 31, when the first input signal Vin1 is at an active level, the clock signal CKA can also be at an active level. This allows the active level of the first input signal Vin1 to be transmitted to the second node N2 through the first control module 310B. At this time, the signal of the second node N2 can control the output module 340B to transmit the output control signal CKB to the drive output terminal OUT, ensuring that the gate drive signal output by the drive output terminal OUT is consistent with the output control signal CKB. To ensure that the active pulses of the gate drive signals G output by the two cascaded shift register units 31 do not overlap, the output control signal CKB should be at an inactive level. That is, during the period when the clock signal CKA is at an active level, the output control signal CKB is at an inactive level. When the first input signal Vin1 becomes inactive, the clock signal CKA can also be inactive. At this time, if no new signal is written to the second node N2, the signal of the second node N2 will remain at an active level, making... The signal from the second node N2 can continue to control the output module 340B to transmit the output control signal CKB to the drive output terminal OUT, so that the gate drive signal G of the drive output terminal OUT can continue to be consistent with the output control signal CKB. At this time, if the output control signal CKB becomes an active level, the gate drive signal G of the drive output terminal OUT will also be an active level. After the output control signal CKB becomes an inactive level, the drive output terminal OUT can also become an inactive level. At this time, the first reset signal CKC of the first reset terminal C can control the reset module 330B to make the signal from the first node N1 active level, so that the inactive level of the first input signal Vin1 is transmitted to the second node N2. The second voltage signal Vgh of the second voltage terminal V2 is transmitted to the third node N3 through the second control module 320B, so that the third node N3 is an active level. Under the control of the active level of the third node N3, the output module 340B transmits the first voltage signal Vgl to the drive output terminal OUT, so that the drive output terminal OUT outputs an inactive level of the gate drive signal. In this way, by shifting the effective pulses of the clock signal CKA, the output control signal CKB, and the first reset signal CKC in sequence, the cascaded shift register units 31 can output the effective pulses of the gate drive signal G in sequence, thereby ensuring the accuracy of the gate drive signal output by each shift register unit 31.

[0136] In an alternative embodiment, reference continues. Figure 16 and Figure 17Each shift register unit 31 may also include a node inter-control module 350B. Under the control of the first input signal Vin1, the node inter-control module 350B can control the signal of the third node N3, and under the control of the signal of the third node N3, control the signal of the second node N2, so that the signal of the second node N2 and the signal of the third node N3 are mutually clamped, ensuring the accuracy of the signals at the second node N2 and the third node N3, so that when the output module 340B outputs the corresponding gate drive signal according to the signals of the second node N2 and the third node N3, the accuracy of the gate drive signal output by the output module 340B can be improved.

[0137] In an exemplary embodiment, the node inter-control module 350B may include a first inter-control transistor M51 and a second inter-control transistor M52. The gate of the first inter-control transistor M51 is electrically connected to the first input terminal IN1, the first terminal of the first inter-control transistor M51 is electrically connected to the first voltage terminal V1, and the second terminal of the first inter-control transistor M51 is electrically connected to the third node N3. This allows the first input signal Vin1 at the first input terminal IN1 to control the first inter-control transistor M51 to be turned on or off. When the first inter-control transistor M51 is turned on, it can control the first voltage terminal V1 to be turned off. The voltage signal Vgl is transmitted to the third node N3, making the third node N3 inactive. The gate of the second inter-control transistor M52 is electrically connected to the third node N3, the first terminal of the second inter-control transistor M52 is electrically connected to the first voltage terminal V1, and the second terminal of the second inter-control transistor M52 is electrically connected to the second node N2. This allows the signal from the third node N3 to control the second inter-control transistor M52 to turn on or off. When the second inter-control transistor M52 is on, it can transmit the first voltage signal Vgl from the first voltage terminal V1 to the second node N2, making the second node N2 inactive. The first inter-control transistor M51 and the second inter-control transistor M52 can be N-type transistors or P-type transistors, and can be configured according to actual needs. This embodiment of the invention does not impose specific limitations on this.

[0138] Optionally, each shift register unit 31 may also include a storage capacitor C2, which is electrically connected between the first voltage terminal V1 and the third node N3 to store the signal of the third node N3 and maintain the voltage of the third node N3, so that the voltage of the third node N3 can control the output module 340B to accurately output the corresponding gate drive signal.

[0139] Optionally, each shift register unit 31 may also include a bootstrap capacitor C1, which is electrically connected between the drive output terminal OUT and the second node N2, so that when the drive output terminal OUT changes, the second node N2 can be controlled to have the same change, thereby enabling the signal of the second node N2 to control the first output transistor M41 in the output module 340B to be accurately turned on or off.

[0140] Optionally, the second node N2 may include a first sub-node N21 and a second sub-node N22. In this case, the shift register unit 31 may also include a Zener transistor M60. The gate of the Zener transistor M60 receives a fixed signal, such as a second voltage signal Vgh. The second voltage signal Vgh can control the Zener transistor M60 to be in a normal conducting state. The first terminal of the Zener transistor M60 can be electrically connected to the first control module 310B to the first sub-node N21, and the first terminal of the Zener transistor M60 can be electrically connected to the output module 340B to the second sub-node N22. The Zener transistor M60 can stabilize the potential of the first sub-node N21 and the second sub-node N22 to prevent the potential of the first sub-node N21 and the second sub-node N22 from being unstable, which would affect the accuracy of the gate drive signal output by the drive output terminal OUT.

[0141] Optionally, when each shift register unit includes a clock signal terminal, an output control terminal, and a first reset terminal, provided that the clock signal, output control signal, and first reset signal received by the same shift register unit are shifted sequentially, the clock signal, output control signal, and first reset signal of each shift register unit can be multiplexed, for example, as shown in the example. Figure 14As shown, the clock signal of the first-stage shift register unit 311 can be multiplexed as the first reset signal of the fifth-stage shift register unit 315 and as the output control signal of the seventh-stage shift register unit 317. The clock signal of the second-stage shift register unit 312 can be multiplexed as the first reset signal of the sixth-stage shift register unit 316 and as the output control signal of the eighth-stage shift register unit 318. The clock signal of the third-stage shift register unit 313 can be multiplexed as the first reset signal of the seventh-stage shift register unit 317 and as the output control signal of the first-stage shift register unit 311. The clock signal of the fourth-stage shift register unit 314 can be multiplexed as the first reset signal of the eighth-stage shift register unit 318 and as the output control signal of the second-stage shift register unit 312. The clock signal of the fifth-stage shift register unit 315 can be multiplexed as the first reset signal of the first-stage shift register unit 311 and as the output control signal of the third-stage shift register unit 313. The clock signal of the sixth-stage shift register unit 316 can be multiplexed as the first reset signal of the second-stage shift register unit 312 and as the output control signal of the fourth-stage shift register unit 314. The clock signal of the seventh-stage shift register unit 317 can be multiplexed as the first reset signal of the third-stage shift register unit 313 and as the output control signal of the fifth-stage shift register unit 315. The clock signal of the eighth-stage shift register unit 318 can be multiplexed as the first reset signal of the fourth-stage shift register unit 314 and as the output control signal of the sixth-stage shift register unit 316. Thus, the gate drive signal G can be shifted sequentially by each eight-stage shift register unit 31 of the drive circuit 30 under the control of eight control signals CK1, CK2, CK3, CK4, CK5, CK6, CK7 and CK8. This reduces the number of control signals supplied to the drive circuit, reduces the number of signal lines used to transmit control signals, simplifies the structure of the display panel, and is beneficial for narrow bezels of the display panel.

[0142] In an alternative embodiment, Figure 18 This is a driving timing diagram of another driving circuit provided in an embodiment of the present invention, in conjunction with reference to... Figure 14 and Figure 18Within one clock cycle t10′, the start times of the effective pulses of control signals CK1, CK2, CK3, CK4, CK5, CK6, CK7, and CK8 are shifted sequentially, and the time interval between the start times of the effective pulses of any two adjacent control signals is less than the width of their effective pulses. This ensures that the effective pulse times of the gate drive signals G output by any two adjacent shift register units 31 overlap, and the overlap time is equal to the overlap time of the effective pulses of any two adjacent control signals. The shift amount of the effective pulses of the gate drive signals G output by any two adjacent shift register units 31 can be equal to the shift amount of the effective pulses of any two adjacent control signals. Thus, by setting the width of the effective pulses of each control signal and the shift amount of the effective pulses of any two adjacent control signals, the width and shift amount of the effective pulses of the gate drive signals G (G1, G2, G3, G4, G5, G6, G7, and G8) output by each shift register unit 31 can be controlled.

[0143] In an alternative embodiment, the reference continues... Figure 14 and Figure 18 For each shift register unit 31 including a clock signal terminal A, an output control terminal B, and a first reset terminal C, when adjacent and unconnected n-stage shift register units 31 form a shift register unit group 301, in the same shift register unit group 301, the effective pulses of the clock signals received by each shift register unit are shifted sequentially, the effective pulses of the output control signals received by each shift register unit are shifted sequentially, and the effective pulses of the first reset signals received by each shift register unit are shifted sequentially, so that the gate drive signals output by each shift register unit 31 can be shifted sequentially.

[0144] In an optional embodiment, the reference continues... Figure 14 and Figure 18 In the case where each shift register unit 31 includes a clock signal terminal A, an output control terminal B, and a first reset terminal C, the clock signal of the i-th shift register unit can be multiplexed as the clock signal of the (i+2*n)-th shift register unit, the output control signal of the i-th shift register unit can be multiplexed as the output control signal of the (i+2*n)-th shift register unit, and the first reset signal of the i-th shift register unit can be multiplexed as the first reset signal of the (i+2*n)-th shift register unit. Thus, providing 2*n control signals to the driving circuit 30 is sufficient to control each stage of the shift register unit 31, reducing the number of control signals provided to the driving circuit 30, thereby reducing the number of signal lines used to transmit control signals, which is beneficial for narrow bezels on the display panel.

[0145] It is understood that the above description is merely an exemplary illustration of the driving process of the driving circuit in the embodiments of the present invention, using two different shift register unit structures as examples. However, the structure of the shift register unit in the embodiments of the present invention is not limited thereto. Provided that the core inventive points of the embodiments of the present invention can be achieved, the embodiments of the present invention do not limit the specific structure of each level of shift register unit.

[0146] It should be noted that the above description is merely an example of illustrating the structure and driving process of the driving circuit by taking each shift register unit as having one drive output terminal and one output control terminal corresponding to the drive output terminal. In the embodiments of the present invention, the number of drive output terminals of each shift register unit can be one or more, and the number of corresponding output control terminals can also be one or more. Furthermore, the number of drive output terminals in the same shift register unit can be the same as the number of output control terminals, so that each output control terminal can control the gate drive signal output by each drive output terminal in a one-to-one correspondence.

[0147] Optionally, when each shift register unit includes m drive output terminals, the effective pulses of the gate drive signals output by each drive output terminal of the same shift register unit are shifted sequentially; m is a positive integer greater than or equal to 2; in the same shift register unit, the drive output terminal of the effective pulse of the j-th output gate drive signal is the j-th drive output terminal; j is a positive integer less than or equal to m; in the same shift register unit, the overlap time between the effective pulse of the gate drive signal output by the j-th drive output terminal and the effective pulse of the gate drive signal output by the (j+1)-th drive output terminal is k*Th.

[0148] For example, when the drive output terminal of the same shift register unit is not reused as a shift output terminal, Figure 19 This is a schematic diagram of another driving circuit provided in an embodiment of the present invention. Figure 20 This is a driving timing diagram of another driving circuit provided in an embodiment of the present invention, in conjunction with reference to... Figure 19 and Figure 20Each shift register unit 31 includes two drive output terminals OUT1 and OUT2, and two output control terminals B1 and B2. The output control signal received by the output control terminal B1 can control the gate drive signal output by the drive output terminal OUT1, and the output control signal received by the output control terminal B2 can control the gate drive signal output by the drive output terminal OUT2. The gate drive signals output by the drive output terminal OUT1 and the drive output terminal OUT2 can be provided to different scan lines 20 respectively to control the switching transistors of different rows of pixels to turn on or off respectively. In this way, each shift register unit 31 can control the switching transistors of two rows of pixels to turn on or off. This helps to reduce the number of shift register units set in the drive circuit, thereby reducing the size of the drive circuit 30 and facilitating the narrow bezel of the display panel.

[0149] Meanwhile, when each shift register unit 31 includes a clock signal terminal A and two output control terminals B1 and B2, three control signals need to be provided to each shift register unit 31. For example, in the first-stage shift register unit 311, the clock signal terminal A receives the clock signal CK1, the output control terminal B1 receives the output control signal CK3, and the output control terminal B2 receives the output control signal CK4. At this time, the effective pulses of the clock signal CK1, the output control signal CK3, and the output control signal CK4 of the first-stage shift register unit 311 are shifted sequentially, and the effective pulse times of the clock signal CK1, the output control signal CK3, and the output control signal CK4 do not overlap. The shifting of the effective pulses of the control signals received by other shift register units 31 is similar to that of the control signals received by the first-stage shift register unit 311, and will not be described in detail here.

[0150] Understandably, when each shift register unit includes a clock signal terminal and two output control terminals, the clock signals and output control signals received by each shift register unit can be multiplexed to reduce the number of control signals provided to the drive circuit. For example... Figure 19 and Figure 20 The system provides six control signals CK1, CK2, CK3, CK4, CK5, and CK6 to the driving circuit. Within one clock cycle, the effective pulses of each control signal CK1, CK2, CK3, CK4, CK5, and CK6 are shifted sequentially. This ensures that the gate drive signals G output from the two drive output terminals of the same shift register unit are shifted sequentially, thereby enabling the gate drive signals G output from each shift register unit to be shifted sequentially. This achieves line-by-line scanning of each pixel in the display panel, allowing data signals to be written to each pixel to control each pixel to accurately display and emit light.

[0151] Correspondingly, such as Figure 21As shown, when each shift register unit 31 includes two drive output terminals OUT1 and OUT2, each shift register unit 31 may include two level conversion modules 321A and 322A, and two output modules 331A and 332A. This allows the level conversion module 321A to provide a corresponding gate drive signal to the output module 331A under the control of the output control signal of the output control terminal B1 and the shift signal of the shift output terminal Next. The gate drive signal is then converted in polarity by the output module 331A and output from the drive output terminal OUT1. The level conversion module 322A is also able to provide a corresponding gate drive signal to the output module 332A under the control of the output control signal of the output control terminal B2 and the shift signal of the shift output terminal Next. The gate drive signal is then converted in polarity by the output module 332A and output from the drive output terminal OUT2. In this way, it can be ensured that each drive output terminal OUT1 and OUT2 of the same shift register unit outputs a different gate drive signal.

[0152] Optionally, when the drive output terminals of the same shift register unit are multiplexed as shift output terminals, for the same shift register unit including m drive output terminals, the drive output terminal of the effective pulse of the j-th output gate drive signal is the j-th drive output terminal; m is a positive integer, and j is a positive integer less than or equal to m; in the same shift register unit, the m-th drive output terminal is multiplexed as a shift output terminal.

[0153] For example, Figure 22 This is a schematic diagram of another driving circuit provided in an embodiment of the present invention. Figure 23 This is a driving timing diagram of another driving circuit provided in an embodiment of the present invention, in conjunction with reference to... Figure 22 and Figure 23Each shift register unit 31 includes two drive output terminals, namely the first drive output terminal OUT1 and the second drive output terminal OUT2. At this time, the second drive output terminal OUT2 is multiplexed as a shift output terminal. At this time, the second drive output terminal OUT2 of the first-stage shift register unit 311 can be electrically connected to the first input terminal IN1 of the fifth-stage shift register unit 315, the second drive output terminal OUT2 of the second-stage shift register unit 312 can be electrically connected to the first input terminal IN1 of the sixth-stage shift register unit 316, the second drive output terminal OUT2 of the third-stage shift register unit 313 can be electrically connected to the first input terminal IN1 of the seventh-stage shift register unit 317, and the second drive output terminal OUT2 of the fourth-stage shift register unit 314 can be electrically connected to the first input terminal IN1 of the eighth-stage shift register unit 318. Thus, in the cascaded i-th stage shift register unit and i+n stage shift register unit, after each drive output terminal of the i-th stage shift register unit outputs a valid pulse of the gate drive signal, the i+n stage shift register unit is controlled to output a valid pulse of the gate drive signal, thereby ensuring that the gate drive signals output by each drive output terminal (OUT1, OUT2) of each stage shift register unit 31 are shifted sequentially.

[0154] Meanwhile, when each shift register unit 31 includes a clock signal terminal A, two output control terminals B1 and B2, and a first reset terminal C, four control signals need to be provided to each shift register unit 31. For example, in the first-stage shift register unit 311, the clock signal terminal A receives the clock signal CK1, the output control terminal B1 receives the output control signal CK8, the output control terminal B2 receives the output control signal CK9, and the first reset terminal C receives the first reset signal CK11. At this time, the effective pulses of the clock signal CK1, the output control signal CK8, the output control signal CK9, and the first reset signal CK11 of the first-stage shift register unit 311 are shifted sequentially, and the effective pulse times of the clock signal CK1, the output control signal CK8, and the output control signal CK9 do not overlap, and the effective pulse times of the first reset signal CK11, the output control signal CK8, and the output control signal CK9 do not overlap. The shifting of the effective pulses of the control signals received by other shift register units 31 is similar to that of the control signals received by the first-stage shift register unit 311, and will not be described in detail here.

[0155] It is understandable that when each shift register unit includes a clock signal terminal, two output control terminals, and a first reset terminal, the clock signal, output control signal, and first reset signal received by each shift register unit can also be multiplexed to reduce the number of control signals provided to the drive circuit. For example Figure 22 and Figure 23The system provides sixteen control signals CK1, CK2, CK3, CK4, CK5, CK6, CK7, CK8, CK9, CK10, CK11, CK12, CK13, CK14, CK15, and CK16 to the driving circuit. Within one clock cycle, the effective pulses of each control signal CK1 to CK16 are shifted sequentially. This ensures that the gate drive signals G output from the two drive output terminals of the same shift register unit are shifted sequentially, thereby enabling the gate drive signals G output from each shift register unit to be shifted sequentially. This achieves line-by-line scanning of each pixel in the display panel, allowing data signals to be written to each pixel to control each pixel to accurately display and emit light.

[0156] Correspondingly, such as Figure 24 As shown, when each shift register unit 31 includes two drive output terminals OUT1 and OUT2, each shift register unit 31 may include two output modules 341B and 342B, so that output module 341B can control the gate drive signal output by drive output terminal OUT1 under the control of the output control signal of output control terminal B1, the signal of the first node N1, and the signal of the second node N2; output module 342B can control the gate drive signal output by drive output terminal OUT1 under the control of the output control signal of output control terminal B2, the signal of the first node N1, and the signal of the second node N2. In this way, it can be ensured that each drive output terminal OUT1 and OUT2 of the same shift register unit outputs different gate drive signals.

[0157] It should be noted that the above is only an exemplary description of the technical solution of the present invention by taking two shift register unit structures as an example to illustrate the two drive output terminals of each shift register unit. In the present invention, the number of drive output terminals in each shift register unit can be set according to actual needs. At this time, the number of drive output terminals in each shift register unit can be equal to n, greater than n, or less than n. The present invention does not make specific limitations on this.

[0158] Optionally, the overlap time between the effective pulse of the gate drive signal output from the m-th drive output terminal in the i-th stage shift register unit and the effective pulse of the gate drive signal output from the first drive output terminal in the (i+1)-th stage shift register unit is k*Th. In this case, compared to the effective pulse of the gate drive signal output from the m-th drive output terminal in the i-th stage shift register unit, the shift amount of the effective pulse of the gate drive signal output from the first drive output terminal in the (i+1)-th stage shift register unit is Th. This ensures that the signal writing time for the pixel electrically connected to the first drive output terminal of the (i+1)-th stage shift register unit is approximately consistent with the driving time Th for one row of pixels. This ensures that the signal writing time for each row of pixels is sufficiently long, guaranteeing the accuracy of the data signals written to each row of pixels, thereby improving the display illumination accuracy of the pixels and contributing to the improvement of the display panel's display effect.

[0159] Optionally, when m ≤ n, the effective pulse times of the gate drive signals output by each drive output terminal of the same shift register unit overlap. In this case, the effective pulse time of the gate drive signals output by each drive output terminal of the same shift register unit can be greater than or equal to m*Th. This ensures that, while maintaining the accuracy of the gate drive signals output by each shift register unit, the effective pulse time of the gate drive signals output by each shift register unit is long enough to allow the pixel's switching transistors to have a sufficiently long on-time when the gate drive signals output by the shift register unit control the on or off of the pixel's switching transistors, thus enabling the corresponding signals to be accurately written into each pixel.

[0160] Optionally, the effective pulse times of the output control signals received by the same shift register unit overlap.

[0161] The output control signals received by each output control terminal of the shift register unit correspond to the effective pulse time of the gate drive signal output by each drive output terminal. In this way, by making the effective pulse time of each output control signal received by the same shift register unit overlap, the effective pulse time of the gate drive signal output by each drive output terminal in the same shift register unit can overlap, thereby ensuring that the effective pulse time of the gate drive signal output by each drive output terminal is long enough, so that the gate of the switching transistor M0 of each pixel 10 has a long enough charging time, ensuring that the switching transistor M0 of each pixel 10 can be in a normal conducting state. This allows the data signal to be accurately written into its corresponding pixel 10 through the conducting switching transistor M0, so that when the pixel 10 displays and emits light according to the data signal written therein, the accuracy of the display brightness of the pixel 10 can be improved, which is beneficial to improving the overall display effect of the display panel 100.

[0162] Optionally, when m>n, the effective pulse times of the gate drive signals output by each drive output terminal from the first drive output terminal to the nth drive output terminal in the same shift register unit overlap; within the same shift register unit, the effective pulse time of the gate drive signal output by the first drive output terminal does not overlap with the effective pulse time of the gate drive signal output by the (n+1)th drive output terminal. Thus, the effective pulse time of the gate drive signal output by each drive output terminal can be less than or equal to n*Th, ensuring that the gate drive signals output by each shift register unit are sufficiently long, allowing the effective pulses of the gate drive signals output by each drive output terminal to shift sequentially. This enables the gate drive signals output by each drive output terminal to sequentially control the switching transistors of each row of pixels to be turned on, and the data signals transmitted by the data lines to be written into each pixel accordingly. This ensures that each pixel can accurately display and emit light based on the data signals written into it, thereby improving the overall display effect of the display panel.

[0163] Optionally, when the output control terminal corresponding to the j-th drive output terminal in the same shift register unit is the j-th output control terminal, the effective pulse times of the output control signals received by each output control terminal from the first output control terminal to the n-th output control terminal in the same shift register unit overlap; in the same shift register unit, the effective pulse time of the output control signal received by the first output control terminal does not overlap with the effective pulse time of the output control signal received by the (n+1)-th output control terminal.

[0164] Since the output control signals received by each output control terminal in the shift register unit correspond to the effective pulse times of the gate drive signals output by each drive output terminal, and the effective pulse times of the gate drive signals output by the drive output terminals typically overlap with the effective pulse times of the output control signals of their corresponding output control terminals, by making the effective pulse times of the output control signals received by the first output control terminal to the nth output control terminal in the same shift register unit overlap, the effective pulse times of the gate drive signals output by the first drive output terminal to the nth drive output terminal in the same shift register unit can overlap, and the same shift register unit can also achieve the same effect. The effective pulse times of the output control signals received by the first output control terminal and the (n+1)th output control terminal in the unit do not overlap, which ensures that the effective pulse times of the gate drive signals output by the first drive output terminal and the (n+1)th drive output terminal do not overlap. Thus, while ensuring that the effective pulse time of the gate drive signals output by each drive output terminal is long enough, the effective pulse times of the gate drive signals output by each drive output terminal can be shifted sequentially, so that the data signals transmitted by the data line can be written into each pixel accordingly. This ensures that each pixel can accurately display and emit light according to the data signals written into it, thereby improving the overall display effect of the display panel.

[0165] It should be noted that the above example only illustrates the sequential shifting of the gate drive signals output from the first drive output terminal to the m-th drive output terminal of the shift register unit, and the sequential shifting of the gate drive signals output from the drive output terminals of each shift register unit. That is, the start time of the effective pulse of the gate drive signal output from the j-th drive output terminal is before the start time of the effective pulse of the gate drive signal output from the (j+1)-th drive output terminal, and the start time of the effective pulse of the gate drive signal output from the m-th drive output terminal of the i-th shift register unit is before the start time of the effective pulse of the gate drive signal output from the first drive output terminal of the (i+1)-th shift register unit. At this time, the gate drive signals output from each drive output terminal of each shift register unit can control the switching transistors of the first row to the last row of pixels to be turned on sequentially, that is, the gate drive signals output from each drive output terminal of each shift register unit can perform forward scanning of each row of pixels in the display panel. In other embodiments of the present invention, the gate drive signals output by each shift register unit can also perform inverted scanning of each row of pixels. In this case, each shift register unit should also include a first scan control terminal and a second scan control terminal. The first scan control signal received by the first scan control terminal can be at an effective level when performing forward scanning of each row of pixels, and the second scan control signal received by the second scan control terminal can be at an effective level when performing reverse scanning of each row of pixels. For ease of description, the following example of each shift register unit including one drive output terminal will be used to illustrate the technical solution of the present invention.

[0166] Optional, Figure 25 This is a schematic diagram of another driving circuit provided in an embodiment of the present invention, such as... Figure 25As shown, each shift register unit 31 may further include a first scan control terminal U2D, a second scan control terminal D2U, and a second input terminal IN2. The first scan control terminal U2D receives a first scan control signal u2d, and the second scan control terminal D2U receives a second scan control signal d2u. The polarity of the first scan control signal u2d of the first scan control terminal U2D is opposite to that of the second scan control signal d2u of the second scan control terminal D2U. The second input terminal IN2 of the i-th shift register unit is electrically connected to the shift output terminal Next of the (i+n)-th shift register unit. For example, the second input terminal IN2 of the first-stage shift register unit 311 is electrically connected to the shift output terminal Next of the third-stage shift register unit 313. Thus, when the first scan control signal u2d of the first scan control terminal U2D is at an effective level, the effective pulse time of the gate drive signal output by the first-stage shift register unit 311 is before the effective pulse time of the gate drive signal output by the third-stage shift register unit 313, and thus each row of pixels can be scanned in the forward direction. When the second scan control signal d2u of the second scan control terminal D2U is at an effective level, the effective pulse time of the gate drive signal output by the third-stage shift register unit 313 is before the effective pulse time of the gate drive signal output by the first-stage shift register unit 311, and thus each row of pixels can be scanned in the reverse direction, thereby enabling the display panel to have diverse display modes.

[0167] Optional, Figure 26 This is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of the present invention, as shown below. Figure 26As shown, when the shift register unit 31 further includes a first scan control terminal U2D, a second scan control terminal D2U, and a second input terminal IN2, and the polarities of the first scan control signal u2d of the first scan control terminal U2D and the second scan control signal d2u of the second scan control terminal D2U are opposite, the shift register unit 31 may also include an input module 350A; the input module 350A is electrically connected between the first input terminal IN1 and the latch module 310A, and the input module 350A is also electrically connected to the first scan control terminal U2D, the second scan control terminal D2U, and the second input terminal IN2 respectively; the input module 350A is used to control the first input signal of the first input terminal to be provided to the latch module 310A when the first scan control signal u2d is at an effective level, and to control the second input signal of the second input terminal to be provided to the latch module 310A when the second scan control signal d2u is at an effective level. Thus, when performing a forward scan of each row of pixels, the effective level of the first scan control signal u2d can control the first input signal Vin1 of the first input terminal IN1 to be provided to the latch module 310A, so that the signal received by the latch module 310A can be consistent with the first input signal Vin1; conversely, when performing a reverse scan of each row of pixels, the effective level of the second scan control signal d2u can control the second input signal Vin2 of the second input terminal IN2 to be provided to the latch module 310A, so that the signal received by the latch module 310A can be consistent with the second input signal Vin2.

[0168] Thus, by setting the input module 350A in the shift register unit 31 to select the signal provided to the latch module 310A, the signals output by the cascaded shift register units 31 at each level can be prevented from affecting each other, ensuring that the shift register units 31 at each level can work accurately and improving the accuracy of the gate drive signals output by the shift register units at each level.

[0169] In one exemplary embodiment, reference continues to... Figure 26The input module 350A may include two transmission gates, Tr1 and Tr2. The input terminal of transmission gate Tr1 is electrically connected to the first input terminal IN1, and the input terminal of transmission gate Tr2 is electrically connected to the second input terminal IN2. The output terminals of both transmission gates Tr1 and Tr2 are electrically connected to the latch module 310A. The forward control terminal and the reverse control terminal of transmission gate Tr1 are electrically connected to the first scan control terminal U2D and the second scan control terminal D2U, respectively. The forward control terminal and the reverse control terminal of transmission gate Tr2 are electrically connected to the second scan control terminal D2U and the first scan control terminal U2D, respectively. Thus, when scanning each pixel in the forward direction, the first scan control signal u2d and the second scan control signal d2u can control the transmission gate Tr1 to be turned on and the transmission gate Tr2 to be turned off, so that the signal provided to the latch module 310A is consistent with the first input signal Vin1. When scanning each pixel in the reverse direction, the first scan control signal u2d and the second scan control signal d2u can control the transmission gate Tr2 to be turned on and the transmission gate Tr1 to be turned off, so that the signal provided to the latch module 310A is consistent with the second input signal Vin2.

[0170] Each transmission gate (Tr1, Tr2) can be composed of two transistors of different types. The gate of the N-type transistor of transmission gate Tr1 can be electrically connected to the first scan control terminal U2D, and the gate of the P-type transistor of transmission gate Tr1 can be electrically connected to the second scan control terminal D2U. The gate of the N-type transistor of transmission gate Tr2 can be electrically connected to the second scan control terminal D2U, and the gate of the P-type transistor of transmission gate Tr1 can be electrically connected to the first scan control terminal U2D.

[0171] In another alternative embodiment, Figure 27 This is a schematic diagram of another driving circuit provided in an embodiment of the present invention, such as... Figure 27 As shown, when the drive output terminal OUT of the same shift register unit 31 is multiplexed as a shift output terminal, the drive output terminal OUT of the i-th stage shift register unit is electrically connected to the first input terminal IN1 of the (i+n)-th stage shift register unit, and the drive output terminal OUT of the (i+n)-th stage shift register unit is electrically connected to the second input terminal IN2 of the i-th stage shift register unit. Thus, when performing a forward scan of each row of pixels, the effective pulse time of the gate drive signal output by the i-th stage shift register unit is earlier than the effective pulse time of the gate drive signal output by the (i+n)-th stage shift register unit; conversely, when performing a reverse scan of each row of pixels, the effective pulse time of the gate drive signal output by the (i+n)-th stage shift register unit is earlier than the effective pulse time of the gate drive signal output by the i-th stage shift register unit.

[0172] It is understood that when each shift register unit includes m drive output terminals, provided that the gate drive signals output by each drive output terminal of each shift register unit are shifted sequentially, the second input terminal of the i-th shift register unit can be any drive output terminal of the (i+n)-th shift register unit. This embodiment of the invention does not specifically limit this. In an optional embodiment, the second input terminal IN2 of the i-th shift register unit can be electrically connected to the m-th drive output terminal OUT of the (i+n)-th shift register unit.

[0173] Optional, Figure 28 This is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of the present invention, as shown below. Figure 28 As shown, the shift register unit also includes a first scan control terminal U2D, a second scan control terminal D2U, a second input terminal IN2, a second reset terminal D, and an input module 360B. The first scan control signal u2d of the first scan control terminal U2D and the second scan control signal d2u of the second scan control terminal D2U have opposite polarities. The input module 360B is electrically connected between the first input terminal IN1 and the first control module 310B. The input module 360B is also electrically connected to the first scan control terminal, the second scan control terminal, and the second input terminal, respectively. The input module 360B is used to control the first scan control signal u2d to be provided to the first control module 310B when the first input signal Vin1 of the first input terminal IN1 is at an active level, and to control the second scan control signal d2u to be provided to the first control module 310B when the second input signal Vin2 of the second input terminal IN2 is at an active level.

[0174] Specifically, during forward scanning of each row of pixels, when the first input signal Vin1 at the first input terminal IN1 is at an active level, it can control the active level of the first scan control signal u2d to be provided to the first control module 310B. When the second input signal Vin2 at the second input terminal IN2 is at an active level, it can control the inactive level of the second scan control signal d2u to be provided to the first control module 310B. This allows the first control module 310B to transmit the active level of the first scan control signal u2d or the inactive level of the second scan control signal d2u to the second node N2 under the control of the clock signal CKA at the clock signal terminal A. Conversely, when performing reverse scanning on each row of pixels, when the second input signal Vin2 of the second input terminal IN2 is at an active level, it can control the active level of the second scan control signal d2u to be provided to the first control module 310B. When the first input signal Vin1 of the first input terminal IN1 is at an active level, it can control the inactive level of the first scan control signal u2d to be provided to the first control module 310B. This allows the first control module 310B to transmit the inactive level of the first scan control signal u2d or the active level of the second scan control signal d2u to the second node N2 under the control of the clock signal CKA of the clock signal terminal A. Thus, by setting the first scan control terminal U2D, the second scan control terminal D2U, the second input terminal IN2, and the input module 360B in the shift register unit 31, the input module 360B can selectively provide signals to the latch module 310A, preventing the signals output by the cascaded shift register units 31 from interfering with each other.

[0175] In an exemplary embodiment, the input module 360B may include a first input transistor M61 and a second input transistor M62. The gate of the first input transistor M61 may be electrically connected to the first input terminal IN1, the first electrode of the first input transistor M61 may be electrically connected to the first scan control terminal U2D, and the second electrode of the first input transistor M61 may be electrically connected to the first control module 310B. The gate of the second input transistor M62 may be electrically connected to the second input terminal IN2, the first electrode of the second input transistor M62 may be electrically connected to the second scan control terminal D2U, and the second electrode of the second input transistor M62 may be electrically connected to the first control module 310B. At this time, the first input signal Vin1 of the first input terminal IN1 can control the first input transistor M61 to turn on or off, so that when the first input signal Vin1 of the first input terminal IN1 controls the first input transistor M61 to turn on, the first scan control signal u2d of the first scan control terminal U2D can be provided to the first control module 310B; the second input signal Vin2 of the second input terminal IN2 can control the second input transistor M62 to turn on or off, so that when the second input signal Vin2 of the second input terminal IN2 controls the second input transistor M62 to turn on, the second scan control signal d2u of the second scan control terminal D2U can be provided to the first control module 310B. The first input transistor M61 and the second input transistor M62 can be N-type transistors or P-type transistors, and can be set according to actual needs; this embodiment of the invention does not specifically limit this.

[0176] Continue to refer to Figure 28 The reset module 330B is also electrically connected to the second reset terminal D, the first scan control terminal U2D, and the second scan control terminal D2U, respectively. The reset module 330B is used to control the first reset signal CKC of the first reset signal terminal C to be provided to the first node N1 when the first scan control signal u2d is at an effective level, and to control the second reset signal CKD of the second reset signal terminal D to be provided to the first node N1 when the second scan control signal d2u is at an effective level. In particular, when performing forward scanning on each pixel, the potential of the first node N1 can be kept consistent with the first reset signal CKC, and when performing reverse scanning on each pixel, the potential of the first node N1 can be kept consistent with the second reset signal CKD. Thus, by electrically connecting the reset module 330B to the second reset terminal D, the first scan control terminal U2D, and the second scan control terminal D2U respectively, the reset module 330B can select the reset time of the first node N1 under the control of the first reset terminal C, the second reset terminal D, the first scan control terminal U2D, and the second scan control terminal D2U. This allows the first node N1 to be reset during both the forward and reverse scan processes, ensuring the accuracy of the potential of the first node N1. This, in turn, helps to improve the accuracy of the gate drive signal output by the shift register unit 31.

[0177] In one exemplary embodiment, reference continues to... Figure 28 The reset module 330B may include a first reset transistor M31 and a second reset transistor M32. The gate of the first reset transistor M31 may be electrically connected to the first scan control terminal U2D, the first terminal of the first reset transistor M31 may be electrically connected to the first reset terminal C, and the second terminal of the first reset transistor M31 may be electrically connected to the first node N1. The gate of the second input transistor M62 may be electrically connected to the second scan control terminal D2U, the first terminal of the second input transistor M62 may be electrically connected to the second reset terminal D, and the second terminal of the second input transistor M62 may be electrically connected to the first node N1. At this time, the first scan control signal u2d of the first scan control terminal U2D can control the first reset transistor M31 to be turned on or off, so that when the first scan control signal u2d of the first scan control terminal U2D controls the first reset transistor M31 to be turned on, the first reset signal CKC of the first reset terminal C can be transmitted to the first node N1; the second scan control signal d2u of the second scan control terminal D2U can control the second reset transistor M32 to be turned on, so that when the second scan control signal d2u of the second scan control terminal D2U controls the second reset transistor M32 to be turned on, the second reset signal CKD of the second reset terminal D can be transmitted to the first node N1. The first reset transistor M31 and the second reset transistor M32 can be N-type transistors or P-type transistors, and can be set according to actual needs. This embodiment of the invention does not specifically limit this.

[0178] Based on the same inventive concept, embodiments of the present invention also provide a display device, which includes the display panel provided in the embodiments of the present invention. Therefore, this display device possesses the technical features of the display panel and its driving method provided in the embodiments of the present invention, and can achieve the beneficial effects of the display panel provided in the embodiments of the present invention. Similarities can be found in the above description of the display panel provided in the embodiments of the present invention, and will not be repeated here.

[0179] For example, Figure 29 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention, such as... Figure 29 As shown, the display device 200 includes the display panel 100 provided in this embodiment of the invention. The display device 200 provided in this embodiment of the invention can be any electronic product with display function, including but not limited to the following categories: mobile phones, televisions, laptops, desktop monitors, tablet computers, digital cameras, smart bracelets, smart glasses, in-vehicle displays, medical devices, industrial control equipment, touch interactive terminals, etc., and this embodiment of the invention does not make any special limitations on these categories.

[0180] It should be understood that the working process of the various forms of pixel circuits shown above can be used to reorder, add, or delete stages. For example, the stages in the working process of the pixel circuits described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and no limitation is made herein.

[0181] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display panel, characterized in that, comprising: a drive circuit, a plurality of scan lines, and a plurality of pixels arranged in an array; the pixels comprise at least one switching transistor; the gates of the switching transistors of at least part of the pixels located in the same row are electrically connected to the same one of the scan lines; the drive circuit comprises a plurality of stages of shift register units; the i-th stage of the shift register unit is cascaded with the (i+n)-th stage of the shift register unit; n is a positive integer greater than or equal to 2, and i is a positive integer; each stage of the shift register units is also electrically connected to each of the scan lines respectively; each stage of the shift register units respectively provides a gate drive signal to each of the scan lines, and the effective pulses of the gate drive signals received by the respective scan lines are shifted sequentially; wherein, the width T0 of the effective pulse of the gate drive signal satisfies T0>(Th+k*Th); 0<k≤(n-1), Th=1 / (F*L), F is the refresh frequency of the display panel, and L is the number of rows of the pixels; the shift amount of the effective pulses of the gate drive signals output by any two adjacent stages of the shift register units is greater than or equal to Th; the shift register unit comprises at least a first input terminal, a clock signal terminal, a shift output terminal, at least one drive output terminal, and at least one output control terminal corresponding to at least one of the drive output terminals; the shift register unit is configured to control the shift signal output by the shift output terminal and the gate drive signal output by the drive output terminal in response to a clock signal received by the clock signal terminal, a first input signal received by the first input terminal, and an output control signal received by the output control terminal; wherein, the shift output terminal of the i-th stage of the shift register unit is electrically connected to the first input terminal of the (i+n)-th stage of the shift register unit; each of the drive output terminals of each stage of the shift register units is electrically connected to each of the scan lines respectively; when each stage of the shift register unit comprises one of the drive output terminals, the overlapping time of the effective pulses of the gate drive signals output by any two adjacent stages of the shift register units is k*Th.

2. The display panel according to claim 1, characterized in that, the effective pulse time of the gate drive signal output by the i-th stage of the shift register unit and the effective pulse time of the gate drive signal output by the (i+n)-th stage of the shift register unit do not overlap.

3. The display panel according to claim 1, characterized in that, in the same shift register unit, the effective pulse of the clock signal and the effective pulse of the output control signal are shifted sequentially, and the effective pulse time of the clock signal and the effective pulse time of the output control signal do not overlap.

4. The display panel according to claim 1, characterized in that, the width of the effective pulse of the clock signal and the width of the effective pulse of the output control signal are both equal to the width of the effective pulse of the gate drive signal.

5. The display panel according to claim 1, characterized in that, the effective pulse time of the clock signal received by the i-th stage of the shift register unit and the effective pulse time of the clock signal received by the (i+n)-th stage of the shift register unit do not overlap; the effective pulse time of the output control signal received by the i-th stage of the shift register unit and the effective pulse time of the output control signal received by the (i+n)-th stage of the shift register unit do not overlap.

6. The display panel according to claim 1, characterized in that, The multiple levels of shift register units constitute multiple shift register unit groups; each shift register unit group includes n levels of shift register units that are not connected to each other and are adjacent to each other; The effective pulse times of the clock signal received by each level of the shift register unit in the same shift register unit group are shifted sequentially; The effective pulse times of the output control signal received by each level of the shift register unit in the same shift register unit group are shifted sequentially.

7. The display panel according to claim 6, characterized in that, The effective pulse times of the gate drive signals output by each level of the shift register unit in the same shift register unit group overlap.

8. The display panel according to claim 7, characterized in that, The effective pulse times of the output control signals received by each level of the shift register unit in the same shift register unit group overlap.

9. The display panel according to claim 1, characterized in that, The clock signal provided to the shift register unit of the i-th stage is multiplexed into the clock signal provided to the shift register unit of the (i+2*n)-th stage; The output control signal provided to the shift register unit of the i-th stage is multiplexed into the output control signal provided to the shift register unit of the (i+2*n)-th stage.

10. The display panel according to claim 6, characterized in that, When each shift register unit includes m drive output terminals, the effective pulses of the gate drive signals output by each drive output terminal of the same shift register unit are shifted sequentially; m is a positive integer greater than or equal to 2. In the same shift register unit, the drive output terminal of the j-th valid pulse that outputs the gate drive signal is the j-th drive output terminal; j is a positive integer less than or equal to m; In the same shift register unit, the overlap time between the effective pulse of the gate drive signal output by the j-th drive output terminal and the effective pulse of the gate drive signal output by the (j+1)-th drive output terminal is k*Th.

11. The display panel according to claim 10, characterized in that, The overlap time between the effective pulse of the gate drive signal output from the m-th drive output terminal in the i-th stage shift register unit and the effective pulse of the gate drive signal output from the first drive output terminal in the (i+1)-th stage shift register unit is k*Th.

12. The display panel according to claim 10, characterized in that, When m≤n, the effective pulse times of the gate drive signals output by each drive output terminal of the same shift register unit overlap.

13. The display panel according to claim 12, characterized in that, The effective pulse times of the output control signals received by the same shift register unit overlap.

14. The display panel according to claim 10, characterized in that, When m>n, the effective pulse times of the gate drive signals output by each of the drive output terminals from the first drive output terminal to the nth drive output terminal of the same shift register unit overlap. In the same shift register unit, the effective pulse time of the gate drive signal output by the first drive output terminal does not overlap with the effective pulse time of the gate drive signal output by the (n+1)th drive output terminal.

15. The display panel according to claim 14, characterized in that, In the same shift register unit, the output control terminal corresponding to the j-th drive output terminal is the j-th output control terminal; The effective pulse times of the output control signals received by each of the output control terminals from the first output control terminal to the nth output control terminal of the same shift register unit overlap. In the same shift register unit, the effective pulse time of the output control signal received by the first output control terminal does not overlap with the effective pulse time of the output control signal received by the (n+1)th output control terminal.

16. The display panel according to claim 1, characterized in that, The shift register unit further includes a latch module, at least one level conversion module corresponding to at least one of the drive output terminals, and at least one output module corresponding to at least one of the level conversion modules; within the same shift register unit: The latch module is electrically connected to the clock signal terminal, the first input terminal, and the shift output terminal, respectively; the latch module is used to respond to the clock signal of the clock signal terminal, latch the first input signal of the first input terminal, and control the shift signal output by the shift output terminal. The level conversion module is electrically connected to the output control terminal, the shift output terminal, and the output module, respectively. The level conversion module is used to control the voltage of the gate drive signal provided to the output module in response to the output control signal and the shift signal of the output control terminal. The output module is also electrically connected to the drive output terminal; the output module is used to control the polarity of the gate drive signal output by the drive output terminal.

17. The display panel according to claim 16, characterized in that, The shift register unit further includes a first scan control terminal, a second scan control terminal, a second input terminal, and an input module; the first scan control signal of the first scan control terminal and the second scan control signal of the second scan control terminal have opposite polarities. The input module is electrically connected between the first input terminal and the latch module, and is also electrically connected to the first scan control terminal, the second scan control terminal, and the second input terminal respectively; the input module is used to control the first input signal of the first input terminal to be provided to the latch module when the first scan control signal is at an active level, and to control the second input signal of the second input terminal to be provided to the latch module when the second scan control signal is at an active level. The second input terminal of the shift register unit of the i-th stage is electrically connected to the shift output terminal of the shift register unit of the (i+n)-th stage.

18. The display panel according to claim 1, characterized in that, In the same shift register unit, when the shift register unit includes m drive output terminals, the drive output terminal that outputs the effective pulse of the gate drive signal is the j-th drive output terminal; m is a positive integer, and j is a positive integer less than or equal to m; In the same shift register unit, the m-th drive output terminal is multiplexed as the shift output terminal.

19. The display panel according to claim 18, characterized in that, The shift register unit further includes a first reset terminal, a first voltage terminal, a second voltage terminal, a first control module, a second control module, a reset module, and at least one output module corresponding to at least one drive output terminal; The reset module is electrically connected to the first reset terminal, the first control module, and the second control module, respectively, and the reset module is electrically connected to the first control module and the second control module at the first node; the reset module is used to control the signal of the first node in response to the first reset signal of the first reset terminal. The first control module is electrically connected to the first input terminal, the clock signal terminal, and the output module, respectively, and the first control module and the output module are electrically connected to the second node; The first control module is used to control the signal of the second node in response to the first input signal of the first input terminal, the clock signal of the clock signal terminal, and the signal of the first node; The second control module is electrically connected to the first voltage terminal, the second voltage terminal, the first node, the second node and the output module respectively, and the second control module and the output module are electrically connected to the third node; The second control module is used to control the first voltage signal of the first voltage terminal to be provided to the third node when the signal of the first node is at an active level, and to control the second voltage signal of the second voltage terminal to be provided to the third node when the signal of the second node is at an active level. The output module is also electrically connected to the output control terminal, the first voltage terminal, and the drive output terminal; the output module is used to control the gate drive signal output by the drive output terminal in response to the output control signal of the output control terminal, the first voltage signal of the first voltage terminal, the signal of the second node, and the signal of the third node. In the same shift register unit, the effective pulses of the clock signal, the output control signal, and the first reset signal are shifted sequentially, and the effective pulse times of the clock signal, the output control signal, and the first reset signal do not overlap.

20. The display panel according to claim 19, characterized in that, The shift register unit further includes a first scan control terminal, a second scan control terminal, a second input terminal, a second reset terminal, and an input module; the first scan control signal of the first scan control terminal has the opposite polarity to the second scan control signal of the second scan control terminal; The input module is electrically connected between the first input terminal and the first control module. The input module is also electrically connected to the first scan control terminal, the second scan control terminal, and the second input terminal, respectively. The input module is used to control the first scan control signal to be provided to the first control module when the first input signal at the first input terminal is at a valid level, and to control the second scan control signal to be provided to the first control module when the second input signal at the second input terminal is at a valid level. The reset module is also electrically connected to the second reset terminal, the first scan control terminal, and the second scan control terminal respectively; the reset module is used to control the first reset signal of the first reset terminal to be provided to the first node when the first scan control signal is at an active level, and to control the second reset signal of the second reset terminal to be provided to the first node when the second scan control signal is at an active level. The second input terminal of the shift register unit of the i-th stage is electrically connected to the m-th drive output terminal of the shift register unit of the (i+n)-th stage.

21. A display device, characterized in that, include: The display panel according to any one of claims 1-20.

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