Clock transmission circuit and semiconductor device

Abstract

The present application relates to a clock transmission circuit and a semiconductor device. A clock transmission circuit includes a clock driver circuit adapted to transmit a clock and adjust a driving force thereof in response to a boost signal, a low-pass filter circuit adapted to receive the clock and output an initialization signal, and a boost signal generation circuit adapted to generate the boost signal, which is activated in response to the initialization signal and deactivated in response to the clock.

Description

Technical Field

[0001] Embodiments of the present invention relate to clock transmission circuits for transmitting clocks in various integrated circuits. Background Technology

[0002] Various integrated circuits, including memory devices, are being developed to have high capacity and operate at high speeds with low power consumption. Semiconductor devices are being designed to operate in sync with increasingly higher clock frequencies to achieve high speeds.

[0003] Today, clock frequencies are increasingly higher than gigahertz (GHz), and in order for semiconductor devices to operate accurately in sync with these high-frequency clocks, the clocks themselves must be extremely precise. In other words, if the clock has significant jitter or a duty cycle deviating from 50:50, the timing of the semiconductor devices operating in sync with the clock will also be off, making it impossible to guarantee stable circuit operation.

[0004] Clock transmission circuits are used to transmit clocks within semiconductor devices or between semiconductor devices, and the clocks transmitted by the clock transmission circuits are required to be of high quality. Summary of the Invention

[0005] Embodiments of the present invention provide a clock transmission circuit capable of transmitting high-quality clocks.

[0006] According to an embodiment of the present invention, a clock transmission circuit includes: a clock driver circuit adapted to transmit a clock and adjust its driving force in response to a boost signal; a low-pass filter circuit adapted to receive a clock and output an initialization signal; and a boost signal generation circuit adapted to generate a boost signal, the boost signal being activated in response to the initialization signal and deactivated in response to a clock.

[0007] According to another embodiment of the present invention, a clock transmission circuit includes: a clock driver circuit adapted to transmit a clock; and a driving force control circuit adapted to increase the rising transition driving force of the output of the clock driver circuit in a low-frequency segment of the clock and decrease the rising transition driving force in a high-frequency segment of the clock.

[0008] According to another embodiment of the present invention, a semiconductor device includes: a clock driver configured to drive an input clock to output an output clock, the input clock being held high in a reset segment, held low in a preamble segment, and toggled in a postamble segment, and repeating a set of segments including the reset segment, the preamble segment, and the postamble segment; a low-pass filter configured to generate an initialization signal that toggles when the input clock toggles at a low frequency and toggles at both ends of the reset segment according to the transition of the input clock; and a boost circuit configured to enable a boost signal according to the rising edge of the initialization signal and disable the boost signal according to the rising edge of the input clock in the postamble segment, wherein the clock driver is further configured to increase its driving force in response to the enabled boost signal to at least accelerate the initial transition of the output clock from a logic low level to a logic high level in the postamble segment. Attached Figure Description

[0009] Figure 1 This is a block diagram illustrating a clock transmission circuit according to an embodiment of the present invention.

[0010] Figure 2 This illustrates an embodiment of the present invention. Figure 1 The timing diagram of the operation.

[0011] Figure 3 This is a block diagram illustrating a clock transmission circuit according to another embodiment of the present invention.

[0012] Figure 4 This illustrates an embodiment of the present invention. Figure 3 The timing diagram shown illustrates the high-speed operation of the clock transmission circuit.

[0013] Figure 5 This illustrates an embodiment of the present invention. Figure 3 The timing diagram shows the low-speed operation of the clock transmission circuit.

[0014] Figure 6 This is a block diagram illustrating a clock transmission circuit according to yet another embodiment of the present invention. Detailed Implementation

[0015] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Throughout this disclosure, similar reference numerals refer to similar parts throughout the various figures and embodiments of the invention.

[0016] Figure 1This is a block diagram illustrating a clock transmission circuit 100 according to an embodiment of the present invention. Figure 2 This illustrates an embodiment of the present invention. Figure 1 The timing diagram of the operation.

[0017] Reference Figure 1 The clock transmission circuit 100 may include two inverters 101 and 103 connected in series. The clock transmission circuit 100 can directly transmit the clock input to the input node IN to the output node OUT.

[0018] Figure 2 The waveforms of the input node IN and output node OUT of the clock transmission circuit 100 are shown. Figure 2 The diagram shows the actual analog waveform and the digital waveform of the output node OUT. It can be seen that the digital waveform changes to "high" or "low" depending on whether the voltage level of the analog waveform is higher or lower than VCC / 2.

[0019] Reference Figure 2 When the clock is deactivated at a "low" level and then activated and toggled, the pulse width WA of the first clock pulse can be narrower than the pulse widths WB of the others. This is because the first clock pulse starts swinging from a voltage level of 0, while the second pulse starts swinging from a ΔV level higher than 0.

[0020] In other words, when the clock is deactivated and then activated, the swing width of the first pulse can be different from the swing width of the second and subsequent pulses, such that the pulse width WA of the first pulse is smaller than the pulse width WB of the second and subsequent pulses.

[0021] Figure 3 This is a block diagram illustrating a clock transmission circuit 300 according to another embodiment of the present invention.

[0022] Reference Figure 3 The clock transmission circuit 300 may include a clock driver circuit 310 and a drive force control circuit 350. The clock transmission circuit 300 can be used to transmit clocks within an integrated circuit chip or to transmit clocks between different integrated circuit chips.

[0023] Clock driver circuit 310 can be used to transmit the input clock CLK_IN to the output clock CLK_OUT. The driving force of clock driver circuit 310 can be adjusted based on the boost signal BOOST. Specifically, when the boost signal BOOST is activated, the rising transition driving force of clock driver circuit 310 from a "low" level to a "high" level can be strengthened. Clock driver circuit 310 may include a first inverter 320 for inverting and outputting the input clock CLK_IN, and a second inverter 330 for inverting the output of the first inverter 320 and outputting the output clock CLK_OUT. The sink current of the first inverter 320 can be adjusted based on the boost signal BOOST.

[0024] The first inverter 320 may include PMOS transistors 321 and 322 and NMOS transistors 323, 324, 325, and 326. PMOS transistor 321 can source the operating current of the first inverter 320 by receiving a ground voltage VSS at its gate and remaining in a sustaining on state. NMOS transistor 324 can sink the operating current of the first inverter 320 by receiving a power supply voltage VCC at its gate and remaining in a sustaining on state. PMOS transistors 322 and NMOS transistor 323 can invert the input clock CLK_IN and output it to the output node of the first inverter 320. NMOS transistors 325 and 326 can be turned on when the boost signal BOOST is activated at a "high" level to sink the operating current of the first inverter 320, and can be turned off when the boost signal BOOST is deactivated at a "low" level. When the boost signal BOOST is activated and NMOS transistors 325 and 326 are turned on, the voltage level transition from "high" to "low" at the output node of the first inverter 320 can be accelerated. Consequently, the output clock CLK_OUT from the second inverter 330 can be accelerated from "low" to "high." That is, the rise of the output clock CLK_OUT can be accelerated.

[0025] The drive force control circuit 350 can generate a boost signal BOOST to increase the rising transition drive force of the clock driver circuit 310 in the low-frequency range of the input clock CLK_IN, and decrease the rising transition drive force of the clock driver circuit 310 in the high-frequency range of the input clock CLK_IN. The drive force control circuit 350 may include a low-pass filter circuit 360 and a boost signal generation circuit 370.

[0026] The low-pass filter circuit 360 can receive an input clock CLK_IN and output an initialization signal RST. As the frequency of the input clock CLK_IN increases, the low-pass filter circuit 360 may hesitate to activate the initialization signal RST. The low-pass filter circuit 360 may include four inverters 361, 362, 363, and 364 connected in series. Among them, inverter 363 may include a PMOS transistor 365, resistors 366 and 367, and an NMOS transistor 368. When the input of inverter 363 is at a "low" level, PMOS transistor 365 can drive the output RST_N of inverter 363 to a "high" level, while when the input of inverter 363 is at a "high" level, NMOS transistor 368 can drive the output RST_N of inverter 363 to a "low" level. Resistors 366 and 367 may interfere with NMOS transistor 368 driving the output RST_N of inverter 363 to a "low" level. When the on-time of NMOS transistor 368 is short due to resistor interference, that is, when the input clock CLK_IN is at a high frequency, inverter 363 may have difficulty driving output RST_N to a "low" level. Therefore, when the input clock CLK_IN has a high frequency, low-pass filter circuit 360 may have difficulty driving the initialization signal RST generated by inverting output RST_N to a "high" level.

[0027] The boost signal generation circuit 370 can activate the boost signal BOOST in response to the activation of the initialization signal RST, and deactivate the boost signal BOOST in response to the rising edge of the input clock CLK_IN. Since the initialization signal RST cannot be activated during the high-frequency segment of the input clock CLK_IN, the boost signal BOOST can remain inactive during this segment. Furthermore, during the low-frequency segment of the input clock CLK_IN, the boost signal BOOST can be activated in response to the activation of the initialization signal RST to increase the rising drive force of the clock driver circuit 310, and the boost signal BOOST can be deactivated in response to the rising edge of the input clock CLK_IN. Ultimately, the boost signal BOOST can be generated such that the clock driver circuit 310 strongly drives the rising edge of the output clock CLK_OUT during the low-frequency segment of the input clock CLK_IN.

[0028] The boost signal generation circuit 370 can be formed by a D flip-flop. The power supply voltage VCC, which is a signal fixed at a "high" level, can be input to the input terminal D of the D flip-flop, and the input clock CLK_IN can be input to the clock terminal. The boost signal can be output from the inverting output terminal QB. Furthermore, the D flip-flop can be initialized in response to the initialization signal RST. The D flip-flop can activate the boost signal BOOST to a "high" level in response to the activation of the initialization signal RST, and deactivate the boost signal BOOST to a "low" level in response to the rising edge of the input clock CLK_IN.

[0029] Figure 4 This illustrates an embodiment according to the present disclosure. Figure 3 The timing diagram shows the high-speed operation of the clock transmission circuit 300.

[0030] Reference Figure 4 The input clock CLK_IN can remain high before time "401", and this segment can be a reset segment. From time "401" to time "403", the input clock CLK_IN can remain in an inactive state at a low level. This segment can be called the preamble segment, and from time "403" to time "405", which is the time after the input clock CLK_IN has toggled 5 times, the input clock CLK_IN can remain in an inactive state at a low level, and this segment can be a postamble segment. After the postamble segment, the segment where the input clock CLK_IN remains high from time "405" to time "407" can be a reset segment. The segment from time "407" to the time when the input clock CLK_IN toggles again can be a preamble segment. There exists a preamble segment in which the input clock CLK_IN is deactivated to a "low" level before the input clock CLK_IN toggles, and a postamble segment in which the input clock CLK_IN is deactivated to a "low" level after the input clock CLK_IN toggles. Furthermore, there is a reset segment between the postamble and the preamble segment where the input clock remains "high".

[0031] The output signal RST_N of the inverter 363 inside the low-pass filter circuit 360 is obtained by delaying and inverting the input clock CLK_IN. Resistors 366 and 367 of the inverter 363 can interfere to drive the output signal RST_N to a "low" level. Figure 4 As can be seen, the signal RST_N maintains the delayed and inverted form of the input clock CLK_IN. However, in the high-frequency range where the input clock CLK_IN toggles rapidly, the signal RST_N does not completely transition to the "low" level. Instead, the level of the signal RST_N slowly decreases and then rises again.

[0032] The initialization signal RST can have a level obtained by inverting the output signal RST_N of inverter 363, and the output signal RST_N of inverter 363 may not transition to a "low" level during the segment where the input clock CLK_IN toggles rapidly. Therefore, it can be seen that the initialization signal RST is not activated to a "high" level during the segment where the input clock CLK_IN toggles rapidly.

[0033] The boost signal BOOST can be activated in response to the activation of the initialization signal RST and deactivated in response to the rising edge of the input clock CLK_IN. There is a slight delay between the activation of the initialization signal RST and the activation of the boost signal BOOST, which may be due to the flip-flop reset delay of the D flip-flop in the boost signal generation circuit 370. Furthermore, there is a slight delay between the rising edge of the input clock CLK_IN and the deactivation of the boost signal BOOST, which is due to the CLK-to-QB delay of the D flip-flop in the boost signal generation circuit 370.

[0034] The boost signal BOOST can be activated to a "high" level during the rising segment of the first pulse of the input clock CLK_IN during the toggle segment of the input clock. Therefore, the clock driver circuit 310 can powerfully drive the rising segment of the first pulse of the output clock CLK_OUT, resulting in a pulse width of the first pulse of the output clock CLK_OUT that is shorter than the width of other pulses.

[0035] Figure 5 This illustrates an embodiment according to the present disclosure. Figure 3 The timing diagram for the low-speed operation of the clock transmission circuit 300 is shown.

[0036] Reference Figure 5 The preamble segment of the input clock CLK_IN, starting at time "501", can end at time "503", and the input clock CLK_IN can begin to toggle from time "503". Even when the input clock CLK_IN toggles, its pulse width can be very wide because it toggles at a low frequency. Therefore, even during the toggling segment of the input clock CLK_IN, the output signal RST_N of the inverter 363 inside the low-pass filter circuit 360 can transition to a "low" level. Consequently, the initialization signal RST, generated by inverting the output signal RST_N of the inverter 363, can be activated several times during the toggling segment of the input clock CLK_IN.

[0037] The boost signal BOOST can be repeatedly activated in response to the activation of the initialization signal RST and deactivated in response to the rising edge of the input clock CLK_IN. Since the boost signal BOOST is activated at a "high" level for each rising segment of the input clock CLK_IN, the clock driver circuit 310 can powerfully drive the rising of the first to fourth pulses of the output clock CLK_OUT. The clock driver circuit 310 can also powerfully drive the rising of the output clock CLK_OUT whenever it toggles.

[0038] During low-speed operation, the pulse width of the output clock CLK_OUT can vary very little depending on the activation / deactivation of the boost signal BOOST, and the pulse width variation is insensitive during low-speed operation with a sufficiently wide pulse width. Therefore, such variation in pulse width will not cause any problems to the operational stability of the system including the clock transmission circuit 300.

[0039] Figure 6 This is a block diagram illustrating a clock transmission circuit 600 according to yet another embodiment of the present invention.

[0040] Reference Figure 6 The clock transmission circuit 600 may include a clock driver circuit 610 and a driving force control circuit 650.

[0041] Clock driver circuit 610 can be used to transmit input clock CLK_IN as output clock CLK_OUT. The driving force of clock driver circuit 610 can be adjusted based on boost signal BOOST. Specifically, when boost signal BOOST is activated, the rising transition driving force of clock driver circuit 610 from "low" level to "high" level can be strengthened. Clock driver circuit 610 may include a first inverter 620 for inverting and outputting input clock CLK_IN, and a second inverter 630 for inverting the output of first inverter 620 and outputting output clock CLK_OUT. Unlike Figure 3 The clock driver circuit 310 shown can adjust the pull-up current of the second inverter 630 based on the boost signal BOOST.

[0042] The second inverter 630 may include PMOS transistors 631, 632, 633, and 634, and NMOS transistors 635 and 636. PMOS transistor 631 can receive a ground voltage VSS at its gate and remain on to pull the operating current of the second inverter 630. NMOS transistor 636 can receive a power supply voltage VCC at its gate and remain on to sink the operating current of the second inverter 630. PMOS transistors 634 and 635 can invert the output of the first inverter 620 and output the output clock CLK_OUT. PMOS transistors 632 and 633 can be turned on when the boost signal BOOST is activated to a "low" level to pull the operating current of the second inverter 630, and can be turned off when the boost signal BOOST is deactivated to a "high" level. When the boost signal BOOST is activated and PMOS transistors 632 and 633 are on, the transition of the output clock CLK_OUT from a "low" level to a "high" level from the second inverter 630 can be accelerated. That is, the rise of the output clock (CLK_OUT) can become faster.

[0043] The drive force control circuit 650 can generate a boost signal BOOST to increase the rising transition drive force of the clock driver circuit 610 in the low-frequency range of the input clock CLK_IN, and decrease the rising transition drive force of the clock driver circuit 610 in the high-frequency range of the input clock CLK_IN. The drive force control circuit 650 may include a low-pass filter circuit 660 and a boost signal generation circuit 670.

[0044] The low-pass filter circuit 660 can receive an input clock CLK_IN and output an initialization signal RST. As the frequency of the input clock CLK_IN increases, the low-pass filter circuit 660 may have difficulty activating the initialization signal RST. The low-pass filter circuit 660 may include four inverters 661, 662, 663, and 664 connected in series. Among them, inverter 663 may include a PMOS transistor 665, resistors 666 and 667, and an NMOS transistor 668. When the input of inverter 663 is at a "low" level, the PMOS transistor 665 can drive the output RST_N of inverter 663 to a "high" level, while when the input of inverter 663 is at a "high" level, the NMOS transistor 668 can drive the output RST_N of inverter 663 to a "low" level. Resistors 666 and 667 can interfere with the NMOS transistor 668 driving the output RST_N of inverter 663 to a low level. When the on-time of the NMOS transistor 668 is short due to resistor interference, that is, when the input clock CLK_IN has a high frequency, the output RST_N of the inverter 663 may be difficult to drive to a "low" level. Therefore, when the input clock CLK_IN has a high frequency, the low-pass filter circuit 660 may have difficulty driving the initialization signal RST to a "high" level, which is generated by inverting the output RST_N of the inverter 663.

[0045] The boost signal generation circuit 670 can activate the boost signal BOOST to a "low" level in response to the activation of the initialization signal RST, and deactivate the boost signal BOOST to a "high" level in response to the rising edge of the input clock CLK_IN. Since the initialization signal RST is not activated during the high-frequency segment of the input clock CLK_IN, the boost signal BOOST can remain inactive during this segment. Furthermore, during the low-frequency segment of the input clock CLK_IN, the boost signal BOOST can be activated in response to the activation of the initialization signal RST to increase the rising drive force of the clock driver circuit 610, and the boost signal BOOST can be deactivated in response to the rising edge of the input clock CLK_IN. Ultimately, the boost signal BOOST can be generated such that the clock driver circuit 610 strongly drives the rising edge of the output clock CLK_OUT during the low-frequency segment of the input clock CLK_IN.

[0046] The boost signal generation circuit 670 can be formed by a D flip-flop. The power supply voltage VCC, which is a signal fixed at a "high" level, can be input to the input terminal D of the D flip-flop, and the input clock CLK_IN can be input to the clock terminal. The boost signal can be output from the output terminal Q. Furthermore, the D flip-flop can be initialized in response to the initialization signal RST. The D flip-flop can activate the boost signal BOOST to a "low" level in response to the activation of the initialization signal RST, and deactivate the boost signal BOOST to a "high" level in response to the rising edge of the input clock CLK_IN.

[0047] Apart from Figure 6 The clock transmission circuit 600 adjusts the driving force of the second inverter 630 of the clock driver circuit 610 based on the boost signal BOOST, except that the activation level of the boost signal BOOST is "low". Figure 6 The clock transmission circuit 600 can be used with Figure 3 The clock transmission circuit 300 operates in the same manner. Therefore, the details regarding... Figure 6 A further detailed description of the clock transmission circuit.

[0048] According to embodiments of the present invention, the quality of the clock transmitted by the clock transmission circuit can be improved.

[0049] Although the invention has been described with reference to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention as defined by the appended claims. Furthermore, these embodiments can be combined to form additional embodiments.

[0050] Cross-references to related applications

[0051] This application claims priority to Korean Patent Application No. 10-2022-0063483, filed on May 24, 2022, the entire contents of which are incorporated herein by reference.

Claims

1. A clock transmission circuit, the clock transmission circuit comprising: A clock driver circuit adapted to transmit a clock and adjust its driving force by adjusting the amount of current flowing through the clock driver circuit based on a boost signal. A low-pass filter circuit adapted to receive the clock and output an initialization signal; as well as A boost signal generation circuit adapted to generate the boost signal, which is activated in response to the initialization signal and deactivated in response to the clock.

2. The clock transmission circuit according to claim 1, wherein, The boost signal generation circuit activates the boost signal in response to the activation of the initialization signal, and deactivates the boost signal in response to the rising edge of the clock.

3. The clock transmission circuit according to claim 1, wherein, The clock driver circuit adjusts the driving force by increasing the amount of current flowing through it when the boost signal is activated.

4. The clock transmission circuit according to claim 1, wherein, As the clock frequency increases, the low-pass filter circuit blocks the activation of the initialization signal.

5. The clock transmission circuit according to claim 4, in, The boost signal generation circuit includes a D flip-flop, which is adapted to receive a signal fixed at a high level through its input terminal, receive the clock through its clock terminal, and output the boost signal through its inverting output terminal. The activation initialization signal initializes the D flip-flop.

6. The clock transmission circuit according to claim 5, wherein, The clock driver circuit includes: A first inverter, adapted to invert the clock to output a first clock and to increase the sink current in the first inverter when the boost signal is activated; and A second inverter is adapted to invert the first clock to output a second clock.

7. The clock transmission circuit according to claim 4, in, The boost signal generation circuit includes a D flip-flop, which is adapted to receive a signal fixed at a high level through its input terminal, receive the clock through its clock terminal, and output the boost signal through its output terminal. The activation initialization signal initializes the D flip-flop.

8. The clock transmission circuit according to claim 7, wherein, The clock driver circuit includes: A first inverter, adapted to invert the clock to output a third clock; and A second inverter is adapted to invert the third clock to output a fourth clock and to increase the pull-out current within the second inverter when the boost signal is activated.

9. A clock transmission circuit, the clock transmission circuit comprising: A clock driver circuit adapted to transmit a clock. as well as A drive force control circuit is provided, which is adapted to increase the rising transition drive force of the clock driver circuit output in the low-frequency range of the clock, and to decrease the rising transition drive force in the high-frequency range of the clock. The clock driver circuit increases or decreases the rising transition driving force by controlling the amount of operating current within the clock driver circuit.

10. A semiconductor device, the semiconductor device comprising: A clock driver that drives an input clock to output an output clock, the input clock being held high in a reset segment, held low in a preamble segment, and toggled in a postamble segment, and repeating a set of segments including the reset segment, the preamble segment, and the postamble segment; A low-pass filter generates an initialization signal that flips when the input clock flips at a low frequency and changes at both ends of the reset segment according to the transition of the input clock. as well as A boost circuit that enables the boost signal based on the rising edge of the initialization signal and disables the boost signal based on the rising edge of the input clock in the subsequent synchronization code segment. The clock driver further increases its driving force in response to an enabled boost signal, thereby accelerating the initial transition of the output clock from logic low to logic high in the post-synchronization code segment. The clock driver increases the driving force by increasing the amount of current flowing through it when the boost signal is enabled.

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