A radiation hardened dual port 16 transistor memory cell array

Abstract

The application discloses an anti-radiation dual-port 16-tube memory cell array, and belongs to the memory field.The anti-radiation dual-port 16-tube memory cell is of a DICE structure, and the array comprises a left port word line WLLn, a right port word line WLRn, a left port bit line BLLn and BLNLn, and a right port bit line BLRn and BLNRn.Four bit lines of a column of memory cells are arranged in the manner of BLLn\BLRn\BLNLn\BLNRn, BLLn and BLNLn are arranged on the same metal layer M3, BLRn and BLNRn are arranged on the same metal layer M4, and the metal layers M3 and M4 are adjacent metal layers.When a dual-port operation is performed, the adjacent metal layer arrangement of the left and right port bit lines can ensure that the delay difference of the left and right port path signal transmission is small.When one-port write operation is performed and the other port simultaneously performs read operation on the same column and adjacent row of cells, the adjacent metal layer arrangement of the left and right port bit lines can avoid the phenomenon that strong data signals on the write path bit line interfere with weak data signals on the adjacent read path bit line through the coupling capacitor between the metal long conductors, thereby causing read failure.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and in particular to a radiation-resistant dual-port 16-tube memory cell array. Background Technology

[0002] The radiation-hardened dual-port SRAM circuit uses two independent address, data, and control buses, allowing two independent entities (such as two processors) to access it simultaneously. The dual-port memory cell is a DICE structure hardened to resist SEU (Single Event Upset) and contains 16 MOS transistors.

[0003] With the continuous development of semiconductor technology, constantly updated electronic products place higher demands on memory performance, including larger capacity and higher read / write speeds. At the same process node, increased memory capacity means increased chip area. Simultaneously, the increased size of the memory cell array leads to increased parasitic RC impedance of the word lines and bit lines, affecting the read / write speed of the memory array. To reduce signal transmission path impedance, methods typically include increasing decoding layers to shorten word and bit line lengths and appropriately increasing linewidth to reduce parasitic resistance; however, these operations also increase chip area.

[0004] To resolve the trade-off between capacity, speed, and area, at the same process node, area reduction is typically achieved by decreasing the size of memory array devices and the spacing of transmission lines, while still meeting design requirements. However, this approach weakens device driving capability and increases coupling capacitance between adjacent word lines and bit lines on the same layer. This problem is exacerbated for radiation-hardened dual-port 16-cell arrays due to their large number of cells and large array area. When a write operation is performed on one port while a read operation is simultaneously performed on a cell in the same column or adjacent row on the other port, the stronger write data signal is affected by the coupling capacitance between bit lines, causing crosstalk to the weaker read data signal, ultimately leading to read failure or even modifying the value stored in the cell currently being read. Summary of the Invention

[0005] The purpose of this invention is to provide a radiation-resistant dual-port 16-tube memory cell array that resolves the contradiction between storage capacity, access speed and array area without adding extra layers, and avoids bit line signal crosstalk when both ports perform read and write operations simultaneously.

[0006] To address the aforementioned technical problems, this invention provides a radiation-resistant dual-port 16-transistor memory cell array, comprising:

[0007] DICE structure radiation-resistant dual-port 16-transistor memory cell, left port word line WLLn, right port word line WLRn, left port bit lines BLLn and BLNLn, right port bit lines BLRn and BLNRn; where n = 0, 1, 2, 3...;

[0008] The DICE structure radiation-resistant dual-port 16-tube storage unit includes a unit tube for storing data information and a selection gate tube for opening the storage unit.

[0009] The left port bit lines BLLn and BLNLn are used to transmit a pair of opposite data signals during left port operation, and they are connected to the source end of the left port selection gate of a column of memory cells.

[0010] The right port bit lines BLRn and BLNRn are used to transmit a pair of opposite data signals during right port operation, and they are connected to the source of the right port selection gate of a column of memory cells.

[0011] The left port word line WLLn is used to select a row of memory cells during left port operation, and it is connected to the gate of the left port selection gate of the row of memory cells.

[0012] The right-port word line WLRn is used to select a row of memory cells during right-port operation, and it is connected to the gate of the right-port selection gate of that row of memory cells.

[0013] In one embodiment, the unit transistors include PMOS transistors MP0, MP1, MP2, MP3, NMOS transistors MN4, MN5, MN6, and MN7; the select gate transistors include NMOS transistors MN8, MN9, MN10, MN11, MN12, MN13, MN14, and MN15.

[0014] The source terminal of PMOS transistor MP0 is connected to the power supply voltage. The drain terminal of PMOS transistor MP0 is simultaneously connected to the drain terminal of NMOS transistor MN8, the drain terminal of NMOS transistor MN4, the gate terminal of PMOS transistor MP1, the drain terminal of NMOS transistor MN12, and the gate terminal of NMOS transistor MN7. The gate terminal of PMOS transistor MP0 is simultaneously connected to the drain terminal of NMOS transistor MN11, the drain terminal of PMOS transistor MP3, the drain terminal of NMOS transistor MN7, the drain terminal of NMOS transistor MN15, and the gate terminal of NMOS transistor MN6.

[0015] The source terminal of PMOS transistor MP1 is connected to the power supply voltage. The drain terminal of PMOS transistor MP1 is simultaneously connected to the drain terminal of NMOS transistor MN9, the gate terminal of PMOS transistor MP2, the drain terminal of NMOS transistor MN5, the gate terminal of NMOS transistor MN4, and the drain terminal of NMOS transistor MN13. The gate terminal of PMOS transistor MP1 is simultaneously connected to the drain terminal of NMOS transistor MN8, the drain terminal of PMOS transistor MP0, the drain terminal of NMOS transistor MN4, the drain terminal of NMOS transistor MN12, and the gate terminal of NMOS transistor MN7.

[0016] The source terminal of PMOS transistor MP2 is connected to the power supply voltage. The drain terminal of PMOS transistor MP2 is connected to the drain terminal of NMOS transistor MN10, the gate terminal of PMOS transistor MP3, the drain terminal of NMOS transistor MN6, the gate terminal of NMOS transistor MN5, and the drain terminal of NMOS transistor MN14. The gate terminal of PMOS transistor MP2 is also connected to the drain terminal of NMOS transistor MN9, the drain terminal of PMOS transistor MP1, the drain terminal of NMOS transistor MN5, the gate terminal of NMOS transistor MN4, and the drain terminal of NMOS transistor MN13.

[0017] The source terminal of PMOS transistor MP3 is connected to the power supply voltage. The drain terminal of PMOS transistor MP3 is simultaneously connected to the drain terminal of NMOS transistor MN11, the gate terminal of PMOS transistor PM0, the drain terminal of NMOS transistor MN7, the gate terminal of NMOS transistor MN6, and the drain terminal of NMOS transistor MN15. The gate terminal of PMOS transistor MP3 is simultaneously connected to the drain terminal of NMOS transistor MN10, the drain terminal of PMOS transistor MP2, the drain terminal of NMOS transistor MN6, the gate terminal of NMOS transistor MN5, and the drain terminal of NMOS transistor MN14.

[0018] The source terminal of NMOS transistor MN4 is grounded. The drain terminal of NMOS transistor MN4 is simultaneously connected to the drain terminal of NMOS transistor MN8, the drain terminal of PMOS transistor MP0, the gate terminal of PMOS transistor MP1, the drain terminal of NMOS transistor MN12, and the gate terminal of NMOS transistor MN7. The gate terminal of NMOS transistor MN4 is simultaneously connected to the drain terminal of NMOS transistor MN9, the gate terminal of PMOS transistor MP2, the drain terminal of NMOS transistor MN5, the drain terminal of PMOS transistor MP1, and the drain terminal of NMOS transistor MN13.

[0019] The source terminal of NMOS transistor MN5 is grounded. The drain terminal of NMOS transistor MN5 is simultaneously connected to the drain terminal of NMOS transistor MN9, the gate terminal of PMOS transistor MP2, the drain terminal of PMOS transistor MP1, the gate terminal of NMOS transistor MN4, and the drain terminal of NMOS transistor MN13. The gate terminal of NMOS transistor MN5 is simultaneously connected to the drain terminal of NMOS transistor MN10, the gate terminal of PMOS transistor MP3, the drain terminal of NMOS transistor MN6, the drain terminal of PMOS transistor MP2, and the drain terminal of NMOS transistor MN14.

[0020] The source of NMOS transistor MN6 is grounded. The drain of NMOS transistor MN6 is simultaneously connected to the drain of NMOS transistor MN10, the gate of PMOS transistor MP3, the drain of PMOS transistor MP2, the gate of NMOS transistor MN5, and the drain of NMOS transistor MN14. The gate of NMOS transistor MN6 is simultaneously connected to the drain of NMOS transistor MN11, the gate of PMOS transistor PM0, the drain of NMOS transistor MN7, the source of PMOS transistor MP3, and the drain of NMOS transistor MN15.

[0021] The source terminal of NMOS transistor MN7 is grounded. The drain terminal of NMOS transistor MN7 is simultaneously connected to the drain terminal of NMOS transistor MN11, the gate terminal of PMOS transistor PM0, the drain terminal of PMOS transistor MP3, the gate terminal of NMOS transistor MN6, and the drain terminal of NMOS transistor MN15. The gate terminal of NMOS transistor MN7 is simultaneously connected to the drain terminal of NMOS transistor MN8, the drain terminal of NMOS transistor MN4, the gate terminal of PMOS transistor MP1, the drain terminal of NMOS transistor MN12, and the drain terminal of PMOS transistor MP0.

[0022] The gate of NMOS transistor MN8 is connected to the word line WLL, the source of NMOS transistor MN8 is connected to the bit line BLL, and the drain of NMOS transistor MN8 is simultaneously connected to the drain of PMOS transistor MP0, the drain of NMOS transistor MN4, the gate of PMOS transistor MP1, the drain of NMOS transistor MN12, and the gate of NMOS transistor MN7.

[0023] The gate of NMOS transistor MN9 is connected to the word line WLL, the source of NMOS transistor MN9 is connected to the bit line BLNL, and the drain of NMOS transistor MN9 is simultaneously connected to the drain of PMOS transistor MP1, the gate of PMOS transistor MP2, the drain of NMOS transistor MN5, the gate of NMOS transistor MN4, and the drain of NMOS transistor MN13.

[0024] The gate of NMOS transistor MN10 is connected to word line WLL, the source of NMOS transistor MN10 is connected to bit line BLL, and the drain of NMOS transistor MN10 is simultaneously connected to the drain of PMOS transistor MP2, the gate of PMOS transistor MP3, the drain of NMOS transistor MN6, the gate of NMOS transistor MN5, and the drain of NMOS transistor MN14.

[0025] The gate of NMOS transistor MN11 is connected to word line WLL, the source of NMOS transistor MN11 is connected to bit line BLNL, and the drain of NMOS transistor MN11 is simultaneously connected to the drain of PMOS transistor MP3, the gate of PMOS transistor PM0, the drain of NMOS transistor MN7, the gate of NMOS transistor MN6, and the drain of NMOS transistor MN15.

[0026] The gate of NMOS transistor MN12 is connected to the word line WLR, the source of NMOS transistor MN12 is connected to the bit line BLR, and the drain of NMOS transistor MN12 is simultaneously connected to the drain of NMOS transistor MN8, the drain of PMOS transistor MP0, the gate of PMOS transistor MP1, the drain of NMOS transistor MN4, and the gate of NMOS transistor MN7.

[0027] The gate of NMOS transistor MN13 is connected to the word line WLR, the source of NMOS transistor MN13 is connected to the bit line BLNR, and the drain of NMOS transistor MN13 is simultaneously connected to the drain of NMOS transistor MN9, the gate of PMOS transistor MP2, the drain of PMOS transistor MP1, the gate of NMOS transistor MN4, and the drain of NMOS transistor MN5.

[0028] The gate of NMOS transistor MN14 is connected to the word line WLR, the source of NMOS transistor MN14 is connected to the bit line BLR, and the drain of NMOS transistor MN14 is simultaneously connected to the drain of NMOS transistor MN10, the gate of PMOS transistor MP3, the drain of PMOS transistor MP2, the gate of NMOS transistor MN5, and the drain of NMOS transistor MN6.

[0029] The gate of NMOS transistor MN15 is connected to the word line WLR, the source of NMOS transistor MN15 is connected to the bit line BLNR, and the drain of NMOS transistor MN15 is connected to the drain of NMOS transistor MN11, the gate of PMOS transistor PM0, the drain of PMOS transistor MP3, the gate of NMOS transistor MN6, and the drain of NMOS transistor MN7.

[0030] In one embodiment, the four bit lines of a column of memory cells are arranged in the manner of BLLn\BLRn\BLNLn\BLNRn, wherein bit lines BLLn and BLNLn are wired using the same metal layer M3, and bit lines BLRn and BLNRn are wired using the same metal layer M4, and metal layers M3 and M4 are adjacent metal layers.

[0031] In one embodiment, the left port word line WLLn is wired using metal layer M2; the right port word line WLRn is wired using metal layer M2.

[0032] This invention provides a radiation-resistant dual-port 16-transistor memory cell array. During dual-port operation, the left and right port bit lines are routed using adjacent metal layers, ensuring a small delay difference in signal transmission between the left and right port paths. When one port performs a write operation while the other port simultaneously performs a read operation on cells in the same column and adjacent rows, the adjacent metal layers on the left and right port bit lines prevent strong data signals on the write path bit lines from crosstalking to weak data signals on adjacent read path bit lines through coupling capacitance between long metal conductors, thus avoiding read failures. Within the same process node and limited chip area, this invention resolves the conflict between storage capacity, access speed, and array area, preventing bit line signal crosstalk during simultaneous read and write operations on both ports. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of the layout structure of a radiation-resistant dual-port 16-tube memory cell array;

[0034] Figure 2 This is a schematic diagram of a radiation-resistant dual-port 16-tube memory cell.

[0035] Figure 3 This is a schematic diagram of the physical layout of a radiation-resistant dual-port 16-tube memory cell array;

[0036] Figure 4 This is a schematic diagram of the physical layout of a radiation-resistant dual-port 16-tube memory cell array in the X direction. Detailed Implementation

[0037] The radiation-resistant dual-port 16-tube memory cell array proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0038] This invention proposes a radiation-resistant dual-port 16-transistor memory cell array, the layout of which is as follows: Figure 1As shown, the memory cell includes a DICE structure radiation-resistant dual-port 16-transistor memory cell, left-port word lines WLLn (n = 0, 1, 2, 3…), right-port word lines WLRn (n = 0, 1, 2, 3…), left-port bit lines BLLn (n = 0, 1, 2, 3…) and BLNLn (n = 0, 1, 2, 3…), and right-port bit lines BLRn (n = 0, 1, 2, 3…) and BLNRn (n = 0, 1, 2, 3…). The four bit lines of a single memory cell are arranged in a BLLn\BLRn\BLNLn\BLNRn configuration. Bit lines BLLn and BLNLn are routed on the same metal layer M3, while bit lines BLRn and BLNRn are routed on the same metal layer M4. Metal layers M3 and M4 are adjacent metal layers. The word lines WLLn and WLRn are left and right port word lines, respectively used to select a certain row of memory cells during left or right port operations, and are wired using the metal layer M2.

[0039] like Figure 2The diagram shows a schematic of a DICE (Dielectric-Independent Circuit-Induced) radiation-hardened dual-port 16-transistor memory cell, including cell transistors for storing data and selection gate transistors for enabling the memory cell. The cell transistors include PMOS transistors MP0, MP1, MP2, MP3, NMOS transistors MN4, MN5, MN6, and MN7; the selection gate transistors include NMOS transistors MN8, MN9, MN10, MN11, MN12, MN13, MN14, and MN15; the source terminal of PMOS transistor MP0 is connected to the power supply voltage, and the drain terminal of PMOS transistor MP0 is simultaneously connected to the drain terminal of NMOS transistor MN8 and NMOS transistor MN15. The drain of MOSFET MN4, the gate of PMOS transistor MP1, the drain of NMOS transistor MN12, and the gate of NMOS transistor MN7 are connected. The gate of PMOS transistor MP0 is also connected to the drain of NMOS transistor MN11, the drain of PMOS transistor MP3, the drain of NMOS transistor MN7, the drain of NMOS transistor MN15, and the gate of NMOS transistor MN6. The source of PMOS transistor MP1 is connected to the power supply voltage. The drain of PMOS transistor MP1 is also connected to the drain of NMOS transistor MN9, the gate of PMOS transistor MP3 (MP2), the drain of NMOS transistor MN5, the gate of NMOS transistor MN4, and the gate of NMOS transistor MN7. The drain of S-MOSFET MN13 and the gate of PMOS transistor MP1 are simultaneously connected to the drains of NMOS transistors MN8, MP0, MN4, MN12, and MN7. The source of PMOS transistor MP2 is connected to the power supply voltage. The drain of PMOS transistor MP2 is connected to the drains of NMOS transistors MN10, MP3, MN6, MN5, and MN14. The gate of PMOS transistor MP2 is simultaneously connected to the drain of NMOS transistor MN9 and the gate of PMOS transistor MP1. The drain of NMOS transistor MN1, the drain of NMOS transistor MN5, the gate of NMOS transistor MN4, and the drain of NMOS transistor MN13 are connected to the power supply voltage. The drain of PMOS transistor MP3 is also connected to the drain of NMOS transistor MN11, the gate of PMOS transistor PM0, the drain of NMOS transistor MN7, the gate of NMOS transistor MN6, and the drain of NMOS transistor MN15. The gate of PMOS transistor MP3 is also connected to the drain of NMOS transistor MN10, the drain of PMOS transistor MP2, the drain of NMOS transistor MN6, the gate of NMOS transistor MN5, and the drain of NMOS transistor MN14.The source of NMOS transistor MN4 is grounded. The drain of NMOS transistor MN4 is simultaneously connected to the drain of NMOS transistor MN8, the drain of PMOS transistor MP0, the gate of PMOS transistor MP1, the drain of NMOS transistor MN12, and the gate of NMOS transistor MN7. The gate of NMOS transistor MN4 is simultaneously connected to the drain of NMOS transistor MN9, the gate of PMOS transistor MP2, the drain of NMOS transistor MN5, the drain of PMOS transistor MP1, and the drain of NMOS transistor MN13. The source of NMOS transistor MN5 is grounded. The drain of NMOS transistor MN5 is simultaneously connected to the drain of NMOS transistor MN9, the gate of PMOS transistor MP2, the drain of PMOS transistor MP1, the gate of NMOS transistor MN4, and NMOS transistor MN13. The drain of NMOS transistor MN5 is connected to the drain of NMOS transistor MN10, the gate of PMOS transistor MP3, the drain of NMOS transistor MN6, the drain of PMOS transistor MP2, and the drain of NMOS transistor MN14. The source of NMOS transistor MN6 is grounded, and its drain is connected to the drain of NMOS transistor MN10, the gate of PMOS transistor MP3, the drain of PMOS transistor MP2, the gate of NMOS transistor MN5, and the drain of NMOS transistor MN14. The gate of NMOS transistor MN6 is connected to the drain of NMOS transistor MN11, the gate of PMOS transistor PM0, the drain of NMOS transistor MN7, the source of PMOS transistor MP3, and the drain of NMOS transistor MN15. The source of S-MOSFET MN7 is grounded. The drain of NMOS MOSFET MN7 is simultaneously connected to the drain of NMOS MOSFET MN11, the gate of PMOS MOSFET PM0, the drain of PMOS MOSFET MP3, the gate of NMOS MOSFET MN6, and the drain of NMOS MOSFET MN15. The gate of NMOS MOSFET MN7 is simultaneously connected to the drain of NMOS MOSFET MN8, the drain of NMOS MOSFET MN4, the gate of PMOS MOSFET MP1, the drain of NMOS MOSFET MN12, and the drain of PMOS MOSFET MP0. The gate of NMOS MOSFET MN8 is connected to the word line WLL, the source of NMOS MOSFET MN8 is connected to the bit line BLL, and the drain of NMOS MOSFET MN8 is simultaneously connected to the drain of PMOS MOSFET MP0, the drain of NMOS MOSFET MN4, the gate of PMOS MOSFET MP1, and the drain of NMOS MOSFET MP15. The drain of MOSFET MN12 and the gate of NMOS transistor MN7 are connected; the gate of NMOS transistor MN9 is connected to word line WLL, the source of NMOS transistor MN9 is connected to bit line BLNL, and the drain of NMOS transistor MN9 is simultaneously connected to the drain of PMOS transistor MP1, the gate of PMOS transistor MP2, the drain of NMOS transistor MN5, the gate of NMOS transistor MN4, and the drain of NMOS transistor MN13; the gate of NMOS transistor MN10 is connected to word line WLL, the source of NMOS transistor MN10 is connected to bit line BLL, and the drain of NMOS transistor MN10 is simultaneously connected to the drain of PMOS transistor MP2, the gate of PMOS transistor MP3, the drain of NMOS transistor MN6, the gate of NMOS transistor MN5, and the drain of NMOS transistor MN14.The gate of NMOS transistor MN11 is connected to the word line WLL, the source of NMOS transistor MN11 is connected to the bit line BLNL, and the drain of NMOS transistor MN11 is simultaneously connected to the drain of PMOS transistor MP3, the gate of PMOS transistor PM0, the drain of NMOS transistor MN7, the gate of NMOS transistor MN6, and the drain of NMOS transistor MN15. The gate of NMOS transistor MN12 is connected to the word line WLR, the source of NMOS transistor MN12 is connected to the bit line BLR, and the drain of NMOS transistor MN12 is simultaneously connected to the drain of NMOS transistor MN8, the drain of PMOS transistor MP0, the gate of PMOS transistor MP1, the drain of NMOS transistor MN4, and the gate of NMOS transistor MN7. The gate of NMOS transistor MN13 is connected to the word line WLR, the source of NMOS transistor MN13 is connected to the bit line BLNR, and the drain of NMOS transistor MN13 is simultaneously connected to NM... The drain of NMOS transistor MN9, the gate of PMOS transistor MP2, the drain of PMOS transistor MP1, the gate of NMOS transistor MN4, and the drain of NMOS transistor MN5 are connected to each other. The gate of NMOS transistor MN14 is connected to the word line WLR, the source of NMOS transistor MN14 is connected to the bit line BLR, and the drain of NMOS transistor MN14 is simultaneously connected to the drain of NMOS transistor MN10, the gate of PMOS transistor MP3, the drain of PMOS transistor MP2, the gate of NMOS transistor MN5, and the drain of NMOS transistor MN6. The gate of NMOS transistor MN15 is connected to the word line WLR, the source of NMOS transistor MN15 is connected to the bit line BLNR, and the drain of NMOS transistor MN15 is connected to the drain of NMOS transistor MN11, the gate of PMOS transistor PM0, the drain of PMOS transistor MP3, the gate of NMOS transistor MN6, and the drain of NMOS transistor MN7.

[0040] The radiation-resistant dual-port 16-tube memory cell array of the present invention has two independent address, data and control buses on the left and right sides, allowing two independent entities (such as two processors) to access the left and right ports simultaneously.

[0041] When a "1" is written to the left port of memory cell n1 (i.e., the memory cell in the first row of the nth column), and a "0" is read from the right port of memory cell n2 (i.e., the memory cell in the second row of the nth column), the word line WLL1 of the left port performing the write operation is connected to a high level. This opens the selection gates MN8, MN9, MN10, and MN11 of the left port of memory cell n1. The bit line BLLn transmits a strong data signal "1", and the bit line BLNLn transmits a strong data signal "0" to the memory cell transistor. PMOS transistors MP0, MP1, MP2, MP3, NMOS transistors MN4, MN5, MN6, and MN7 are used. The right port pass word line WLR2, which performs the read operation, is connected to a high level. This enables the right port selection gates MN12, MN13, MN14, and MN15 of the n2 memory cell. The bit line BLRn, pre-charged to a high level, is discharged to a weak data signal "0" through memory cell transistors MP1, MN4, MP3, and MN6. This invention uses metal layer M3 to complete the long wire routing of bit lines BLL and BLNL, and metal layer M4 to complete the long wire routing of bit lines BLR and BLNR, ensuring that in differential transmission, the data signals transmitted on bit lines BL and BLN have the same amplitude but opposite phase. This invention uses adjacent metal layers to complete the left port bit line routing, which ensures a small delay difference in the signal transmission between the left and right ports, and avoids the phenomenon that when writing "1" to the left port of memory cell n1 and reading "0" to the right port of memory cell n2, the strong data signal "1" on bit line BLL crosstalks the weak data signal "0" on bit line BLR through the coupling capacitor between the long metal wires, which can lead to read failure or even change the data stored inside memory cell n2.

[0042] When a "0" is written to the right port of memory cell n2, and a "1" is read from the left port of memory cell n1 in the same column and adjacent row, the right port path word line WLR2 for the write operation is connected to a high level, opening the right port selection gates MN12, MN13, MN14, and MN15 of memory cell n2. Bit line BLRn transmits a strong data signal "0" and bit line BLNRn transmits a strong data signal "1" to memory cell transistors PMOS transistors MP0, MP1, MP2, MP3, MN4, MN5, MN6, and MN7. The left port path word line WLL1 for the read operation is connected to a high level, opening the left port selection gates MN8, MN9, MN10, and MN11 of memory cell n1. Bit line BLNLn, pre-charged to a high level, discharges to a weak data signal "0" through memory cell transistors MP0, MN5, MP2, and MN7. The wiring method of the present invention can avoid the phenomenon that when writing "0" to the right port of the n2 memory cell and reading "1" to the left port of the n1 memory cell, the strong data signal "1" on the bit line BLNRn crosstalks the weak data signal "0" on the BLNLn through the coupling capacitor between the long metal wires, which can lead to read failure or even change the data stored inside the n1 memory cell.

[0043] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A radiation-resistant dual-port 16-transistor memory cell array, characterized in that, include: DICE structure radiation-resistant dual-port 16-transistor memory cell, left port word line WLLn, right port word line WLRn, left port bit lines BLLn and BLNLn, right port bit lines BLRn and BLNRn; where n=0, 1, 2, 3…; The DICE structure radiation-resistant dual-port 16-tube storage unit includes a unit tube for storing data information and a selection gate tube for opening the storage unit. The left port bit lines BLLn and BLNLn are used to transmit a pair of opposite data signals during left port operation, and they are connected to the source end of the left port selection gate of a column of memory cells. The right port bit lines BLRn and BLNRn are used to transmit a pair of opposite data signals during right port operation, and they are connected to the source of the right port selection gate of a column of memory cells. The left port word line WLLn is used to select a row of memory cells during left port operation, and it is connected to the gate of the left port selection gate of the row of memory cells. The right port word line WLRn is used to select a row of memory cells during right port operation, and it is connected to the gate of the right port selection gate of the row of memory cells. The unit transistors include PMOS transistors MP0, MP1, MP2, MP3, NMOS transistors MN4, MN5, MN6, and MN7; the selector gate transistors include NMOS transistors MN8, MN9, MN10, MN11, MN12, MN13, MN14, and MN15. The source terminal of PMOS transistor MP0 is connected to the power supply voltage. The drain terminal of PMOS transistor MP0 is simultaneously connected to the drain terminal of NMOS transistor MN8, the drain terminal of NMOS transistor MN4, the gate terminal of PMOS transistor MP1, the drain terminal of NMOS transistor MN12, and the gate terminal of NMOS transistor MN7. The gate terminal of PMOS transistor MP0 is simultaneously connected to the drain terminal of NMOS transistor MN11, the drain terminal of PMOS transistor MP3, the drain terminal of NMOS transistor MN7, the drain terminal of NMOS transistor MN15, and the gate terminal of NMOS transistor MN6. The source terminal of PMOS transistor MP1 is connected to the power supply voltage. The drain terminal of PMOS transistor MP1 is simultaneously connected to the drain terminal of NMOS transistor MN9, the gate terminal of PMOS transistor MP2, the drain terminal of NMOS transistor MN5, the gate terminal of NMOS transistor MN4, and the drain terminal of NMOS transistor MN13. The gate terminal of PMOS transistor MP1 is simultaneously connected to the drain terminal of NMOS transistor MN8, the drain terminal of PMOS transistor MP0, the drain terminal of NMOS transistor MN4, the drain terminal of NMOS transistor MN12, and the gate terminal of NMOS transistor MN7. The source terminal of PMOS transistor MP2 is connected to the power supply voltage. The drain terminal of PMOS transistor MP2 is connected to the drain terminal of NMOS transistor MN10, the gate terminal of PMOS transistor MP3, the drain terminal of NMOS transistor MN6, the gate terminal of NMOS transistor MN5, and the drain terminal of NMOS transistor MN14. The gate terminal of PMOS transistor MP2 is also connected to the drain terminal of NMOS transistor MN9, the drain terminal of PMOS transistor MP1, the drain terminal of NMOS transistor MN5, the gate terminal of NMOS transistor MN4, and the drain terminal of NMOS transistor MN13. The source terminal of PMOS transistor MP3 is connected to the power supply voltage. The drain terminal of PMOS transistor MP3 is simultaneously connected to the drain terminal of NMOS transistor MN11, the gate terminal of PMOS transistor PM0, the drain terminal of NMOS transistor MN7, the gate terminal of NMOS transistor MN6, and the drain terminal of NMOS transistor MN15. The gate terminal of PMOS transistor MP3 is simultaneously connected to the drain terminal of NMOS transistor MN10, the drain terminal of PMOS transistor MP2, the drain terminal of NMOS transistor MN6, the gate terminal of NMOS transistor MN5, and the drain terminal of NMOS transistor MN14. The source terminal of NMOS transistor MN4 is grounded. The drain terminal of NMOS transistor MN4 is simultaneously connected to the drain terminal of NMOS transistor MN8, the drain terminal of PMOS transistor MP0, the gate terminal of PMOS transistor MP1, the drain terminal of NMOS transistor MN12, and the gate terminal of NMOS transistor MN7. The gate terminal of NMOS transistor MN4 is simultaneously connected to the drain terminal of NMOS transistor MN9, the gate terminal of PMOS transistor MP2, the drain terminal of NMOS transistor MN5, the drain terminal of PMOS transistor MP1, and the drain terminal of NMOS transistor MN13. The source terminal of NMOS transistor MN5 is grounded. The drain terminal of NMOS transistor MN5 is simultaneously connected to the drain terminal of NMOS transistor MN9, the gate terminal of PMOS transistor MP2, the drain terminal of PMOS transistor MP1, the gate terminal of NMOS transistor MN4, and the drain terminal of NMOS transistor MN13. The gate terminal of NMOS transistor MN5 is simultaneously connected to the drain terminal of NMOS transistor MN10, the gate terminal of PMOS transistor MP3, the drain terminal of NMOS transistor MN6, the drain terminal of PMOS transistor MP2, and the drain terminal of NMOS transistor MN14. The source of NMOS transistor MN6 is grounded. The drain of NMOS transistor MN6 is simultaneously connected to the drain of NMOS transistor MN10, the gate of PMOS transistor MP3, the drain of PMOS transistor MP2, the gate of NMOS transistor MN5, and the drain of NMOS transistor MN14. The gate of NMOS transistor MN6 is simultaneously connected to the drain of NMOS transistor MN11, the gate of PMOS transistor PM0, the drain of NMOS transistor MN7, the source of PMOS transistor MP3, and the drain of NMOS transistor MN15. The source terminal of NMOS transistor MN7 is grounded. The drain terminal of NMOS transistor MN7 is simultaneously connected to the drain terminal of NMOS transistor MN11, the gate terminal of PMOS transistor PM0, the drain terminal of PMOS transistor MP3, the gate terminal of NMOS transistor MN6, and the drain terminal of NMOS transistor MN15. The gate terminal of NMOS transistor MN7 is simultaneously connected to the drain terminal of NMOS transistor MN8, the drain terminal of NMOS transistor MN4, the gate terminal of PMOS transistor MP1, the drain terminal of NMOS transistor MN12, and the drain terminal of PMOS transistor MP0. The gate of NMOS transistor MN8 is connected to the word line WLL, the source of NMOS transistor MN8 is connected to the bit line BLL, and the drain of NMOS transistor MN8 is simultaneously connected to the drain of PMOS transistor MP0, the drain of NMOS transistor MN4, the gate of PMOS transistor MP1, the drain of NMOS transistor MN12, and the gate of NMOS transistor MN7. The gate of NMOS transistor MN9 is connected to the word line WLL, the source of NMOS transistor MN9 is connected to the bit line BLNL, and the drain of NMOS transistor MN9 is simultaneously connected to the drain of PMOS transistor MP1, the gate of PMOS transistor MP2, the drain of NMOS transistor MN5, the gate of NMOS transistor MN4, and the drain of NMOS transistor MN13. The gate of NMOS transistor MN10 is connected to word line WLL, the source of NMOS transistor MN10 is connected to bit line BLL, and the drain of NMOS transistor MN10 is simultaneously connected to the drain of PMOS transistor MP2, the gate of PMOS transistor MP3, the drain of NMOS transistor MN6, the gate of NMOS transistor MN5, and the drain of NMOS transistor MN14. The gate of NMOS transistor MN11 is connected to word line WLL, the source of NMOS transistor MN11 is connected to bit line BLNL, and the drain of NMOS transistor MN11 is simultaneously connected to the drain of PMOS transistor MP3, the gate of PMOS transistor PM0, the drain of NMOS transistor MN7, the gate of NMOS transistor MN6, and the drain of NMOS transistor MN15. The gate of NMOS transistor MN12 is connected to the word line WLR, the source of NMOS transistor MN12 is connected to the bit line BLR, and the drain of NMOS transistor MN12 is simultaneously connected to the drain of NMOS transistor MN8, the drain of PMOS transistor MP0, the gate of PMOS transistor MP1, the drain of NMOS transistor MN4, and the gate of NMOS transistor MN7. The gate of NMOS transistor MN13 is connected to the word line WLR, the source of NMOS transistor MN13 is connected to the bit line BLNR, and the drain of NMOS transistor MN13 is simultaneously connected to the drain of NMOS transistor MN9, the gate of PMOS transistor MP2, the drain of PMOS transistor MP1, the gate of NMOS transistor MN4, and the drain of NMOS transistor MN5. The gate of NMOS transistor MN14 is connected to the word line WLR, the source of NMOS transistor MN14 is connected to the bit line BLR, and the drain of NMOS transistor MN14 is simultaneously connected to the drain of NMOS transistor MN10, the gate of PMOS transistor MP3, the drain of PMOS transistor MP2, the gate of NMOS transistor MN5, and the drain of NMOS transistor MN6. The gate of NMOS transistor MN15 is connected to the word line WLR, the source of NMOS transistor MN15 is connected to the bit line BLNR, and the drain of NMOS transistor MN15 is connected to the drain of NMOS transistor MN11, the gate of PMOS transistor PM0, the drain of PMOS transistor MP3, the gate of NMOS transistor MN6, and the drain of NMOS transistor MN7.

2. The radiation-resistant dual-port 16-transistor memory cell array as described in claim 1, characterized in that, The four bit lines of a column of memory cells are arranged in the manner of BLLn\BLRn\BLNLn\BLNRn. Bit lines BLLn and BLNLn are routed on the same metal layer M3, and bit lines BLRn and BLNRn are routed on the same metal layer M4. Metal layers M3 and M4 are adjacent metal layers.

3. The radiation-resistant dual-port 16-transistor memory cell array as described in claim 1, characterized in that, The left port word line WLLn uses metal layer M2 wiring; the right port word line WLRn uses metal layer M2 wiring.

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