Electronic device

Abstract

The present disclosure provides an electronic device, comprising a substrate, a first conductive layer, an insulating layer, and a second conductive layer, the first conductive layer is disposed on the substrate, the first conductive layer has a first connection line and a second connection line, in a period, the first connection line is used to transmit a positive polarity signal and the second connection line is used to transmit a negative polarity signal, the insulating layer is disposed on the first conductive layer, the second conductive layer is disposed on the insulating layer, the second conductive layer comprises a plurality of parts, and covers the first connection line and the second connection line, and the number of the first connection line covered by each of the plurality of parts is equal to the number of the second connection line covered.

Description

Technical Field

[0001] This disclosure relates to electronic devices, and more particularly to the wiring structure design of electronic devices. Background Technology

[0002] Electronic devices, including display panels, such as tablets, laptops, smartphones, monitors, and televisions, have become indispensable necessities in modern society. With the booming development of these consumer electronics products, consumers have high expectations for their quality, functionality, and price.

[0003] In recent years, display panels have evolved towards narrow bezel designs that reduce the peripheral area of ​​the driving substrate. The wiring configuration in the fan-out area of ​​this peripheral region is one of the key factors affecting the peripheral area's size. To accommodate the narrow bezel design, the linewidth, spacing, and other components of the traces on the driving substrate need to be miniaturized accordingly, increasing manufacturing complexity. Furthermore, the wiring in the fan-out area overlaps with the substrate's cutting paths, making it prone to damage during substrate cutting and consequently affecting product performance.

[0004] As mentioned above, developing wiring structure designs that can improve the reliability or performance of electronic devices is one of the topics that the industry is currently focusing on researching. Summary of the Invention

[0005] According to some embodiments of this disclosure, an electronic device is provided, comprising a substrate, a first conductive layer, an insulating layer, and a second conductive layer. The first conductive layer is disposed on the substrate and has a first connection line and a second connection line. In one cycle, the first connection line is used to transmit a positive polarity signal and the second connection line is used to transmit a negative polarity signal. The insulating layer is disposed on the first conductive layer and the second conductive layer is disposed on the insulating layer. The second conductive layer comprises multiple portions and covers the first connection line and the second connection line. The number of first connection lines covered by each of the multiple portions is equal to the number of second connection lines covered.

[0006] To make the features or advantages of this disclosure more apparent and understandable, some embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0007] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:

[0008] Figure 1 The diagram shows a top view of the electronic device according to some embodiments of the present disclosure;

[0009] Figure 2 According to some embodiments of this disclosure, corresponding to Figure 1 A schematic diagram of the cross-sectional structure of an electronic device with line A-A'.

[0010] Figure 3 According to some embodiments of this disclosure, corresponding to Figure 1 A schematic diagram of the cross-sectional structure of an electronic device with line A-A'.

[0011] Figure 4 According to some embodiments of this disclosure, corresponding to Figure 1 A schematic diagram of the cross-sectional structure of an electronic device with line A-A'.

[0012] Figure 5 According to some embodiments of this disclosure, corresponding to Figure 1 A schematic diagram of the cross-sectional structure of an electronic device with line A-A'.

[0013] Figure 1-5 The annotations in the attached figures are explained as follows:

[0014] 10: Electronic devices

[0015] 100: Substrate

[0016] 110: Sealing assembly

[0017] 120: Electronic Components

[0018] 200: Circuit Structure

[0019] 210: First conductive layer

[0020] 210a: First connecting line

[0021] 210b: Second connecting line

[0022] 210c: Third connecting line

[0023] 220: Second conductive layer

[0024] 220p: Partial

[0025] 300: Insulation layer

[0026] A-A': Cutoff line

[0027] CT: Cutting track

[0028] D1: Distance

[0029] D2: Distance

[0030] DA: Display Area

[0031] NA: Surrounding Area

[0032] P1: Spacing

[0033] T1: Thickness

[0034] T2: Thickness

[0035] W1: Width

[0036] W2: Width

[0037] W3: Width Detailed Implementation

[0038] The following provides a detailed description of an electronic device based on embodiments of the present disclosure. It should be understood that the following description provides many different embodiments for implementing various forms of some embodiments of the present disclosure. The specific components and arrangements described below are merely for clear and simple description of some embodiments of the present disclosure. Of course, these are merely examples and not intended to limit the scope of the present disclosure. Furthermore, similar and / or corresponding reference numerals may be used in different embodiments to identify similar and / or corresponding components for clear description of the present disclosure. However, the use of these similar and / or corresponding reference numerals is merely for clear and simple description of some embodiments of the present disclosure and does not imply any association between the different embodiments and / or structures discussed.

[0039] It should be understood that relative terms, such as "lower," "bottom," "higher," or "top," may be used in the embodiments to describe the relative relationship of one component of the figures to another. It is understood that if the apparatus in the figures is flipped upside down, the component described as being on the "lower" side will become the component on the "higher" side. Embodiments of this disclosure can be used in conjunction with the accompanying drawings. Figure 1 It should be understood that the accompanying drawings of this disclosure are also considered part of the disclosure. It should be understood that the drawings of this disclosure are not drawn to scale, and in fact, the dimensions of components may be arbitrarily enlarged or reduced to clearly show the features of this disclosure.

[0040] Furthermore, when it is mentioned that a first material layer is located on or above a second material layer, it may include situations where the first material layer and the second material layer are in direct contact, or situations where the first material layer and the second material layer are not in direct contact, that is, situations where there may be one or more other material layers between the first material layer and the second material layer. However, if the first material layer is located directly on the second material layer, it indicates that the first material layer and the second material layer are in direct contact.

[0041] Furthermore, it should be understood that the ordinal numbers used in the specification and claims, such as "first," "second," etc., to modify components, do not in themselves imply any prior ordinal number for that (or those) component, nor do they represent the order of one component with another, or the order of manufacturing processes. The use of these ordinal numbers is solely to clearly distinguish one component with a certain name from another component with the same name. The claims and specification may not use the same terminology; for example, the first component in the specification may be the second component in the claims.

[0042] In some embodiments of this disclosure, terms such as "connection" and "interconnection," unless specifically defined, may refer to two structures being in direct contact, or to two structures not being in direct contact, wherein another structure is disposed between the two structures. Furthermore, these terms regarding engagement and connection may also include cases where both structures are movable or both structures are fixed. In addition, the terms "electrical connection" or "electrical coupling" include any direct and indirect electrical connection means.

[0043] In this text, the terms "about" and "substantially" typically indicate a range within 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value. The phrase "range between a first value and a second value" indicates that the range includes the first value, the second value, and other values ​​in between.

[0044] It should be understood that the features described below can be replaced, reorganized, or combined in several different embodiments to complete other embodiments without departing from the spirit of this disclosure. Features between embodiments can be arbitrarily combined and used as long as they do not violate the spirit of the invention or conflict with it.

[0045] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It is understood that such terms, for example, as defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the relevant art and the background or context of this disclosure, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in embodiments of this disclosure.

[0046] According to embodiments of this disclosure, an electronic device is provided with a specific wiring configuration in the fan-out region of a substrate. For example, by covering the same number of first and second connecting lines with a second conductive layer, voltage polarity interference between adjacent lines can be reduced, or the function of preventing line damage can be maintained, even with a reduced line spacing. According to embodiments of this disclosure, the wiring configuration structure can improve machine capacity utilization and process yield.

[0047] According to embodiments of this disclosure, the electronic device may include a display device, a touch device, a sensing device, or a splicing device, but is not limited thereto. The electronic device may be a bendable or flexible electronic device. The display device may be a non-emissive display device or a self-emissive display device. The sensing device may be a sensing device that senses capacitance, light, heat, or ultrasound, but is not limited thereto. Furthermore, the electronic device may, for example, include liquid crystal, quantum dot (QD), fluorescence, phosphorescence, other suitable materials, or combinations thereof. The electronic device may include electronic components, which may include passive and active components, such as capacitors, resistors, inductors, diodes, transistors, etc. Diodes may include light-emitting diodes (LEDs) or photodiodes. Light-emitting diodes may, for example, include organic light-emitting diodes (OLEDs), mini LEDs, micro LEDs, or quantum dot LEDs, but are not limited thereto. According to some embodiments, the electronic device may include a panel and / or a backlight module. The panel may include, for example, a liquid crystal panel or other self-emissive panels, but is not limited thereto. The splicing device may be, for example, a display splicing device, but is not limited thereto. It should be understood that the electronic device may be any of the foregoing arrangements and combinations, but is not limited thereto. The following description of the electronic device will use a display device as an example, but this disclosure is not limited thereto.

[0048] Please refer to Figure 1 , Figure 1 The figures shown are top views of an electronic device 10 according to some embodiments of the present disclosure. It should be understood that, for clarity, some components of the electronic device 10 are omitted from the accompanying drawings, and only some components are schematically shown. According to some embodiments, additional features may be added to the electronic device 10 described below. According to other embodiments, some features of the electronic device 10 described below may be replaced or omitted.

[0049] Electronic device 10 may include substrate 100, which may have a display area DA and a peripheral area NA, the peripheral area NA being disposed around the display area DA. According to some embodiments, the peripheral area NA of substrate 100 has a bonding area (e.g., Figure 1 The area located below the cutting channel CT) is the junction area, which can be the area where signal lines are joined with other electronic components. Furthermore, the electronic device 10 may include a circuit structure 200, which extends from the display area DA to the peripheral area NA and is electrically connected to the electronic components 120 disposed on the substrate 100. The circuit structure 200 can be fanned out. Detailed information about the circuit structure 200 will be provided below.

[0050] The substrate 100 can serve as a driving substrate, and a driving circuit (not shown) can be disposed on the substrate 100. The driving circuit may include an active driving circuit and / or a passive driving circuit. According to some embodiments, the driving circuit may include thin-film transistors (TFTs) (e.g., switching transistors, driving transistors, reset transistors, or other thin-film transistors), data lines, scan lines, touch signal lines, conductive pads, dielectric layers, capacitors, or other lines, but is not limited thereto. Furthermore, the thin-film transistor may be a top-gate thin-film transistor, a bottom-gate thin-film transistor, or a dual-gate or double-gate thin-film transistor. The thin-film transistor includes at least one semiconductor layer, which includes, but is not limited to, amorphous silicon, low-temp polysilicon (LTPS), metal oxides, other suitable materials, or combinations thereof, but is not limited thereto. The metal oxide may include, but is not limited to, indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium gallium zinc tin oxide (IGZTO), other suitable materials, or combinations thereof.

[0051] According to some embodiments, the driving circuit can be electrically connected to the electronic component 120 via the circuit structure 200. According to some embodiments, the electronic component 120 may include an integrated circuit (IC), a microchip, or other suitable electronic components that can provide electronic or logic signals, but is not limited thereto. According to some embodiments, the electronic component 120 may be disposed on the substrate 100 in the form of a chip-on-film (COF) package or a chip-on-glass (COG) package, but is not limited thereto. Furthermore, the number of electronic components 120 is not limited to those shown in the figures; according to different embodiments, the electronic device 10 may have any suitable number of electronic components 120.

[0052] Furthermore, substrate 100 may comprise a rigid substrate or a flexible substrate. According to some embodiments, the material of substrate 100 may include glass, quartz, sapphire, polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polydimethylsiloxane (PDMS), other suitable materials, or combinations thereof, but is not limited thereto. According to some embodiments, substrate 100 may comprise a flexible printed circuit board (FPC).

[0053] In addition, such as Figure 1 As shown, according to some embodiments, the electronic device 10 may have a sealing component 110, which may be disposed in the peripheral area NA and may surround the display area DA. According to some embodiments, the sealing component 110 may be disposed between the substrate 100 and a opposing substrate (not shown) disposed thereops, and a modulation material (not shown, but may include liquid crystal molecules) may be fixed within the sealing component 110, but this disclosure is not limited thereto. According to some embodiments, the aforementioned opposing substrate may be a color filter substrate, for example, it may include a substrate and a light-shielding layer and / or a color filter layer disposed thereon.

[0054] The sealing assembly 110 may have a single-layer or multi-layer structure. According to some embodiments, the material of the sealing assembly 110 may include, but is not limited to, polyethylene terephthalate (PET), polyethylene (PE), polyethersulfone (PES), polycarbonate (PC), polymethyl methacrylate (PMMA), epoxy resin, other suitable materials, or combinations thereof. According to some embodiments, the sealing assembly 110 may include a photocurable adhesive, a thermocurable adhesive, a photothermal curable adhesive, other suitable materials, or combinations thereof, but is not limited to these. For example, the sealing assembly 110 may include optically clear adhesive (OCA), optically clear resin (OCR), pressure-sensitive adhesive (PSA), other suitable materials, or combinations thereof, but is not limited to these.

[0055] It is worth noting that after the substrate 100 and the opposing substrate are assembled, the opposing substrate can be cut along the cutting path CT to remove a portion of the opposing substrate and expose a portion of the substrate 100 (e.g., Figure 1The area located below the cleaving tract CT is shown in the figure. However, since the cleaving tract CT partially overlaps with the circuit structure 200 on the substrate 100 in the normal direction (e.g., the Z direction in the figure), the cleaving process may damage the circuit structure 200. According to embodiments of the present disclosure, the fan-out circuit structure 200 located in the peripheral region NA has a specific configuration that can reduce the risk of circuit damage and reduce voltage polarity interference between adjacent lines even when the line spacing is reduced.

[0056] For details, please refer to Figure 2 , Figure 2 According to some embodiments of this disclosure, corresponding to Figure 1 A schematic diagram of the cross-sectional structure of an electronic device with line A-A'. Figure 2 Displays the detailed structure of circuit structure 200.

[0057] The circuit structure 200 of the electronic device 10 may include a first conductive layer 210, an insulating layer 300, and a second conductive layer 220. The first conductive layer 210 may be disposed on the substrate 100, the insulating layer 300 may be disposed on the first conductive layer 210, and the second conductive layer 220 may be disposed on the insulating layer 300. The first conductive layer 210 may have a first connecting line 210a and a second connecting line 210b, and the insulating layer 300 and the second conductive layer 220 may cover (or span) the first connecting line 210a and the second connecting line 210b. In other words, in the normal direction of the substrate 100 (e.g., the Z direction in the figure), the insulating layer 300 and the second conductive layer 220 overlap with the first connecting line 210a and the second connecting line 210b. The insulating layer 300 and the second conductive layer 220 can protect the first conductive layer 210, reduce the risk of circuit damage, or reduce corrosion or oxidation caused by the reaction of moisture or oxygen with the first conductive layer 210.

[0058] The first connecting line 210a can be used to transmit a positive polarity signal (marked with the symbol "+" in the figures for ease of explanation), and the second connecting line 210b can be used to transmit a negative polarity signal (marked with the symbol "-" in the figures for ease of explanation). According to some embodiments, the first connecting line 210a and the second connecting line 210b can be arranged alternately. According to some embodiments, the first conductive layer 210 can be electrically connected to the electronic component 120; furthermore, the first connecting line 210a and the second connecting line 210b can be used to transmit data line signals of the driving circuit, but are not limited thereto. It should be understood that the polarity of the signals transmitted by the first connecting line 210a and the second connecting line 210b can be alternately changed; that is, when the first connecting line 210a changes from transmitting a positive polarity signal to transmitting a negative polarity signal, the second connecting line 210b will change from transmitting a negative polarity signal to transmitting a positive polarity signal. The signal polarity of the first connecting line 210a and the second connecting line 210b can change periodically, but this disclosure is not limited thereto.

[0059] Furthermore, the number of first connecting lines 210a covered by the second conductive layer 220 is equal to the number of second connecting lines 210b covered by the second conductive layer 220. It is worth noting that if the number of first connecting lines 210a covered by the second conductive layer 220 is not equal to the number of second connecting lines 210b covered by it, the capacitive coupling effect of the first connecting lines 210a and the second connecting lines 210b may not be canceled when switching between high and low voltages (positive and negative polarities), causing an error between the actual output voltage and the ideally set voltage, thereby affecting the performance of the electronic device, for example, causing differences in brightness between pixels.

[0060] Furthermore, according to some embodiments, the second conductive layer 220 may include multiple portions 220p, which are not connected, and each of the multiple portions 220p may each cover (or span) at least one first connecting line 210a and at least one second connecting line 210b. In other words, at least one or more first connecting lines 210a and at least one or more second connecting lines 210b may share a portion 220p. Figure 2 As shown, each of the aforementioned portions 220p covers a first connecting line 210a and a second connecting line 210b. The positive and negative polarity signals transmitted by the first connecting line 210a and the second connecting line 210b covered by each portion 220p are the same, and the capacitive coupling effect can cancel each other out. Even when the line spacing is reduced, voltage polarity interference between adjacent lines can still be reduced.

[0061] Furthermore, the first connecting line 210a may have a width W1, and the second connecting line 210b may have a width W2. According to some embodiments, the width W1 of the first connecting line 210a may be greater than or equal to 1 micrometer and less than or equal to 10 micrometers (i.e., 1 μm ≤ width W1 ≤ 10 μm). According to some embodiments, the width W2 of the second connecting line 210b may be greater than or equal to 1 micrometer and less than or equal to 10 micrometers (i.e., 1 μm ≤ width W2 ≤ 10 μm).

[0062] According to embodiments of this disclosure, width W1 refers to the maximum width of the first connecting line 210a in a direction perpendicular to the normal direction of the substrate 100 (e.g., the X direction in the figures), and width W2 refers to the maximum width of the second connecting line 210b in a direction perpendicular to the normal direction of the substrate 100 (e.g., the X direction in the figures).

[0063] Furthermore, adjacent first connecting lines 210a and second connecting lines 210b may have a distance D1 (i.e., line spacing). According to some embodiments, the distance D1 may be greater than or equal to 1 micrometer and less than or equal to 20 micrometers (i.e., 1 μm ≤ distance D1 ≤ 20 μm). On the other hand, adjacent portions 220p of the second conductive layer 220 may have a distance D2. According to some embodiments, the distance D2 may be greater than or equal to 1 micrometer and less than or equal to 20 micrometers (i.e., 1 μm ≤ distance D2 ≤ 20 μm). According to some embodiments, the distance D2 between portions 220p of the second conductive layer 220 may be less than or equal to the distance D1 between the first connecting lines 210a and second connecting lines 210b.

[0064] According to embodiments of this disclosure, distance D1 refers to the minimum distance between adjacent first connection line 210a and second connection line 210b in a direction perpendicular to the normal direction of substrate 100 (e.g., the X direction in the figures). Distance D2 refers to the minimum distance between adjacent portions 220p of the second conductive layer 220 in a direction perpendicular to the normal direction of substrate 100 (e.g., the X direction in the figures).

[0065] Furthermore, a pitch P1 may be present between the first connecting line 210a and the second connecting line 210b. According to some embodiments, the pitch P1 may be greater than or equal to 1 micrometer and less than or equal to 30 micrometers (i.e., 1 μm ≤ pitch P1 ≤ 30 μm).

[0066] According to an embodiment of the present disclosure, the spacing P1 refers to the distance between one side edge (e.g., the left edge) of the first connecting line 210a and the same side edge (e.g., the left edge) of the nearest second connecting line 210b in a direction perpendicular to the normal direction of the substrate 100 (e.g., the X direction in the figures).

[0067] Furthermore, it should be understood that, according to embodiments of this disclosure, the width, thickness, or height of each component, and the spacing or distance between components, can be measured using a scanning electron microscope (SEM), an optical microscope (OM), an alpha-step thickness gauge, an ellipsometry, or other suitable methods. Specifically, according to some embodiments, a scanning electron microscope can be used to obtain a cross-sectional image containing the components to be measured, and the width, thickness, or height of each component, and the spacing or distance between components, can be measured.

[0068] As for the foregoing, according to the embodiments of this disclosure, by means of the configuration design of the circuit structure 200, even when the distance D1 (line spacing) or pitch P1 between the first connecting line 210a and the second connecting line 210b is relatively small, voltage polarity interference between adjacent lines can still be reduced. Furthermore, it is worth noting that, according to the embodiments of this disclosure, since the second conductive layer 220 can cover (or span) at least one first connecting line 210a and at least one second connecting line 210b, the second conductive layer 220 can have a larger width (e.g., greater than the line width of the first connecting line 210a or the second connecting line 210b), thereby reducing process difficulty or improving process yield.

[0069] Furthermore, the material of the first conductive layer 210 may include metallic conductive materials, transparent conductive materials, other suitable materials, or combinations thereof, but is not limited thereto. Metallic conductive materials may include copper (Cu), silver (Ag), gold (Au), tin (Sn), aluminum (Al), molybdenum (Mo), tungsten (W), chromium (Cr), nickel (Ni), platinum (Pt), titanium (Ti), any of the aforementioned metal alloys, other suitable materials, or combinations thereof, but are not limited thereto. Transparent conductive materials may include transparent conductive oxides (TCOs), such as indium tin oxide (ITO), antimony zinc oxide (AZO), tin oxide (SnO), zinc oxide (ZnO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), antimony tin oxide (ATO), other suitable transparent conductive materials, or combinations thereof, but are not limited thereto. Furthermore, the first conductive layer 210 may have a single-layer structure or a multi-layer structure.

[0070] According to some embodiments, the first conductive layer 210 can be formed by screen printing, inkjet printing, chemical vapor deposition, physical vapor deposition, electroplating, electroless electroplating, other suitable methods, or combinations thereof. According to some embodiments, the first conductive layer 210 can be patterned to form multiple portions 220p by one or more photolithography and / or etching processes. According to some embodiments, the photolithography process may include, but is not limited to, photoresist coating (e.g., spin coating), soft baking, hard baking, shielding alignment, exposure, post-exposure baking, photoresist development, cleaning, and drying. The etching process may include, but is not limited to, dry etching or wet etching processes.

[0071] According to some embodiments, the material of the insulating layer 300 may comprise organic materials, inorganic materials, other suitable materials, or combinations thereof, but is not limited thereto. For example, inorganic materials may comprise silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, other suitable materials, or combinations thereof, but are not limited thereto. For example, organic materials may comprise epoxy resins, silicone resins, acrylic resins (e.g., polymethyl methacrylate (PMMA)), benzocyclobutene (BCB), polyimide, polyester, polydimethylsiloxane (PDMS), perfluoroalkoxyalkane (PFA), other suitable materials, or combinations thereof, but are not limited thereto.

[0072] According to some embodiments, the insulating layer 300 can be formed by coating process, chemical vapor deposition process, physical vapor deposition process, printing process, evaporation process, sputtering process, other suitable processes, or combinations thereof.

[0073] Furthermore, the insulating layer 300 may have a thickness T1. According to some embodiments, the thickness T1 of the insulating layer 300 may be greater than or equal to 0.05 micrometers and less than or equal to 0.8 micrometers (i.e., 0.05 μm ≤ thickness T1 ≤ 0.8 μm).

[0074] According to embodiments of this disclosure, thickness T1 refers to the maximum thickness of insulating layer 300 in the normal direction of substrate 100 (e.g., the Z direction in the figures).

[0075] Furthermore, the material of the second conductive layer 220 may include a transparent conductive material, other suitable materials, or combinations thereof, but is not limited thereto. According to some embodiments, the second conductive layer 220 is a transparent conductive material. The transparent conductive material may include transparent conductive oxides (TCOs), such as indium tin oxide (ITO), zinc antimony oxide (AZO), tin oxide (SnO), zinc oxide (ZnO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), antimony tin oxide (ATO), other suitable transparent conductive materials, or combinations thereof, but is not limited thereto. Furthermore, the second conductive layer 220 may have a single-layer structure or a multi-layer structure.

[0076] Furthermore, the method for forming the second conductive layer 220 can be the same as or similar to the process for forming the first conductive layer 210, and will not be repeated here.

[0077] Furthermore, the second conductive layer 220 (or a portion of 220p) may have a thickness T2. According to some embodiments, the thickness T2 of the second conductive layer 220 may be greater than or equal to 0.1 micrometers and less than or equal to 0.5 micrometers (i.e., 0.1 μm ≤ thickness T2 ≤ 0.5 μm).

[0078] According to embodiments of this disclosure, thickness T2 refers to the maximum thickness of the second conductive layer 220 in the normal direction of the substrate 100 (e.g., the Z direction in the figures).

[0079] It should be understood that, for the sake of clarity, Figure 2 Some components of the electronic device 10 are omitted, and only some components are schematically shown. According to some embodiments, other conductive layers or insulating layers may be disposed between the substrate 100 and the first conductive layer 210. For example, other conductive layers may be used to transmit scan line (gate line) signals of the driving circuit, and other insulating layers may include gate insulating layers, but are not limited thereto.

[0080] Next, please refer to Figure 3 , Figure 3 According to other embodiments of this disclosure, corresponding to Figure 1 The diagram shows a cross-sectional view of the electronic device 10 along line A-A'. It should be understood that components or components that are the same or similar to those described above will be indicated by the same or similar designations in the following text, and their materials, manufacturing methods and functions are the same or similar to those described above, so this part will not be repeated in the following text.

[0081] like Figure 3As shown, according to some embodiments, multiple portions 220p of the second conductive layer 220 may each cover two first connecting lines 210a and two second connecting lines 210b. The number of first connecting lines 210a covered by the second conductive layer 220 is equal to the number of second connecting lines 210b covered by the second conductive layer 220. Specifically, the total positive polarity signal transmitted by the first connecting lines 210a and second connecting lines 210b covered by each portion 220p is equal to the total negative polarity signal, and the capacitive coupling effect can cancel each other out.

[0082] It should be understood that, although in the embodiments shown in the accompanying drawings, each portion 220p of the second conductive layer 220 covers the same number of first connecting lines 210a and second connecting lines 210b, according to other embodiments, different portions 220p may cover different numbers of first connecting lines 210a and second connecting lines 210b. For example, some portions 220p of the second conductive layer 220 may cover one first connecting line 210a and one second connecting line 210b, while some portions 220p of the second conductive layer 220 may cover two first connecting lines 210a and two second connecting lines 210b, but this disclosure is not limited thereto. Furthermore, a portion 220p of the second conductive layer 220 may cover one set of first connecting lines 210a and second connecting lines 210b (i.e., one first connecting line 210a and one second connecting line 210b), or two, three, four, five, or other suitable sets, and this disclosure is not limited thereto.

[0083] Next, please refer to Figure 4 , Figure 4 According to other embodiments of this disclosure, corresponding to Figure 1 A schematic diagram of the cross-sectional structure of the electronic device 10 along line A-A'.

[0084] like Figure 4 As shown, according to some embodiments, the first conductive layer 210 may further include a third connecting line 210c, which may be disposed between the first connecting line 210a and the second connecting line 210b. Furthermore, in addition to the first connecting line 210a and the second connecting line 210b, the second conductive layer 220 may further cover the third connecting line 210c. In other words, in the normal direction of the substrate 100 (e.g., the Z direction in the figures), the second conductive layer 220 may overlap with the first connecting line 210a, the second connecting line 210b, and the third connecting line 210c. According to some embodiments, the third connecting line 210c can be used to transmit touch signals. According to some embodiments, the first connecting line 210a, the second connecting line 210b, and the third connecting line 210c may be arranged alternately.

[0085] In this embodiment, the number of first connecting lines 210a covered by the second conductive layer 220 is equal to the number of second connecting lines 210b covered by the second conductive layer 220. Furthermore, the second conductive layer 220 may include multiple portions 220p, which are not connected, and each portion 220p may cover at least one first connecting line 210a, at least one second connecting line 210b, and at least one third connecting line 210c. In this embodiment, the sum of the number of first connecting lines 210a covered by a portion 220p of the second conductive layer 220, the number of second connecting lines 210b covered, and the number of third connecting lines 210c covered is an odd number.

[0086] like Figure 4 As shown, each of the multiple portions 220p of the second conductive layer 220 covers a first connecting line 210a, a second connecting line 210b, and a third connecting line 210c. The positive and negative polarity signals transmitted by the first connecting line 210a and the second connecting line 210b covered by each portion 220p are the same. Furthermore, since the average value of the polarity signal transmitted by the third connecting line 210c is equivalent to close to 0, the total positive polarity signal and the total negative polarity signal transmitted by the first connecting line 210a, the second connecting line 210b, and the third connecting line 210c are also equal, so that the capacitive coupling effect can cancel each other out.

[0087] Furthermore, the third connecting line 210c may have a width W3. According to some embodiments, the width W3 of the third connecting line 210c may be greater than or equal to 1 micrometer and less than or equal to 10 micrometers (i.e., 1 μm ≤ width W3 ≤ 10 μm).

[0088] According to an embodiment of this disclosure, the width W3 refers to the maximum width of the third connecting line 210c in a direction perpendicular to the normal direction of the substrate 100 (e.g., the X direction in the figures).

[0089] As mentioned above, there may be a distance D1 (i.e., line spacing) between adjacent first connecting lines 210a and second connecting lines 210b. In this embodiment, there is also a distance D1 between the third connecting line 210c and its adjacent first connecting line 210a or second connecting line 210b. Furthermore, as mentioned above, there may be a spacing P1 between the first connecting lines 210a and second connecting lines 210b. In this embodiment, there is also a spacing P1 between the third connecting line 210c and its adjacent first connecting line 210a or second connecting line 210b.

[0090] Next, please refer to Figure 5 , Figure 5 According to other embodiments of this disclosure, corresponding to Figure 1 A schematic diagram of the cross-sectional structure of the electronic device 10 along line A-A'.

[0091] like Figure 5 As shown, in this embodiment, the first conductive layer 210 further includes a third connecting line 210c, which can be disposed between the first connecting line 210a and the second connecting line 210b. The number of first connecting lines 210a covered by the second conductive layer 220 is also equal to the number of second connecting lines 210b covered by the second conductive layer 220. In this embodiment, the sum of the number of first connecting lines 210a covered by a portion 220p of the second conductive layer 220, the number of second connecting lines 210b covered, and the number of third connecting lines 210c covered is an even number.

[0092] like Figure 5 As shown, multiple portions 220p of the second conductive layer 220 can each cover a first connecting line 210a, a second connecting line 210b, and two third connecting lines 210c. The first connecting line 210a and the second connecting line 210b covered by each portion 220p transmit the same positive and negative polarity signals. Furthermore, since the polarity signal transmitted by the third connecting line 210c is essentially equal to 0, the total positive polarity signal and the total negative polarity signal transmitted by the first connecting line 210a, the second connecting line 210b, and the third connecting line 210c are also equal, so that the capacitive coupling effect can cancel each other out.

[0093] As mentioned above, although in the embodiments shown in the figures, each portion 220p of the second conductive layer 220 covers the same number of first connecting lines 210a, second connecting lines 210b, and third connecting lines 210c, according to other embodiments, different portions 220p may cover different numbers of first connecting lines 210a, second connecting lines 210b, and third connecting lines 210c, as long as the polarity signals transmitted by the first connecting lines 210a, second connecting lines 210b, and third connecting lines 210c covered by the second conductive layer 220 can cancel out the capacitive coupling effect.

[0094] In summary, according to embodiments of this disclosure, an electronic device is provided that has a specific wiring configuration in the fan-out region of a substrate. For example, by covering the same number of first and second connecting lines with a second conductive layer, voltage polarity interference between adjacent lines can be reduced, or the function of preventing line damage can be maintained, even when the line spacing is reduced. According to embodiments of this disclosure, the wiring configuration structure can improve machine capacity utilization and process yield.

[0095] While the embodiments and advantages of this disclosure have been disclosed above, it should be understood that anyone skilled in the art can make combinations, modifications, substitutions, and refinements without departing from the spirit and scope of this disclosure. Features between embodiments of this disclosure can be freely combined and used as long as they do not violate the spirit of the invention or conflict with it. Furthermore, the scope of protection of this disclosure is not limited to the processes, machines, manufacturing, material composition, apparatus, methods, and steps described in the specific embodiments of the specification. Anyone skilled in the art can understand from the disclosure of this disclosure that current or future developed processes, machines, manufacturing, material composition, apparatus, methods, and steps can be used according to this disclosure as long as they can perform substantially the same function or obtain substantially the same results in the embodiments described herein. Therefore, the scope of protection of this disclosure includes the aforementioned processes, machines, manufacturing, material composition, apparatus, methods, and steps. The scope of protection of this disclosure shall be determined by the scope of the appended claims. No embodiment or claim of this disclosure needs to achieve all the purposes, advantages, and features disclosed in this disclosure.

[0096] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and improvements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be defined by the claims.

Claims

1. An electronic device, characterized in that, include: One substrate; A first conductive layer is disposed on the substrate. The first conductive layer has a first connection line and a second connection line. In one cycle, the first connection line is used to transmit a positive polarity signal and the second connection line is used to transmit a negative polarity signal. An insulating layer is disposed on the first conductive layer; as well as A second conductive layer is disposed on the insulating layer, the second conductive layer comprising multiple portions and covering the first connecting line and the second connecting line; The number of first connecting lines covered by each of the plurality of parts is equal to the number of second connecting lines covered by each of the plurality of parts.

2. The electronic device as claimed in claim 1, characterized in that, The material of the second conductive layer includes a transparent conductive material.

3. The electronic device as claimed in claim 1, characterized in that, The multiple parts are not connected.

4. The electronic device as claimed in claim 1, characterized in that, It further includes an electronic component disposed on the substrate, wherein the first conductive layer is electrically connected to the electronic component.

5. The electronic device as claimed in claim 1, characterized in that, The first connecting line and the second connecting line are arranged alternately.

6. The electronic device as claimed in claim 1, characterized in that, The first conductive layer further includes a third connecting line, and the second conductive layer further covers the third connecting line.

7. The electronic device as claimed in claim 6, characterized in that, Each of the plurality of parts covers at least one first connecting line, at least one second connecting line, and at least one third connecting line.

8. The electronic device as claimed in claim 7, characterized in that, The multiple parts are not connected.

9. The electronic device as claimed in claim 6, characterized in that, The third connection line is used to transmit a touch signal.

10. The electronic device as claimed in claim 6, characterized in that, The third connecting line is disposed between the first connecting line and the second connecting line.

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