Trench power semiconductor device and method of manufacturing the same

Abstract

The present application provides a trench power semiconductor device and a manufacturing method thereof. The trench power semiconductor device includes a semiconductor substrate, a semiconductor epitaxial layer with a trench, a source polysilicon, an oxide layer, a gate layer and a gate oxide layer. The source polysilicon is disposed in the trench of the semiconductor epitaxial layer. The source polysilicon is composed of a crown polysilicon and a polysilicon filling layer. The crown polysilicon is conformal to the trench and has a recess. The polysilicon filling layer is disposed in the recess. The oxide layer is disposed between the source polysilicon and the semiconductor epitaxial layer. The oxide layer has a substantially uniform thickness. The gate layer is disposed on the source polysilicon in the trench. The gate oxide layer is disposed between the gate layer and the source polysilicon and between the gate layer and the semiconductor epitaxial layer. The profile of the crown polysilicon improves the trench filling ability of the polysilicon filling layer and improves the reliability of the trench power semiconductor device.

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a trench power semiconductor device and a method for manufacturing the same. Background Technology

[0002] As semiconductor components become smaller and smaller, the aspect ratio of trenches also becomes larger and larger. Therefore, gaps are easily generated when filling trenches, which may have a negative impact on the electrical performance of the final component.

[0003] For example, in the structure and process of shielded gate trench MOSFETs (SGT MOSFETs), the height, depth, and width of the trench (i.e., the trench is relatively deep but the opening is relatively small) make it difficult to form uniform polysilicon within it. Polysilicon voids often exist after filling, and this phenomenon is particularly noticeable in the depth of the trench. Especially when polysilicon is grown in the furnace tube, it is grown along the oxide layer on the trench wall, so its opening will gradually close up to form voids. After the polysilicon is etched back to form the shielding electrode, if these voids happen to be located on the top surface of the shielding electrode, it will cause defects such as depressions and sharp corners on the surface of the shielding electrode. After the subsequent gate oxide layer and gate electrode are completed, tip discharge will occur at these sharp corners, causing a short circuit between the shielding electrode (or source polysilicon) and the gate electrode, reducing the breakdown voltage and affecting the performance of the trench power semiconductor device. Summary of the Invention

[0004] This invention relates to a trench power semiconductor device that can improve the problem of reduced breakdown voltage and enhance the reliability of the trench power semiconductor device.

[0005] The present invention also relates to a method for manufacturing a trench-type power semiconductor device, which can prevent the formation of gaps in the source polysilicon or avoid gaps from approaching the surface of the source polysilicon, so as to avoid a decrease in breakdown voltage.

[0006] According to an embodiment of the present invention, a trench-type power semiconductor device includes a semiconductor substrate, a semiconductor epitaxial layer, a source polysilicon, an oxide layer, a gate layer, and a gate oxide layer. The semiconductor epitaxial layer is formed on the semiconductor substrate and has trenches. The source polysilicon is disposed in the trenches of the semiconductor epitaxial layer. An oxide layer is disposed between the source polysilicon and the semiconductor epitaxial layer, wherein the oxide layer has a substantially uniform thickness. The gate layer is disposed in the trenches and located on the source polysilicon. The gate oxide layer is disposed between the gate layer and the source polysilicon, and between the gate layer and the semiconductor epitaxial layer. The source polysilicon is composed of a crown-shaped polysilicon and a polysilicon filling layer, wherein the crown-shaped polysilicon conforms to the trench to have a recess, and the polysilicon filling layer is disposed within the recess.

[0007] In the trench power semiconductor device according to an embodiment of the present invention, the recessed portion of the crown polysilicon described above has a profile that is wider at the top and narrower at the bottom.

[0008] In a trench power semiconductor device according to an embodiment of the present invention, the oxide layer further includes an extension located above the crown polysilicon, the extension having a structure that is thicker at the bottom and thinner at the top, so as to form an opening with an area larger than that of the recess.

[0009] In the trench power semiconductor device according to an embodiment of the present invention, the polysilicon filling layer of the source polysilicon described above may also fill the opening described above.

[0010] In the trench power semiconductor device according to an embodiment of the present invention, the ratio of the depth of the opening to the depth of the trench is 1:100 to 5:100.

[0011] In a trench power semiconductor device according to an embodiment of the present invention, the bottom surface of the opening described above may be an inclined surface that slopes from the top of the crown polysilicon toward the sidewall of the trench.

[0012] According to an embodiment of the present invention, a method for manufacturing a trench-type power semiconductor device includes the following steps: forming a semiconductor epitaxial layer on a semiconductor substrate, and forming a first trench in the semiconductor substrate. Then, forming an oxide layer on the surface of the semiconductor epitaxial layer and the inner surface of the first trench to form a second trench. Forming a first polysilicon layer on the semiconductor epitaxial layer, covering the oxide layer, wherein the thickness of the first polysilicon layer is less than half the width of the second trench. Next, etching back the first polysilicon layer to form a crown-shaped polysilicon in the second trench, exposing the oxide layer on the surface of the semiconductor epitaxial layer and the oxide layer at the top of the second trench. Forming a second polysilicon layer on the semiconductor epitaxial layer, filling the recesses of the crown-shaped polysilicon to form source polysilicon. Then, removing a portion of the source polysilicon to expose the oxide layer on the surface of the semiconductor epitaxial layer and a portion of the oxide layer within the first trench, and then removing the exposed oxide layer to expose a portion of the sidewalls of the first trench. Then, a gate oxide layer is formed on the surface of the source polysilicon and on the sidewalls of the exposed first trench, and a gate layer is formed on the gate oxide layer in the first trench.

[0013] In the manufacturing method according to an embodiment of the present invention, after forming a crown-shaped polysilicon in the second trench described above, the method may further include performing oxide wet etching to thin the exposed oxide layer and form an opening with an area larger than the recess of the crown-shaped polysilicon described above.

[0014] In the manufacturing method according to an embodiment of the present invention, the ratio of the depth of the opening to the depth of the first groove is 1:10 to 5:10.

[0015] In the manufacturing method according to an embodiment of the present invention, the step of forming a second polysilicon layer on a semiconductor epitaxial layer includes filling the opening described above with the second polysilicon layer.

[0016] In the manufacturing method according to an embodiment of the present invention, the bottom surface of the opening is an inclined surface that slopes from the top of the crown polycrystalline silicon toward the sidewall of the first trench.

[0017] In the manufacturing method according to an embodiment of the present invention, the step of removing a portion of the above-described source polysilicon includes re-etching the second polysilicon layer and a portion of the crown polysilicon.

[0018] In the manufacturing method according to an embodiment of the present invention, the angle between the sidewall of the opening and the surface of the semiconductor epitaxial layer is greater than 45° and less than 90°.

[0019] Based on the above, the source polysilicon in the trench power semiconductor device of the present invention is composed of crown polysilicon and a polysilicon filling layer. By using the outline of the crown polysilicon, gaps are generated in the subsequently filled polysilicon filling layer, or at least there are no gaps on its top. Therefore, no sharp corners are generated at the interface between the source polysilicon and the gate layer, which can solve the short circuit phenomenon between the source polysilicon and the gate layer, improve the breakdown voltage of the trench power semiconductor device, and improve the reliability of the trench power semiconductor device.

[0020] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0021] Figure 1 This is a cross-sectional schematic diagram of a trench power semiconductor device according to a first embodiment of the present invention.

[0022] Figure 2 This is a cross-sectional schematic diagram of a trench power semiconductor device according to a second embodiment of the present invention.

[0023] Figures 3A to 3F This is a cross-sectional schematic diagram of the manufacturing process of a trench power semiconductor device according to a third embodiment of the present invention.

[0024] Figures 4A to 4E This is a cross-sectional schematic diagram of the manufacturing process of a trench power semiconductor device according to a fourth embodiment of the present invention.

[0025] Explanation of reference numerals in the attached figures

[0026] 10, 20: Trench power semiconductor devices

[0027] 100, 300: Semiconductor substrate

[0028] 102, 302: Semiconductor epitaxial layer

[0029] 102s, 302s: Surface

[0030] 104. SP: Source-type polycrystalline silicon

[0031] 106, 304: Oxide layer

[0032] 108, 314: Gate layer

[0033] 110, 312: Gate oxide layer

[0034] 110a, 312a: First gate oxide portion

[0035] 110b, 312b: Second gate oxide portion

[0036] 112: Trench

[0037] 114, 306': Crown-shaped polycrystalline silicon

[0038] 116: Polycrystalline silicon filling layer

[0039] 118, 310: Depression

[0040] 200: Extension

[0041] 306: First polycrystalline silicon layer

[0042] 308: Second polysilicon layer

[0043] d1, d2, d3: Depth

[0044] O: Opening

[0045] t1, t1', t2, t3, t4: Thickness

[0046] T1: First trench

[0047] T2: Second trench

[0048] w1, w1', w2: Width

[0049] θ: included angle Detailed Implementation

[0050] The following description provides detailed examples and accompanying drawings, but these examples are not intended to limit the scope of the invention. Furthermore, the drawings are for illustrative purposes only and are not drawn to scale. For ease of understanding, the same components will be referred to by the same reference numerals in the following description.

[0051] Furthermore, the terms "includes," "including," and "has" used in the text are all open-ended terms, meaning "including but not limited to."

[0052] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various components, parts, regions, layers, and / or portions, these components, parts, regions, and / or portions should not be limited by these terms. These terms are used only to distinguish one component, part, region, layer, or portion from another. Therefore, the “first component,” “part,” “region,” “layer,” or “part” discussed below may be referred to as a second component, part, region, layer, or portion without departing from the teachings of this document.

[0053] Furthermore, directional terms mentioned in this document, such as "up" and "down," are only used to refer to the directions in the accompanying drawings and are not intended to limit the invention.

[0054] Figure 1 This is a cross-sectional schematic diagram of a trench power semiconductor device according to a first embodiment of the present invention.

[0055] Please refer to Figure 1 The trench-type power semiconductor device 10 includes a semiconductor substrate 100, a semiconductor epitaxial layer 102, a source polysilicon 104, an oxide layer 106, a gate layer 108, and a gate oxide layer 110. The semiconductor epitaxial layer 102 is grown on the surface of the semiconductor substrate 100 and has a trench 112. The source polysilicon 104 is disposed in the trench 112 of the semiconductor epitaxial layer 102, and the source polysilicon 104 is composed of a crown polysilicon 114 and a polysilicon filling layer 116. The crown polysilicon 114 and the trench 112 are conformally shaped to have a recess 118, and the polysilicon filling layer 116 is disposed within the recess 118. In this embodiment, the recess 118 of the crown-shaped polysilicon 114 has a profile that is wider at the top and narrower at the bottom; that is, the width w1 at the upper end of the recess 118 is greater than the width w2 at the lower end of the recess 118, for example, the ratio of width w1 to width w2 is between 1 and 1.5. If the ratio of width w1 to width w2 is greater than 1 and less than 1.5, it is beneficial for the polysilicon filling layer 116 to be filled. Figure 1 In this embodiment, although the cross-section at the bottom of the groove 112 is a right angle, the present invention is not limited thereto; in another embodiment, the cross-section at the bottom of the groove 112 may also be arc-shaped.

[0056] In the first embodiment, there may be gaps (not shown) inside the source polysilicon 104, but these gaps will only form in the narrower portion at the bottom of the polysilicon filling layer 116, and such gaps will not affect the interface profile between the gate layer 108 and the source polysilicon 104; that is, no sharp recesses will be formed on the surface of the source polysilicon 104. In a preferred embodiment, there are no gaps inside the entire source polysilicon 104.

[0057] Please continue to refer to Figure 1The oxide layer 106 is disposed between the source polysilicon 104 and the semiconductor epitaxial layer 102, wherein the oxide layer 106 has a substantially uniform thickness; that is, the oxide layer 106 is formed along the sidewalls and bottom surface of the trench 112, and the thickness t1 of the oxide layer 106 on the sidewalls of the trench 112 is substantially the same as the thickness t2 on the bottom surface of the trench 112. The gate layer 108 is disposed in the trench 112 and located on the source polysilicon 104, wherein the material of the gate layer 108 is, for example, polysilicon or metal. The gate oxide layer 110 includes a first gate oxide portion 110a and a second gate oxide portion 110b. The first gate oxide portion 110a is disposed between the gate layer 108 and the source polysilicon 104, and the second gate oxide portion 110b is disposed between the gate layer 108 and the semiconductor epitaxial layer 102. The second gate oxide portion 110b may extend from the sidewall of the trench 112 to the surface 102s of the semiconductor epitaxial layer 102, but the present invention is not limited thereto. In another embodiment, the second gate oxide portion 110b may be formed only on the sidewall of the trench 112.

[0058] In the first embodiment, since the semiconductor epitaxial layer 102 is typically made of silicon and the source polysilicon 104 is polysilicon, the difference in their oxidation rates results in the thickness t3 of the first gate oxide portion 110a being greater than the thickness t4 of the second gate oxide portion 110b. However, the material of the semiconductor epitaxial layer 102 is not limited to the above, and other materials known in the semiconductor field can be used instead. In one embodiment, the ratio of the thickness t3 of the first gate oxide portion 110a to the thickness t4 of the second gate oxide portion 110b is approximately 1:2.

[0059] In one embodiment, the semiconductor epitaxial layer 102 may be doped with dopants according to existing technology in the art to form doped regions (not shown) with different conductivity characteristics therein, serving as the source, body region, etc. of the trench power semiconductor device 10, but the present invention is not limited thereto. For example, the semiconductor substrate 100 may be an N+ silicon substrate, the semiconductor epitaxial layer 102 may be an N- epitaxial layer, and N+ doped regions (not shown) may be provided on the surface of the semiconductor epitaxial layer 102 on both sides of the gate layer 108 as source regions.

[0060] In one embodiment, the materials of oxide layer 106 and gate oxide layer 110 are, for example, silicon oxide, but the present invention is not limited thereto.

[0061] In this embodiment, since the source polysilicon 104 of the trench power semiconductor device 10 is composed of a crown polysilicon 114 and a polysilicon filling layer 116, and the contour of the crown polysilicon 114 helps to improve the trench filling capability of the polysilicon filling layer 116, gaps are avoided at the top of the source polysilicon 104; that is, no sharp recesses are generated on the surface of the source polysilicon 104, thus solving the short circuit phenomenon between the source polysilicon 104 and the gate layer 108, improving the breakdown voltage of the trench power semiconductor device 10, and improving reliability.

[0062] Figure 2 This is a cross-sectional schematic diagram of a trench power semiconductor device according to a second embodiment of the present invention, wherein the same reference numerals as in the first embodiment are used to indicate the same or similar parts and components, and the relevant content of the same or similar parts and components can also refer to the content of the first embodiment, and will not be repeated here.

[0063] exist Figure 2 In this embodiment, the oxide layer 106 further includes an extension 200 located above the crown polysilicon 114, and the extension 200 has a structure that is thicker at the bottom and thinner at the top, so as to form an opening O with an opening area larger than that of the recess 118. The angle θ between the sidewall of the opening O and the surface 102s of the semiconductor epitaxial layer 102 is, for example, greater than 45° and less than 90°. The polysilicon filling layer 116 of the source polysilicon 104 can also fill the opening O. In the second embodiment, the ratio of the depth d1 of the opening O to the depth d2 of the trench 112 is, for example, 1:100 to 5:100. For example, if the depth d2 of the trench 112 is 5 μm, then the depth d1 of the opening O can be between 0.1 μm and 5 μm. Moreover, due to the etching process, the bottom surface of the opening O is an inclined surface that slopes from the top of the crown polysilicon 114 toward the sidewall of the trench 112.

[0064] In this embodiment, since the extension 200 of the oxide layer 106 forms an opening O with a larger opening area, it facilitates the formation of the polysilicon filling layer 116 and fills the recess 118 in the crown polysilicon 114, thereby further ensuring that no gaps are formed in the source polysilicon 104. The specific formation method of the extension 200 of the oxide layer 106 will be described below.

[0065] Figures 3A to 3F This is a cross-sectional schematic diagram of the manufacturing process of a trench power semiconductor device according to a third embodiment of the present invention.

[0066] Please refer to Figure 3AA semiconductor substrate 300 is provided. The material of the semiconductor substrate 300 is, for example, silicon. A semiconductor epitaxial layer 302 is then formed on the semiconductor substrate 300 using an epitaxial process. In one embodiment, the semiconductor substrate 300 is an N+ silicon substrate and the semiconductor epitaxial layer 302 is an N- epitaxial layer.

[0067] Please continue to refer to Figure 3A A first trench T1 is formed in the semiconductor epitaxial layer 302. The method for forming the first trench T1 includes, for example, first forming a hard mask layer (not shown) on the surface 302s of the semiconductor epitaxial layer 302, then forming a patterned photoresist layer (not shown) using photolithography, and using the aforementioned patterned photoresist layer as a mask to etch the hard mask layer, transferring the pattern therein to the hard mask layer. Then, using the patterned hard mask layer as a mask, the semiconductor epitaxial layer 302 is etched to obtain the first trench T1.

[0068] Next, please refer to Figure 3B An oxide layer 304 is formed on the surface 302s of the semiconductor epitaxial layer 302 and the inner surface of the first trench T1, thereby forming the second trench T2. The method for forming the oxide layer 304 is, for example, thermal oxidation. Then, a first polysilicon layer 306 is formed on the semiconductor epitaxial layer 302, covering the oxide layer 304, wherein the thickness t1' of the first polysilicon layer 306 is less than half the width w1' of the second trench T2. Therefore, the first polysilicon layer 306 does not completely fill the second trench T2, but rather conforms to the shape of the second trench T2.

[0069] Next, please refer to Figure 3C , back etching Figure 3B The first polysilicon layer 306 forms a crown-shaped polysilicon layer 306' in the second trench T2, exposing the oxide layer 304 on the surface 302s of the semiconductor epitaxial layer 302 and the oxide layer 304 at the top of the second trench T2. In one embodiment, the above-mentioned back etching method is dry etching, and the etching gas used is, for example, chlorine (Cl2) at 15-130 sccm or hydrogen bromide (HBr) at 10-60 sccm, with an etching power of, for example, 150-600 W. Since there is a difference in the concentration of the etching gas at the top and bottom of the second trench T2, the first polysilicon layer 306 near the top of the second trench T2 will be removed first, while the first polysilicon layer 306 near the bottom of the second trench T2 is not easily removed. Therefore, the structure after back etching will be crown-shaped, and the recessed portion 310 therein will have a profile that is wider at the top and narrower at the bottom.

[0070] Then, please continue to refer to Figure 3CA second polysilicon layer 308 is formed on the semiconductor epitaxial layer 302, and the recesses 310 of the crown polysilicon 306' are filled to form source polysilicon SP. Since the recesses 310 in the crown polysilicon 114 have a profile that is wider at the top and narrower at the bottom, it helps to improve the trench filling capability of the second polysilicon layer 308 and avoids the formation of gaps at the top of the second polysilicon layer 308.

[0071] Next, please refer to Figure 3D The process involves removing a portion of the source polysilicon SP to expose the oxide layer 304 on the surface 302s of the semiconductor epitaxial layer 302 and a portion of the oxide layer 304 within the first trench T1. In one embodiment, the step of removing a portion of the source polysilicon SP includes etching back the second polysilicon layer 308 and a portion of the crown polysilicon 306', wherein the etching back method can refer to the previous step, but the invention is not limited thereto. Furthermore, the step of removing a portion of the source polysilicon SP may also include chemical mechanical planarization (CMP), but the invention is not limited thereto.

[0072] Then, please refer to Figure 3E Using source polysilicon SP as a mask, the exposed oxide layer 304 is removed to expose part of the sidewall of the first trench T1.

[0073] Then, please refer to Figure 3F A gate oxide layer 312 is formed on the surface of the source polysilicon SP and on the sidewalls of the exposed first trench T1. For example, a thermal oxidation reaction, such as furnace oxidation, can be performed to oxidize the semiconductor epitaxial layer 302 exposed in the first trench T1 to form a first gate oxide portion 312a on the surface of the source polysilicon SP and a second gate oxide portion 312b on the sidewalls of the first trench T1. Because the semiconductor epitaxial layer 302 is typically made of silicon and the source polysilicon SP is polycrystalline silicon, their oxidation rates differ, resulting in the first gate oxide portion 312a being thicker than the second gate oxide portion 312b.

[0074] Please continue to refer to Figure 3F A gate layer 314 is formed on the gate oxide layer 312 in the first trench T1. The step of forming the gate layer 314 is, for example, firstly depositing a layer of metal or polysilicon to fill the first trench T1, and then performing chemical mechanical planarization to remove the metal or polysilicon outside the first trench T1.

[0075] The manufacturing method of the third embodiment can avoid the formation of gaps on the top of the source polysilicon SP, thereby solving the short circuit phenomenon between the source polysilicon SP and the gate layer 314, and thus improving the breakdown voltage and reliability of the trench power semiconductor device.

[0076] Figures 4A to 4EThis is a cross-sectional schematic diagram of the manufacturing process of a trench power semiconductor device according to a fourth embodiment of the present invention, wherein the same reference numerals as in the third embodiment are used to indicate the same or similar parts and components, and the relevant content of the same or similar parts and components can also refer to the content of the third embodiment, and will not be repeated here.

[0077] Figure 4A It is a continuation of the third embodiment. Figure 3B Steps, Figure 4A The image shows a crown-shaped polysilicon 306' formed in the second trench T2 after back etching, exposing the oxide layer 304 on the surface 302s of the semiconductor epitaxial layer 302 and the oxide layer 304 on top of the second trench T2.

[0078] Then, please refer to Figure 4B Oxidation wet etching is performed to thin the exposed oxide layer 304 and form an opening O with an opening area larger than that of the recess 310 of the crown polysilicon 306'. In one embodiment, the above-mentioned oxide wet etching method is wet etching, and the etchant used is, for example, BOE (NH4F:HF), the etching temperature is, for example, 20°C to 50°C, and the etching time is, for example, 1 to 500 seconds. The angle θ between the sidewall of the opening O and the surface 302s of the semiconductor epitaxial layer 302 is, for example, greater than 45° and less than 90°. In a fourth embodiment, the ratio of the depth d3 of the opening O to the depth d2 of the first trench T1 is, for example, 1:10 to 5:10; the bottom surface of the opening O is an inclined surface that slopes from the top of the crown polysilicon 306' toward the sidewall of the first trench T1.

[0079] Then, please refer to Figure 4C A second polysilicon layer 308 is formed on the semiconductor epitaxial layer 302, filling the recess 310 and opening O of the crown polysilicon 306' to form the source polysilicon SP. Since there is an opening O with a larger opening area above the crown polysilicon 306', no gaps are formed in the second polysilicon layer 308 within the opening O during the formation of the second polysilicon layer 308 by means such as chemical vapor deposition. Preferably, no gaps are formed in the entire second polysilicon layer 308.

[0080] Next, please refer to Figure 4D First, a portion of the source polysilicon SP is removed to expose the oxide layer 304 on the surface 302s of the semiconductor epitaxial layer 302 and a portion of the oxide layer 304 within the first trench T1. Furthermore, in Figure 4DThe second polysilicon layer 308 in the opening O is still partially retained; however, the present invention is not limited thereto. In another embodiment, the step of removing part of the source polysilicon SP may involve removing the second polysilicon layer 308 in the opening O, or further removing the top sharp corner of the crown polysilicon 306'. Then, the exposed oxide layer 304 is removed to expose part of the sidewall of the first trench T1. The method for removing part of the source polysilicon SP can be referred to in the third embodiment, and will not be described again.

[0081] Finally, please refer to Figure 4E A gate oxide layer 312 is formed on the surface of the source polysilicon SP and on the sidewalls of the exposed first trench T1, and a gate layer 314 is formed on the gate oxide layer 312 in the first trench T1. The method for forming the gate oxide layer 312 (including the first gate oxide portion 312a and the second gate oxide portion 312b) and the gate layer 314 can be referred to the third embodiment, and therefore will not be described again.

[0082] In summary, the source polysilicon of the trench power semiconductor device of the present invention can be composed of a crown-shaped polysilicon and a polysilicon filling layer. Furthermore, an opening with a larger opening area can be formed above the crown-shaped polysilicon to improve the trench-filling capability of the subsequently filled polysilicon filling layer, resulting in a seamless source polysilicon or at least a seamless top layer. Therefore, the interface between the source polysilicon and the gate layer is flat and without sharp corners, preventing short circuits between the source polysilicon and the gate layer. This ensures that the breakdown voltage of the trench power semiconductor device is within a predetermined value, thereby improving reliability.

[0083] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A trench-type power semiconductor device, characterized in that, The trench power semiconductor device includes: Semiconductor substrate; A semiconductor epitaxial layer is formed on the semiconductor substrate, and the semiconductor epitaxial layer has trenches; Source polycrystalline silicon is disposed in the trench of the semiconductor epitaxial layer; An oxide layer is disposed between the source polysilicon and the semiconductor epitaxial layer, wherein the oxide layer has a uniform thickness; A gate layer is disposed in the trench and located on the source polysilicon; and A gate oxide layer is disposed between the gate layer and the source polysilicon and between the gate layer and the semiconductor epitaxial layer, wherein... The source polycrystalline silicon is composed of a crown-shaped polycrystalline silicon and a polycrystalline silicon filling layer. The crown-shaped polycrystalline silicon has a recessed portion that conforms to the shape of the trench, and the polycrystalline silicon filling layer is disposed in the recessed portion. The recessed portion of the crown-shaped polycrystalline silicon has a profile that is wider at the top and narrower at the bottom, and the ratio of the width of the upper end of the recessed portion to the width of the lower end of the recessed portion is between 1 and 1.

5.

2. The trench power semiconductor device according to claim 1, characterized in that, The oxide layer further includes an extension located above the crown-shaped polycrystalline silicon. The extension has a structure that is thicker at the bottom and thinner at the top, so as to form an opening area larger than that of the recess.

3. The trench power semiconductor device according to claim 2, characterized in that, The polysilicon filling layer of the source polysilicon further fills the opening.

4. The trench power semiconductor device according to claim 2, characterized in that, The angle between the sidewall of the opening and the surface of the semiconductor epitaxial layer is greater than 45° and less than 90°.

5. The trench power semiconductor device according to claim 2, characterized in that, The ratio of the depth of the opening to the depth of the trench is 1:100 to 5:

100.

6. The trench power semiconductor device according to claim 2, characterized in that, The bottom surface of the opening is an inclined surface that slopes from the top of the crown-shaped polycrystalline silicon toward the sidewall of the trench.

7. A method for manufacturing a trench-type power semiconductor device, characterized in that, The method for manufacturing the trench-type power semiconductor device includes: Forming a semiconductor epitaxial layer on a semiconductor substrate; A first trench is formed in the semiconductor epitaxial layer; An oxide layer is formed on the surface of the semiconductor epitaxial layer and the inner surface of the first trench to form a second trench; A first polysilicon layer is formed on the semiconductor epitaxial layer to cover the oxide layer, wherein the thickness of the first polysilicon layer is less than half the width of the second trench; The first polysilicon layer is etched back to form a crown-shaped polysilicon in the second trench, exposing the oxide layer on the surface of the semiconductor epitaxial layer and the oxide layer at the top of the second trench, wherein the recess of the crown-shaped polysilicon has a profile that is wider at the top and narrower at the bottom, and the ratio of the width of the upper end of the recess to the width of the lower end of the recess is between 1 and 1.

5. A second polysilicon layer is formed on the semiconductor epitaxial layer and filled into the recess of the crown polysilicon to form a source polysilicon. A portion of the source polysilicon is removed to expose the oxide layer on the surface of the semiconductor epitaxial layer and a portion of the oxide layer within the first trench; Remove the exposed oxide layer to expose a portion of the sidewalls of the first trench; A gate oxide layer is formed on the surface of the source polysilicon and on the sidewalls of the exposed first trench; and A gate layer is formed on the gate oxide layer within the first trench.

8. The method for manufacturing a trench-type power semiconductor device according to claim 7, characterized in that, After forming the crown-shaped polysilicon in the second trench, the process further includes performing oxide wet etching to thin the exposed oxide layer and form an opening with an area larger than that of the recess in the crown-shaped polysilicon.

9. The method for manufacturing a trench-type power semiconductor device according to claim 8, characterized in that, The angle between the sidewall of the opening and the surface of the semiconductor epitaxial layer is greater than 45° and less than 90°.

10. The method for manufacturing a trench-type power semiconductor device according to claim 8, characterized in that, The ratio of the depth of the opening to the depth of the first groove is 1:10 to 5:

10.

11. The method for manufacturing a trench-type power semiconductor device according to claim 8, characterized in that, The bottom surface of the opening is an inclined surface that slopes from the top of the crown-shaped polycrystalline silicon toward the sidewall of the first trench.

12. The method for manufacturing a trench-type power semiconductor device according to claim 8, characterized in that, The step of forming the second polysilicon layer on the semiconductor epitaxial layer includes filling the opening with the second polysilicon layer.

13. The method for manufacturing a trench-type power semiconductor device according to claim 7, characterized in that, The step of removing a portion of the source polysilicon includes: etching back the second polysilicon layer and a portion of the crown polysilicon.

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