MOSFET series drive signal delay voltage equalization circuit based on FPGA delay chain and control method thereof

Abstract

The application provides a MOSFET series drive signal delay voltage equalization circuit of a delay chain and a control method thereof, and belongs to the technical field of power electronic conversion. The MOSFET series voltage equalization circuit is usually used in medium and high voltage high power power electronic equipment, and needs to reduce the MOSFET series unbalanced voltage to ensure the normal operation of the circuit. The MOSFET series drive signal delay voltage equalization control method collects the drain-source voltage information of the MOSFET, modulates the off time of the drive signal of the MOSFET, compensates the MOSFET series voltage imbalance through delay, and realizes the MOSFET series voltage equalization. The application has high-resolution delay compensation, so that the delay voltage equalization control has high-precision voltage regulation capability, and has flexibility and expandability.

Description

Technical Field

[0001] This invention belongs to the field of power electronic conversion technology, specifically relating to a MOSFET series drive signal delay voltage equalization circuit, and proposing a drive signal delay method based on FPGA delay chain for the control of drive signals. Background Technology

[0002] In the field of flexible DC power transmission and distribution, medium- and high-power power electronic equipment is the core component. These equipment can adjust power quality and improve grid transmission stability. The power and performance requirements of medium- and high-power power electronic equipment are constantly increasing, and the voltage withstand capability requirements of power devices are also rising accordingly. However, the voltage levels of current power devices cannot meet the needs of high-power equipment. Using power devices in series is a simple way to solve the problem of insufficient voltage withstand capability. In high-power applications, using low-voltage power devices in series can not only improve the voltage withstand level but also save costs and simplify circuit topology, making it of broad research significance.

[0003] The biggest problem with using power devices in series is uneven voltage distribution. In practical applications, factors such as parasitic parameters and differences in the device's own parameters can lead to uneven voltage distribution, which can cause device damage in severe cases. Currently, voltage equalization methods for MOSFET series connections are mainly divided into power-side voltage equalization schemes and gate-side voltage equalization schemes. Power-side voltage equalization schemes mainly involve connecting a buffer circuit in parallel across the drain and source terminals to suppress voltage and current spikes generated during dynamic processes, thus achieving dynamic voltage equalization. Gate-side voltage equalization schemes are mainly divided into single-drive capacitor coupling control, active gate voltage control, and drive signal delay control. Single-drive capacitor coupling control provides a drive signal to the bottom MOSFET through a single drive, while other MOSFETs are turned on and off through coupling capacitors. This method has the problem of not being able to control the MOSFET turn-off time. Active gate voltage control uses the voltage across the MOSFET as feedback to adjust the gate drive voltage to achieve voltage equalization control. However, during the switching dynamic process, the MOSFET operates in the active region, increasing switching losses. Drive signal delay control is a control method proposed to address the voltage imbalance caused by delay differences in MOSFET drives. It achieves voltage balance by controlling the delay time of the drive signals of the two gate drivers. The delay step size is closely related to the accuracy of voltage balance. However, current drive signal delay control methods are limited by the delay step size and do not have high-precision voltage balance capabilities. In addition, the use of delay chips reduces the flexibility and scalability of the system. Summary of the Invention

[0004] To address the aforementioned shortcomings in existing technologies, this invention proposes a MOSFET series drive signal delay and voltage equalization control method based on an FPGA delay chain. This method achieves high-precision drive signal delay, resulting in higher voltage balance accuracy for the series MOSFETs. Furthermore, the use of a field-programmable array (FPGA) satisfies the system's flexibility and scalability.

[0005] To achieve the above-mentioned objectives, the technical solution of the present invention is as follows:

[0006] A MOSFET series drive signal delay voltage equalization circuit based on a Field Programmable Gate Array (FPGA) delay chain includes: a series MOSFET group, a delay signal control unit, N drive units, N voltage sampling units, and N circuit protection units;

[0007] The series MOSFET group consists of N MOSFETs of the same type connected in series, where N is a natural number greater than or equal to 2;

[0008] The N driving units are connected to the gates of each MOSFET, receive driving signals, and control the connected MOSFETs to turn on and off.

[0009] The N voltage sampling units are connected to the source and drain of each MOSFET to sample the drain-source voltage of each MOSFET and collect the voltage across each MOSFET.

[0010] The N circuit protection units are connected in parallel with each MOSFET to protect each MOSFET;

[0011] The delay signal control unit uses an FPGA as its control core. It collects the voltage information across each MOSFET through N voltage sampling units and calculates the delay time ΔT of each MOSFET drive signal. N The delay chain is based on the delay time ΔT N Adjust the PWM signal to send turn-off drive signals to the drive unit in sequence, thereby achieving voltage balance of the series MOSFETs;

[0012] Furthermore, the delay signal control unit includes a delay chain and a PWM modulation unit. The output of the PWM modulation unit is connected to the input of the delay chain, and the timing of the PWM signal output to the drive unit is adjusted through the delay chain. The delay chain contains M delay units, where M is a natural number greater than 1. Each delay unit includes a NAND gate and a 2-to-1 data selector. One input pin of the NAND gate serves as the PWM signal input of the delay chain, called the PWM input. The other input pin is determined by the delay time ΔT of the drive signal. N The delay time input is determined, and the output of the NAND gate is connected to the selection terminal of a 2-to-1 data selector. The signal at input 1 (in1) of the 2-to-1 data selector for all delay units is always 1. The signal at input 2 (in2) of the 2-to-1 data selector for the first delay unit is always 0, and its output is connected to input 2 (in2) of the 2-to-1 data selector for the second delay unit. Other delay units are connected sequentially, i.e., the output of the (M-1)th delay unit is connected to input 2 (in2) of the 2-to-1 data selector for the Mth delay unit. The output of the Mth delay unit outputs the delayed PWM signal. The delay time t of a single delay unit is... step The time it takes for the input signal to pass through a 2-to-1 data selector.

[0013] Another objective of this invention is to provide a MOSFET series drive signal delay equalization control method based on the MOSFET series drive signal delay equalization circuit described above, wherein the delay of the turn-off drive signals of other MOSFETs is adjusted based on the turn-off drive signal of the first MOSFET1.

[0014] Furthermore, a method for delaying and equalizing voltage of MOSFET series drive signals based on an FPGA delay chain is provided, wherein the Nth MOSFET... N The specific implementation steps for delaying the shutdown drive signal are as follows:

[0015] 1) Voltage sampling unit 1 and voltage sampling unit N sample MOSFET1 and MOSFET2 respectively. N The voltage V across the terminals ds1 With V dsN V ds1 With V dsN Voltage information is converted by an ADC and input into a delay signal control unit;

[0016] 2) The delay signal control unit receives signals from MOSFET1 and MOSFET2. N Based on the voltage information at both ends, the voltage difference ΔV = V between the two MOSFETs is calculated. ds1 -V dsN If ΔV>0, increase the MOSFET size. NThe delay time ΔT of the turn-off drive signal N If ΔV < 0, reduce the MOSFET size. N The delay time ΔT of the turn-off drive signal N If ΔV = 0, then keep the MOSFET running. N The delay time ΔT of the turn-off drive signal N constant;

[0017] 3) Delay time ΔT for turning off the drive signal N As the input signal of the delay chain, calculate Where t step Operators representing the delay time of a single delay unit This means taking an integer not greater than n, setting the delay time input signal of the NAND gate in the nth delay unit to 1, and setting the delay time input signal of the NAND gate in other delay units to 0;

[0018] 4) The PWM modulation unit of the delay signal control unit sends a PWM signal to the delay chain. The output of the NAND gate of the nth delay unit is a signal of 1, and the outputs of the NAND gates of the other delay units are signals of 0. This makes the selection signal of the nth 2-to-1 data selector 1, and the selection signals of the other 2-to-1 data selectors 0. Then, the signal 1 of the nth 2-to-1 data selector is output to the (n+1)th 2-to-1 data selector. The signal is transmitted sequentially until the Mth 2-to-1 data selector. Therefore, starting from the nth delay unit, the PWM signal passes through n delay units and is output from the output of the Mth delay unit. The PWM signal is delayed by n*t. step ;

[0019] 5) Input the PWM signal obtained in step 4 into the drive unit N to drive the MOSFET. N When the signal is high-level to turn on and low-level to turn off, the drive signal is delayed by n*t relative to the drive signal of MOSFET1. step The time.

[0020] Furthermore, the aforementioned MOSFET series drive signal delay equalization control method based on FPGA delay chain repeatedly adjusts the turn-off drive signal delay of the second to Nth MOSFETs in different switching cycles, so that the first MOSFET1 turns off earliest, and the other MOSFETs turn off after a corresponding delay time, thereby achieving equalization of the turn-off voltage of the series MOSFET group.

[0021] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0022] (1) Compared with the existing MOSFET drive signal delay control method, the present invention has a higher resolution delay step size, thereby achieving a higher precision voltage balance effect.

[0023] (2) Compared with the existing MOSFET drive signal delay control method, the delay chain based on FPGA does not require additional hardware auxiliary circuits, and has better flexibility and scalability.

[0024] (3) The present invention improves the voltage balance regulation accuracy of series MOSFETs, and is applicable to medium and high voltage high power electronic equipment, providing greater possibilities for the series use of medium and high voltage devices. Attached Figure Description

[0025] Figure 1 A schematic diagram of a MOSFET series drive signal delay and voltage equalization circuit based on an FPGA delay chain provided by the present invention.

[0026] Figure 2 A schematic diagram of a delay signal control unit based on an FPGA delay chain provided by the present invention.

[0027] Figure 3 A system architecture diagram based on an FPGA delay chain is provided for this invention.

[0028] Figure 4 A timing diagram based on an FPGA delay chain is provided for this invention.

[0029] Figure 5 MOSFET N Schematic diagram of voltage equalization effect with MOSFET1 during delay Detailed Implementation

[0030] To describe the present invention more specifically and to make its objectives, technical solutions, and advantages clearer, the present invention will be further described in detail below with reference to the accompanying drawings.

[0031] like Figure 1 As shown, this invention provides a MOSFET series drive signal delay voltage equalization circuit based on an FPGA delay chain. This circuit includes a series MOSFET group consisting of N identical MOSFETs connected in series, a delay signal control unit, N drive units, N voltage sampling units, and N circuit protection units. Each drive unit, voltage sampling unit, and circuit protection unit is connected one-to-one with one of the N MOSFETs, where N is a positive integer greater than or equal to 2. The functions of the drive units, voltage sampling units, and circuit protection units are as follows:

[0032] The drive unit receives drive signals and controls the connected MOSFETs to turn on and off.

[0033] The voltage sampling unit samples the drain-source voltage of each MOSFET and collects the voltage across each MOSFET.

[0034] The circuit protection unit provides overvoltage and overcurrent protection for each MOSFET.

[0035] The delay signal control unit, as the main control structure of the system, uses an FPGA as its control core. It collects the drain-source voltage information of each MOSFET acquired by the voltage sampling unit and calculates the appropriate delay time ΔT for each drive unit. N The delayed turn-off signal is sent to each drive unit through a delay chain to control the corresponding MOSFET to turn off, thereby achieving voltage balance of the series MOSFETs.

[0036] like Figure 2 As shown, the delay signal control unit includes a delay chain and a PWM modulation unit. The PWM modulation unit includes a counter and a comparator. It counts using a clock signal, incrementing the counter value with each clock signal. The count value is compared with a preset switching frequency value in the comparator to output a PWM signal of a specific frequency. The output of the PWM modulation unit is connected to the input of the delay chain, which adjusts the timing of the PWM signal output to the drive unit.

[0037] The specific structure of the delay chain is as follows: Figure 3 As shown, it contains M delay units, where M is a natural number greater than 1. Each delay unit contains a NAND gate and a 2-to-1 data selector. One input pin of the NAND gate serves as the PWM signal input terminal of the delay chain, called the PWM input terminal. The other input pin signal is determined by the delay time ΔT of the drive signal. N The delay time input is determined, and the delay time ΔT is defined as follows: N The relationship between the delay time inputs of the corresponding NAND gates is shown in Table 1. The output of the NAND gate is connected to the selection terminal of a 2-to-1 data selector. The signal at input terminal in1 of the 2-to-1 data selector 1 of all delay units is always 1, the signal at input terminal in2 of the 2-to-1 data selector 2 of the first delay unit is always 0, and the output is connected to input terminal in2 of the 2-to-1 data selector 2 of the second delay unit. The other delay units are connected sequentially, that is, the output of the (M-1)th delay unit is connected to input terminal in2 of the 2-to-1 data selector 2 of the Mth delay unit, and the output of the Mth delay unit outputs the delayed PWM signal. The delay time t of a single delay unit is... step The time it takes for the input signal to pass through a 2-to-1 data selector.

[0038]

[0039] Table 1

[0040] like Figure 4The timing diagram shown illustrates the principle behind this delay chain's delay of the input PWM signal:

[0041] In each switching cycle, the counter begins counting with the FPGA's clock cycle. When the counter reaches a set value, the comparator generates a PWM signal, which is input to the delay chain. In the delay chain, the signal is delayed by one delay step (t) each time it passes through a logic element. step It indicates. In Figure 4 In this process, the PWM drive signal passes through four logic elements, with a total delay of 4t. step .

[0042] Based on the aforementioned MOSFET series drive signal delay voltage equalization circuit, the following describes in detail a specific implementation method for MOSFET series drive signal delay voltage equalization control based on an FPGA delay chain, specifically for the Nth MOSFET. N The specific implementation steps for delaying the shutdown drive signal are as follows:

[0043] First, voltage sampling unit 1 and voltage sampling unit N sample MOSFET1 and MOSFET2 respectively. N The voltage V across the terminals ds1 With V dsN V ds1 With V dsN The voltage information is converted by the ADC and input to the delay signal control unit. The delay signal control unit receives data from MOSFET1 and MOSFET2. N Based on the voltage information at both ends, the voltage difference ΔV = V between the two MOSFETs is calculated. ds1 -V dsN If ΔV>0, increase the MOSFET size. N The delay time ΔT of the turn-off drive signal N If ΔV < 0, reduce the MOSFET size. N The delay time ΔT of the turn-off drive signal N If ΔV = 0, then keep the MOSFET running. N The delay time ΔT of the turn-off drive signal N Unchanged. The delay time ΔT for turning off the drive signal remains unchanged. N The input is fed into the delay chain and calculated. Where t step Operators representing the delay time of a single delay unit Let n be an integer not greater than n. Set the input signal of the NAND gate in the nth delay unit to 1, and the input signals of the NAND gates in other delay units to 0, as shown in Table 1. The PWM modulation unit of the delay signal control unit sends a PWM signal with a specific switching frequency to the delay chain. The NAND gate output of the nth delay unit outputs a signal of 1, and the NAND gate outputs of other delay units output signals of 0. This makes the selection signal of the nth 2-to-1 data selector 1, and the selection signals of other 2-to-1 data selectors 0. Then, the signal 1 from the nth 2-to-1 data selector is output to the (n+1)th 2-to-1 data selector. The signal is transmitted sequentially until the Mth 2-to-1 data selector. Therefore, starting from the nth delay unit, the PWM signal passes through n delay units and is output from the output of the Mth delay unit. The PWM signal is delayed by n*t. step Ultimately, the delay was n*t. step The PWM signal is output to the Nth drive unit, and the original PWM signal is output to the first drive unit, causing the MOSFET to... N The drive signal relative to MOSFET1 is delayed by n*t. step Then shut down.

[0044] like Figure 5 As shown, the Nth device MOSFET is given. N The voltage balancing effect between the first device MOSFET1 and the first device MOSFET is due to the MOSFET N The received turn-off drive signal is delayed by td relative to the turn-off signal received by MOSFET1, resulting in a faster voltage rise rate for the MOSFET. N The voltage after turn-off is the same as that of MOSFET1, which has a slower voltage rise rate, after turn-off, thus achieving voltage balance of the series MOSFET group.

[0045] The turn-off drive signal delay of the second to Nth MOSFETs is repeatedly adjusted in different switching cycles. Taking the first device MOSFET1 as the reference, the other MOSFETs are turned off after a corresponding delay time, so as to achieve voltage equalization when the series MOSFET group is turned off.

[0046] The embodiments described above are merely preferred embodiments of the present invention and are not intended to limit the invention. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, all technical solutions obtained through equivalent substitution or transformation fall within the protection scope of the present invention.

Claims

1. A MOSFET series drive signal delay voltage equalization circuit based on a Field Programmable Gate Array (FPGA) delay chain and its control method, characterized in that, The FPGA-based MOSFET series drive signal delay voltage equalization circuit includes: a series MOSFET group, a delay signal control unit, N drive units, N voltage sampling units, and N circuit protection units; The series MOSFET group consists of N MOSFETs of the same type connected in series, where N is a natural number greater than or equal to 2; The N driving units are connected to the gates of each MOSFET, receive driving signals, and control the connected MOSFETs to turn on and off. The N voltage sampling units are connected to the source and drain of each MOSFET to sample the source and drain voltages of each MOSFET and collect the source and drain voltages of each MOSFET. The N circuit protection units are connected in parallel with each MOSFET to protect each MOSFET; The aforementioned delay signal control unit uses an FPGA as its control core. It collects the voltage information across each MOSFET through N voltage sampling units and calculates the delay time ∆T of the drive signal for each MOSFET. N According to the delay time ∆T N Adjust the PWM signal to send turn-off drive signals to the drive unit in sequence, thereby achieving voltage balance of the series MOSFET turn-off. The delay signal control unit includes a delay chain and a PWM modulation unit. The output of the PWM modulation unit is connected to the input of the delay chain, and the timing of the PWM signal output to the drive unit is adjusted through the delay chain. The delay chain contains M delay units, where M is a natural number greater than 1. Each delay unit includes a NAND gate and a 2-to-1 data selector. One input pin of the NAND gate serves as the PWM signal input of the delay chain, called the PWM input. The other input pin is determined by the delay time ∆T of the drive signal. N The delay time input is determined by the NAND gate; the output of the NAND gate is connected to the selection terminal of a 2-to-1 data selector. The signal at input 1 (in1) of the 2-to-1 data selector for all delay units is always 1. The signal at input 2 (in2) of the 2-to-1 data selector for the first delay unit is always 0. Its output is connected to input 2 (in2) of the 2-to-1 data selector for the second delay unit. Other delay units are connected sequentially, i.e., the output of the (M-1)th delay unit is connected to input 2 (in2) of the 2-to-1 data selector for the Mth delay unit. The output of the Mth delay unit outputs the delayed PWM signal. The delay time t of a single delay unit is... step The time it takes for the input signal to pass through a 2-to-1 data selector.

2. The method for delaying and equalizing voltage of MOSFET series drive signals based on an FPGA delay chain according to claim 1, characterized in that, The turn-off drive signal of the first MOSFET1 is used as a reference, and the turn-off drive signals of other MOSFETs are adjusted by delay.

3. The MOSFET series drive signal delay voltage equalization control method based on FPGA delay chain according to claim 1, wherein the Nth MOSFET N The specific implementation steps for delaying the shutdown drive signal are as follows: 1) Voltage sampling unit 1 and voltage sampling unit N sample MOSFET1 and MOSFET2 respectively. N The voltage V across the terminals ds1 With V dsN V ds1 With V dsN Voltage information is converted by an ADC and input into a delay signal control unit; 2) The delay signal control unit receives signals from MOSFET1 and MOSFET2. N Based on the voltage information at both ends, the voltage difference ∆V = V between the two MOSFETs is calculated. ds1 -V dsN If ∆V>0, increase the MOSFET size. N The delay time ∆T of the turn-off drive signal N If ∆V < 0, reduce the MOSFET size. N The delay time ∆T of the turn-off drive signal N If ∆V=0, then keep the MOSFET. N The delay time ∆T of the turn-off drive signal N constant; 3) Delay time ∆T for turning off the drive signal N As the input signal of the delay chain, calculate , where t step Operators representing the delay time of a single delay unit This means taking an integer not greater than n, setting the delay time input signal of the NAND gate in the nth delay unit to 1, and setting the delay time input signal of the NAND gate in other delay units to 0; 4) The PWM modulation unit of the delay signal control unit sends a PWM signal to the delay chain. The output of the NAND gate of the nth delay unit outputs a signal of 1, and the outputs of the NAND gates of the other delay units output signals of 0. This makes the selection signal of the nth 2-to-1 data selector 1, and the selection signals of the other 2-to-1 data selectors 0. Then, the signal 1 output by the nth 2-to-1 data selector is output to the (n+1)th 2-to-1 data selector. The signal is transmitted sequentially until the Mth 2-to-1 data selector. Therefore, starting from the nth delay unit, the PWM signal passes through n delay units and is output from the output of the Mth delay unit. The PWM signal is delayed by n*t. step ; 5) Input the PWM signal obtained in step 4 into the drive unit N to drive the MOSFET. N When the signal is high-level to turn on and low-level to turn off, the drive signal is delayed by n*t relative to the drive signal of MOSFET1. step The time.

4. The method for delaying and equalizing voltage of MOSFET series drive signals based on an FPGA delay chain according to claim 1, characterized in that, By repeatedly adjusting the turn-off drive signal delay of the second to Nth MOSFETs in different switching cycles, the first MOSFET1 is turned off earliest, and the other MOSFETs are turned off after a corresponding delay time, thus achieving voltage equalization during the turn-off of the series MOSFET group.

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