A modulation method for reducing the common-mode voltage of an H8 inverter

Abstract

The present invention discloses a modulation method for reducing the common-mode voltage of an H8 inverter based on an effective fully open-circuit zero vector. This method replaces the traditional zero-vector modulation method by maintaining the effective switching state of the three-phase bridge arms by completely shutting down two switches on the DC bus, thereby achieving a common-mode voltage of 0V under the action of the zero vector. Since the switching sequence designed in this invention ensures that the switching state of the three-phase bridge arms remains unchanged when the two switches on the DC bus are activated, there is no common-mode voltage spike problem caused by the dead time of the three-phase bridge arms.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, specifically to a modulation method for reducing the common-mode voltage of an H8 inverter. Background Technology

[0002] Two-level voltage source inverters (VSIs) are widely used in photovoltaic grid-connected systems and motor drives due to their advantages such as small size, low cost, and high efficiency. However, the common-mode voltage (CMV) characteristics they exhibit in applications bring some adverse effects to the motor and the power grid. Under the influence of common-mode voltage, charge gradually accumulates on the motor shaft. When it reaches a certain level, it can break down the insulating lubricant, generating shaft current and leakage current, while also producing electromagnetic interference (EMI), leading to driver failure or interference with other surrounding electronic equipment. In addition, because there are multiple common-mode impedance paths in the motor, the high-frequency changing common-mode voltage may generate shaft current in the motor bearings. Excessive common-mode voltage can cause excessive shaft voltage and shaft current, leading to motor overheating and ultimately bearing damage.

[0003] Currently, CMV reduction solutions are mainly based on hardware methods, using passive or active filters to mitigate the adverse effects of CMV on two-level three-phase inverters. Current CMV reduction methods based on PWM improvements avoid directly using the zero vector by employing different combinations of effective vectors, thereby suppressing common-mode voltage jumps. However, these modulation optimization methods inevitably sacrifice voltage utilization or output current harmonic characteristics to varying degrees, and system losses increase accordingly with the number of switching cycles.

[0004] The H8 inverter is a device that converts direct current into alternating current. Existing common-mode voltage suppression methods based on the H8 inverter work by adding two switching transistors and coordinating with the two-level VSI zero vector. The common-mode voltage is reduced by adding a parallel capacitor to the switching transistors or by using an improved modulation method. This suppression method based on the traditional zero vector increases additional hardware costs or switching losses. Summary of the Invention

[0005] This invention addresses the shortcomings of existing technologies and proposes a modulation method for reducing the common-mode voltage of H8 inverters based on the diode freewheeling characteristics of switching devices. This method can be applied to photovoltaic and other CMV-sensitive systems.

[0006] The technical solution of the present invention is as follows:

[0007] A modulation method for reducing the common-mode voltage of an H8 inverter, characterized by: effective fully open-circuit zero vector V open_activeIn this state, the upper and lower switches S7 and S8 on the DC bus of the H8 inverter are in the off state, and the switches S1, S3, and S5 on the upper arm of the A, B, and C phases of the H8 inverter and the switches S2, S4, and S6 on the lower arm are in the effective vector action state; the output current i A >0, natural freewheeling occurs between the load and the switching transistor; common-mode voltage V cm It equals 0V.

[0008] Let 1 represent the switch state as on and 0 represent the switch state as off. Each voltage vector V x Corresponding to a switching state, x is the binary number of the switching state S1S3S5, x = 1...6; the effective fully open-circuit zero vector V open_active Under these conditions, the switching sequence of the switching states in each sector within one carrier cycle is as follows:

[0009] Sector 1: 00-V4(00-100)--11-V4(11-100)--11-V6(11-110)--00-V6(00-110)--11-V6(11-110)--11-V4(11-100)--00-V4(00-100); Sector 2: 00-V2(00-010)--11-V2(11-010)--11-V6(11-110)--00-V 6(00-110)--11-V6(11-110)--11-V2(11-010)--00-V2(00-010); Third sector: 00-V2(00-010)--11-V2(11-010)--11-V3(11-011)--00-V3(00-011)--11-V3(11-011)--11-V2(11-010)--00-V2(00-010); Fourth sector: 00-V1(00-001)--11-V1(11-001)--11-V3(11-011)--00-V3(00-011)--11-V3(11-011)--11-V1(11-001)--00-V1(00-001); Fifth sector: 00-V1(00-001)--11-V1(11-001)--11-V5(11-101)--00-V 5(00-101)--11-V5(11-101)--11-V1(11-001)--00-V1(00-001); Sixth sector: 00-V4(00-100)--11-V4(11-100)--11-V5(11-101)--00-V5(00-101)--11-V5(11-101)--11-V4(11-100)--00-V4(00-100).

[0010] In one carrier cycle, the effective fully open-circuit zero vector V open_active Arranged in the middle and on both sides of a cycle.

[0011] The junction capacitances of the upper and lower switching transistors S7 and S8 on the DC bus of the H8 inverter are equal, and the DC power supply voltage V dc The common-mode voltage V is shared equally by the two switching transistors. cm equals V dc / 2.

[0012] The technical effects of this invention are as follows:

[0013] This invention discloses a modulation method for reducing the common-mode voltage of an H8 inverter based on an effective fully open-circuit zero vector. This method replaces the traditional zero vector by maintaining the effective switching state of the three-phase bridge arms by completely shutting down two switches on the DC bus, thus achieving a common-mode voltage of 0V under the action of the zero vector. Because the switching sequence designed in this invention ensures that the switching state of the three-phase bridge arms remains unchanged when the two switches on the DC bus are activated, the common-mode voltage spike problem caused by the dead time of the three-phase bridge arms is eliminated.

[0014] This invention experimentally compares the common-mode voltage, operating efficiency, and output current quality of the modulation method presented in this paper, traditional VSI, and two other open-circuit zero-vector methods. The H8 inverter of this invention can effectively reduce CMV under zero-vector conditions over a wide modulation ratio range without affecting output current quality, while also ensuring high system efficiency. Therefore, compared with existing H8 inverter common-mode rejection strategies, it has superior performance and greater application value. Attached Figure Description

[0015] Figure 1 Topology diagram of H8 inverter

[0016] Figure 2(a) shows the output current i A When <0, V open_active Schematic diagram of the continuous flow process

[0017] Figure 2(b) shows the output current i A When V > 0, open_active Schematic diagram of the continuous flow process

[0018] Figure 3 For V open_active Simplified common-mode circuit diagram

[0019] Figure 4 This is a schematic diagram of the first sector vector synthesis based on effective fully open-circuit zero vector modulation according to the present invention.

[0020] Figure 5 This is a schematic diagram of the switching sequence and common-mode voltage within the first sector based on effective fully open-circuit zero-vector modulation according to the present invention.

[0021] Figure 6 This is a schematic diagram of the second sector vector synthesis based on effective all-open-path zero vector modulation according to the present invention.

[0022] Figure 7 This is a schematic diagram of the switching sequence and common-mode voltage within the second sector based on effective fully open-circuit zero-vector modulation, as per the present invention.

[0023] Figure 8 This is a schematic diagram of the third sector vector synthesis based on effective fully open-circuit zero vector modulation according to the present invention.

[0024] Figure 9 This is a schematic diagram of the switching sequence and common-mode voltage in the third sector based on effective fully open-circuit zero-vector modulation according to the present invention.

[0025] Figure 10 This is a schematic diagram of the fourth sector vector synthesis based on effective fully open-circuit zero vector modulation according to the present invention.

[0026] Figure 11 This is a schematic diagram of the switching sequence and common-mode voltage in the fourth sector based on effective fully open-circuit zero-vector modulation according to the present invention.

[0027] Figure 12 This is a schematic diagram of the fifth sector vector synthesis based on effective fully open-circuit zero vector modulation according to the present invention.

[0028] Figure 13 This is a schematic diagram of the switching sequence and common-mode voltage in the fifth sector based on effective fully open-circuit zero-vector modulation according to the present invention.

[0029] Figure 14 This is a schematic diagram of the sixth sector vector synthesis based on effective fully open-circuit zero vector modulation according to the present invention.

[0030] Figure 15 This is a schematic diagram of the switching sequence and common-mode voltage in the sixth sector based on effective fully open-circuit zero-vector modulation according to the present invention.

[0031] Figure 16 The equivalent circuit diagram of this invention based on effective all-on zero vector modulation is shown below.

[0032] Figure 17(a) shows the simulated waveform of traditional SVPWM modulation at a modulation ratio m = 0.8.

[0033] Figure 17(b) shows the simulated waveform of the modulation method of the present invention at a modulation ratio m = 0.8.

[0034] Figure 17(c) shows the simulated waveform of the open-circuit zero vector (00-111, 00-000) modulation method at a modulation ratio m = 0.8.

[0035] Figure 17(d) shows the simulated waveform of the open-circuit zero vector (01-111, 10-000) modulation method at a modulation ratio m = 0.8.

[0036] Figure 18(a) shows the experimental waveforms of traditional SVPWM modulation at a modulation ratio m = 0.8.

[0037] Figure 18(b) shows the experimental waveforms of the modulation method of the present invention at a modulation ratio m = 0.8.

[0038] Figure 18(c) shows the experimental waveforms of the open-circuit zero vector (00-111, 00-000) modulation method at a modulation ratio m = 0.8.

[0039] Figure 18(d) shows the experimental waveforms of the open-circuit zero vector (01-111, 10-000) modulation method at a modulation ratio m = 0.8.

[0040] Figure 19(a) shows the experimental waveforms of traditional SVPWM modulation at a modulation ratio m = 0.2.

[0041] Figure 19(b) shows the experimental waveforms of the modulation method of the present invention at a modulation ratio m = 0.2.

[0042] Figure 19(c) shows the experimental waveforms of the open-circuit zero vector (00-111, 00-000) modulation method at a modulation ratio m = 0.2.

[0043] Figure 19(d) shows the experimental waveforms of the open-circuit zero vector (01-111, 10-000) modulation method at a modulation ratio m = 0.2.

[0044] Figure 20 The output current THD variation curves for four modulation methods at different modulation ratios.

[0045] Figure 21 Efficiency curves of four modulation methods at different modulation ratios. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0047] like Figure 1 As shown, the H8 inverter is a conventional two-level three-phase voltage source inverter (VSI) with one switching transistor S7 and another S8 connected in series above and below the DC bus. dc It is the input voltage on the DC side of the inverter, V AO V BO V COThese are the voltages between AO, BO, and CO, respectively. P and N are the positive and negative terminals of the DC power supply, respectively. P' and N' are the positive and negative terminals of the traditional two-level VSI.

[0048] The H8 inverter has two switching states: active switching state and zero switching state. During the active switching state, energy is transferred between the DC power supply and the load; therefore, S7 and S8 must be on during active switching. The effective vector of the H8 inverter is 11-V. active During the zero-switching state, natural freewheeling occurs between the load and the switching transistor, so the switching states of S7 and S8 can be arbitrarily selected.

[0049] Based on the switching states of S7 and S8, the zero-switching state (zero vector) of the H8 inverter can be divided into three types:

[0050] 1) Traditional zero vector V zero_conv Traditional two-level VSI zero vector V zero Under this action, S7 and S8 are turned on, and this switch state is the same as the zero vector of a traditional two-level VSI, i.e., 11-V. zero .

[0051] 2) Open-circuit zero vector V open_zero Traditional two-level VSI zero vector V zero Under the action, at least one of the switches S7 and S8 will be turned off, including 01-111, 10-000, 00-111 and 00-000.

[0052] 3) The effective fully open-circuit zero vector V of the present invention open_active The effective vector refers to the state where the six switches S1-S6 are in an effective vector state, and the two switches S7 and S8 are both in the conducting state; the effective fully open zero vector V open_active This refers to the six switches S1-S6 being in an active vector state, while switches S7 and S8 are both in an off state. The traditional two-level VSI active vector V... active Under this action, S7 and S8 are completely turned off, i.e., 00-V active Therefore, it is defined as the effective fully open-circuit zero vector V. open_active .

[0053] In this invention, the effective fully open-circuit zero vector ensures that the switching states of the six switches S1-S6 remain between the effective vector throughout the entire modulation process, controlling the simultaneous on / off state of switches S7 and S8. Common-mode voltage (CMV) is defined as the average value of the voltage between the inverter output and reference ground, i.e.

[0054] H8 inverter common-mode voltage value V under effective vector cm As shown in Table 1: Table 1

[0055] For the H8 inverter, the switching states of the upper and lower bridge arms are reversed: S1 and S2 are reversed, S3 and S4 are reversed, and S5 and S6 are reversed. Therefore, the switching states are only represented by S7S8-S1S3S5. 1 indicates the switch is on, and 0 indicates the switch is off. For example, if S1S3S5 is 110, then S2S4S6 is 001. Only one switch in the upper and lower bridge arms is on. Each voltage vector V x (x is the binary number of the state of switches S1S3S5, x = 1...6) corresponds to one switching state. In this invention, when the switching state of S1S3S5 is 110, the corresponding voltage vector is V6.

[0056] In an effective fully open-circuit zero vector V open_active Under this condition, in order to ensure that the three-phase load does not open circuit, natural freewheeling must be completed between the load and the switching transistor.

[0057] The embodiment uses an effective fully open-circuit zero vector V open_active Taking (00-100) as an example, the red part represents the conductive part, as shown in Figure 2-a. Assuming that the output current i>0 is the direction of current flow, when the output current i A If the current is less than 0, phase A cannot form a loop, leading to an open-circuit fault in the output current; as shown in Figure 2-b, assuming the output current i A With a voltage >0, the freewheeling diode of the lower bridge arm S2 in phase A is conducting, and a freewheeling circuit exists in the three-phase bridge arms of the inverter, which will not cause an output open-circuit fault. At the same time, the upper bridge arm S1 in phase A is conducting, and point P'N' is the equipotential point, i.e., U P’N’ =0. Therefore, to ensure the safe application of an effective fully open-circuit zero vector, energy in the H8 inverter must flow from the DC side to the AC side.

[0058] H8 inverter effectively fully open-circuit zero vector V open_active Under the influence of the inverter, point P'N' is at the same potential, and the upper and lower arms of the three bridge arms are directly connected. The output potential points ABC are at the same potential as P'N', and the DC power supply voltage V at this time is... dc The voltage distribution is entirely shared by S7 and S8. The junction capacitance of the six switches on the three arms of the inverter will not affect the uneven voltage distribution. If the inherent junction capacitance of S7 and S8 is approximately equal, the DC power supply voltage Vdc is evenly divided between the two switches, resulting in each receiving a portion of V. dc Half of it, simplified circuit as Figure 3 As shown. According to equation (1) and Figure 3 It can be seen that the effective fully open-circuit zero vector V open_active common-mode voltage V cmIt equals 0V.

[0059] This invention employs a modulation method based on effective fully open-circuit zero vectors, using six effective vectors and six corresponding effective fully open-circuit zero vectors. The reference voltage vector V within each sector... ref It is synthesized from two adjacent effective vectors and two effective fully open-circuit zero vectors, wherein the two effective fully open-circuit zero vectors of the synthesized reference voltage vector correspond to the two effective vectors respectively. The effective vector 11-V4 (11-100) corresponds to the effective fully open-circuit zero vector 00-V4 (00-100); the effective vector 11-V6 (11-110) corresponds to the effective fully open-circuit zero vector 00-V6 (00-110); the effective vector 11-V2 (11-010) corresponds to the effective fully open-circuit zero vector 00-V2 (00-010); the effective vector 11-V3 (11-011) corresponds to the effective fully open-circuit zero vector 00-V3 (00-011); the effective vector 11-V1 (11-001) corresponds to the effective fully open-circuit zero vector 00-V1 (00-001); and the effective vector 11-V5 (11-101) corresponds to the effective fully open-circuit zero vector 00-V5 (00-101).

[0060] The switching sequence of the switching states of each sector within one carrier cycle is as follows:

[0061] First sector: 00-V4(00-100)--11-V4(11-100)--11-V6(11-110)--00-V6(00-110)--11-V6(11-110)--11-V4(11-100)--00-V4(00-100);

[0062] Second sector: 00-V2(00-010)--11-V2(11-010)--11-V6(11-110)--00-V6(00-110)--11-V6(11-110)--11-V2(11-010)--00-V2(00-010);

[0063] Third sector: 00-V2(00-010)--11-V2(11-010)--11-V3(11-011)--00-V3(00-011)--11-V3(11-011)--11-V2(11-010)--00-V2(00-010);

[0064] Fourth sector: 00-V1(00-001)--11-V1(11-001)--11-V3(11-011)--00-V3(00-011)--11-V3(11-011)--11-V1(11-001)--00-V1(00-001);

[0065] Fifth sector: 00-V1(00-001)--11-V1(11-001)--11-V5(11-101)--00-V5(00-101)--11-V5(11-101)--11-V1(11-001)--00-V1(00-001);

[0066] Sector 6: 00-V4(00-100)--11-V4(11-100)--11-V5(11-101)--00-V5(00-101)--11-V5(11-101)--11-V4(11-100)--00-V4(00-100).

[0067] The zero vector of each sector is selected from the two effective fully open zero vectors corresponding to the two adjacent effective voltage vectors within the sector.

[0068] like Figure 4 , Figure 5 As shown, the reference voltage vector V in the first sector ref It is synthesized from the effective vectors 11-V4 (11-100) and 11-V6 (11-110) and the effective fully open-circuit zero vectors 00-V4 (00-100) and 00-V6 (00-110). The switching sequence is 00-V4 (00-100)--11-V4 (11-100)--11-V6 (11-110)--00-V6 (00-110)--11-V6 (11-110)--11-V4 (11-100)--00-V4 (00-100).

[0069] like Figure 6 , Figure 7 As shown, the reference voltage vector V in the second sector ref It is synthesized from the effective vectors 11-V6 (11-110) and 11-V2 (11-010) and the effective fully open-circuit zero vectors 00-V6 (00-110) and 00-V2 (00-010). The switching sequence is 00-V2 (00-010)--11-V2 (11-010)--11-V6 (11-110)--00-V6 (00-110)--11-V6 (11-110)--11-V2 (11-010)--00-V2 (00-010).

[0070] like Figure 8 , Figure 9 As shown, the reference voltage vector V in the third sector ref It is synthesized from the effective vectors 11-V3 (11-011) and 11-V2 (11-010) and the effective fully open-circuit zero vectors 00-V3 (00-011) and 00-V2 (00-010). The switching sequence is 00-V2 (00-010)--11-V2 (11-010)--11-V3 (11-011)--00-V3 (00-011)--11-V3 (11-011)--11-V2 (11-010)--00-V2 (00-010).

[0071] like Figure 10 , Figure 11 As shown, the reference voltage vector V in the fourth sector ref It is synthesized from the effective vectors 11-V3 (11-011) and 11-V1 (11-001) and the effective fully open-circuit zero vectors 00-V3 (00-011) and 00-V1 (00-001). The switching sequence is 00-V1 (00-001)--11-V1 (11-001)--11-V3 (11-011)--00-V3 (00-011)--11-V3 (11-011)--11-V1 (11-001)--00-V1 (00-001).

[0072] like Figure 12 , Figure 13 As shown, the reference voltage vector V in the fifth sector ref It is synthesized from the effective vectors 11-V5 (11-101) and 11-V1 (11-001) and the effective fully open-circuit zero vectors 00-V5 (00-101) and 00-V1 (00-001). The switching sequence is 00-V1 (00-001)--11-V1 (11-001)--11-V5 (11-101)--00-V5 (00-101)--11-V5 (11-101)--11-V1 (11-001)--00-V1 (00-001).

[0073] like Figure 14 , Figure 15 As shown, the reference voltage vector V in the sixth sector refIt is synthesized from the effective vectors 11-V5 (11-101) and 11-V4 (11-100) and the effective fully open-circuit zero vectors 00-V5 (00-101) and 00-V4 (00-100). The switching sequence is 00-V4 (00-100)--11-V4 (11-100)--11-V5 (11-101)--00-V5 (00-101)--11-V5 (11-101)--11-V4 (11-100)--00-V4 (00-100).

[0074] Using the effective vector 11-V active At that time, the CMV of the H8 inverter and the traditional VSI are the same, which is ±V. dc / 6. Using an effective fully open-circuit zero vector 00-V active At that time, the CMV of the H8 inverter dropped to 0V.

[0075] The vector arrangement, switching states, and common-mode voltage of the first sector for one carrier cycle are as follows: Figure 5 As shown, T4' is the effective fully open-circuit zero vector V. open_active The duration of (00-100) is T6', where T6' is the effective fully open-circuit zero vector V. open_active The duration of action of (00-110) is the sum of T4' and T6', which is the total zero vector duration. In one carrier cycle, the effective fully open zero vector V... open_active The common-mode voltage is 0V when the sectors are arranged in the middle and on both sides of a cycle. The principle is the same for other sectors, so it will not be described in detail here.

[0076] The following experiments verify the superior performance of the modulation method based on effective fully open zero vector of the present invention.

[0077] Table 2 compares the number of switching operations, conduction losses, and output efficiency of the four modulation methods over one carrier cycle. As can be seen from Table 2, the modulation method of this invention has the same number of switching operations as traditional SVPWM modulation, while the other two zero-vector methods have more switching operations than traditional SVPWM. Table 2

[0078] like Figure 16 As shown in the figure, the equivalent circuit under effective fully open zero vector action is illustrated, with the red portion representing the conducting portion. It can be seen from the figure that under effective fully open zero vector action, both the upper and lower arms of the three-phase bridge participate in the freewheeling process. Compared to traditional SVPWM modulation, the modulation strategy proposed in this paper increases the conduction loss of three anti-parallel freewheeling diodes. Furthermore, the initial energy stored in the junction capacitance inside the switching transistor is completely released during the zero vector action period, which also leads to increased conduction loss. Therefore, this modulation method increases conduction loss compared to traditional SVPWM modulation.

[0079] Therefore, the modulation strategy based on open-circuit zero vectors 00-000 and 00-111 in this invention, compared to the traditional SVPWM modulation strategy, only increases switching losses, while its conduction losses are the same as those of traditional SVPWM. The modulation strategy based on open-circuit zero vectors 01-000 and 10-000, due to the six external switching device capacitors, significantly increases the conduction losses under the zero vector effect; the lower the modulation ratio, the greater the conduction losses.

[0080] The effectiveness of the modulation method of the present invention will be verified through simulation and experiment. Table 3 shows the simulation and experimental parameters.

[0081] Figures 17(a)-17(d) The following are simulated common-mode voltage waveforms at a modulation ratio of 0.8, presented sequentially: traditional SVPWM modulation, the effective fully open-circuit zero-vector modulation method of this invention, a modulation method using open-circuit zero vectors (00-111, 00-000), and a modulation method using open-circuit zero vectors (01-111, 10-000). As can be seen from Figure 17(b), the common-mode voltage V of the modulation method proposed in this invention... cm The voltage levels are approximately 0V and ±52V, verifying the common-mode voltage V under effective full-open zero vector operation of the modulation method of this invention. cm The common-mode peak voltage is reduced to 0, a 67% decrease compared to traditional SVPWM (155V). As shown in Figure 17(c), the common-mode peak voltage based on the open-path vector (00-111, 00-000) modulation strategy is approximately 110V, which is close to the theoretically calculated ±5V. dc / 14 is the same. As can be seen from Figure 17(d), the common-mode voltage level under the open-circuit vector (01-111, 10-000) modulation strategy is about ±52V, which also verifies the theoretical result that the common-mode voltage under the open-circuit zero vector is the same as the common-mode voltage under the effective vector.

[0082] Figures 18(a)-18(d) It can be seen that each modulation method produces a common-mode voltage spike, which is mainly caused by the non-ideal switching characteristics and dead-time effect of the device. As shown in Figures 18(a) and 18(b), the voltage spike caused by the non-ideal switching characteristics of the device in this invention is around 50V. However... Figure 18(c) and 18(d) The common-mode voltage waveform using open-circuit zero vector achieved ±150V, or ±V, during open-circuit zero vector switching. dc / 2, this is due to the common-mode voltage spike caused by the dead-time effect under open-circuit zero-vector switching. The present invention employs an effective fully open-circuit zero-vector, ensuring that the switching states of the six switches in the VSI remain in an effective vector state, thus avoiding the common-mode voltage spike caused by the dead-time effect. Therefore, the modulation strategy proposed in this invention can not only reduce the common-mode voltage under zero-vector action but also significantly reduce the common-mode spike under zero-vector switching.

[0083] Figures 19(a)-19(d) Experimental waveforms based on four different zero-vector modulation methods at a modulation ratio of 0.2 are presented. As can be seen from the figures, the common-mode voltage waveform is essentially the same as that at high modulation ratios. The experimental waveforms of common-mode voltage at different modulation ratios demonstrate that the common-mode suppression strategy based on effective open-circuit zero vectors proposed in this invention can not only reduce the common-mode voltage amplitude but also effectively reduce the common-mode variation. At a modulation ratio of 0.2, the common-mode voltage value is essentially near 0V, further suppressing the peak-to-peak value and variation of the common-mode voltage, indicating that the modulation method of this invention is still applicable at low modulation ratios.

[0084] Figures 18 and 19 show the current waveforms of the four methods, with THDs of approximately 1.5% and 5.5%, respectively. The current THDs of the four methods are not significantly different and are acceptable under the same modulation ratio, and the current waveform quality of the four methods is good. Figure 20 The output current THD variation curves for four modulation methods under different modulation ratios are presented. The figures show that the THD differs slightly among the four modulation strategies at low modulation ratios. Once the modulation ratio exceeds 0.4, the current THD of the four modulation strategies becomes essentially the same. Therefore, the output waveform quality of the common-mode rejection strategy based on zero vector modulation is generally good.

[0085] Figure 21The efficiency of four different zero-vector modulation methods is presented. Experiments were conducted to compare these four methods at different modulation ratios using an LMG500 power analyzer. As shown in the figures, the common-mode rejection modulation strategy based on open-circuit zero vector (01-111, 10-000) is relatively efficient at high modulation ratios, although lower than the other three strategies. However, its efficiency drops sharply as the modulation ratio decreases. This is because the charging and discharging time of the switching transistors is prolonged due to the six parallel capacitors during state switching, leading to increased capacitor losses. This severely impacts the inverter's lifespan, thus limiting the effectiveness of this modulation method at low modulation ratios. Except for the significantly reduced efficiency of the open-circuit zero vector (01-111, 10-000) modulation strategy, the efficiency of the other three methods is relatively similar. Since S7 and S8 of the traditional SVPWM remain on without switching, its efficiency is the highest. The efficiency of the open-circuit zero vector (00-111, 00-000) modulation strategy is higher than that of the proposed strategy, but its common-mode rejection capability is poor. The efficiency of the method proposed in this invention is lower than that of the traditional method and the open-path zero vector (00-111, 00-000), but the efficiency reduction is smaller, and the common-mode rejection capability is the best, which is acceptable in practice. The efficiency of the four modulation strategies obtained in the experiment is consistent with the theoretical analysis.

[0086] It should be noted that the specific embodiments described above enable those skilled in the art to more fully understand the present invention, but do not limit the present invention in any way. Therefore, although the present invention has been described in detail with reference to the accompanying drawings and embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the present invention. In short, all technical solutions and improvements that do not depart from the spirit and scope of the present invention should be covered within the protection scope of the present invention patent.

Claims

1. A modulation method for reducing the common-mode voltage of an H8 inverter, characterized in that: Effective fully open-circuit zero vector V open_active In this state, the upper and lower switches S7 and S8 on the DC bus of the H8 inverter are in the off state, and the switches S1, S3, and S5 on the upper arm of the A, B, and C phases of the H8 inverter and the switches S2, S4, and S6 on the lower arm are in the effective vector action state; the output current i A >0, natural freewheeling occurs between the load and the switching transistor; common-mode voltage V cm Equal to 0V; Let 1 represent the switch state as on and 0 represent the switch state as off. Each voltage vector V x Corresponding to a switching state, x=1……6; the effective fully open-circuit zero vector V open_active Under these conditions, the switching sequence of the switching states in each sector within one carrier cycle is as follows: First sector: 00- (00-100)--11- (11-100) --11- (11-110)--00- (00-110)--11- (11-110) --11- (11-100)--00- (00-100); Second sector: 00- (00-010)--11- (11-010) --11- (11-110)--00- (00-110)--11- (11-110) --11- (11-010) --00- (00-010); Third sector: 00- (00-010)--11- (11-010) --11- (11-011) --00- (00-011)--11- (11-011) --11- (11-010) --00- (00-010); Fourth sector: 00- (00-001)--11- (11-001) --11- (11-011) --00- (00-011)--11- (11-011) --11- (11-001)--00- (00-001); Fifth sector: 00- (00-001)--11- (11-001) --11- (11-101)--00- (00-101)--11- (11-101) --11- (11-001)--00- (00-001); Sector 6: 00- (00-100)--11- (11-100) --11- (11-101)--00- (00-101)--11- (11-101) --11- (11-100)--00- (00-100).

2. The modulation method for reducing the common-mode voltage of an H8 inverter as described in claim 1, characterized in that: In one carrier cycle, the effective fully open-circuit zero vector V open_active Arranged in the middle and on both sides of a cycle.

3. The modulation method for reducing the common-mode voltage of an H8 inverter as described in claim 1, characterized in that: The junction capacitances of the upper and lower switching transistors S7 and S8 on the DC bus of the H8 inverter are equal, and the DC power supply voltage V dc The common-mode voltage V is shared equally by the two switching transistors. cm equals V dc / 2.

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