A lightweight PUF circuit based on threshold loss of MOS transistor

Abstract

The application discloses a kind of light PUF circuits based on MOS tube threshold loss, including N-stage delay unit and an arbitrator, delay unit includes 6 inverters and 4 MOS tubes, 4 MOS tubes are PMOS tube or all are NMOS tube, only one PMOS tube or one NMOS tube is used in each path in each stage delay unit, no transmission gate is used by one PMOS tube and one NMOS tube, when delay unit transmits low level (4 MOS tubes are PMOS tube) or high level (4 MOS tubes are NMOS tube), MOS tube on transmission path all exists threshold loss, so that the PMOS tube and NMOS tube in third inverter and sixth inverter are all in conduction state, finally its output end will be charged to high level or discharged to low level, greatly expand the delay deviation size when delay unit output;Advantage is that hardware overhead is less, and randomness is higher.

Description

Technical Field

[0001] This invention relates to PUF circuits, and more particularly to a lightweight PUF circuit based on MOSFET threshold loss. Background Technology

[0002] Physically Unclonable Functions (PUFs), as a novel chip-level security technology, generate responses by extracting inherent process variations within the hardware circuitry. This technology does not rely on stored keys or identification information, thus providing enhanced security. Because the variations in each hardware entity are random and uncontrollable, PUF circuits possess physical unclonability, unpredictability, and low hardware cost, offering a solution for resource-constrained IoT security applications.

[0003] Arbiter Physically Unclonable Function (APUF), as a typical strong PUF, has been widely studied due to its advantages such as simple structure, low cost, and abundant excitation-response pairs. The block diagram of a traditional APUF circuit is shown below. Figure 1 As shown, it includes N delay units and an arbitrator, where N=2. m Where m is an integer greater than or equal to 6. When the APUF circuit is working, the square wave signal, serving as the trigger signal, is split into upper and lower paths and enters the first-stage delay unit, then propagates from the first-stage delay unit to the next stage. When the square wave signal enters a certain stage delay unit, it passes through that stage delay unit parallel or intersecting under the influence of the control signal connected to that stage. The circuit diagram of each delay unit in a traditional APUF circuit is as follows: Figure 2 As shown, it consists of 8 inverters INV1-INV8 and 8 MOSFETs P1-P4 and N1-N4. N1 and P1 form the first transmission gate, N2 and P2 form the second transmission gate, N3 and P3 form the third transmission gate, and N4 and P4 form the fourth transmission gate. When the square wave signal is split into two signals (the first square wave signal is called IN0, and the second square wave signal is called IN1) and enter a certain delay unit, if the control signal S input to that delay unit... i =0, at this time P1 and P3 in this stage of delay unit are turned on, N2 and N4 are not turned on, S i After passing through INV4 and INV8, the signal flips to 1, N1 and N3 are turned on, while P2 and P4 are not turned on. That is, when S... iWhen the signal is 0, the first and third transmission gates are on, and the second and fourth transmission gates are off. The first square wave signal IN0 is inverted by INV1, passes through the first transmission gate, and is then inverted by INV3 to generate and output the square wave signal OUT0. The second square wave signal IN1 is inverted by INV6, passes through the third transmission gate, and is then inverted by INV7 to generate and output the square wave signal OUT1. At this time, the first square wave signal IN0 and the second square wave signal IN1 pass through this delay unit in parallel. If the control signal S connected to this delay unit... i =1, at this time N2 and N4 in this stage of delay unit are turned on, P1 and P3 are not turned on, S i The signal flips to 0 after passing through INV4 and INV8, P2 and P4 are turned on, and N1 and N3 are turned off. That is, when S... i When the value is 1, the second and fourth transmission gates are turned on, and the first and third transmission gates are turned off; the first square wave signal IN0 is inverted by INV5, passes through the fourth transmission gate, and is then inverted by INV7 to output OUT1; the second square wave signal IN1 is inverted by INV2, passes through the second transmission gate, and is then inverted by INV3 to output OUT0; at this time, the first square wave signal IN0 and the second square wave signal IN1 cross-pass through this stage of delay unit. In a traditional APUF circuit, the square wave signal OUT0 output from the previous stage delay unit is used as the first square wave signal IN0 of the next stage delay unit, and the square wave signal OUT1 output from the previous stage delay unit is used as the second square wave signal IN1 of the next stage delay unit. After N stages of delay units, the two square wave signals output from the Nth stage delay unit are input to the arbitrator. Due to the influence of MOSFET process deviation, there will be a delay difference between the two square wave signals output from the Nth stage delay unit. The arbitrator compares and extracts the delay difference between these two signals to generate a response and output.

[0004] However, since the delay unit of the traditional APUF circuit uses multiple transmission gates, and each transmission gate requires two MOS transistors, the area occupied by each delay unit is relatively large, resulting in a large hardware overhead for the traditional APUF circuit. In addition, since the transmission gate is a complementary CMOS structure, there is almost no threshold loss of MOS transistors, resulting in a small delay deviation when the square wave signal passes through it. The delay deviation of the two square wave signals output by the Nth stage delay unit is small, resulting in poor randomness of the final response generated by the APUF circuit. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a lightweight PUF circuit based on MOS transistor threshold loss with low hardware overhead and high randomness of the generated response.

[0006] The technical solution adopted by this invention to solve the above-mentioned technical problems is as follows: a lightweight PUF circuit based on MOS transistor threshold loss, comprising N-stage delay units and an arbitrator, where N=2 m Where m is an integer greater than or equal to 6, the N-level delay units have the same structure and are cascaded sequentially. These N-level delay units are referred to as the 1st to the Nth level delay units. The Nth level delay unit is connected to the arbitrator. Each delay unit, under the control of the control signal output to it, causes two square wave signals output to it to pass parallel or crosswise, generating two square wave signals for output. The two square wave signals generated by the previous delay unit are output to the next delay unit. The arbitrator is used to compare and extract the delay deviation of the two square wave signals output by the Nth level delay unit. To generate a response and output, the delay unit includes six inverters and four MOSFETs. All four MOSFETs are either PMOS or NMOS transistors. The six inverters are referred to as the first inverter, second inverter, third inverter, fourth inverter, fifth inverter, and sixth inverter, respectively. The four MOSFETs are referred to as the first MOSFET, second MOSFET, third MOSFET, and fourth MOSFET, respectively. The input terminal of the first inverter serves as the first input terminal of the delay unit, used to input a first square wave signal. The input terminal of the fourth inverter serves as... The second input terminal of the delay unit is used to receive a second square wave signal. The output terminal of the first inverter, the source of the first MOS transistor, and the source of the second MOS transistor are connected. The output terminal of the fourth inverter, the source of the third MOS transistor, and the source of the fourth MOS transistor are connected. The drain of the first MOS transistor, the drain of the fourth MOS transistor, and the input terminal of the third inverter are connected. The drain of the second MOS transistor, the drain of the third MOS transistor, and the input terminal of the sixth inverter are connected. The gate of the first MOS transistor, the input terminal of the second inverter, the gate of the third MOS transistor, and the input terminal of the fifth inverter are connected, and their connection terminals serve as the control terminal of the delay unit for receiving control signals. The output terminal of the second inverter is connected to the gate of the second MOS transistor. The output terminal of the fifth inverter is connected to the gate of the fourth PMOS transistor. The output terminals of the third inverter and the sixth inverter serve as the two output terminals of the delay unit for generating and outputting two square wave signals.

[0007] When all four MOSFETs are PMOS transistors, the arbiter includes two two-input NAND gates. Each two-input NAND gate has a first input terminal, a second input terminal, and an output terminal. The two two-input NAND gates are referred to as the first two-input NAND gate and the second two-input NAND gate, respectively. The first input terminal of the first two-input NAND gate and the second input terminal of the second two-input NAND gate are used to input the two square wave signals output by the Nth stage delay unit. The second input terminal of the first two-input NAND gate and the output terminal of the second two-input NAND gate are connected, and their connection terminal is the output terminal of the arbiter, used to output a response. The output terminal of the first two-input NAND gate and the first input terminal of the second two-input NAND gate are connected.

[0008] When all four MOSFETs are NMOS transistors, the arbiter includes two two-input NOR gates. Each two-input NOR gate has a first input terminal, a second input terminal, and an output terminal. The two two-input NOR gates are referred to as the first two-input NOR gate and the second two-input NOR gate, respectively. The first input terminal of the first two-input NOR gate and the second input terminal of the second two-input NOR gate are used to receive two square wave signals output by the Nth stage delay unit. The second input terminal of the first two-input NOR gate is connected to the output terminal of the second two-input NOR gate, and the connection terminal is the output terminal of the arbiter, used to output a response. The output terminal of the first two-input NOR gate is connected to the first input terminal of the second two-input NOR gate.

[0009] Compared with the prior art, the advantage of this invention lies in that each delay unit of the lightweight PUF circuit is constructed using 6 inverters and 4 MOS transistors, with all 4 MOS transistors being either PMOS or NMOS transistors. If all 4 MOS transistors in each delay unit of the lightweight PUF circuit are PMOS transistors, when the square wave signal (i.e., the trigger signal) is split into upper and lower square wave signals (the first square wave signal is called IN0, and the second square wave signal is called IN1) and enters a certain delay unit, if the control signal S input to that delay unit... i =0, at this time the first MOSFET and the third MOSFET in this delay unit are turned on, S i After passing through the second and fifth inverters, the signal is flipped to 1, and the second and fourth MOSFETs are not turned on. The first square wave signal IN0 is inverted by the first inverter, passes through the first MOSFET, and is then inverted by the third inverter to generate and output the square wave signal OUT0. The second square wave signal IN1 is inverted by the fourth inverter, passes through the third MOSFET, and is then inverted by the sixth inverter to generate and output the square wave signal OUT1. The first square wave signal IN0 and the second square wave signal IN1 pass through this delay unit in parallel. If the control signal S connected to this delay unit... i=1, at this time the first MOSFET and the third MOSFET in this delay unit are not turned on, S i After passing through the second and fifth inverters, the signal is flipped to 0, and the second and fourth MOSFETs are turned on. The first square wave signal IN0 is inverted by the first inverter, passes through the second MOSFET, and is then inverted by the sixth inverter to generate and output the square wave signal OUT1. The second square wave signal IN1 is inverted by the fourth inverter, passes through the fourth MOSFET, and is then inverted by the third inverter to generate and output the square wave signal OUT0. The first square wave signal IN0 and the second square wave signal IN1 cross-pass through this stage of the delay unit, which generates and outputs the square wave signal. OUT0 serves as the first square wave signal IN0 input to the next stage delay unit. This stage delay unit generates and outputs square wave signal OUT1, which serves as the second square wave signal IN1 input to the next stage delay unit. Thus, after the square wave signal is input to the first stage delay unit of this PP-PUF circuit, this process continues through N stages. The Nth stage delay unit generates and outputs two square wave signals to the arbitrator composed of two cross-coupled NAND gates. Due to process variations in all PMOS transistors in the Nth stage delay unit, the signal reaches... The two square wave signals input to the arbitrator will have a significant delay deviation. When both square wave signals are high, the arbitrator's output is in a hold state, meaning its output response Q remains unchanged. When both square wave signals are low, the arbitrator's output response Q is 1. When one square wave signal is high and the other is low, the arbitrator's output response Q is either 1 or 0. Since the two external square wave signals enter the first-stage delay unit simultaneously, after being delayed by N stages of delay units, the output... There is a time delay between the two square wave signals output to the arbitrator, so they will not arrive at the arbitrator simultaneously. One of the two square wave signals arriving at the arbitrator will be at a high level, and the other at a low level. The arbitrator generates its response output based on this state. If all four MOS transistors in each delay unit of the lightweight PUF circuit are NMOS transistors, when the square wave signal (i.e., the trigger signal) is split into two square wave signals (the first signal is called IN0, and the second signal is called IN1) and enters a certain delay unit, if the control signal S input to that delay unit... i =1, at this time the first MOSFET and the third MOSFET in this delay unit are turned on, S iAfter passing through the second and fifth inverters, the signal is flipped to 0, and the second and fourth MOSFETs are not conducting. The first square wave signal IN0 is inverted by the first inverter, passes through the first MOSFET, and is then inverted by the third inverter to generate and output the square wave signal OUT0. The second square wave signal IN1 is inverted by the fourth inverter, passes through the third MOSFET, and is then inverted by the sixth inverter to generate and output the square wave signal OUT1. The first square wave signal IN0 and the second square wave signal IN1 pass through this delay unit in parallel. If the control signal S connected to this delay unit... i =0, at this time the first MOSFET and the third MOSFET in this delay unit are not turned on, S iAfter passing through the second and fifth inverters, the signal is flipped to 1, and the second and fourth MOSFETs are turned on. The first square wave signal IN0 is inverted by the first inverter, passes through the second MOSFET, and is then inverted by the sixth inverter to generate and output the square wave signal OUT1. The second square wave signal IN1 is inverted by the fourth inverter, passes through the fourth MOSFET, and is then inverted by the third inverter to generate and output the square wave signal OUT0. The first square wave signal IN0 and the second square wave signal IN1 cross-pass through this stage of the delay unit, and this stage of the delay unit generates and outputs the square wave signal OUT0 as the first square wave. The signal IN0 generates and outputs a square wave signal OUT1 from this delay unit. The second square wave signal IN1 is input into the next delay unit. Thus, after the square wave signal is input into this NN-PUF circuit, it passes through N delay units. The Nth delay unit outputs two square wave signals to the arbitrator composed of two cross-coupled NOR gates. Due to process variations in all NMOS transistors in the Nth delay unit, there will be a significant delay deviation between the two square wave signals reaching the arbitrator. When both square wave signals input to the arbitrator are low, the arbitrator's output is in a hold state. That is, its output response Q remains unchanged; when both square wave signals input to the arbitrator are high, the output response Q of the arbitrator is 0; when one of the two square wave signals input to the arbitrator is low and the other is high, the output response Q of the arbitrator is 0 or 1; since the two external square wave signals enter the first-stage delay unit simultaneously, after being delayed by the N-stage delay unit, there is a delay deviation between the two square wave signals output to the arbitrator, so they will not arrive at the arbitrator simultaneously. One of the two square wave signals arriving at the arbitrator will be high and the other low. This state generates a response output; therefore, in the lightweight PUF circuit of this invention, each path in each delay unit uses only one PMOS transistor or one NMOS transistor, without using a transmission gate composed of one PMOS transistor and one NMOS transistor, thereby reducing the number of MOS transistors used in the delay unit and reducing hardware overhead. Moreover, when the delay unit transmits a low level, if all four MOS transistors are PMOS transistors, the PMOS transistors on the transmission path cannot be pulled down to the full swing low level (VSS), but can only be pulled down to the threshold voltage V of the PMOS transistor. thp absolute value | V thp This ensures that the voltage reaching the input terminals of the third and sixth inverters is equal to the threshold voltage V of the PMOS transistor. thp absolute value | V thpAt this point, the PMOS and NMOS transistors inside the third and sixth inverters are both in the ON state, causing these two inverters to undergo a discharge process while charging (charging is primary, discharging is secondary). Ultimately, their outputs will be charged to a high level, significantly increasing the delay deviation of the delay unit output and increasing the randomness of the PUF circuit. If all four MOS transistors were NMOS transistors, the NMOS transistors on the transmission path could not be pulled up to a full swing high level (VDD), but only to VDD-V. thn (V thn (where V is the threshold voltage of the NMOS transistor) so that the voltage reaching the input terminals of the third and sixth inverters is VDD-V. thn At this point, the PMOS and NMOS transistors inside the third and sixth inverters are both in the on state, so that these two inverters will have a charging process while discharging (discharging is the main process and charging is the secondary process). Finally, their output terminals will be discharged to a low level, which greatly expands the delay deviation when the delay unit outputs and increases the randomness of the PUF circuit. Therefore, this invention improves the structure of the delay unit by using fewer MOS transistors to implement the delay unit (the number of MOS transistors is reduced by 8 compared to the existing delay unit), and also reduces the number of inverters, resulting in lower hardware overhead. Moreover, due to the threshold loss of the MOS transistors in each delay unit, the delay deviation when the delay unit outputs is greatly expanded, resulting in higher randomness of the final output response. Attached Figure Description

[0010] Figure 1 This is a block diagram of a traditional APUF circuit.

[0011] Figure 2 This is a circuit diagram of the delay unit in a traditional APUF circuit.

[0012] Figure 3 This is a circuit diagram of the delay unit of the lightweight PUF circuit based on MOS transistor threshold loss according to Embodiment 1 of the present invention.

[0013] Figure 4 This is a circuit diagram of an arbitrator based on a lightweight PUF circuit with MOS transistor threshold loss according to Embodiment 1 of the present invention.

[0014] Figure 5 This is a circuit diagram of the delay unit of the lightweight PUF circuit based on MOS transistor threshold loss according to Embodiment 2 of the present invention.

[0015] Figure 6 This is a circuit diagram of the arbitrator based on the threshold loss of a MOS transistor in Embodiment 2 of the present invention.

[0016] Figure 7 This is the layout of the delay unit in a traditional APUF circuit;

[0017] Figure 8 This is a layout of the delay unit of the lightweight PUF circuit based on MOS transistor threshold loss according to Embodiment 1 of the present invention;

[0018] Figure 9 This is a layout of the delay unit of the lightweight PUF circuit based on MOS transistor threshold loss according to Embodiment 2 of the present invention;

[0019] Figure 10(a) shows the intra-chip Hamming distance and inter-chip Hamming distance of the lightweight PUF circuit based on MOS transistor threshold loss in Embodiment 1 of the present invention.

[0020] Figure 10(b) shows the intra-chip Hamming distance and inter-chip Hamming distance of the lightweight PUF circuit based on MOS transistor threshold loss in Embodiment 2 of the present invention.

[0021] Figure 11(a) is a structural diagram of a single transmission path of the delay unit of the lightweight PUF circuit based on MOS transistor threshold loss in Embodiment 1 of the present invention.

[0022] Figure 11(b) shows 200 Monte Carlo simulations of a single transmission path as shown in Figure 11(a);

[0023] Figure 12(a) is a structural diagram of a single transmission path of the delay unit of the lightweight PUF circuit based on MOS transistor threshold loss in Embodiment 2 of the present invention;

[0024] Figure 12(b) shows 200 Monte Carlo simulations of a single transmission path as shown in Figure 12(a). Detailed Implementation

[0025] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0026] Example 1: As Figure 1 and Figure 3 As shown, a lightweight PUF circuit based on MOSFET threshold loss includes N-stage delay units and an arbitrator, where N=2. mWhere m is an integer greater than or equal to 6, the N-level delay units have the same structure and are cascaded sequentially. These N-level delay units are referred to as the 1st to the Nth level delay units. The Nth level delay unit is connected to an arbiter. Each delay unit, under the control of the control signal output to it, causes two square wave signals output to it to pass parallel or crosswise, generating two square wave signal outputs. The two square wave signals generated by the previous delay unit are output to the next delay unit. The arbiter is used to compare the delay deviation of the two square wave signals output by the Nth level delay unit to generate a response. The output delay unit includes six inverters and four MOSFETs, all of which are PMOS transistors. The six inverters are designated as INV1, INV2, INV3, INV4, INV5, and INV6. The four MOSFETs are designated as M1, M2, M3, and M4. The input of INV1 serves as the first input of the delay unit, used to receive the first square wave signal. The input terminal of the quad inverter INV4 serves as the second input terminal of the delay unit, used to input the second square wave signal. The output terminal of the first inverter INV1 is connected to the source of the first MOSFET M1 and the source of the second MOSFET M2. The output terminal of the fourth inverter INV4 is connected to the source of the third MOSFET M3 and the source of the fourth MOSFET M4. The drains of the first MOSFET M1 and the fourth MOSFET M4 are connected to the input terminal of the third inverter INV3. The drains of the second MOSFET M2 and the third MOSFET M3 are connected to the input terminal of the sixth inverter INV6. The input terminals are connected to the gate of the first MOS transistor M1, the input terminal of the second inverter INV2, the gate of the third MOS transistor M3, and the input terminal of the fifth inverter INV5. These connections serve as the control terminals of the delay unit, used to receive control signals. The output terminal of the second inverter INV2 is connected to the gate of the second MOS transistor M2. The output terminal of the fifth inverter INV5 is connected to the gate of the fourth PMOS transistor. The output terminals of the third inverter INV3 and the sixth inverter INV6 serve as the two output terminals of the delay unit, used to generate and output two square wave signals.

[0027] In this embodiment, as Figure 4As shown, the arbitrator includes two two-input NAND gates. Each two-input NAND gate has a first input terminal, a second input terminal, and an output terminal. The two two-input NAND gates are referred to as the first two-input NAND gate NAND1 and the second two-input NAND gate NAND2, respectively. The first input terminal of the first two-input NAND gate NAND1 and the second input terminal of the second two-input NAND gate NAND2 are used to input the two square wave signals output by the Nth stage delay unit. The second input terminal of the first two-input NAND gate NAND1 and the output terminal of the second two-input NAND gate NAND2 are connected, and their connection terminal is the output terminal of the arbitrator, used to output the response. The output terminal of the first two-input NAND gate NAND1 and the first input terminal of the second two-input NAND gate NAND2 are connected.

[0028] The lightweight PUF circuit based on MOS transistor threshold loss in this embodiment is referred to as the PP-PUF circuit. In this PP-PUF circuit, when the square wave signal (i.e., the trigger signal) is split into two square wave signals (the first square wave signal is called IN0, and the second square wave signal is called IN1) and enters a certain delay unit, if the control signal S input to that delay unit... i =0, at this time the first MOS transistor M1 and the third MOS transistor M3 in this delay unit are turned on, S i After passing through the second inverter INV2 and the fifth inverter INV5, the signal is flipped to 1, and the second MOSFET M2 and the fourth MOSFET M4 are not turned on. The first square wave signal IN0 is inverted by the first inverter INV1, passes through the first MOSFET M1, and is then inverted by the third inverter INV3 to generate and output the square wave signal OUT0. The second square wave signal IN1 is inverted by the fourth inverter INV4, passes through the third MOSFET M3, and is then inverted by the sixth inverter INV6 to generate and output the square wave signal OUT1. The first square wave signal IN0 and the second square wave signal IN1 pass through this delay unit in parallel. If the control signal S connected to this delay unit... i =1, at this time the first MOS transistor M1 and the third MOS transistor M3 in this delay unit are not turned on, S iAfter passing through the second inverter INV2 and the fifth inverter INV5, the signal is flipped to 0, and the second MOSFET M2 and the fourth MOSFET M4 are turned on. The first square wave signal IN0 is inverted by the first inverter INV1, passes through the second MOSFET M2, and is then inverted by the sixth inverter INV6 to generate and output the square wave signal OUT1. The second square wave signal IN1 is inverted by the fourth inverter INV4, passes through the fourth MOSFET M4, and is then inverted by the third inverter INV3 to generate and output the square wave signal OUT0. The first square wave signal IN0 and the second square wave signal IN1 cross through this stage of the delay unit. This stage of the delay unit generates and outputs the square wave signal OUT0 as the first square wave signal IN0 input to the next stage of the delay unit, and generates and outputs the square wave signal OUT1 as the second square wave signal IN1 input to the next stage of the delay unit. Therefore, when a square wave signal is input to the first stage delay unit of the PP-PUF circuit, after passing through N stages of delay units, the Nth stage delay unit generates and outputs two square wave signals to the arbitrator composed of two cross-coupled NAND gates. Due to process variations in all PMOS transistors in the Nth stage delay unit, there will be a significant delay deviation between the two square wave signals reaching the arbitrator. According to the arbitrator's circuit structure, when both square wave signals input to the arbitrator are high, the arbitrator's output is in a hold state, meaning its output response Q remains unchanged; when both square wave signals input to the arbitrator are low, the arbitrator's output response Q is 1. When the first two-input NAND gate NAND1 (i.e., the first input of the arbitrator) receives a high level first, and the second two-input NAND gate NAND2 (i.e., the second input of the arbitrator) receives a high level subsequently, the first square wave signal entering the arbitrator is high, and the second square wave signal is low, resulting in a arbitrator output response Q of 1. When the second two-input NAND gate NAND1 receives a high level, the second two-input NAND gate NAND2 receives a high level subsequently, resulting in a high square wave signal and a low square wave signal entering the arbitrator, and a low square wave signal. AND2 (the second input of the arbitrator) first receives a high level, and the first two-input NAND gate NAND1 (the first input of the arbitrator) then receives a high level. At this time, the first square wave signal entering the arbitrator is low and the second square wave signal is high. Therefore, the response Q output by the arbitrator is 0. Since the two external square wave signals enter the first-stage delay unit at the same time, after being delayed by the N-stage delay unit, there is a delay deviation between the two square wave signals output to the arbitrator. Therefore, they will not arrive at the arbitrator at the same time. One of the two square wave signals arriving at the arbitrator is high and the other is low. The arbitrator generates a response output based on this state.

[0029] In this PP-PUF circuit, only one PMOS transistor is used in each path of the delay unit, instead of a transmission gate consisting of one PMOS transistor and one NMOS transistor. This reduces the number of MOS transistors used and lowers hardware overhead. Furthermore, when transmitting a low level, the PMOS transistor cannot be pulled down to a full-swing low level (VSS), but only to the PMOS transistor's threshold voltage V. thp absolute value | V thp This ensures that the voltage reaching the input terminals of the third inverter INV3 and the sixth inverter INV6 is equal to the threshold voltage V of the PMOS transistor. thp absolute value | V thp At this time, the PMOS and NMOS transistors inside the third inverter INV3 and the sixth inverter INV6 are both in the conducting state, so that these two inverters will have a discharge process while charging (charging is the main process and discharging is the secondary process). Finally, their output terminals will be charged to a high level, which greatly expands the delay deviation when the delay unit outputs and increases the randomness of the PUF circuit.

[0030] Example 2: Figure 1 and Figure 5 As shown, a lightweight PUF circuit based on MOSFET threshold loss includes N-stage delay units and an arbitrator, where N=2. mWhere m is an integer greater than or equal to 6, the N-level delay units have the same structure and are cascaded sequentially. These N-level delay units are referred to as the 1st to the Nth level delay units. The Nth level delay unit is connected to an arbiter. Each delay unit, under the control of the control signal output to it, causes two square wave signals output to it to pass parallel or crosswise, generating two square wave signal outputs. The two square wave signals generated by the previous delay unit are output to the next delay unit. The arbiter is used to compare the delay deviation of the two square wave signals output by the Nth level delay unit to generate a response. The output delay unit includes six inverters and four MOSFETs, all of which are NMOS transistors. The six inverters are designated as INV1, INV2, INV3, INV4, INV5, and INV6. The four MOSFETs are designated as M1, M2, M3, and M4. The input of INV1 serves as the first input of the delay unit, used to receive the first square wave signal. The input terminal of the quad inverter INV4 serves as the second input terminal of the delay unit, used to input the second square wave signal. The output terminal of the first inverter INV1 is connected to the source of the first MOSFET M1 and the source of the second MOSFET M2. The output terminal of the fourth inverter INV4 is connected to the source of the third MOSFET M3 and the source of the fourth MOSFET M4. The drains of the first MOSFET M1 and the fourth MOSFET M4 are connected to the input terminal of the third inverter INV3. The drains of the second MOSFET M2 and the third MOSFET M3 are connected to the input terminal of the sixth inverter INV6. The input terminals are connected to the gate of the first MOS transistor M1, the input terminal of the second inverter INV2, the gate of the third MOS transistor M3, and the input terminal of the fifth inverter INV5. These connections serve as the control terminals of the delay unit, used to receive control signals. The output terminal of the second inverter INV2 is connected to the gate of the second MOS transistor M2. The output terminal of the fifth inverter INV5 is connected to the gate of the fourth PMOS transistor. The output terminals of the third inverter INV3 and the sixth inverter INV6 serve as the two output terminals of the delay unit, used to generate and output two square wave signals.

[0031] In this embodiment, as Figure 6As shown, the arbitrator includes two two-input NOR gates, each with a first input, a second input, and an output. These two gates are referred to as the first two-input NOR gate NOR1 and the second two-input NOR gate NOR2. The first input of the first two-input NOR gate NOR1 and the second input of the second two-input NOR gate NOR2 are used to input the two square wave signals output by the Nth stage delay unit. The second input of the first two-input NOR gate NOR1 is connected to the output of the second two-input NOR gate NOR2, and this connection is the output of the arbitrator, used to output a response. The output of the first two-input NOR gate NOR1 is connected to the first input of the second two-input NOR gate NOR2.

[0032] The lightweight PUF circuit based on MOS transistor threshold loss in this embodiment is referred to as the NN-PUF circuit. In this NN-PUF circuit, when the square wave signal (i.e., the trigger signal) is split into two square wave signals (the first square wave signal is called IN0, and the second square wave signal is called IN1) and enters a certain delay unit, if the control signal S input to that delay unit... i =1, at this time the first MOS transistor M1 and the third MOS transistor M3 in this delay unit are turned on, S i After passing through the second inverter INV2 and the fifth inverter INV5, the signal flips to 0, and the second MOSFET M2 and the fourth MOSFET M4 are not turned on. The first square wave signal IN0 is inverted by the first inverter INV1, passes through the first MOSFET M1, and is then inverted by the third inverter INV3 to generate and output the square wave signal OUT0. The second square wave signal IN1 is inverted by the fourth inverter INV4, passes through the third MOSFET M3, and is then inverted by the sixth inverter INV6 to generate and output the square wave signal OUT1. The first square wave signal IN0 and the second square wave signal IN1 pass through this delay unit in parallel. If the control signal S connected to this delay unit... i =0, at this time the first MOS transistor M1 and the third MOS transistor M3 in this delay unit are not turned on, S iAfter passing through the second inverter INV2 and the fifth inverter INV5, the signal is flipped to 1, and the second MOSFET M2 and the fourth MOSFET M4 are turned on. The first square wave signal IN0 is inverted by the first inverter INV1, passes through the second MOSFET M2, and is then inverted by the sixth inverter INV6 to generate and output the square wave signal OUT1. The second square wave signal IN1 is inverted by the fourth inverter INV4, passes through the fourth MOSFET M4, and is then inverted by the third inverter INV3 to generate and output the square wave signal OUT0. The first square wave signal IN0 and the second square wave signal IN1 cross through this stage of the delay unit. This stage of the delay unit generates and outputs the square wave signal OUT0 as the first square wave signal IN0. The second square wave signal IN1 generated and output by this stage of the delay unit is input into the next stage of the delay unit. Therefore, when a square wave signal is input into the NN-PUF circuit, after passing through the N-stage delay unit, the N-stage delay unit outputs two square wave signals to the arbitrator composed of two cross-coupled NOR gates. Due to the process deviation of all NMOS transistors in the N-stage delay unit, the two square wave signals reaching the arbitrator will have a significant delay deviation. According to the circuit structure of the arbitrator, when both input square wave signals are low, the output of the arbitrator remains in a hold state, meaning its output response Q remains unchanged. When both input square wave signals are high, the output response Q is 0. When the first two-input NOR gate NOR1 (the first input of the arbitrator) receives a low level first, followed by the second two-input NOR gate NOR2 (the second input of the arbitrator), the first square wave signal entering the arbitrator is low, and the second square wave signal is high, resulting in an output response Q of 0. When the second two-input NOR gate NOR2 (the second input of the arbitrator) receives a low level first, followed by the first two-input NOR gate NOR1 (the first input of the arbitrator), the first square wave signal entering the arbitrator is high, and the second square wave signal is low, the output response Q is 1. Since the two external square wave signals enter the first-stage delay unit at the same time, after being delayed by the N-stage delay unit, there is a delay deviation between the two square wave signals output to the arbitrator. Therefore, they will not arrive at the arbitrator at the same time. The two square wave signals that arrive at the arbitrator are in a state where one is high level and the other is low level. The arbitrator generates a response output based on this state.

[0033] In this NN-PUF circuit, since only one NMOS is used in each path of the delay unit, instead of a transmission gate composed of one PMOS and one NMOS, the number of MOS transistors used is reduced, thus lowering hardware overhead. Furthermore, when transmitting a high level, the NMOS transistor cannot be pulled up to the full swing high level (VDD), but only to VDD-V. thn (Vthn (where V is the threshold voltage of the NMOS transistor) so that the voltage reaching the input terminals of the third inverter INV3 and the sixth inverter INV6 is VDD-V thn At this time, the PMOS and NMOS transistors inside the third inverter INV3 and the sixth inverter INV6 are both in the conducting state, so that these two inverters will also have a charging process while discharging (discharging is the main process and charging is the secondary process). Finally, their output terminals will be discharged to a low level, which greatly expands the delay deviation when the delay unit outputs and increases the randomness of the PUF circuit.

[0034] The layout of the delay unit in a traditional APUF circuit is as follows: Figure 7 As shown; the layout of the delay unit of the lightweight PUF circuit based on MOS transistor threshold loss in Embodiment 1 of the present invention is as follows. Figure 8 As shown; the layout of the delay unit of the lightweight PUF circuit based on MOS transistor threshold loss in Embodiment 2 of the present invention is as follows. Figure 9 As shown. Analysis Figures 7 to 9 It can be seen that the delay unit of the lightweight PUF circuit based on MOS transistor threshold loss in Embodiments 1 and 2 of the present invention uses only 16 MOS transistors (two MOS transistors for each inverter, and a total of 12 MOS transistors for 4 inverters), and the layout area is 4.6852μm. 2 Compared to the delay unit of the traditional APUF circuit (which uses 24 MOSFETs), it reduces the number of MOSFETs by 8, lowers hardware overhead, saves 35% of area overhead, and is more lightweight.

[0035] The reliability and uniqueness of PUF circuits are described by the intra-chip Hamming distance and the inter-chip Hamming distance, respectively. The closer the intra-chip Hamming distance is to 0, the better the reliability. The closer the inter-chip Hamming distance is to 0.5, the better the uniqueness.

[0036] Figure 10(a) shows the intra-chip Hamming distance and inter-chip Hamming distance of the lightweight PUF circuit based on MOS transistor threshold loss in Embodiment 1 of this invention. The intra-chip Hamming distance test method for the PP-PUF circuit is as follows: Noise three times the frequency of the square wave signal is added to the PUF circuit under the same standard environment of 27℃ and 1.2V, and 30 noise simulations are performed, extracting 1000 responses each time. Finally, the intra-chip Hamming distance is calculated. Figure 10(a) shows that the intra-chip Hamming distance of the PP-PUF circuit is 0.0039, exhibiting good reliability. The inter-chip Hamming distance test method for the PP-PUF circuit is as follows: Under the same standard environment of 27℃ and 1.2V, the PUF circuit is subjected to 50 Monte Carlo simulations, extracting 10,000 responses each time. Finally, the inter-chip Hamming distance is calculated. Figure 10(a) shows that the inter-chip Hamming distance of the PP-PUF circuit is 0.5005, exhibiting good uniqueness.

[0037] Figure 10(b) shows the intra-chip Hamming distance and inter-chip Hamming distance of the lightweight PUF circuit based on MOS transistor threshold loss in Embodiment 2 of the present invention. The intra-chip Hamming distance and inter-chip Hamming distance of the PP-PUF circuit are the same as those of the PP-PUF circuit. As can be seen from Figure 10(b), the intra-chip Hamming distance of the NN-PUF circuit is 0.0247, which has good reliability, and the inter-chip Hamming distance is 0.5008, which has good uniqueness.

[0038] Figure 11(a) shows the structure of a single transmission path of the delay unit of the lightweight PUF circuit based on the threshold loss of a MOS transistor in Embodiment 1 of the present invention; Figure 11(b) shows the 200th Monte Carlo simulation diagram of the single transmission path shown in Figure 11(a). As can be seen from Figure 11(b), the square wave signal reaches point A after being flipped by inverter T1, and after passing through the PMOS transistor, the threshold voltage V of the PMOS transistor is output at point B. thp absolute value | V thp The signal is then inverted by T2 to output a square wave signal OUT. This delay unit utilizes the threshold loss of the square wave signal as it transitions from high to low level via the PMOS transistor, significantly extending the delay deviation as the output square wave signal OUT rises from low to high level, thus enhancing the randomness of the PUF circuit.

[0039] Figure 12(a) shows the structure of a single transmission path of the delay unit of the lightweight PUF circuit based on MOS transistor threshold loss in Embodiment 2 of the present invention; Figure 12(b) shows the 200th Monte Carlo simulation diagram of the single transmission path shown in Figure 12(a). As can be seen from Figure 12(b), the square wave signal reaches point C after being flipped by inverter T1, and outputs VDD-V at point D after passing through the NMOS transistor. thn The signal is then output as a square wave signal OUT via inverter T2. This delay unit utilizes the threshold loss during the rise of the square wave signal from low to high level via the NMOS transistor, significantly extending the delay deviation when the output square wave signal OUT falls from high to low level, thus enhancing the randomness of the PUF circuit.

[0040] The conventional APUF circuit, the PP-PUF circuit of Embodiment 1, and the NN-PUF circuit of Embodiment 2 of this invention were subjected to NIST SP 800-22 randomness testing. A P-value greater than 0.01 was considered passing. 100,000 responses were extracted from each of the three PUF circuits for testing. Specific test data are shown in Table 1. As can be seen from the data in Table 1, the conventional APUF circuit passed only 2 test items, while the PP-PUF circuit of Embodiment 1 and the NN-PUF circuit of Embodiment 2 both passed 9 test items, 7 more than the conventional APUF circuit, demonstrating better randomness.

[0041] In summary, the lightweight PUF circuit based on MOS transistor threshold loss is lighter than the traditional APUF circuit and has a larger delay deviation at the output of the Nth delay unit, thus exhibiting better randomness and making it more suitable for key generation and identity authentication in resource-constrained IoT security fields.

Claims

1. A lightweight PUF circuit based on MOSFET threshold loss, comprising N-stage delay units and an arbitrator, where N=2 m Where m is an integer greater than or equal to 6, the N-level delay units have the same structure and are cascaded sequentially. These N-level delay units are referred to sequentially as the 1st to the Nth level delay units. The Nth level delay unit is connected to the arbitrator. Each delay unit, under the control of the control signal output to it, causes two square wave signals output to it to pass parallel or crosswise, generating two square wave signals for output. The two square wave signals generated by the previous delay unit are output to the next delay unit. The arbitrator is used to compare the delay deviation of the two square wave signals output by the Nth level delay unit to generate a response and output. Its characteristic is... The delay unit includes six inverters and four MOSFETs. All four MOSFETs are either PMOS or NMOS transistors. The six inverters are referred to as the first inverter, second inverter, third inverter, fourth inverter, fifth inverter, and sixth inverter. The four MOSFETs are referred to as the first MOSFET, second MOSFET, third MOSFET, and fourth MOSFET. The input terminal of the first inverter serves as the first input terminal of the delay unit, used to input a first square wave signal. The input terminal of the fourth inverter serves as the second input terminal of the delay unit, used to input a second square wave signal. The output terminal of the first inverter is connected to the source of the first MOSFET and the source of the second MOSFET. The output terminal of the fourth inverter is connected to the source of the third MOSFET and the source of the fourth MOSFET. The source of the MOSFET is connected, the drain of the first MOSFET, the drain of the fourth MOSFET, and the input of the third inverter are connected, the drain of the second MOSFET, the drain of the third MOSFET, and the input of the sixth inverter are connected, the gate of the first MOSFET, the input of the second inverter, the gate of the third MOSFET, and the input of the fifth inverter are connected, and their connection points serve as the control terminals of the delay unit for receiving control signals. The output of the second inverter is connected to the gate of the second MOSFET, the output of the fifth inverter is connected to the gate of the fourth MOSFET, and the outputs of the third and sixth inverters serve as the two output terminals of the delay unit for generating and outputting two square wave signals.

2. The lightweight PUF circuit based on MOS transistor threshold loss according to claim 1, characterized in that... When all four MOSFETs are PMOS transistors, the arbiter includes two two-input NAND gates. Each two-input NAND gate has a first input terminal, a second input terminal, and an output terminal. The two two-input NAND gates are referred to as the first two-input NAND gate and the second two-input NAND gate, respectively. The first input terminal of the first two-input NAND gate and the second input terminal of the second two-input NAND gate are used to input the two square wave signals output by the Nth stage delay unit. The second input terminal of the first two-input NAND gate and the output terminal of the second two-input NAND gate are connected, and their connection terminal is the output terminal of the arbiter, used to output a response. The output terminal of the first two-input NAND gate and the first input terminal of the second two-input NAND gate are connected.

3. A lightweight PUF circuit based on MOS transistor threshold loss according to claim 1, characterized in that... When all four MOSFETs are NMOS transistors, the arbiter includes two two-input NOR gates. Each two-input NOR gate has a first input terminal, a second input terminal, and an output terminal. The two two-input NOR gates are referred to as the first two-input NOR gate and the second two-input NOR gate, respectively. The first input terminal of the first two-input NOR gate and the second input terminal of the second two-input NOR gate are used to receive two square wave signals output by the Nth stage delay unit. The second input terminal of the first two-input NOR gate is connected to the output terminal of the second two-input NOR gate, and the connection terminal is the output terminal of the arbiter, used to output a response. The output terminal of the first two-input NOR gate is connected to the first input terminal of the second two-input NOR gate.

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