A comparator input circuit resistant to total dose hardening

Abstract

The application provides a comparator input circuit resistant to total dose hardening, comprising: a first PMOS transistor, the gate of which is used as an input terminal, the source of the first PMOS transistor being connected to an external power supply; a second PMOS transistor, the gate of which is connected to a reference voltage, the source of the second PMOS transistor being connected to the external power supply; a first NMOS transistor, the drain and gate of which are short-circuited, and the drain of the first NMOS transistor being connected to the drain of the first PMOS transistor, the source of the second PMOS transistor being connected to the ground; a second NMOS transistor, the gate of which is connected to the gate of the first NMOS transistor, the source of the first NMOS transistor being connected to the ground; the drain of the first NMOS transistor and the drain of the second PMOS transistor being connected to serve as an output terminal; and a voltage dividing branch, which divides the voltage of the external power supply to provide the reference voltage, wherein the gate oxide thickness of the PMOS transistor is greater than the gate oxide thickness of the NMOS transistor. The application can effectively improve the ability of the circuit to resist total dose effect.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design applications, and more particularly to a comparator input circuit that is resistant to total dose hardening. Background Technology

[0002] With the development of the aerospace industry, integrated circuits are increasingly used in the control systems of aerospace systems. Therefore, the requirements for radiation hardening of integrated circuits in the aerospace environment are becoming increasingly stringent. Traditional high-voltage drive circuits, due to the need to withstand voltages above 20V, often use thick-gate oxide NMOS devices in their input stage structures. Without process hardening measures, thick-gate oxide NMOS devices cannot withstand a total dose of 30 klad(Si) or higher; with process hardening measures, they can withstand a maximum total dose of 100 klad(Si). Therefore, total dose hardening measures are needed to improve the total dose resistance of integrated circuits and promote their application in aerospace systems. Summary of the Invention

[0003] In view of the problems existing in the prior art, the present invention proposes a comparator input circuit with enhanced total dose resistance, which mainly solves the problem that the total dose resistance capability of existing devices is difficult to meet application requirements.

[0004] To achieve the above and other objectives, the technical solution adopted by the present invention is as follows.

[0005] This application provides a comparator input circuit for resistance to total dose hardening, comprising: a first PMOS transistor, the gate of which serves as the input terminal, and the source of which is connected to an external power supply; a second PMOS transistor, the gate of which is connected to a reference voltage, and the source of which is connected to an external power supply; a first NMOS transistor, the drain of which is shorted to its gate and connected to the drain of the first PMOS transistor, and the source of which is grounded; a second NMOS transistor, the gate of which is connected to the gate of the first NMOS transistor, and the source of which is grounded; the drain of the first NMOS transistor and the drain of the second PMOS transistor connected as the output terminal; and a voltage divider branch for dividing the voltage of the external power supply to provide the reference voltage, wherein the gate oxide thickness of the PMOS transistor is greater than that of the NMOS transistor.

[0006] In one embodiment of this application, the first PMOS transistor and the second PMOS transistor have the same size.

[0007] In one embodiment of this application, the first NMOS transistor and the second NMOS transistor have the same size.

[0008] In one embodiment of this application, both the first PMOS transistor and the second PMOS transistor can have a gate oxide thickness of 60 nm.

[0009] In one embodiment of this application, both the first NMOS transistor and the second NMOS transistor can have a gate oxide thickness of 30 nm.

[0010] In one embodiment of this application, the voltage divider branch includes a first resistor and a second resistor. One end of the first resistor is connected to the external power supply, and the other end of the first resistor is connected to one end of the second resistor. The other end of the second resistor is grounded, and the connection point of the first resistor and the second resistor serves as the output terminal of the reference voltage.

[0011] In one embodiment of this application, the reference voltage is adjusted by adjusting the resistance ratio of the first resistor to the second resistor.

[0012] In one embodiment of this application, the resistance ratio of the first resistor to the second resistor is 37:3.

[0013] In one embodiment of this application, under 300 krad (Si) irradiation, the threshold voltage drift of the first PMOS transistor and the second PMOS transistor is the same; under 300 krad (Si) irradiation, the threshold voltage drift of the first NMOS transistor and the second NMOS transistor is the same.

[0014] In one embodiment of this application, the reference voltage includes 1.5V.

[0015] As described above, the comparator input circuit for total dose hardening provided by the present invention has the following beneficial effects.

[0016] This application constructs a comparator input circuit using two PMOS transistors and two NMOS transistors. The gate oxide thickness of the PMOS transistors is greater than that of the NMOS transistors, avoiding the use of thick-gate oxide NMOS transistors with weaker total dose resistance. This improves the total dose resistance of the input circuit, ensuring the safety of integrated circuits in aerospace radiation environments. The circuit structure is simple and does not require additional special components to achieve the required total dose resistance. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of a comparator input short circuit for anti-total dose hardening in one embodiment of this application.

[0018] Figure 2 This is a schematic diagram of the simulation results of the comparator input circuit in one embodiment of this application.

[0019] Explanation of icon numbers:

[0020] P1 - First PMOS transistor, P2 - Second PMOS transistor, IN - Input terminal, IN1 - Output terminal, N1 - First NMOS transistor, N2 - Second NMOS transistor, R1 - First resistor, R2 - Second resistor, V H -High level, V DD - Power supply voltage, V REF - Reference voltage. Detailed Implementation

[0021] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0022] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0023] Please see Figure 1 The present invention provides a comparator input circuit for resistance to total dose hardening, the circuit comprising: a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, a second NMOS transistor N2, and a voltage divider branch.

[0024] In one embodiment, the gate of the first PMOS transistor P1 serves as the input terminal of the entire input circuit, used to connect to the input voltage IN of the comparator, and the source of the first PMOS transistor P1 is connected to the external power supply voltage V. DD Specifically, the source of the first PMOS transistor P1 can be directly connected to an external power supply V. DD The drain of the first PMOS transistor P1 is connected to the drain of the first NMOS transistor N1. Similarly, the source of the second PMOS transistor P2 can be directly connected to an external power supply, or connected to the high-level V. H The gate of the second PMOS transistor P2 is connected to the reference voltage V. REFThe drain of the second PMOS transistor P2 is connected to the drain of the second NMOS transistor N2, serving as the output terminal of the entire input circuit. The drain and gate of the first NMOS transistor N1 are shorted, and the gate of the first NMOS transistor N1 is connected to the gate of the second NMOS transistor N2. The sources of the first NMOS transistor N1 and the second NMOS transistor N2 are grounded.

[0025] In one embodiment, the first PMOS transistor P1 and the second PMOS transistor P2 can be thick-gate oxide transistors, and the first NMOS transistor N1 and the second NMOS transistor N2 can be thin-gate oxide transistors. That is, the gate oxide thickness of the PMOS transistor is greater than that of the NMOS transistor. This avoids the use of thick-gate oxide NMOS transistors with weaker total dose resistance, thereby improving the problem of failure of the input structure of the traditional high-voltage drive circuit under total dose effect and ensuring the safety of the circuit system in the space radiation environment.

[0026] In one embodiment, the size of the first PMOS transistor P1 can be set to be the same as the size of the second PMOS transistor P2. Similarly, the size of the first NMOS transistor N1 can be set to be the same as the size of the second NMOS transistor N2.

[0027] In one embodiment, the voltage divider branch may include a first resistor R1 and a second resistor R2, with one end of the first resistor R1 connected to an external power supply voltage V. DD One end is connected to one end of the first resistor R1 and the other end of the second resistor R2, which is grounded. The gate of the second PMOS transistor P2 is connected between the first resistor R1 and the second resistor R2, with the voltage of the second resistor R2 relative to ground used as the reference voltage. The value of the reference voltage can be adjusted by changing the resistance ratio of the first resistor R1 and the second resistor R2. For example, the resistance ratio of the first resistor R1 to the second resistor R2 can be set to 37:3. The source-drain current of the transistor can be calculated as follows:

[0028]

[0029] The first PMOS transistor P1 and the second PMOS transistor P2 have the same dimensions and their threshold voltage is approximately -1.1V. The first NMOS transistor N1 and the second NMOS transistor N2 have the same dimensions. When the external power supply voltage VDD = 20V, by adjusting the resistance ratio of the first resistor R1 to the second resistor R2 to 37:3, the reference voltage VDD can be adjusted. REF The voltage level is designed to be 1.5V.

[0030] Please see Figure 2 , Figure 2 This is a schematic diagram of the simulation results of the comparator input circuit in one embodiment of this application. When the input level IN is lower than 0.8V, VGS (P1)>V GS (P2) The current generated on VH mainly flows through the branch composed of the first PMOS transistor P1 and the first NMOS transistor N1. The first PMOS transistor P1 is turned on, the first NMOS transistor N1 is turned on, the level at point A is high, the second NMOS transistor N2 is turned on, the output level of IN1 is close to GND, the output terminal IN1 is low, and the simulation results show that IN1 is about 1mV at this time.

[0031] When the input level IN is higher than 2.4V, V GS (P1) < V GS (P2), the current generated on VH mainly flows through the branch composed of the second PMOS transistor P2 and the second NMOS transistor N2. The second PMOS transistor P2 is turned on, and the output level of the output terminal IN1 is close to V. H The output terminal IN1 is at a high level.

[0032] In one embodiment, both the first PMOS transistor P1 and the second PMOS transistor P2 can have a gate oxide thickness of 60 nm.

[0033] In one embodiment, both the first NMOS transistor N1 and the second NMOS transistor N2 can have a gate oxide thickness of 30 nm.

[0034] In one embodiment, when the circuit is irradiated with 300 klad (Si), the threshold voltage drift of the first PMOS transistor P1 and the second PMOS transistor P2 is the same.

[0035] In one embodiment, when the circuit is irradiated with 300 klad (Si), the threshold voltage drift of the first NMOS transistor N1 and the second NMOS transistor N2 is the same.

[0036] Specifically, when the circuit is irradiated with 300 krad (Si), the first PMOS transistor P1 and the second PMOS transistor P2 are thick-gate oxide PMOS transistors, and their threshold voltages drift from -1.1V to about -1.5V. The second NMOS transistor N1 and the second NMOS transistor N2 are thin-gate oxide NMOS transistors, and their threshold voltages drift from about 1.5V to about 1.2V.

[0037] After irradiation, when the input level IN is below 0.8V, V GS (P1)>V GS (P2), V HThe current generated still flows through the branch composed of the first PMOS transistor P1 and the first NMOS transistor N1. The first PMOS transistor P1 is turned on, the first NMOS transistor N1 is turned on, the level at point A is high, the second NMOS transistor N2 is turned on, the output level of the output terminal IN1 is close to GND, and the output IN1 is still low.

[0038] When the input level IN is higher than 2.4V, V GS (P1) < V GS (P2), V H The current generated still flows through the branch composed of the first PMOS transistor P1 and the first NMOS transistor N1. The second PMOS transistor P2 is turned on, and the output level of the output terminal IN1 is close to VH. The output IN1 is still high.

[0039] It can be seen that when the circuit is irradiated with a total dose of 300 krad (Si), the output terminal IN1 is the same as before irradiation, that is, the radiation hardening comparator input circuit of this application embodiment can work normally under a total dose of 300 krad (Si).

[0040] Based on the above technical solution of this application, when the circuit is irradiated with 300 krad (Si), the threshold voltages of P1 and P2 drift from -1.1V to approximately -1.5V, while N1 and N2, being thin-gate oxide NMOS transistors, drift from approximately 1.5V to approximately 1.2V. The threshold voltage drift amounts of the first PMOS transistor P1 and the second PMOS transistor P2 are the same, as are the threshold voltage drift amounts of the first NMOS transistor N1 and the second NMOS transistor N2. This does not affect the current distribution of the comparator input structure or the voltage at the output terminal IN1 after irradiation, thus achieving the goal of improving the total dose irradiation resistance of the high-voltage input stage structure.

[0041] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A comparator input circuit with resistance to total dose hardening, characterized in that, include: The first PMOS transistor has its gate as the input terminal and its source connected to an external power supply. The gate of the second PMOS transistor is connected to the reference voltage, and the source of the second PMOS transistor is connected to an external power supply. The drain of the first NMOS transistor is shorted to the gate and connected to the drain of the first PMOS transistor, and the source of the first NMOS transistor is grounded. The gate of the second NMOS transistor is connected to the gate of the first NMOS transistor, and the source of the second NMOS transistor is grounded; the drain of the second NMOS transistor is connected to the drain of the second PMOS transistor as the output terminal. The voltage divider branch divides the voltage of the external power supply to provide the reference voltage, wherein the gate oxide thickness of the PMOS transistor is greater than that of the NMOS transistor.

2. The comparator input circuit for anti-total dose hardening according to claim 1, characterized in that, The first PMOS transistor has the same dimensions as the second PMOS transistor.

3. The comparator input circuit for anti-total dose hardening according to claim 1, characterized in that, The first NMOS transistor has the same size as the second NMOS transistor.

4. The comparator input circuit for anti-total dose hardening according to claim 2, characterized in that, Both the first PMOS transistor and the second PMOS transistor have a gate oxide thickness of 60 nm.

5. The comparator input circuit for anti-total dose hardening according to claim 3, characterized in that, Both the first NMOS transistor and the second NMOS transistor have a gate oxide thickness of 30 nm.

6. The comparator input circuit for anti-total dose hardening according to claim 1, characterized in that, The voltage divider branch includes a first resistor and a second resistor. One end of the first resistor is connected to the external power supply, and the other end of the first resistor is connected to one end of the second resistor. The other end of the second resistor is grounded, and the connection point of the first resistor and the second resistor serves as the output terminal of the reference voltage.

7. The comparator input circuit for anti-total dose hardening according to claim 6, characterized in that, The reference voltage is adjusted by changing the resistance ratio of the first resistor to the second resistor.

8. The comparator input circuit for total dose hardening according to claim 7, characterized in that, The resistance ratio of the first resistor to the second resistor is 37:

3.

9. The comparator input circuit for anti-total dose hardening according to claim 1, characterized in that, Under 300 klad (Si) irradiation, the threshold voltage drift of the first PMOS transistor and the second PMOS transistor is the same; Under 300 klad (Si) irradiation, the threshold voltage drift of the first NMOS transistor and the second NMOS transistor is the same.

10. The comparator input circuit for anti-total dose hardening according to claim 1, characterized in that, The reference voltage is 1.5V.

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