Self-resetting circuit adaptable to different power-on speeds of power supply

Abstract

The application discloses a self-resetting circuit which can adapt to different power-on speeds of a power supply, one end of a Detector module is connected with the power supply Vdd, and one end of the Detector module outputs an sc signal; the sc signal is connected with a power-on self-resetting module POR and is controlled by a switch S1; the Detector module is used for detecting the power-on voltage of the power supply Vdd, and outputs the sc signal and opens the switch S1 after reaching a set Detector module trigger voltage; vdd_c rises from 0 to the vdd voltage, triggers the power-on self-resetting module POR, and outputs a valid reset waveform. The resistance value of the pull-down resistor R1 is greater than 1 Mohm, which is used for pulling down vdd_c to the ground and reducing power consumption; the switch S1 is a PMOS transistor, which is used for controlling the input of the sc signal. The above-mentioned circuit can effectively trigger the self-resetting under the condition of not increasing the RC area, and can meet the power-on speed of the power supply, thereby improving the performance of the power-on self-resetting circuit.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a self-reset circuit that can adapt to different power-on speeds. Background Technology

[0002] Traditional power-on reset (POR) circuits typically use RC delay modules to achieve power-on reset. However, when the power-on speed is very slow, much longer than the RC delay time, a reset failure may occur. Figure 1 The diagram shows a conventional power-on self-reset circuit in the prior art. When the power-on time of VDD is slower than the RC delay time, the reset will not occur in the stable region of VDD, causing the power-on reset to fail. Figure 2 The diagram illustrates a power-on reset failure in the prior art. The correct reset position should be after vdd has stabilized, with por_out remaining low for a period of time, such as... Figure 3 The diagram shown illustrates a correct reset using existing technology.

[0003] In some cases, especially when the power supply line is a long twisted pair, the power-on is slow. The internal area of ​​the chip is limited and cannot provide enough RC to meet the slow power-on, which may result in incorrect reset. Summary of the Invention

[0004] The purpose of this invention is to provide a self-reset circuit that can adapt to different power-on speeds. This circuit can effectively trigger self-reset at any power-on speed without increasing the RC area, thereby improving the performance of the power-on self-reset circuit.

[0005] The objective of this invention is achieved through the following technical solution:

[0006] A self-reset circuit adaptable to different power-on speeds, the circuit comprising a detector module, a switch S1, a pull-down resistor R1, and a power-on self-reset module POR, wherein:

[0007] One end of the Detector module is connected to the power supply VDD, and the other end outputs a switch control SC signal; the SC signal is controlled by switch S1 and connected to the power-on self-reset module POR.

[0008] The Detector module is used to detect the power-on voltage of the power supply Vdd, and outputs the sc signal and turns on the switch S1 after the set Detector module trigger voltage is reached;

[0009] The switch S1 is a PMOS or CMOS transistor, and its control signal is the sc signal output by the Detector module. The sc signal controls the opening or closing of the switch. The input signal of the switch S1 is the power supply vdd, and the output signal is the power transmission signal vdd_c. When the sc signal is 0, vdd_c = vdd, otherwise vdd_c = 0.

[0010] When the power signal vdd_c rises from 0 to the power supply vdd, the power-on self-reset module POR is triggered, and a valid reset waveform is output.

[0011] The pull-down resistor R1 has a resistance greater than 1 Mohm and is used to pull the power supply signal vdd_c down to ground to reduce power consumption.

[0012] As can be seen from the technical solution provided by the present invention, the above circuit can effectively trigger self-reset at any power-on speed without increasing the RC area, thereby improving the performance of the power-on self-reset circuit. Attached Figure Description

[0013] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a schematic diagram of the structure of a traditional power-on self-reset circuit in the prior art;

[0015] Figure 2 This is a schematic diagram illustrating power-on reset failure in the prior art;

[0016] Figure 3 A schematic diagram illustrating the correct reset using existing technology;

[0017] Figure 4 A schematic diagram of the structure of a self-reset circuit that can adapt to different power-on speeds provided in an embodiment of the present invention;

[0018] Figure 5 This is a timing diagram of the self-reset circuit described in an embodiment of the present invention;

[0019] Figure 6 This is a schematic diagram of the Detector module described in an embodiment of the present invention. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments, and do not constitute a limitation of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present invention.

[0021] like Figure 4 The diagram shown is a schematic representation of a self-reset circuit adaptable to different power-on speeds provided in an embodiment of the present invention. The circuit includes a detector module, a switch S1, a pull-down resistor R1, and a power-on self-reset module POR, wherein:

[0022] One end of the Detector module is connected to the power supply VDD, and the other end outputs a switch control (sc) signal; the sc signal is controlled by switch S1 and connected to the power-on self-reset module POR.

[0023] The Detector module is used to detect the power-on voltage of the power supply Vdd, and outputs the sc signal and turns on the switch S1 after the set Detector module trigger voltage is reached;

[0024] The switch S1 is a PMOS or CMOS transistor, and its control signal is the sc signal output by the Detector module. The sc signal controls the opening or closing of the switch. The input signal of the switch S1 is the power supply vdd, and the output signal is the power transmission signal vdd_c. When the sc signal is 0, vdd_c = vdd, otherwise vdd_c = 0.

[0025] When the power signal vdd_c rises from 0 to the power supply vdd, the power-on self-reset module POR is triggered, and a valid reset waveform is output.

[0026] The pull-down resistor R1 has a resistance greater than 1 Mohm and is used to pull the power signal vdd_c to ground to reduce power consumption. In specific implementation, the pull-down resistor R1 is used to pull the power signal vdd_c to ground so that there is a fixed initial level. Before the power supply reaches the threshold, vdd_c = 0, so that the entire circuit is in a non-working state. Using a resistor greater than 1 Mohm, or even a larger resistor, is a consideration for power consumption. After vdd_c = vdd, the power consumption is relatively small.

[0027] like Figure 5 The diagram shown is a timing diagram of the self-reset circuit according to an embodiment of the present invention, and its operation process is as follows:

[0028] 1. Before Vdd is powered on, vdd_c is pulled down to ground by the pull-down resistor R1, and the entire circuit does not work;

[0029] 2. When VDD starts to power on but does not reach the trigger voltage of the detector module, the SC signal is high, switch S1 is open, VDD_C is 0, the power-on self-reset module POR does not work, and the output por_out is low.

[0030] 3. When Vdd is powered on and reaches or exceeds the trigger voltage of the detector module, the SC signal is pulled low, switch S1 is closed, Vdd_C rises from 0 to Vdd, triggering the power-on self-reset module POR, and outputting a valid reset waveform por_out.

[0031] In specific implementation, such as Figure 6 The diagram shown is a structural schematic of the Detector module according to an embodiment of the present invention. The Detector module consists of two parts, including a voltage divider circuit module and a comparator circuit module, wherein:

[0032] The input of the comparator circuit module is connected to the output of the voltage divider circuit module, and the output of the comparator circuit module is the sc signal;

[0033] The voltage divider circuit module consists of three cascaded NMOS transistors connected in the form of diodes and a voltage divider resistor R2;

[0034] The comparator circuit module is implemented using an inverter. The output signal of the voltage divider circuit module, after entering the comparator circuit module, can generate a flip signal. This comparator circuit module consists of a PMOS and an NMOS transistor. The comparison threshold is the flip threshold of the inverter, which is determined by the size and manufacturing process of the PMOS and NMOS transistors. In practice, this comparator circuit module can also be implemented using other comparators.

[0035] In addition, the NMOS transistors in the detector module can be replaced with PMOS transistors or diodes, and the number of NMOS transistors and the resistance value of resistor R2 can be adjusted as needed;

[0036] In practice, the value of R2 can be greater than 1 Mohm, thereby reducing power consumption.

[0037] It is worth noting that the contents not described in detail in the embodiments of the present invention belong to the prior art known to those skilled in the art.

[0038] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims. The information disclosed in the background section is intended only to enhance the understanding of the overall background technology of the present invention and should not be construed as an admission or implication in any way that such information constitutes prior art known to those skilled in the art.

Claims

1. A self-resetting circuit adaptable to different power-on speeds, characterized in that, The circuit includes a detector module, a switch S1, a pull-down resistor R1, and a power-on self-reset module POR, wherein: One end of the detector module is connected to the power supply VDD, and the other end outputs a switch control SC signal; the switch S1 is controlled by the switch control SC signal and connected to the power-on self-reset module POR. The detection module is used to detect the power-on voltage of the power supply Vdd, and outputs a switch control sc signal after the set detection module trigger voltage is reached, and turns on the switch S1. The control signal for switch S1 is the switch control sc signal output by the detector module, which controls the opening or closing of switch S1. The input signal for switch S1 is power supply vdd, and the output signal is power transmission signal vdd_c. When the switch control sc signal is 0, vdd_c = vdd; otherwise, vdd_c = 0. When the power signal vdd_c rises from 0 to the power supply vdd, the power-on self-reset module POR is triggered, and a valid reset waveform is output. The pull-down resistor R1 has a resistance greater than 1 Mohm and is used to pull the power signal vdd_c to ground to reduce power consumption. The input terminal of switch S1 is connected to the power supply Vdd, the control terminal is connected to the switch control signal sc, and the output terminal is connected to one end of the pull-down resistor R1 and the power-on self-reset module POR; the other end of the pull-down resistor R1 is grounded.

2. The self-reset circuit adaptable to different power-on speeds according to claim 1, characterized in that, The detection module includes a voltage divider circuit module and a comparator circuit module, wherein: The input of the comparator circuit module is connected to the output of the voltage divider circuit module, and the output of the comparator circuit module is a switch control sc signal; The voltage divider circuit module consists of three cascaded NMOS transistors connected in the form of diodes and a voltage divider resistor R2; The comparator circuit module is implemented by an inverter, and the output signal of the voltage divider circuit module can generate a flip signal after entering the comparator circuit module. The comparator circuit module consists of a PMOS and an NMOS transistor. The comparison threshold is the inverter's flip threshold, which is determined by the size and process conditions of the PMOS and NMOS transistors.

3. The self-reset circuit adaptable to different power-on speeds according to claim 2, characterized in that, The NMOS transistors in the detector module can be replaced with PMOS transistors or diodes, and the number of NMOS transistors and the resistance value of the voltage divider resistor R2 can be adjusted as needed.

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