Fast-locking low-jitter phase-locked loop

Abstract

The application provides a kind of low-jitter phase-locked loop of quick locking, adopts the charge pump phase-locked loop based on double ring, utilizes auxiliary phase error detection and phase difference gain amplification module APD&At dynamic amplification phase error to speed up the frequency locking speed, and by controlling the frequency ratio change to adjust reference clock signal and feedback clock signal in the process of frequency locking keep phase error minimization, specifically including frequency discriminator phase detector PFD, auxiliary phase error detection and phase difference gain amplification module APD&At, voltage current conversion circuit V-I, frequency divider DIV, current control oscillator CCO and frequency voltage module F-V;The application can keep the minimization of the phase error of reference clock signal and feedback clock signal in the process of frequency locking, and by dynamic amplification phase error to speed up the frequency locking speed;Utilize feedback to increase the range of output frequency, and reduce the performance influence of PVT variation on phase noise and jitter.

Description

Technical Field

[0001] This invention relates to a fast-locking, low-jitter phase-locked loop, belonging to the field of integrated circuit technology. Background Technology

[0002] Phase-locked loops (PLLs) are widely used in communication systems and clock generation processors. The functionality and performance of the PLL play a decisive role in the overall system. For example, when the PLL is switching frequencies, it cannot transmit data, so the PLL's lock time must be fast enough to avoid reducing the data rate, and fast locking is an important component of low power consumption. Phase noise and jitter affect data error rates. Therefore, PLLs need to have good phase noise, jitter, and lock time.

[0003] Since the phase noise, phase jitter, and settling time of a phase-locked loop system are closely related to the loop's transfer function, the locking time can be accelerated by increasing the bandwidth during the locking process. However, increasing the bandwidth will also worsen the phase noise performance.

[0004] Currently, bandwidth switching technology is used to speed up the locking time. However, when the output frequency reaches the final frequency, the phase still needs to be locked, and frequency modulation is used to continue phase locking, which wastes locking time. As the PVT (process, power supply voltage, temperature) changes, the parameters that make up the loop transfer function (charge pump current, oscillator gain, etc.) will change, which will worsen the output noise of the entire phase-locked loop.

[0005] like Figure 1 Theoretical analysis is performed on a charge pump phase-locked loop based on a traditional double-loop circuit. Its loop transfer function is as follows: Among them, H loop Where C is the loop gain, S is the capacitance, and A is the complex frequency. i Where N is the conversion gain of the voltage-to-current conversion circuit, and I is the division ratio of the frequency divider. cp1 with I cp2 K represents the charging and discharging currents of the two charge pump branches. CCO This refers to the current-controlled gain of the current-controlled oscillator.

[0006] The loop bandwidth w of the phase-locked loop system can be obtained. -3dB The damping factor ξ is respectively: From the above equation, it can be seen that the loop bandwidth is closely related to parameters such as the damping factor, charge pump current, frequency division ratio, capacitance, and current control gain. Furthermore, it can be observed that the loop bandwidth is related to the charge pump current I. cp1Since this is irrelevant, dual-loop charge pump phase-locked loops are more suitable for controlling individual loop parameters to accelerate the locking speed and reduce jitter. However, as the loop bandwidth increases and the locking time accelerates, the phase error is not zero when the reference frequency equals the feedback frequency, requiring frequency modulation to achieve phase locking, which increases the locking time.

[0007] The above-mentioned issues should be considered and resolved during the design process of a fast-locking, low-jitter phase-locked loop. Summary of the Invention

[0008] The purpose of this invention is to provide a fast-locking, low-jitter phase-locked loop to solve the problems in the prior art, such as large phase error and long locking time during frequency locking, and the need to reduce the impact of PVT changes on phase noise and jitter performance.

[0009] The technical solution of this invention is:

[0010] A fast-locking, low-jitter phase-locked loop (PLL) employs a dual-loop charge pump PLL. It utilizes an auxiliary phase error detection and phase difference gain amplification module (APD&At) to dynamically amplify the phase error, accelerating frequency locking. Furthermore, it minimizes the phase error between the reference clock signal and the feedback clock signal during frequency locking by controlling the frequency division ratio. The PLL includes a phase-frequency discriminator (PFD), an auxiliary phase error detection and phase difference gain amplification module (APD&At), a voltage-to-current conversion circuit (VI), a frequency divider (DIV), a current-controlled oscillator (CCO), and a frequency-to-voltage conversion module (FV).

[0011] Frequency and phase detector (PFD): Detects the frequency difference or phase difference between the input reference clock signal and the feedback clock signal from the frequency divider (DIV), and outputs UP and DN signals reflecting the phase error, directly controlling the charge pump I. cp2 The charge and discharge time;

[0012] Auxiliary Phase Error Detection and Phase Difference Gain Amplification Module (APD&At): Dynamically amplifies the phase error of the input UP and DN signals, generating UP1 and DN1 signals to control charge pump I. cp1 The charging and discharging time of capacitor C is determined, and control signals S0-S3 are generated to control charge pump I. cp2 The magnitude of the charging current changes with the frequency division ratio of the control frequency divider;

[0013] Voltage-to-current conversion circuit VI: Converts the voltage across capacitor C into output current I. I Output current I I With charge pump I cp2 The resulting currents are added together to obtain the current Ictr;

[0014] The current-controlled oscillator (CCO) generates the desired output clock frequency Fout from the input current Ictr and controls the voltage V. c Linear feedback charge pump I according to a set ratio cp2 As a charge pump I cp2 The current is used to ensure that the bandwidth does not change with the frequency division ratio;

[0015] Frequency-to-voltage module FV: Converts the output clock frequency Fout into the output voltage V. f This feedback is then fed back to the current-controlled oscillator (CCO) to form a closed loop, thereby increasing the linearity of the CCO and detecting the output frequency to pre-start the CCO to reach the predetermined frequency.

[0016] Frequency divider DIV: Based on the frequency division ratio change of the auxiliary phase error detection and phase difference gain amplification module APD&At, the output clock frequency Fout generates a feedback clock signal and outputs it to the frequency and phase detector PFD.

[0017] Furthermore, the Auxiliary Phase Error Detection and Phase Difference Gain Amplification Module (APD&At) includes a two-input XOR gate, four adjustable delay units, four D flip-flops, four switches, a six-input OR gate, two RS flip-flops composed of two two-input NOR gates, and two AND gates.

[0018] The circuit starts working when the enable signal S4 of the six-input OR gate is 1. The frequency and phase detector PFD generates a signal UP carrying phase error and a signal DN, which are XORed to generate a signal T0, which is output to the six-input OR gate. The signal T0 is then output to the D input of the four D flip-flops. The signal T0 passes through four cascaded adjustable delay units to generate signals T1, T2, T3, and T4, respectively. The rising edges of signals T1, T2, T3, and T4 are used as trigger signals and connected to the CLK terminals of the four D flip-flops to determine the pulse width. The Q outputs of the four D flip-flops are connected to switches S0, S1, S2, and S3, respectively.

[0019] The frequency and phase detector (PFD) generates a phase error signal UP and a phase error signal DN, which are input to the RS flip-flop to determine whether the phase of the reference clock signal leads or lags the feedback clock signal.

[0020] Signals T1, T2, T3, and T4 are passed through switches S0, S1, S2, and S3 respectively, then input to a six-input OR gate to output signal T5. The four switches S0-S3 dynamically control the gain of the phase error. Signal T5 is ANDed with the output signals of the lead and lag terminals of the RS flip-flop through two AND gates, outputting signals UP1 and DN1 respectively to control I. cp1 .

[0021] Furthermore, the phase detector (PFD) generates a phase error signal UP and a phase error signal DN, which are then input to the RS flip-flop to determine whether the reference clock signal phase leads or lags the feedback clock signal. Specifically, when the reference clock signal phase leads the feedback clock signal phase, the lead terminal of the RS flip-flop outputs 1, and the lag terminal outputs 0; when the reference clock signal phase lags the feedback clock signal phase, the lead terminal of the RS flip-flop outputs 0, and the lag terminal outputs 1.

[0022] Furthermore, control signals S0-S3 control the division ratio of the frequency divider, specifically,

[0023] When the pulse width t0 representing the phase error signal T0 is less than the delay time τ of the delay unit, the 4-bit control signals S0-S3 are 0000, and the change in the control frequency division ratio is Δn0 = 0.

[0024] When the pulse width t0 representing the phase error signal T0 is less than 2τ and greater than τ, the 4-bit control signals S0-S3 are 1000, and the oscillator output oscillation period is assumed to be T. cco The reference clock period is T. ref The maximum change in the control frequency division ratio is

[0025] When the pulse width t0, representing the phase error signal T0, is less than 3τ and greater than 2τ, the 4-bit control signals S0-S3 are 1100, and the maximum change in the control frequency division ratio is...

[0026] When the pulse width t0, representing the phase error signal T0, is less than 4τ and greater than 3τ, the 4-bit control signals S0-S3 are 1110, and the maximum change in the control frequency division ratio is...

[0027] When the pulse width t0 representing the phase error signal T0 is greater than 4τ, the 4-bit control signals S0-S3 are 1111, and the maximum change in the control frequency division ratio is...

[0028] Furthermore, this fast-locking, low-jitter phase-locked loop has two operating modes: a fast-locking mode and a normal-locking mode.

[0029] When the phase error is greater than When in fast lock mode, switch S3 is set to 1, controlling charge pump I. cp2 Shutdown, via charge pump I cp1 A loop is used for phase-frequency locking;

[0030] When the phase error is less than In normal lockout mode, switch S3 is set to 0, controlling charge pump I. cp2 It is enabled to provide zero-point compensation and uses a dual-ring phase-locked loop for phase locking.

[0031] Furthermore, in the frequency-to-voltage module FV, the output frequency is detected to pre-start the current and control the oscillator CCO to reach a predetermined frequency. Specifically, this involves comparing the output voltage V of the frequency-to-voltage module FV. f With the set reference voltage V2, at V f When the frequency reaches >V2, the oscillation frequency meets the preset requirement, the capacitor charging path is closed, and the phase-locked loop (PLL) is started to perform a frequency-phase locking process. f When the frequency is ≤V2, the oscillation frequency has not reached the preset requirement, so the capacitor continues to be charged to speed up the frequency locking speed.

[0032] Furthermore, it also includes a configuration module Config: used to configure the division ratio of the frequency divider, the tuning curve of the current control gain of the current-controlled oscillator CCO, the delay time τ of the delay unit of the auxiliary phase error detection and phase difference gain amplification module APD&At, and to perform initialization reset.

[0033] The beneficial effects of this invention are:

[0034] I. This fast-locking, low-jitter phase-locked loop (PLL) uses a dual-loop charge pump PLL and adaptively dynamically controls the division ratio of the feedback loop divider to minimize the phase error between the reference clock signal and the feedback clock signal during frequency locking. It also accelerates the frequency locking speed by dynamically amplifying the phase error. Furthermore, it utilizes feedback to increase the output frequency range and reduce the impact of PVT variations on phase noise and jitter performance.

[0035] II. This invention utilizes an auxiliary phase error detection and phase difference gain amplification module (APD&At) to detect the magnitude of the phase error. By adjusting the frequency division ratio, the reference clock signal and the feedback clock signal are adjusted to minimize the phase error during frequency locking. Furthermore, At amplifies the error, increasing the charging time of capacitor C and reducing its impact on the frequency locking time. This minimizes the phase error during frequency locking, thereby accelerating the locking time and resulting in a faster locking time compared to bandwidth switching technology.

[0036] Third, this fast-locking low-jitter phase-locked loop uses a frequency-to-voltage module (FV) and a current-controlled oscillator (CCO) to form negative feedback to increase the linearity of the oscillator and reduce the impact of PVT changes, thereby improving jitter performance. It also uses multiple tuning curves to reduce sensitivity to noise.

[0037] IV. This type of fast-locking, low-jitter phase-locked loop uses a pre-start process where the frequency-to-voltage module (FV) detects whether the output frequency has reached the preset frequency, thus accelerating the frequency locking process. Attached Figure Description

[0038] Figure 1 This is a schematic diagram illustrating a traditional double-ring charge pump phase-locked loop;

[0039] Figure 2 This is an illustrative diagram illustrating the low-jitter phase-locked loop with rapid locking according to an embodiment of the present invention;

[0040] Figure 3 This is a schematic diagram illustrating the auxiliary phase error detection and phase difference gain amplification module APD&At in the embodiment.

[0041] Figure 4 This is a schematic diagram of the working timing of the auxiliary phase error detection and phase difference gain amplification module APD&At in the embodiment;

[0042] Figure 5 This is a schematic diagram illustrating the voltage-to-current conversion circuit VI in the embodiment;

[0043] Figure 6 This is a schematic diagram of the working timing of the low-jitter phase-locked loop for fast locking in the embodiment;

[0044] Figure 7 This is a schematic diagram of the negative feedback circuit formed by the current-controlled oscillator CCO and the frequency-to-voltage module FV in the embodiment;

[0045] Figure 8 This is a schematic diagram of the tuning curve of the current-controlled gain of the current-controlled oscillator (CCO) in the embodiment.

[0046] Figure 9 This is a schematic diagram comparing the frequency change over time during the locking process of the fast-locking low-jitter phase-locked loop in the embodiment with that of the conventional dual-ring charge pump phase-locked loop. Detailed Implementation

[0047] The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0048] Example

[0049] A fast-locking, low-jitter phase-locked loop employs a dual-loop charge pump phase-locked loop. It utilizes an auxiliary phase error detection and phase difference gain amplification module (APD&At) to dynamically amplify the phase error, thereby accelerating frequency locking. Furthermore, it minimizes the phase error between the reference clock signal and the feedback clock signal during frequency locking by controlling the frequency division ratio. Figure 2It includes a frequency and phase detector (PFD), an auxiliary phase error detection and phase difference gain amplification module (APD&At), a voltage-to-current conversion circuit (VI), a frequency divider (DIV), a current-controlled oscillator (CCO), and a frequency-to-voltage conversion module (FV).

[0050] Frequency and phase detector (PFD): Detects the frequency difference or phase difference between the input reference clock signal and the feedback clock signal from the frequency divider (DIV), and outputs UP and DN signals reflecting the phase error, directly controlling the charge pump I. cp2 The charge and discharge time;

[0051] Auxiliary Phase Error Detection and Phase Difference Gain Amplification Module (APD&At): Dynamically amplifies the phase error of the input UP and DN signals, generating UP1 and DN1 signals to control charge pump I. cp1 The charging and discharging time of capacitor C is determined, and control signals S0-S3 are generated to control charge pump I. cp2 The magnitude of the charging current changes with the frequency division ratio of the control frequency divider;

[0052] Voltage-to-current conversion circuit VI: Converts the voltage across capacitor C into output current I. I Output current I I With charge pump I cp2 The resulting currents are added together to obtain the current Ictr;

[0053] The current-controlled oscillator (CCO) generates the desired output clock frequency Fout from the input current Ictr and controls the voltage V. c Linear feedback charge pump I according to a set ratio cp2 As a charge pump I cp2 The current is used to ensure that the bandwidth does not change with the frequency division ratio;

[0054] Frequency-to-voltage module FV: Converts the output clock frequency Fout into the output voltage V. f This feedback is then fed back to the current-controlled oscillator (CCO) to form a closed loop, maintaining the linearity of the current-controlled gain, and detecting the output frequency to pre-start the current-controlled oscillator (CCO) to reach the predetermined frequency.

[0055] Frequency divider DIV: Based on the frequency division ratio change of the auxiliary phase error detection and phase difference gain amplification module APD&At, the output clock frequency Fout generates a feedback clock signal and outputs it to the frequency and phase detector PFD.

[0056] This fast-locking, low-jitter phase-locked loop (PLL) uses a dual-loop charge pump PLL and adaptively dynamically controls the division ratio of the feedback loop divider to minimize the phase error between the reference clock signal and the feedback clock signal during frequency locking. It also accelerates the frequency locking speed by dynamically amplifying the phase error. Furthermore, it utilizes feedback to increase the output frequency range and reduce the impact of PVT variations on phase noise and jitter performance.

[0057] like Figure 3 The Auxiliary Phase Error Detection and Phase Difference Gain Amplification Module (APD&At) includes a two-input XOR gate, four adjustable delay units, four D flip-flops, four switches, a six-input OR gate, two RS flip-flops composed of two two-input NOR gates, and two AND gates.

[0058] The circuit starts working when the enable signal S4 of the six-input OR gate is 1. The frequency and phase detector PFD generates a signal UP carrying phase error and a signal DN, which are XORed to generate a signal T0, which is output to the six-input OR gate. The signal T0 is then output to the D input of the four D flip-flops. The signal T0 passes through four cascaded adjustable delay units to generate signals T1, T2, T3, and T4, respectively. The rising edges of signals T1, T2, T3, and T4 are used as trigger signals and connected to the CLK terminals of the four D flip-flops to determine the pulse width. The Q outputs of the four D flip-flops are connected to switches S0, S1, S2, and S3, respectively.

[0059] The frequency and phase detector (PFD) generates a phase error signal UP and a phase error signal DN, which are input to the RS flip-flop to determine whether the phase of the reference clock signal leads or lags the feedback clock signal.

[0060] Signals T1, T2, T3, and T4 are passed through switches S0, S1, S2, and S3 respectively, then input to a six-input OR gate to output signal T5. The four switches S0-S3 dynamically control the gain of the phase error. Signal T5 is ANDed with the output signals of the lead and lag terminals of the RS flip-flop through two AND gates, outputting signals UP1 and DN1 respectively to control I. cp1 .

[0061] The Auxiliary Phase Error Detection and Phase Difference Gain Amplification Module (APD&At) can determine the phase error output by the PFD, output 4-bit control signals S0-S3, and amplify the phase error. The specific workflow of the APD&At module is as follows: Figure 4As shown, the PFD starts working when the enable signal S4 is 1. The PFD generates UP and DN signals carrying phase error, which are then passed through an XOR gate to produce signal T0. One path of signal T0 passes through a cascaded delay chain τ, generating signals T1, T2, T3, and T4; the other path of signal T0 is connected to the D input of the D flip-flop. The rising edges of signals T1, T2, T3, and T4 are used as trigger signals connected to the CLK terminal of the D flip-flop to determine the pulse width. Signals UP and DN are also input to an RS flip-flop composed of NOR gates to determine whether the reference clock signal phase leads or lags the feedback clock signal phase. When the reference clock signal phase leads the feedback clock signal phase, the lead output is 1 and the lag output is 0; when the reference clock signal phase lags the feedback clock signal phase, the lead output is 0 and the lag output is 1. The generated control signals S0-S3 and lead / lag signals dynamically control the division ratio of the frequency divider. S0-S3 controls how much the division ratio changes, while lead / lag controls the addition or subtraction of the division ratio, thereby minimizing the phase error between the reference signal and the feedback signal.

[0062] Control signals S0-S3 control the division ratio of the frequency divider, specifically...

[0063] If the pulse width (t0) of the phase error signal T0 is less than τ, the 4-bit control signals S0-S3 are 0000, and the change in the control frequency division ratio is Δn0 = 0.

[0064] If t0 is less than 2τ and greater than τ, the 4-bit control signals S0-S3 are 1000, assuming the oscillator output oscillation period is T. cco The reference clock period is T. ref The maximum change in the control frequency division ratio is

[0065] If t0 is less than 3τ and greater than 2τ, the 4-bit control signal S0-S3 is 1100, and the maximum change in the control frequency division ratio is...

[0066] If t0 is less than 4τ and greater than 3τ, the 4-bit control signal S0-S3 is 1110, and the maximum change in the control frequency division ratio is...

[0067] If t0 is greater than 4τ, the four-position control signal S0-S3 is 1111, and the maximum change in the control frequency division ratio is...

[0068] This is because the phase-locked loop adjusts the frequency by detecting the phase error. When the reference frequency is equal to the feedback frequency, frequency modulation is still required to achieve phase locking due to unequal phases, which will prolong the locking time. By dynamically minimizing the phase error during the frequency locking process, it can avoid the need for additional frequency modulation to achieve phase locking when the output frequency reaches the locked frequency. However, as the frequency division ratio of the frequency divider is adjusted to reduce the phase error, this will shorten the charge and discharge time of the charge pump and prolong the charging time for the capacitor, which leads to the prolongation of the loop's response time to the phase and results in prolonged frequency locking time. To solve this problem, switches S0-S3 are used to control signals T1-T4 to generate signal T5 through an OR gate, so as to dynamically amplify the phase error, which can increase the charge pump I cp1 's charge and discharge time, thereby accelerating the frequency locking. The T5 signal is respectively ANDed with the lead signal and the lag signal, and then outputs UP1 and DN1 signals to control I cp1 .

[0069] Switches S0-S3 can dynamically control the gain of the phase error. When the switch control signal is 1, it controls the switch to close, and when it is 0, it controls the switch to open. Assuming t5 is the pulse width of the output signal T5, and At is the amplification gain. If t0<τ, S0-S3 is 0000, the output t5=t0, and the gain At=1; if τ<t0<2τ, S0-S3 is 1000, the output t5=t0+τ, and the gain At=1+τ / t0; if 2τ<t0<3τ, S0-S3 is 1100, the output t5=t0+2τ, and the gain At=1+2τ / t0; if 3τ<t0<4τ, S0-S3 is 1110, the output t5=t0+3τ, and the gain At=1+3τ / t0; if 4τ<t0, S0-S3 is 1111, the output t5=t0+4τ, and the gain At=1+4τ / t0. The maximum range of gain variation 1<At<5 can be achieved, which increases the charging time for the capacitor, and the control current Ictr of the current-controlled oscillator is obtained as:

[0070]

[0071] Wherein, △φ is the phase error, A i is the conversion gain of the voltage-to-current conversion circuit V-I, and the voltage-to-current conversion circuit V-I is as shown in Figure 5 , which is connected to the source of MOS tube NM1 through resistor R3, and the input is connected to the gate of NM1 tube. Negative feedback is used to increase the linearity and stability of A i , and negative feedback is used at the output to increase the output impedance and improve the accuracy of current copying. Wherein the current of I cp2 is determined by the control voltage V c of the voltage-controlled oscillator in the CCO. Figure 6This is a timing diagram of the phase-locked loop (PLL), showing the changes in the frequency division ratio and the corresponding charging time during the PLL locking process.

[0072] This fast-locking, low-jitter phase-locked loop has two operating modes: fast-locking mode and normal-locking mode.

[0073] When the phase error is relatively large, greater than In fast lock mode, switch S3 is set to 1, controlling charge pump I. cp2 Close, via I cp1 A loop is used for phase-frequency locking. The control current for the oscillator at this time is... Using At to accelerate the charging and discharging time of capacitor C speeds up the frequency lock-in time, while dynamically adjusting the phase error through the frequency division ratio provides zero-point compensation, eliminating the need for a charge pump I during rapid lock-in. cp2 This can stabilize the loop.

[0074] If the phase error is less than At this time, it is in normal locking mode, switch S3 is 0, and control I... cp2 Open, provide zero-point compensation, and use a dual-ring phase-locked loop for phase locking. At this time, due to I cp2 ∝V c V c ∝W out ∝N*W ref W out W is the angular frequency of the oscillator output clock signal. ref Given the angular frequency of the input clock reference signal, we can obtain I. cp2 ∝N*W ref We can assume I cp2 =x*N*W ref At this time, the loop bandwidth is It can be observed that the loop bandwidth is independent of the frequency division ratio N. Regarding the damping factor... Because I cp2 ∝N*Wref, setting I cp1 ∝N*Wref2, which ensures that the damping factor does not change with the frequency division ratio.

[0075] like Figure 7 The frequency-to-voltage module FV includes a switched capacitor, an operational amplifier, a resistor R1, a comparator, and a two-output non-overlapping clock generation module. This module can convert the output frequency of a current-controlled oscillator (CCO) into a voltage value V. f This feedback is then sent to the current-controlled oscillator (CCO), which includes resistor R2, capacitor C3, operational amplifier, and voltage-controlled oscillator (VCO). Switch S5 is configured by the configuration circuit config, which adjusts the oscillator's tuning curve by controlling the current I1. Figure 8As shown, reducing the slope of the tuning curve can decrease noise interference. Furthermore, negative feedback can increase the linearity of the oscillator and reduce its phase noise. The detailed derivation is as follows:

[0076] Assume K close-cco For the closed-loop CCO gain, the switched capacitor can be equivalent to a resistor, which can be obtained when the oscillator is stable:

[0077] Ictr*R2+I1*R2=V1+V1*Fout*C1*R1

[0078] The output clock frequency Fout is:

[0079]

[0080] in Therefore, the current-controlled gain is only related to the ratio of resistors R2 and R1, the reference voltage V1, and the capacitor C1, effectively reducing the impact of PVT changes on the current-controlled gain. Thus, the negative feedback provides good linearity. Furthermore, by changing the current I1, the tuning curve of the closed-loop oscillator can be altered, offering four adjustable levels configured according to the Config division ratio. Different tuning curves exist in different output frequency ranges, achieving low current-controlled gain and reducing sensitivity to noise. Moreover, the closed-loop feedback suppresses the phase noise of the VCO.

[0081] like Figure 7 In the frequency-to-voltage module FV, the output frequency is detected to pre-start the current and control the oscillator CCO to reach a predetermined frequency. Specifically, this involves comparing the output voltage V of the frequency-to-voltage module FV. f With the set reference voltage V2, at V f When the oscillation frequency reaches the preset requirement (>V2), it is turned off. Figure 2 The charging path of capacitor C initiates the phase-locked loop (PLL), and the frequency and phase locking process is performed through the loop; at V f When V2 is less than or equal to 2, the oscillation frequency does not meet the preset requirements. Therefore, the capacitor C in step 2 is charged to speed up the frequency locking speed.

[0082] This type of fast-locking, low-jitter phase-locked loop has a pre-start process when it officially begins operation. This process involves charging the capacitor to start the oscillator. The output voltage of the frequency-to-voltage module FV is monitored, and a comparator is used, with one end connected to the output terminal V of FV. f V f = V1 + V1 * Fout * C1 * R1, the other end of the comparator is connected to the reference voltage V2, and by comparing V fThe value of V2 determines the oscillator frequency range. When the FV output voltage is greater than the set reference voltage, an S4 signal of 1 will be output, indicating that the oscillation frequency has reached the preset requirement. Then, the charging path will be closed, and the frequency and phase detector and charge pump I will be activated. cp1 I cp2 Modules such as frequency dividers begin the frequency phase-locking process through a loop. If the output of S4 is 0, it indicates that the oscillation frequency has not reached the preset requirement, and the capacitor continues to charge to accelerate the frequency locking speed. This is then controlled by the output voltage V. f Feedback is sent back to the current-controlled oscillator (CCO) to reduce oscillator noise.

[0083] This fast-locking, low-jitter phase-locked loop also includes a configuration module Config: used to configure the division ratio of the frequency divider, the tuning curve of the current-controlled oscillator CCO, the delay time τ of the delay unit of the auxiliary phase error detection and phase difference gain amplification module APD&At, and to perform initialization reset.

[0084] This fast-locking, low-jitter phase-locked loop (PLL) uses a reference clock signal from the crystal oscillator input through the left Frefclk port. A frequency and phase detector module detects the frequency difference or phase difference between the input reference clock and the feedback clock from the frequency divider, outputting signals UP and DN reflecting the phase error. One of these signals, UP and DN, is used by the auxiliary phase error detection and phase difference gain amplification module APD&At to generate signals UP1 and DN1 to control the charge pump I. cp1 The charging and discharging time of capacitor C is determined, and S0-S3 control signals are generated to control charge pump I. cp2 The charging current is related to the division ratio of the frequency divider; another signal, UP, and signal DN directly control the charge pump I. cp2 The charging and discharging time. The voltage of capacitor C is converted into current by a voltage-to-current converter, and then compared with I. cp2 The generated currents are summed to obtain a current Ictr, which is used to control the current-controlled oscillator module to generate the final required output clock frequency Fout, and V... c Charge pump I with linear feedback at a certain ratio cp2 As I cp2 The current is used to ensure that the bandwidth remains unchanged regardless of the division ratio. The frequency-to-voltage module converts the output clock frequency Fout into a voltage and feeds it back to the current-controlled oscillator to maintain the linearity of the current-controlled gain, and detects the output frequency to pre-start the oscillator to reach the predetermined frequency. Config allows configuration of the division ratio of the frequency divider, the tuning curve of the current-controlled gain, and the delay time τ of the delay unit of the APD&At module, and performs initialization reset.

[0085] This fast-locking, low-jitter phase-locked loop (PLL) uses an auxiliary phase error detection and phase difference gain amplification module (APD&At) to detect the phase error. It adjusts the reference clock signal and feedback clock signal by adjusting the frequency division ratio to minimize the phase error during frequency locking. The APD&At module amplifies the error, increasing the charging time of capacitor C and reducing its impact on frequency locking time. This minimizes the phase error during frequency locking, accelerating the locking time and resulting in a faster locking time compared to bandwidth switching techniques.

[0086] The comparison of frequency versus time during the locking process of this fast-locking, low-jitter phase-locked loop in the embodiment with that of a conventional dual-loop charge pump phase-locked loop is shown in the figure. Figure 9 Experiments have verified that this fast-locking, low-jitter phase-locked loop in the embodiment can significantly reduce the locking time.

[0087] This fast-locking, low-jitter phase-locked loop uses a frequency-to-voltage module (FV) and a current-controlled oscillator (CCO) to form negative feedback to increase the linearity of the oscillator and reduce the impact of PVT variations, thereby improving jitter performance. It also uses multiple tuning curves to reduce sensitivity to noise.

[0088] The above description is merely an embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of the present invention should be included within the scope of the claims of the present invention.

Claims

1. A fast-locking, low-jitter phase-locked loop, characterized in that: A dual-ring charge pump phase-locked loop (PLL) is employed, utilizing an auxiliary phase error detection and phase difference gain amplification module (APD&At) to dynamically amplify the phase error and accelerate frequency locking. Furthermore, the phase error between the reference clock signal and the feedback clock signal is minimized during frequency locking by controlling the frequency division ratio. Specifically, the circuit includes a frequency-phase detector (PFD), an auxiliary phase error detection and phase difference gain amplification module (APD&At), a voltage-to-current conversion circuit (VI), a frequency divider (DIV), a current-controlled oscillator (CCO), and a frequency-to-voltage conversion module (FV). Frequency and phase detector (PFD): Detects the frequency difference or phase difference between the input reference clock signal and the feedback clock signal from the frequency divider (DIV), and outputs UP and DN signals reflecting the phase error, directly controlling the charge pump I. cp2 The charge and discharge time; Auxiliary Phase Error Detection and Phase Difference Gain Amplification Module (APD&At): Dynamically amplifies the phase error of the input UP and DN signals, generating UP1 and DN1 signals to control charge pump I. cp1 The charging and discharging time of capacitor C is determined, and control signals S0-S3 are generated to control charge pump I. cp2 The magnitude of the charging current changes with the frequency division ratio of the control frequency divider; Voltage-to-current conversion circuit VI: Converts the voltage across capacitor C into output current I. I Output current I I With charge pump I cp2 The resulting currents are added together to obtain the current Ictr; The current-controlled oscillator (CCO) generates the desired output clock frequency Fout from the input current Ictr and controls the voltage V. c Linear feedback charge pump I according to a set ratio cp2 As a charge pump I cp2 The current is used to ensure that the bandwidth does not change with the frequency division ratio; Frequency-to-voltage module FV: Converts the output clock frequency Fout into the output voltage V. f This feedback is then fed back to the current-controlled oscillator (CCO) to form a closed loop, thereby increasing the linearity of the CCO and detecting the output frequency to pre-start the CCO to reach the predetermined frequency. Frequency divider DIV: Based on the frequency division ratio change of the auxiliary phase error detection and phase difference gain amplification module APD&At, the output clock frequency Fout generates a feedback clock signal and outputs it to the frequency and phase detector PFD.

2. The fast-locking, low-jitter phase-locked loop as described in claim 1, characterized in that: The Auxiliary Phase Error Detection and Phase Difference Gain Amplification Module (APD&At) includes a two-input XOR gate, four adjustable delay units, four D flip-flops, four switches, a six-input OR gate, two RS flip-flops composed of two two-input NOR gates, and two AND gates. The circuit starts working when the enable signal S4 of the six-input OR gate is 1. The frequency and phase detector PFD generates a signal UP carrying phase error and a signal DN, which are XORed to generate a signal T0, which is output to the six-input OR gate. The signal T0 is then output to the D input of the four D flip-flops. The signal T0 passes through four cascaded adjustable delay units to generate signals T1, T2, T3, and T4, respectively. The rising edges of signals T1, T2, T3, and T4 are used as trigger signals and connected to the CLK terminals of the four D flip-flops to determine the pulse width. The Q outputs of the four D flip-flops are connected to switches S0, S1, S2, and S3, respectively. The frequency and phase detector (PFD) generates a phase error signal UP and a phase error signal DN, which are input to the RS flip-flop to determine whether the phase of the reference clock signal leads or lags the feedback clock signal. Signals T1, T2, T3, and T4 are passed through switches S0, S1, S2, and S3 respectively, then input to a six-input OR gate to output signal T5. The four switches S0-S3 dynamically control the gain of the phase error. Signal T5 is ANDed with the output signals of the lead and lag terminals of the RS flip-flop through two AND gates, outputting signals UP1 and DN1 respectively to control I. cp1 .

3. The fast-locking, low-jitter phase-locked loop as described in claim 2, characterized in that: The frequency and phase detector (PFD) generates a phase error signal UP and a phase error signal DN, which are then input to the RS flip-flop to determine whether the phase of the reference clock signal leads or lags the feedback clock signal. Specifically, when the phase of the reference clock signal leads the phase of the feedback clock signal, the lead terminal of the RS flip-flop outputs 1, and the lag terminal of the RS flip-flop outputs 0. When the phase of the reference clock signal lags behind the phase of the feedback clock signal, the output of the lead terminal of the RS flip-flop is 0, and the output of the lag terminal of the RS flip-flop is 1.

4. The fast-locking, low-jitter phase-locked loop as described in claim 2, characterized in that: Control signals S0-S3 control the division ratio of the frequency divider, specifically... When the pulse width t0 representing the phase error signal T0 is less than the delay time τ of the delay unit, the 4-bit control signals S0-S3 are 0000, and the change in the control frequency division ratio is Δn0 = 0. When the pulse width t0 representing the phase error signal T0 is less than 2τ and greater than τ, the 4-bit control signals S0-S3 are 1000, and the oscillator output oscillation period is assumed to be T. cco The reference clock period is T. ref The maximum change in the control frequency division ratio is When the pulse width t0, representing the phase error signal T0, is less than 3τ and greater than 2τ, the 4-bit control signals S0-S3 are 1100, and the maximum change in the control frequency division ratio is... When the pulse width t0, representing the phase error signal T0, is less than 4τ and greater than 3τ, the 4-bit control signals S0-S3 are 1110, and the maximum change in the control frequency division ratio is... When the pulse width t0 representing the phase error signal T0 is greater than 4τ, the 4-bit control signals S0-S3 are 1111, and the maximum change in the control frequency division ratio is...

5. The fast-locking, low-jitter phase-locked loop as described in any one of claims 1-4, characterized in that: This fast-locking, low-jitter phase-locked loop has two operating modes: fast-locking mode and normal-locking mode. When the phase error is greater than When in fast lock mode, switch S3 is set to 1, controlling charge pump I. cp2 Shutdown, via charge pump I cp1 A loop is used for phase-frequency locking; When the phase error is less than In normal lockout mode, switch S3 is set to 0, controlling charge pump I. cp2 It is enabled to provide zero-point compensation and uses a dual-ring phase-locked loop for phase locking.

6. The fast-locking, low-jitter phase-locked loop as described in any one of claims 1-4, characterized in that: In the frequency-to-voltage module FV, the output frequency is detected to pre-start the current and control the oscillator CCO to reach a predetermined frequency. Specifically, this is done by comparing the output voltage V of the frequency-to-voltage module FV. f With the set reference voltage V2, at V f When the frequency reaches V2, the oscillation frequency meets the preset requirement, the charging path of capacitor C is closed, and the phase-locked loop (PLL) is started to perform a frequency and phase locking process through the loop; at V f When V2 is less than or equal to 2, the oscillation frequency does not meet the preset requirements, so capacitor C continues to be charged to speed up the frequency locking speed.

7. The fast-locking, low-jitter phase-locked loop as described in any one of claims 1-4, characterized in that: It also includes a configuration module Config: used to configure the division ratio of the frequency divider, the tuning curve of the current control gain of the current control oscillator CCO, the delay time τ of the delay unit of the auxiliary phase error detection and phase difference gain amplification module APD&At, and to perform initialization reset.

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