Encoding method and apparatus

Abstract

Embodiments of the present application provide an encoding method and device, which are used to improve the encoding gain under RCM. The method comprises: performing bit mapping on k source bits with reliability lower than a first threshold in a first bit sequence to obtain a second bit sequence, wherein the first bit sequence is obtained by performing bit mapping on a source bit sequence after adding a cyclic redundancy check (CRC) bit, the k source bits are bits in the source bit sequence, and the length of the first bit sequence is equal to the length of the second bit sequence; performing exclusive or operation on bits in a bit sequence obtained by encoding the first bit sequence and bits in a bit sequence obtained by encoding the second bit sequence to obtain a third bit sequence; or, encoding the second bit sequence to obtain the third bit sequence; and mapping the bit sequence obtained by encoding the first bit sequence and the third bit sequence onto an orthogonal frequency division multiplexing (OFDM) symbol. rv1 rv1 ​​

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to encoding methods and apparatus. Background Technology

[0002] In smart home scenarios, existing power grids can be used to achieve large-scale interconnection of home smart devices. However, irregular and high-intensity pulse interference may occur between various electrical devices on power lines. To address this, the International Telecommunication Union-Telecommunication Standardization Sector (ITU-T) G.9960 protocol employs robust communication mode (RCM) to combat pulse interference and improve the reliability of information transmission.

[0003] Specifically, in RCM, such as Figure 1 As shown, the S segments (sessions) of codewords after polarization coding and rate matching, with index numbers 0, 1, 2...S-1, constitute the first group (group#1 of S sessions). The S segments in the first group are cyclically shifted according to the parameter CSS2 to obtain the S segments with index numbers CSS2, (CSS2+1)%S, (CSS2+2)%S...(CSS2+S-1)%S, which is the second group (group#2 of S sessions), and concatenated with the first group. Similarly, the S segments in the first group can be further shifted according to the parameter... After performing a cyclic shift, the segments are concatenated sequentially. Finally, the S segments in the first group of S segments are arranged according to the parameters. Perform a circular shift to obtain the index numbers in sequence. The S segments, that is, the S-th segment. Group And the first of the previously obtained S segments The groups are cascaded. Among them, the parameters... The value can be obtained by looking up a table. The first group of S segments can also be called the first forward error correction code (FEC) copy (FEC copy #1), the second group of S segments can also be called the second FEC copy, and so on for the S segments. Group can also be called the first Copy.

[0004] In the RCM described above, the S segments of the rate-matched codeword are repeated N times. rep Each iteration follows a cyclic section shift (CSS) parameter to counteract potential pulse interference during transmission. However, as N... rep With the increase of [something], the additional combine (CC) gain that the receiver can obtain is limited. Summary of the Invention

[0005] This application provides an encoding method and apparatus for improving the encoding gain under RCM. To achieve the above objective, the embodiments of this application adopt the following technical solutions:

[0006] Firstly, an encoding method is provided. The apparatus for performing the encoding method can be an encoding device or a module applied in the encoding device, such as a Bluetooth chip or a chip system. The method includes: dividing a first bit sequence into bits with a reliability lower than a first threshold by k... rv1 The first bit sequence is obtained by bit mapping the source bit sequence, where the first bit sequence is obtained by bit mapping after adding cyclic redundancy check (CRC) bits to the source bit sequence. rv1 Each source bit is a bit in the source bit sequence, and the length of the first bit sequence is equal to the length of the second bit sequence. The bits in the bit sequence obtained by encoding the first bit sequence and the bits in the bit sequence obtained by encoding the second bit sequence are XORed to obtain the third bit sequence; or, the second bit sequence is encoded to obtain the third bit sequence. The bit sequence obtained by encoding the first bit sequence and the third bit sequence are mapped onto Orthogonal Frequency Division Multiplexing (OFDM) symbols.

[0007] For the same source bit sequence, compared to the existing technology that directly encodes the first bit sequence and maps it to OFDM symbols, the encoding method provided in this application introduces a second bit sequence, so that the bit sequence obtained after encoding the first bit sequence and the third bit sequence can be mapped to OFDM symbols. Obviously, for the same source bit sequence, in addition to obtaining the bit sequence after encoding the first bit sequence, this application embodiment can also obtain more encoded codewords, i.e., the third bit sequence. If the signal is affected by pulse interference during transmission, the proportion of erroneous codewords to total codewords is smaller compared to the prior art. In other words, by introducing more redundant information, this application embodiment enables the receiving device to correctly recover the source data with a higher probability, thereby improving the coding gain and thus enhancing the reliability of the entire system. Furthermore, in this application embodiment, k bits with a reliability lower than a first threshold can be selected from the first bit sequence.rv1 One source bit is used to generate the second bit sequence. Since bits with low reliability are more prone to errors during decoding at the receiving end, this k-bit sequence is used... rv1 The source bits generate a second bit sequence, which is then encoded to obtain a third bit sequence. This enhances the decoding performance of the receiving device.

[0008] In conjunction with the first aspect above, in one possible implementation, mapping the bit sequence obtained after encoding the first bit sequence and the third bit sequence onto OFDM symbols includes: after rate matching the bit sequence obtained after encoding the first bit sequence, segmenting it into M1 groups of S segments, and for the x1-th group of S segments, performing the following operation: repeating the x1-th group of S segments N times... rv0 This process is repeated time and again using the corresponding segmented cyclic shift CSS parameters to obtain N. rv0 ×S segments; where M1, S, x1, and N rv0 All are positive integers, and 1 ≤ x1 ≤ M1; after rate matching of the third bit sequence, it is segmented into M1 groups of S segments, and for the S segments of the x2 group, the following operation is performed: repeat the operation N times on the S segments of the x2 group. rv1 This process is repeated cyclically according to the corresponding CSS parameters, resulting in N. rv1 ×S segments; where x2 and N rv1 All are positive integers, and 1 ≤ x2 ≤ M1; This N rv0 ×S segments and the N rv1 The N segments are concatenated sequentially and mapped onto OFDM symbols, or, in units of segments, the N segments are... rv0 ×S segments and the N rv1 The ×S segments are interleaved and concatenated, and mapped onto OFDM symbols. In this scheme, the bit sequence obtained after encoding the first bit sequence and the third bit sequence can be reasonably segmented, repeated, cyclically shifted, and combined and mapped onto OFDM symbols, so that more encoded codewords can be carried on the same OFDM symbol.

[0009] In conjunction with the first aspect mentioned above, in one possible implementation, the second bit sequence has K bits with a reliability higher than the second threshold. rv1 The bits are k bits in the first bit sequence whose reliability is lower than the first threshold. rv1 Add L to each source bit rv1 The CRC bits are obtained, where K rv1 =k rv1 +L rv1 k rv1 L rv1 and Krv1 It is a positive integer. In this scheme, k is the number of bits in the first bit sequence whose reliability is lower than the first threshold. rv1 Add L to each source bit rv1 One CRC bit, capable of verifying k rv1 Inspecting whether errors occur in the source bits during transmission can improve the accuracy of the receiving device in recovering the source data.

[0010] In conjunction with the first aspect above, in one possible implementation, after rate matching of the bit sequence obtained by encoding the first bit sequence, it is segmented into M1 groups of S segments, including: after rate matching of the bit sequence obtained by encoding the first bit sequence, it is divided into M codewords, each codeword containing E bits; the last codeword in the M codewords is repeated multiple times, so that the number of codewords is H×M2; the H×M2 codewords are divided into M2 groups, each group containing H codewords; for the H codewords in the x3 group, the following operations are performed: concatenating the H codewords and placing the concatenated H×E bits into the first circular buffer; concatenating the first B×S-H×E bits of the H codewords at the end of the H codewords; where H, E, M2 and x3 are all positive integers, and 1≤x3≤M2; B represents the number of bits in each segment; reading B×S bits from the circular buffer to generate a group of S segments, where each segment contains B bits. Since the segmentation process involved in this solution can refer to the relevant steps in the existing technology, it can increase the compatibility of this solution with the existing technology.

[0011] In conjunction with the first aspect above, in one possible implementation, after rate matching of the third bit sequence, it is segmented into M1 groups of S segments, including: after rate matching of the third bit sequence, dividing it into M codewords, each codeword containing E bits; repeating the last codeword in the M codewords multiple times, so that the number of codewords is H×M2; dividing the H×M2 codewords into M2 groups, each group containing H codewords; for the H codewords in the x3 group, performing the following operations: concatenating the H codewords and placing the concatenated H×E bits into the first circular buffer; concatenating the first B×S-H×E bits of the H codewords at the end of the H codewords; where H, E, M2, and x3 are all positive integers, and 1≤x3≤M2; B represents the number of bits in each segment; reading B×S bits from the circular buffer to generate a group of S segments, where each segment contains B bits. Since the segmentation process involved in this solution can refer to the relevant steps in the existing technology, it can increase the compatibility of this solution with the existing technology.

[0012] In conjunction with the first aspect above, in one possible implementation, rate matching is performed on the bit sequence obtained after encoding the pair of first bit sequences, including: bit interleaving of the fourth bit sequence; wherein the fourth bit sequence is the bit sequence obtained after sub-block interleaving and bit selection of the bit sequence obtained after encoding the pair of first bit sequences; rate matching is performed on the third bit sequence, including: bit interleaving of the fifth bit sequence; wherein the fifth bit sequence is the bit sequence obtained after sub-block interleaving and bit selection of the third bit sequence.

[0013] In conjunction with the first aspect described above, in one possible implementation, the encoding method provided in this application further includes: placing a fourth bit sequence and a fifth bit sequence into a second circular buffer; wherein the fourth bit sequence is a bit sequence obtained by sub-block interleaving and bit selection after encoding the first bit sequence; the fifth bit sequence is a bit sequence obtained by sub-block interleaving and bit selection after encoding the third bit sequence; when retransmitting the source bit sequence, the bit sequence is read starting from the first bit of the fourth bit sequence or the fifth bit sequence, and bit interleaving is performed on the read bit sequence. In this scheme, when retransmitting the source bit sequence, it is only necessary to read the sequence in the second circular buffer and then perform interleaving, without having to repeat the steps of adding CRC, bit mapping, encoding, sub-block interleaving and / or bit selection, which can save hardware and software resources and time.

[0014] Secondly, an encoding apparatus is provided for implementing the above-described method. This encoding apparatus includes modules, units, or means corresponding to the implementation of the above-described method. These modules, units, or means can be implemented in hardware, software, or by hardware executing corresponding software. The hardware or software includes one or more modules or units corresponding to the above-described functions.

[0015] In conjunction with the second aspect above, in one possible implementation, the encoding device includes: a processor and a memory coupled to the processor; the memory is used to store programs and data; the processor is used to execute the program stored in the memory to perform the following function: the processor is used to encode k bits in the first bit sequence whose reliability is lower than a first threshold. rv1 The first bit sequence is obtained by bit mapping the source bit sequence, where the first bit sequence is obtained by bit mapping after adding cyclic redundancy check (CRC) bits to the source bit sequence. rv1The first bit sequence is a bit in the source bit sequence, and the length of the first bit sequence is equal to the length of the second bit sequence. The processor is further configured to perform an XOR operation on the bits in the bit sequence obtained after encoding the first bit sequence and the bits in the bit sequence obtained after encoding the second bit sequence to obtain a third bit sequence; or, the processor is further configured to encode the second bit sequence to obtain a third bit sequence; the processor is further configured to map the bit sequence obtained after encoding the first bit sequence and the third bit sequence onto an orthogonal frequency division multiplexing (OFDM) symbol.

[0016] In conjunction with the second aspect above, in one possible implementation, the processor is further configured to map the bit sequence obtained after encoding the first bit sequence and the third bit sequence onto OFDM symbols, including: performing rate matching on the bit sequence obtained after encoding the first bit sequence, segmenting it into M1 groups of S segments, and performing the following operation on the x1-th group of S segments: repeating the x1-th group of S segments N times. rv0 This process is repeated time and again using the corresponding segmented cyclic shift CSS parameters to obtain N. rv0 ×S segments; where M1, S, x1, and N rv0 All are positive integers, and 1 ≤ x1 ≤ M1; used to rate match the third bit sequence, segment it into M1 groups of S segments, and for the x2 group of S segments, perform the following operation: repeat the x2 group of S segments N times. rv1 This process is repeated cyclically according to the corresponding CSS parameters, resulting in N. rv1 ×S segments; where x2 and N rv1 All are positive integers, and 1 ≤ x2 ≤ M1; used to store N rv0 ×S segments and the N rv1 ×S segments are concatenated sequentially and mapped onto OFDM symbols, or, used to segment the N... rv0 ×S segments and the N rv1 The ×S segments are interleaved and cascaded, and mapped onto OFDM symbols.

[0017] In conjunction with the second aspect above, in one possible implementation, the second bit sequence has K bits with a reliability higher than the second threshold. rv1 The bits are k bits in the first bit sequence whose reliability is lower than the first threshold. rv1 Add L to each source bit rv1 The CRC bits are obtained, where K rv1 =k rv1 +L rv1 k rv1 L rv1 and Krv1 It is a positive integer.

[0018] In conjunction with the second aspect above, in one possible implementation, the communication device further includes a memory; the processor is further configured to, after rate matching the bit sequence obtained by encoding the pair of first bit sequences, segment it into M1 groups of S segments, including: dividing the bit sequence obtained by rate matching the bit sequence obtained by encoding the pair of first bit sequences into M codewords, each codeword containing E bits; repeating the last codeword in the M codewords multiple times, such that the number of codewords is H×M2; and dividing the H×M2... The codewords are divided into M2 groups, each containing H codewords. For the H codewords in the x3 group, the following operations are performed: concatenate the H codewords and put the concatenated H×E bits into the memory; concatenate the first B×S-H×E bits of the H codewords to the end of the H codewords; where H, E, M2, and x3 are all positive integers, and 1≤x3≤M2; B represents the number of bits in each segment; read B×S bits from the memory to generate a group of S segments, where each segment contains B bits.

[0019] In conjunction with the second aspect above, in one possible implementation, the communication device further includes a memory; the processor is further configured to, after rate matching the third bit sequence, segment it into M1 groups of S segments, including: dividing the third bit sequence into M codewords after rate matching, each codeword containing E bits; repeating the last codeword in the M codewords multiple times, such that the number of codewords is H×M2; dividing the H×M2 codewords into M2 groups, each group containing H codewords; performing the following operations on the H codewords in the x3 group: concatenating the H codewords and placing the concatenated H×E bits into the memory; concatenating the first B×S-H×E bits of the H codewords at the end of the H codewords; wherein H, E, M2, and x3 are all positive integers, and 1≤x3≤M2; B represents the number of bits in each segment; and reading B×S bits from the memory to generate a group of S segments, wherein each segment contains B bits.

[0020] In conjunction with the second aspect above, in one possible implementation, the processor is further configured to perform rate matching on the bit sequence obtained after encoding the pair of first bit sequences, including: performing bit interleaving on the fourth bit sequence; wherein the fourth bit sequence is a bit sequence obtained after sub-block interleaving and bit selection on the bit sequence obtained after encoding the pair of first bit sequences; the processor is further configured to perform rate matching on the third bit sequence, including: performing bit interleaving on the fifth bit sequence; wherein the fifth bit sequence is a bit sequence obtained after sub-block interleaving and bit selection on the third bit sequence.

[0021] In conjunction with the second aspect above, in one possible implementation, the communication device further includes a memory; the processor is further configured to store a fourth bit sequence and a fifth bit sequence into the memory; wherein the fourth bit sequence is a bit sequence obtained by sub-block interleaving and bit selection of the bit sequence obtained after encoding the first bit sequence; the fifth bit sequence is a bit sequence obtained by sub-block interleaving and bit selection of the third bit sequence; the processor is further configured to, when retransmitting the source bit sequence, read the bit sequence starting from the first bit of the fourth bit sequence or the fifth bit sequence, and perform bit interleaving on the read bit sequence.

[0022] Thirdly, a communication device is provided, comprising: a processor; the processor being coupled to a memory and, after reading computer instructions stored in the memory, executing the method described in the first aspect above according to the instructions.

[0023] In conjunction with the third aspect above, in one possible implementation, the communication device further includes a memory for storing computer instructions.

[0024] In conjunction with the third aspect described above, in one possible implementation, the communication device further includes a communication interface; this communication interface is used for communication between the communication device and other devices. For example, the communication interface may be a transceiver, an input / output interface, an interface circuit, an output circuit, an input circuit, a pin, or related circuitry, etc.

[0025] In conjunction with the third aspect described above, in one possible implementation, the communication device can be a chip or a chip system. When the communication device is a chip system, it can be composed of chips or may include chips and other discrete components.

[0026] Fourthly, a computer-readable storage medium is provided that stores instructions which, when executed on a computer, enable the computer to perform the method described in the first aspect.

[0027] Fifthly, a transmitting end device is provided, the transmitting end device including a front-end module and the encoding device described in the second aspect above; the encoding device is used to encode a source bit sequence and map it onto OFDM symbols; the front-end module is used to convert the output of the encoding device into a wireless signal and transmit the wireless signal.

[0028] In conjunction with the fifth aspect above, in one possible implementation, the transmitting device further includes a modulation module; the front-end module is configured to convert the output of the encoding device into a wireless signal and transmit the wireless signal, including: modulating the output of the encoding device into a high-frequency signal through the modulation module; converting the high-frequency signal into a wireless signal and transmitting the wireless signal.

[0029] In a sixth aspect, a communication system is provided, the communication system including a receiving end device and a transmitting end device as described in the fifth aspect above; the receiving end device is configured to receive a wireless signal from the transmitting end device and recover the source bit sequence based on the wireless signal.

[0030] In a seventh aspect, a computer program product containing instructions is provided, which, when run on a computer, enables the computer to perform the method described in the first aspect.

[0031] The technical effects of any possible implementation of aspects two through seven can be found in the first aspect or the technical effects of different implementations of the first aspect, and will not be repeated here. Attached Figure Description

[0032] Figure 1 A schematic diagram of the existing RCM solution. Figure 1 ;

[0033] Figure 2 This is a flowchart of parameter calculation in the existing RCM scheme;

[0034] Figure 3 A schematic diagram of the existing RCM solution. Figure 2 ;

[0035] Figure 4 A schematic diagram of the architecture of a communication system provided in this application embodiment. Figure 1 ;

[0036] Figure 5 A schematic diagram of the architecture of a communication system provided in this application embodiment. Figure 2 ;

[0037] Figure 6 Schematic diagram of the communication device provided in the embodiments of this application Figure 1 ;

[0038] Figure 7 A flowchart illustrating an encoding method provided in an embodiment of this application;

[0039] Figure 8 A schematic diagram illustrating the encoding device provided in this application for adding CRC bits to a source bit sequence;

[0040] Figure 9 A schematic diagram illustrating the generation method of the first bit sequence provided in an embodiment of this application;

[0041] Figure 10 A schematic diagram illustrating the generation method of the second bit sequence provided in an embodiment of this application;

[0042] Figure 11 A schematic diagram illustrating the polar code encoding of the first bit sequence by the encoding device provided in this embodiment of the application;

[0043] Figure 12 A schematic diagram illustrating a method for generating a third bit sequence according to an embodiment of this application;

[0044] Figure 13 A schematic diagram illustrating another method for generating the third bit sequence provided in an embodiment of this application;

[0045] Figure 14 A schematic diagram illustrating the generation and processing method of the first bit sequence provided in an embodiment of this application;

[0046] Figure 15 A schematic diagram illustrating bit selection provided in an embodiment of this application;

[0047] Figure 16 A schematic diagram illustrating the encoding device provided in this application for repeating and cyclically shifting S segments;

[0048] Figure 17 This is a schematic diagram illustrating the relationship between the bit sequence and the starting position provided in an embodiment of this application.

[0049] Figure 18 Schematic diagram of the communication device provided in the embodiments of this application Figure 2 . Detailed Implementation

[0050] To facilitate understanding of the technical solutions of the embodiments of this application, a brief introduction to the relevant technologies or terms of this application is given below.

[0051] First, the parameter calculation of the RCM scheme.

[0052] As described in the background section, large-scale interconnection of home smart devices can be achieved using existing power networks. Consequently, power line communication (PLC) technology has emerged. In a PLC system based on orthogonal frequency division multiplexing (OFDM), for a given number of bits K that each OFDM symbol can carry... p The number of times the code is repeated, N repThe number of bits E and the CSS parameters in each codeword can be determined by parameters such as... Figure 2 The following steps are shown to calculate the parameters of the RCM scheme, including the codeword-level coherence number H, the number of bits in each segment B, and the number of segments in each group S:

[0053] Step S201: K p Divide by N rep Round down to the nearest integer to get X. This step can also be expressed in programming language as: X = floor(K p / N rep ).

[0054] Step S202: Determine if the remainder when X is divided by 4 is 0. This step can also be expressed in programming language as: mod(X,4) == 0. If the result is yes, then execute step S3a; if no, then execute step S3b.

[0055] Step S203a: K p Divide by N rep Round down and subtract 1 to get B. This step can also be expressed in programming language as: B = floor(K p / N rep )-1.

[0056] Step S203b: K p Divide by N rep Round down to the nearest integer to get B. This step can also be expressed in programming language as: B = floor(K p / N rep ).

[0057] Step S204: Divide E by B and round up to get S. This step can also be expressed in programming language as: S = ceil(E / B).

[0058] Step S205: Determine if S is 1. If the result is yes, proceed to step S6; otherwise, end the process.

[0059] Step S206:

[0060] Choose the smallest H that satisfies S > 1, where S = ceil(H * E / B). For example, if the initial value of H is 1, substituting it into the formula S = ceil(H * E / B) will give the value of S corresponding to H = 1. If S > 1 is not satisfied, the value of H is increased by 1, becoming 2. Each time the value of H increases by 1, until S > 1 is satisfied, at which point the value of H no longer increases. At this point, the value of H is the selected value.

[0061] It should be noted that H is a positive integer, with a default value of 1.

[0062] Second, the RCM scheme maps rate-matched codewords to OFDM symbols.

[0063] For the FEC codewords 1, 2, ..., M generated after rate matching, they can be obtained as follows: Figure 3 The following steps are mapped onto OFDM symbols.

[0064] Step S301: Repeat the last codeword among the above M codewords multiple times, so that the number of codewords is divisible by H; that is, the number of codewords can be H×M2, where M2 is a positive integer. Each codeword contains E bits.

[0065] Divide the H×M2 codewords into M2 groups, each group containing H codewords. For any group of H codewords, steps S302 to S304 can be performed. The following explanation uses the first group of H codewords as an example:

[0066] Step S302: Concatenate H codewords and put the concatenated H×E bits into a circular buffer;

[0067] The first B×S-H×E bits of the H codewords are repeatedly concatenated at the end of the H codewords;

[0068] Read B×S bits from the circular buffer to generate a set of S segments with index numbers from 0 to S-1; where each segment contains B bits.

[0069] Step S303: Repeat the above process of generating the first group of S segments from the first group of H codewords N times. rep This process is repeated cyclically according to the corresponding CSS parameters, resulting in N. rep ×S segments. For specific implementation methods of repetition and cyclic shifting, please refer to the background technology. Figure 1 The corresponding implementation examples will not be described in detail here.

[0070] Step S304, K p K bits are mapped to one OFDM symbol, where K p Each bit contains N rep N segments rep ×B bits, and K of the pseudo random binary sequence (PRBS). p -B×N rep 1 bit.

[0071] It should be noted that the CSS parameters in step S303 can be obtained through a lookup table. For example, the procedure for creating a CSS parameter lookup table is as follows:

[0072]

[0073]

[0074] Third, the problems with existing RCM solutions.

[0075] As described in the background section, the aforementioned RCM can only be achieved by repeating N segments of the S-segments of the rate-matched codeword. rep Each iteration involves a cyclic shift based on the corresponding CSS parameters to counteract potential pulse interference during transmission. For example, N... rep The correspondence between the CC gain and the gain that the receiver can obtain is shown in Table 1 below:

[0076] Table 1

[0077]

[0078] As shown in Table 1, with N rep As the value of CC gain increases, the rate of increase in CC gain gradually slows down, and the value of CC gain becomes limited.

[0079] To address the limitation of CC gain in existing RCM schemes, the embodiments of this application can improve the coding gain, thereby enabling the receiver to correctly recover the source data with a higher probability, and thus improving the reliability of the entire system.

[0080] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. In the description of this application, unless otherwise stated, " / " indicates that the objects before and after are in an "or" relationship. For example, A / B can represent A or B. "And / or" in this application is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone, where A and B can be singular or plural. Furthermore, in the description of this application, unless otherwise stated, "multiple" refers to two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple. Furthermore, to facilitate a clear description of the technical solutions in the embodiments of this application, the terms "first" and "second" are used in the embodiments of this application to distinguish identical or similar items with substantially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that "first" and "second" are not necessarily different. Meanwhile, in the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is being used as an example, illustration, or description. Any embodiment or design scheme described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of terms such as "exemplary" or "for example" is intended to present related concepts in a concrete manner for ease of understanding.

[0081] like Figure 4 The diagram illustrates a communication system 40 provided in an embodiment of this application. The communication system 40 includes a transmitting end device 401 and a receiving end device 402. The transmitting end device 401 is used to transmit bits k from a first bit sequence whose reliability is lower than a first threshold. rv1 The first bit sequence is obtained by bit mapping the source bit sequence after adding CRC bits and then performing bit mapping. rv1Each source bit is a bit in a source bit sequence, and the length of the first bit sequence is equal to the length of the second bit sequence. The transmitting device 401 is further configured to perform an XOR operation on the bits in the bit sequence obtained after encoding the first bit sequence and the bits in the bit sequence obtained after encoding the second bit sequence to obtain a third bit sequence; and map the bit sequence obtained after encoding the first bit sequence and the third bit sequence onto OFDM symbols. Alternatively, the transmitting device 401 is further configured to map the bit sequence obtained after encoding the first bit sequence and the third bit sequence onto OFDM symbols, wherein the third bit sequence and the second bit sequence are the same bit sequence. The specific implementation and technical effects of this scheme will be described in detail in subsequent method embodiments, and will not be repeated here. The transmitting device 401 is also configured to transmit a wireless signal to the receiving device 402. Correspondingly, the receiving device 402 is configured to receive the wireless signal from the transmitting device 401 and recover the source bit sequence based on the received wireless signal.

[0082] Figure 5 A specific example of a communication system 40 provided in an embodiment of this application is shown.

[0083] In the transmitting device 401, the source bit sequence from the medium access control (MAC) layer is processed by the RCM incremental redundancy (IR) coding module 501, the modulation module 502, and the front-end module 503, and then converted into a wireless signal, which is transmitted by the transmitting antenna. The RCM IR coding module 501 maps the source bit sequence onto OFDM symbols; the specific processing flow can be found in the coding method provided in the embodiments of this application. The modulation module 502 converts the baseband signal output by the RCM IR coding module 501 into a high-frequency signal suitable for channel transmission. The modulation method can be, for example, 64 quadrature amplitude modulation (64QAM), which is not limited in this embodiment. The front-end module 503, also known as the radio frequency module, is used to convert the signal output by the modulation module 502 into a wireless signal.

[0084] In the receiving device 402, the received wireless signal passes through the front-end module 504, demodulation module 505, and RCM IR decoding module 506, and the recovered source bit sequence is transmitted to the MAC layer. The front-end module 504, also known as the radio frequency module, is used to convert the received wireless signal into a wired signal; the demodulation module 505 generates log likelihood ratio (LLR) soft information based on the signal output from the front-end module 504; and the RCM IR decoding module 506 recovers the source bit sequence based on the LLR soft information.

[0085] It should be noted that, due to factors such as channel noise, the source bit sequence in the transmitting device 401 and the recovered source bit sequence in the receiving device 402 may differ. This application aims to improve the similarity between these two sequences, even if the number of identical bits in the two sequences is greater.

[0086] Optionally, the functions of the transmitting device in this application embodiment can be implemented by one device, multiple devices working together, or one or more functional modules within a single device. This application embodiment does not specifically limit these functions. It is understood that the above functions can be network elements in hardware devices, software functions running on dedicated hardware, a combination of hardware and software, or virtualization functions instantiated on a platform (e.g., a cloud platform).

[0087] For example, the relevant functions of the transmitting device in the embodiments of this application can be achieved through... Figure 6 This is achieved through the communication device 600.

[0088] Figure 6 The diagram shown is a structural schematic of a communication device 600 provided in an embodiment of this application. The communication device 600 includes one or more processors 601, a communication line 602, and at least one communication interface. Figure 6 (This is merely an example illustration of a communication interface 604 and a processor 601; optionally, a memory 603 may also be included.)

[0089] The processor 601 may be a CPU, a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits used to control the execution of programs according to the present application.

[0090] The communication line 602 may include a path for connecting different components.

[0091] The communication interface 604 can be a transceiver module used to communicate with other devices or communication networks, such as Ethernet, RAN, WLAN, etc. For example, the transceiver module can be a transceiver or a similar device. Optionally, the communication interface 604 can also be a transceiver circuit located within the processor 601, used to implement the processor's signal input and signal output.

[0092] The memory 603 can be a device with storage functionality. For example, it can be read-only memory (ROM) or other types of static storage devices capable of storing static information and instructions; random access memory (RAM) or other types of dynamic storage devices capable of storing information and instructions; electrically erasable programmable read-only memory (EEPROM); compact disc read-only memory (CD-ROM) or other optical disc storage; optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.); magnetic disk storage media or other magnetic storage devices; or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but not limited thereto. The memory can exist independently and be connected to the processor via communication line 602. The memory can also be integrated with the processor.

[0093] The memory 603 stores computer execution instructions for implementing the scheme of this application, and its execution is controlled by the processor 601. The processor 601 executes the computer execution instructions stored in the memory 603, thereby implementing the encoding method provided in the embodiments of this application.

[0094] Alternatively, in this embodiment, the processor 601 may execute the processing-related functions in the encoding method provided in the following embodiments of this application, and the communication interface 604 may be responsible for communicating with other devices or communication networks. This embodiment does not specifically limit this.

[0095] The computer execution instructions in the embodiments of this application may also be referred to as application code, and the embodiments of this application do not specifically limit this.

[0096] In a specific implementation, as one embodiment, the processor 601 may include one or more CPUs, for example... Figure 6 CPU0 and CPU1 in the CPU.

[0097] In a specific implementation, as one example, the communication device 600 may include multiple processors, such as... Figure 6 the processor 601 and the processor 607 in. Each of these processors may be a single-CPU processor, or a multi-CPU processor. The processor herein may refer to one or more devices, circuits, and / or processing cores for processing data (for example, computer program instructions).

[0098] In a specific implementation, as an embodiment, the communication apparatus 600 may further include an output device 605 and an input device 606. The output device 605 is in communication with the processor 601, and can display information in various manners.

[0099] The above-mentioned communication apparatus 600 may be a general-purpose apparatus or a dedicated apparatus. For example, the communication apparatus 600 may be a desktop computer, a portable computer, a network server, a personal digital assistant (PDA), a mobile phone, a tablet computer, a wireless terminal apparatus, a vehicle-mounted terminal apparatus, an embedded device, or a device having Figure 6 a similar structure in. The embodiments of the present application do not limit the type of the communication apparatus 600.

[0100] In the following, the embodiments of the present application will be specifically described in conjunction with Figures 1 to 6 the coding method provided by the embodiments of the present application.

[0101] As shown in Figure 7 , a coding method provided by the embodiment of the present application is shown, and the coding method includes the following steps:

[0102] S701. The coding apparatus performs bit mapping on k source bits with reliability lower than a first threshold in a first bit sequence rv1 to obtain a second bit sequence, where the first bit sequence is a bit sequence obtained by adding CRC bits to a source bit sequence and then performing bit mapping, and the k rv1 source bits are bits in the source bit sequence, and the length of the first bit sequence is equal to the length of the second bit sequence.

[0103] In the embodiment of the present application, represents a sequence with a length of max(j-i+1, 0) When j<i, the sequence is empty This is explained uniformly herein, and no further description will be given later.

[0104] Taking the source bit sequence as an example, Figure 8 shows the process in which the coding apparatus adds CRC bits to the source bit sequence . The source bit sequence consists of bits b0, b1...b K-L-1Composition, in bit b K-L-1 Then, the encoding device can add the CRC bits. K-L CRC K-L+1 …CRC K-1 This forms a bit sequence of length K. The encoding device is a source bit sequence Adding CRC bits enables the receiving device to use the CRC-aided successive cancellation list (CA-SCL) algorithm to improve decoding performance.

[0105] For example, Figure 9 The encoding device is shown for bit sequences The process of performing bit mapping to obtain the first bit sequence. Specifically, the encoding device maps the bit sequence... One or more bits with fixed values ​​are mapped to a bit sequence of length N, i.e., the first bit sequence. Above. One or more bits with fixed values ​​can be either bits "0" or bits "1". These fixed-value bits, because they do not carry any information, can be called frozen bits. Correspondingly, the bit sequence... Because they carry information, they can be called information bits. For example... Figure 8 The illustrated embodiment, bit sequence Contains source bit sequence and CRC bits.

[0106] It should be noted that the first bit sequence The bit indexes in the protocol correspond to specific reliability levels. Bits carried at lower reliability indexes are more prone to errors during decoding at the receiving end. A reliability metric table, used to record the correspondence between bit indices and reliability levels, can be pre-defined according to the protocol. During bit mapping, the bit sequence can be... Information bits are preferentially mapped to bit indices with high reliability.

[0107] Combination Figure 9 , Figure 10 The process of the encoding device generating the second bit sequence is illustrated. As described above, the first bit sequence... It includes source bits, CRC bits, and frozen bits. The encoding device can encode the first bit sequence. k with reliability below the first threshold rv1 The source bits are mapped to obtain the second bit sequence.

[0108] Optionally, K in the second bit sequence has a reliability higher than the second threshold.rv1 The bits are k bits in the first bit sequence whose reliability is lower than the first threshold. rv1 Add L to each source bit rv1 The CRC bits are obtained, where K rv1 =k rv1 +L rv1 k rv1 L rv1 and K rv1 It is a positive integer. In this scheme, k is the number of bits in the first bit sequence whose reliability is lower than the first threshold. rv1 Add L to each source bit rv1 One CRC bit, capable of verifying k rv1 Inspecting whether errors occur in the source bits during transmission can improve the accuracy of the receiving device in recovering the source data.

[0109] Assumption Figure 10 The available physical resources in the middle are E rv1 Bits, expected code rate: R rv1 And R rv1 satisfy To ensure that k rv1 If the reliability of bit mapping of one source bit is considered, then the second bit sequence... The number of information bits is Among them, "indicates that it is much smaller than, This represents rounding up, with the expected bitrate R. rv1 It can be obtained through simulation or as an empirical value.

[0110] It should be noted that, in order to make the accompanying diagrams more concise and intuitive, Figure 10 The encoding device is not shown as the first bit sequence. k with reliability below the first threshold rv1 Add L to each source bit rv1 The process of CRC bits.

[0111] S702, the encoding device performs an XOR operation on the bits in the bit sequence obtained after encoding the first bit sequence and the bits in the bit sequence obtained after encoding the second bit sequence to obtain the third bit sequence; or, the encoding device encodes the second bit sequence to obtain the third bit sequence.

[0112] In this embodiment of the application, since the length of the first bit sequence is equal to the length of the second bit sequence, the two bit sequences encoded by the same encoder are also equal in length.

[0113] In embodiments of this application, the encoder may be, for example, a polar code encoder. Exemplarily, the encoding device may encode a first bit sequence of length N. Perform the Kronecker product operation to obtain the encoded bit sequence. Specifically, It can satisfy the following formula (1):

[0114]

[0115] Where N = 2 n n is a positive integer, and N represents the length of the first bit sequence or the length of the bit sequence obtained after encoding the first bit sequence; G represents the Kronecker product of order n. N Let represent the generating matrix of N×N.

[0116] The following uses the first bit sequence Taking {u0,u1,u2,…,v7}, i.e., N=8, as an example, the process of polar code encoding is explained.

[0117] like Figure 11 As shown, the first bit after encoding is The second bit is The third bit is The 4th bit is The 5th bit is The 6th bit is The 7th bit is The 8th bit is d7 = u7. Wherein, This represents the XOR operation.

[0118] For example, the encoding device can encode the second bit sequence Encode to obtain the third bit sequence For specific encoding methods, please refer to the above description of the first bit sequence. The encoding method will not be elaborated here.

[0119] Figure 12 This paper illustrates a method for generating a third bit sequence. The source bit sequence, after being processed by the CRC addition module 120, can be used as input to the bit mapping module 121. The output of the bit mapping module 121 is the first bit sequence. For a detailed implementation of the bit mapping, please refer to [link to documentation]. Figure 9 The illustrated embodiment. The encoding device encodes k bits in the first bit sequence whose reliability is lower than a first threshold. rv1Each source bit is input to the bit mapping module 122, and the output of the bit mapping module 122 is the second bit sequence; or, the encoding device encodes k bits in the first bit sequence whose reliability is lower than the first threshold. rv1 After adding CRC bits to the source bits, the input is given to the bit mapping module 122. The output of the bit mapping module 122 is the second bit sequence. For the specific implementation of bit mapping, please refer to [link to relevant documentation]. Figure 10 The embodiment shown illustrates this. The encoding device inputs a first bit sequence into encoding module 123 and a second bit sequence into encoding module 124, wherein the output of encoding module 124 is a third bit sequence. The third bit sequence can be used as input to rate matching module 125, which is used to perform rate matching on the bit sequence. Specific functions of rate matching module 125 can be found in the relevant description in step S703, and will not be repeated here.

[0120] For example, the encoding device can encode the first bit sequence Encode to obtain a bit sequence The encoding device can also process the second bit sequence. Encode to obtain a bit sequence Encoding devices can encode bit sequences bits and bit sequences Perform an XOR operation on the bits in the sequence to obtain the third bit sequence. Right now, The following formula (2) can be satisfied:

[0121]

[0122] Here, mod() represents the modulo operation.

[0123] For example, Figure 13 Another method for generating the third bit sequence is shown. In this method, the source bit sequence, after being processed by the CRC addition module 120, can be used as the input to the bit mapping module 121. The output of the bit mapping module 121 is the first bit sequence. For a detailed implementation of the bit mapping, please refer to [link to documentation]. Figure 9 The illustrated embodiment. The encoding device encodes k bits in the first bit sequence whose reliability is lower than a first threshold. rv1 Each source bit is input to the bit mapping module 122, and the output of the bit mapping module 122 is the second bit sequence; or, the encoding device encodes k bits in the first bit sequence whose reliability is lower than the first threshold. rv1 After adding CRC bits to the source bits, the input is given to the bit mapping module 122. The output of the bit mapping module 122 is the second bit sequence. For the specific implementation of bit mapping, please refer to [link to relevant documentation]. Figure 10The illustrated embodiment. The encoding device inputs a first bit sequence into encoding module 123 and a second bit sequence into encoding module 124, and performs an XOR operation on the bits in the two encoded bit sequences to obtain a third bit sequence. The third bit sequence can be used as input to rate matching module 125, which is used to perform rate matching on the bit sequences. Specific functions are described in the relevant steps S703 and will not be repeated here.

[0124] For example, Figure 14 The generation and processing of the first bit sequence are illustrated. The source bit sequence, after being processed by the CRC addition module 120, can be used as the input to the bit mapping module 121. The output of the bit mapping module 121 is the first bit sequence. For a detailed implementation of the bit mapping, please refer to [link to documentation]. Figure 9 The embodiment shown. The first bit sequence can also be used as input to the encoding module 123. The bit sequence obtained after the encoding device encodes the first bit sequence can be used as input to the rate matching module 130. The rate matching module 130 is used to perform rate matching on the bit sequence. For details of its function, please refer to the relevant description in step S703, which will not be repeated here.

[0125] S703, The encoding device maps the bit sequence obtained after encoding the first bit sequence and the third bit sequence onto OFDM symbols.

[0126] For the same source bit sequence, compared to the existing technology that directly encodes the first bit sequence and maps it to OFDM symbols, the encoding method provided in this application introduces a second bit sequence, so that the bit sequence obtained after encoding the first bit sequence and the third bit sequence can be mapped to OFDM symbols. Obviously, for the same source bit sequence, in addition to obtaining the bit sequence after encoding the first bit sequence, this application embodiment can also obtain more encoded codewords, i.e., the third bit sequence. If the signal is affected by pulse interference during transmission, the proportion of erroneous codewords to total codewords is smaller compared to the prior art. In other words, by introducing more redundant information, this application embodiment enables the receiving device to correctly recover the source data with a higher probability, thereby improving the coding gain and thus enhancing the reliability of the entire system. Furthermore, in this application embodiment, k bits with a reliability lower than a first threshold can be selected from the first bit sequence. rv1 One source bit is used to generate the second bit sequence. Since bits with low reliability are more prone to errors during decoding at the receiving end, this k-bit sequence is used... rv1 The source bits generate a second bit sequence, which is then encoded to obtain a third bit sequence. This enhances the decoding performance of the receiving device.

[0127] Optionally, step S703 includes: after the encoding device performs rate matching on the bit sequence obtained by encoding the first bit sequence, it segments it into M1 groups of S segments, and for the x1 group of S segments, it performs the following operation: the encoding device repeats the x1 group of S segments N times. rv0 This process is repeated cyclically according to the corresponding CSS parameters, resulting in N. rv0 ×S segments; where M1, S, x1, and N rv0 All are positive integers, and 1 ≤ x1 ≤ M1; after rate matching the third bit sequence, the encoding device divides it into M1 groups of S segments, and for the x2 group of S segments, performs the following operation: the encoding device repeats the x2 group of S segments N times. rv1 This process is repeated cyclically according to the corresponding CSS parameters, resulting in N. rv1 ×S segments; where x2 and N rv1 All are positive integers, and 1 ≤ x2 ≤ M1; the encoding device will encode N rv0 ×S segments and N rv1 ×S segments are concatenated sequentially and mapped onto OFDM symbols, or, segment by segment, the encoding device encodes N... rv0 ×S segments and N rv1 The ×S segments are interleaved and concatenated, and mapped onto OFDM symbols. In this scheme, the bit sequence obtained after encoding the first bit sequence and the third bit sequence can be reasonably segmented, repeated, cyclically shifted, and combined and mapped onto OFDM symbols, so that more encoded codewords can be carried on the same OFDM symbol.

[0128] In the embodiments of this application, rate matching may include sub-block interleaver, bit selection, and bit interleaver.

[0129] Combining the above formula (1), the encoding device encodes the first bit sequence The bit sequence obtained after encoding is in, It can be used as the input bit sequence for sub-block interleaving. The encoding device can... Divide into m sub-blocks and interleave them. The resulting bit sequence is:

[0130] For example, the pseudocode for sub-block interleaving of polar codes can be as follows:

[0131]

[0132] When m = 32, the pattern of interleaved sub-blocks can be shown in Table 2.

[0133] Table 2

[0134] 0 0 4 3 8 8 12 10 16 12 20 14 24 24 28 27 1 1 5 5 9 16 13 18 17 20 21 22 25 25 29 29 2 2 6 6 10 9 14 11 18 13 22 15 26 26 30 30 3 4 7 7 11 17 15 19 19 21 23 23 27 28 31 31

[0135] Where i represents the sub-block index after interleaving, and P(i) is the sub-block index before interleaving corresponding to the sub-block index i after interleaving.

[0136] For example, Figure 15 The bit selection process is illustrated. The input to bit selection can be a sequence of bits that has undergone sub-block interleaving. After repetition, punching, or truncating, the output is a bit sequence. Here, repetition refers to the repetition of the bit sequence y0,...,y E-N-1 And concatenate to the bit sequence After that, punching refers to deleting the preceding bit sequence y0,…,y N-E-1 , retain the last bit sequence y N-E ,...,y N-1 The output bit sequence. Truncation refers to deleting a portion of the bit sequence y. E ,...,y N-1 Retain the preceding bit sequence y0,...,y E-1 The bit sequence as output.

[0137] In this embodiment, bit interleaving is used to propagate burst errors generated on the channel over time, transforming them into random errors, so that the receiving device can use common encoding and decoding techniques for error correction. The input to bit interleaving can be a bit sequence that has undergone bit selection. The output of bit interleaving can be Bit interleaving typically includes row-column interleaving and triangular interleaving.

[0138] For example, the pseudocode for a possible row-column interleaver with X rows and Y columns is as follows, where, Indicates rounding up:

[0139]

[0140]

[0141] Similarly, the encoding device can also perform rate matching on the third bit sequence. The specific implementation method can refer to the method of rate matching on the bit sequence obtained after encoding the first bit sequence, as described above, and will not be repeated here.

[0142] Optionally, after rate matching the bit sequence obtained by encoding the first bit sequence, the encoding device segments it into M1 groups of S segments, including: after rate matching the bit sequence obtained by encoding the first bit sequence, the encoding device divides it into M codewords, each codeword containing E bits; the encoding device repeats the last codeword in the M codewords multiple times, so that the number of codewords is H×M2; the encoding device divides the H×M2 codewords into M2 groups, each group containing H codewords; for For the H codewords in the x3 group, the encoding device performs the following operations: The encoding device concatenates the H codewords and places the concatenated H×E bits into the first circular buffer; the encoding device concatenates the first B×S – H×E bits of the H codewords at the end of the H codewords; where H, E, M2, and x3 are all positive integers, and 1 ≤ x3 ≤ M2; B represents the number of bits in each segment; the encoding device reads B×S bits from the circular buffer to generate a group of S segments, where each segment contains B bits. The segmentation process can be referred to... Figure 3 Steps S301 and S302 in the illustrated embodiment will not be repeated here. This solution can increase compatibility with existing technologies.

[0143] Optionally, after rate matching the third bit sequence, the encoding device segments it into M1 groups of S segments, including: after rate matching, the encoding device divides the third bit sequence into M codewords, each codeword containing E bits; the encoding device repeats the last codeword in the M codewords multiple times, making the number of codewords H×M2; the H×M2 codewords are divided into M2 groups, each group containing H codewords; for the H codewords in the x3 group, the encoding device performs the following operations: the encoding device concatenates the H codewords and puts the concatenated H×E bits into the first circular buffer; the first B×S-H×E bits of the H codewords are concatenated at the end of the H codewords; where H, E, M2, and x3 are all positive integers, and 1≤x3≤M2; B represents the number of bits in each segment; the encoding device reads B×S bits from the circular buffer to generate a group of S segments, where each segment contains B bits. The segmentation process can be referred to Figure 3 Steps S301 and S302 in the illustrated embodiment will not be repeated here. This solution can increase compatibility with existing technologies.

[0144] Figure 16 This illustration shows the process of repeating and cyclically shifting the S segments of the x1 group and the S segments of the x2 group, respectively, in an embodiment of this application. The encoding device repeats the S segments of the x1 group N times. rv0 This process is repeated cyclically according to the corresponding CSS parameters, resulting in N. rv0 ×S segments, i.e., RV0; the encoding device repeats the S segments of the x2th group N times. rv1This process is repeated cyclically according to the corresponding CSS parameters, resulting in N. rv1 The system consists of S segments, or RV1; where the S segments in the x1th group are obtained from the encoded bit sequence of the first bit sequence, and the S segments in the x2th group are obtained from the third bit sequence. For details on the repetition and cyclic shifting process, please refer to [link to documentation]. Figure 3 Step S303 in the illustrated embodiment will not be repeated here. In this embodiment, the codeword repetition count N of the existing RCM scheme is... rep Split into N RV0 With N RV1 And N rep equals N RV0 With N RV1 The sum, that is, the number of repetitions of the S segments in the x1-th group obtained from the encoded bit sequence based on the first bit sequence, is N. RV0 The number of repetitions of the S segments in the x2 group obtained from the third bit sequence is N. RV1 .

[0145] In one possible implementation, the encoding device can encode N rv0 ×S segments and N rv1 The ×S segments are concatenated in sequence, i.e. [RV0, RV1], and mapped onto OFDM symbols.

[0146] In another possible implementation, the encoding device can divide N into segments. rv0 ×S segments and N rv1 ×S segments are interleaved and concatenated, i.e., [RV00, RV10, RV01, RV11...], and mapped onto OFDM symbols. Among them, RV0... i This represents the segment with index i in RV0, and RV1 i This represents the segment with index number i in RV1.

[0147] Optionally, the encoding device performs rate matching on the bit sequence obtained after encoding the first bit sequence, including: the encoding device performs bit interleaving on the fourth bit sequence; wherein the fourth bit sequence is the bit sequence obtained after sub-block interleaving and bit selection on the bit sequence obtained after encoding the first bit sequence; the encoding device performs rate matching on the third bit sequence, including: the encoding device performs bit interleaving on the fifth bit sequence; wherein the fifth bit sequence is the bit sequence obtained after sub-block interleaving and bit selection on the third bit sequence.

[0148] Optionally, the encoding method provided in this application embodiment further includes: the encoding device placing the fourth bit sequence and the fifth bit sequence into a second circular buffer; wherein, the fourth bit sequence is the bit sequence obtained by the encoding device after encoding the first bit sequence and performing sub-block interleaving and bit selection; the fifth bit sequence is the bit sequence obtained by the encoding device after performing sub-block interleaving and bit selection on the third bit sequence. When retransmitting the source bit sequence, the encoding device reads the bit sequence starting from the first bit of the fourth bit sequence or the fifth bit sequence, and performs bit interleaving on the read bit sequence. In this scheme, when retransmitting the source bit sequence, it is only necessary to read the sequence in the second circular buffer and then perform interleaving, without having to repeat the steps of adding CRC, bit mapping, encoding, sub-block interleaving and / or bit selection, which can save hardware and software resources and time.

[0149] For example, the encoding device encodes the first bit sequence and then performs sub-block interleaving and bit selection on the resulting bit sequence to obtain the fourth bit sequence. Similarly, the encoding device can also perform sub-block interleaving and bit selection on the third bit sequence to obtain the fifth bit sequence. Therefore, the encoding device can encode the fourth bit sequence. and the fifth bit sequence Put into the second circular buffer E b ,Right now,

[0150] In this embodiment, when retransmitting the source bit sequence, the encoding device can read a portion of the fourth bit sequence, the fourth bit sequence, the fourth bit sequence and a portion of the fifth bit sequence, the fourth bit sequence and the fifth bit sequence, a portion of the fifth bit sequence, or the fifth bit sequence from the second circular buffer, depending on available physical resources. This embodiment does not limit the specific choice of the fifth bit sequence. The starting position of the bit sequence, i.e., the position of the first bit in the bit sequence, can be as shown in Table 3:

[0151] Table 3

[0152]

[0153] Here, we assume the starting position of the fourth bit sequence is position 0, and the offset of the starting position of the fifth bit sequence relative to the starting position of the fourth bit sequence is E. rv0 This offset is the length of the fourth bit sequence; therefore, the starting position of the fifth bit sequence is position E. rv0 When retransmitting the source bit sequence, the encoding device can start from position 0 and read the bit sequence as bit sequence 1 to be read during retransmission; the encoding device can also start from position E. rv0To begin, read the bit sequence, which will be used as bit sequence 2 for retransmission.

[0154] Figure 17 A schematic diagram illustrating the relationship between the bit sequence and its starting position is shown. The fourth and fifth bit sequences constitute the entire second buffer, with the fourth bit sequence starting at position 0 and the fifth bit sequence starting at position E. rv0 The bit sequence read during retransmission can have the same starting position as the fourth bit sequence, for example, Figure 17 The bit sequence read during retransmission is 1; or, the bit sequence read during retransmission can also have the same starting position as the fifth bit sequence, for example, Figure 17 The bit sequence 2 read during retransmission.

[0155] It should be noted that when the encoding device is integrated into the transmitting device, the above... Figures 7 to 17 The actions in the illustrated embodiment can also be performed by the sending device.

[0156] Among them, since the transmitting device in the above embodiments can adopt such as Figure 6 The architecture of the communication device 600 shown indicates that the operation of the transmitting device in the above embodiment can be determined by... Figure 6 The processor 601 or processor 607 in the communication device 600 shown calls the application code stored in the memory 603 to instruct the sending device to execute it; this embodiment does not impose any limitations on this.

[0157] It is understood that the methods and / or steps implemented by the encoding device in the above embodiments can also be implemented by components (e.g., chips or circuits) that can be used in the encoding device.

[0158] Accordingly, embodiments of this application also provide a communication device for implementing the various methods described above. It is understood that, in order to achieve the above functions, the communication device includes hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should readily recognize that, based on the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0159] This application embodiment can divide the communication device into functional modules according to the above method embodiment. For example, each function can be divided into its own functional module, or two or more functions can be integrated into one processing module. The integrated module can be implemented in hardware or as a software functional module. It should be noted that the module division in this application embodiment is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods.

[0160] Figure 18 A schematic diagram of a communication device 18 is shown. The communication device 18 includes a processor 181 and a memory 182 coupled to the processor 181.

[0161] Taking the communication device 18 as an example of the encoding device in the above method embodiment, then: the processor 181 is used to encode the bits in the first bit sequence whose reliability is lower than a first threshold. rv1 The first bit sequence is obtained by bit mapping the source bit sequence after adding CRC bits and then performing bit mapping. rv1 Each source bit is a bit in a source bit sequence, and the length of the first bit sequence is equal to the length of the second bit sequence; the processor 181 is further configured to perform an XOR operation on the bits in the bit sequence obtained after encoding the first bit sequence and the bits in the bit sequence obtained after encoding the second bit sequence to obtain a third bit sequence; or, the processor 181 is further configured to encode the second bit sequence to obtain the third bit sequence; the processor 181 is further configured to map the bit sequence obtained after encoding the first bit sequence and the third bit sequence onto OFDM symbols.

[0162] In one possible implementation, the processor 181 is further configured to map the bit sequence obtained after encoding the first bit sequence and the third bit sequence onto OFDM symbols, including: after rate matching the bit sequence obtained after encoding the first bit sequence, segmenting it into M1 groups of S segments, and for the x1-th group of S segments, performing the following operation: repeating the x1-th group of S segments N times. rv0 This process is repeated cyclically according to the corresponding CSS parameters, resulting in N. rv0 ×S segments; where M1, S, x1, and N rv0 All are positive integers, and 1 ≤ x1 ≤ M1; used to rate match the third bit sequence, segment it into M1 groups of S segments, and for the x2 group of S segments, perform the following operation: repeat the x2 group of S segments N times. rv1 This process is repeated cyclically according to the corresponding CSS parameters, resulting in N. rv1×S segments; where x2 and N rv1 All are positive integers, and 1 ≤ x2 ≤ M1; used to convert N rv0 ×S segments and N rv1 ×S segments are concatenated sequentially and mapped onto OFDM symbols, or, used to segment N segments. rv0 ×S segments and N rv1 The ×S segments are interleaved and cascaded, and mapped onto OFDM symbols.

[0163] In one possible implementation, K in the second bit sequence has a reliability higher than a second threshold. rv1 The bits are k bits in the first bit sequence whose reliability is lower than the first threshold. rv1 Add L to each source bit rv1 The CRC bits are obtained, where K rv1 =k r1v +L r1 k rv1 L rv1 and K rv1 It is a positive integer.

[0164] In one possible implementation, the processor 181 is further configured to perform rate matching on the bit sequence obtained after encoding the first bit sequence, and then segment it into M1 groups of S segments, including: dividing the bit sequence obtained after encoding the first bit sequence into M codewords after rate matching, each codeword containing E bits; repeating the last codeword in the M codewords multiple times, so that the number of codewords is H×M2; dividing the H×M2 codewords into M2 groups, each group... It contains H codewords; for the H codewords in the x3 group, it performs the following operations: concatenates the H codewords and puts the concatenated H×E bits into memory 182; concatenates the first B×S-H×E bits of the H codewords at the end of the H codewords; where H, E, M2 and x3 are all positive integers, and 1≤x3≤M2; B represents the number of bits in each segment; reads B×S bits from memory 182 to generate a group of S segments, where each segment contains B bits.

[0165] In one possible implementation, processor 181 is further configured to, after rate matching the third bit sequence, segment it into M1 groups of S segments, including: dividing the third bit sequence into M codewords after rate matching, each codeword containing E bits; repeating the last codeword in the M codewords multiple times, such that the number of codewords is H×M2; dividing the H×M2 codewords into M2 groups, each group containing H codewords; performing the following operations on the H codewords in the x3 group: concatenating the H codewords and placing the concatenated H×E bits into memory 182; concatenating the first B×S-H×E bits of the H codewords at the end of the H codewords; where H, E, M2, and x3 are all positive integers, and 1≤x3≤M2; B represents the number of bits in each segment; and reading B×S bits from memory 182 to generate a group of S segments, where each segment contains B bits.

[0166] In one possible implementation, the processor 181 is further configured to perform rate matching on the bit sequence obtained after encoding the first bit sequence, including: performing bit interleaving on the fourth bit sequence; wherein the fourth bit sequence is the bit sequence obtained after sub-block interleaving and bit selection on the bit sequence obtained after encoding the first bit sequence; the processor 181 is further configured to perform rate matching on the third bit sequence, including: performing bit interleaving on the fifth bit sequence; wherein the fifth bit sequence is the bit sequence obtained after sub-block interleaving and bit selection on the third bit sequence.

[0167] In one possible implementation, the processor 181 is further configured to store the fourth bit sequence and the fifth bit sequence into the memory 182; wherein the fourth bit sequence is a bit sequence obtained by sub-block interleaving and bit selection after encoding the first bit sequence; the fifth bit sequence is a bit sequence obtained by sub-block interleaving and bit selection after encoding the third bit sequence; the processor 181 is further configured to read the bit sequence starting from the first bit of the fourth bit sequence or the fifth bit sequence when retransmitting the source bit sequence, and to perform bit interleaving on the read bit sequence.

[0168] All relevant content of each step involved in the above method embodiments can be referenced from the functional description of the corresponding functional module, and will not be repeated here.

[0169] In this embodiment, the communication device 18 is presented in an integrated manner, divided into various functional modules. Here, "module" can refer to a specific ASIC, circuit, processor and memory executing one or more software or firmware programs, integrated logic circuit, and / or other devices that can provide the above-mentioned functions.

[0170] When the communication device 18 is the encoding device in the above method embodiments, in a simple embodiment, those skilled in the art will realize that the communication device 18 can be included in... Figure 6 The communication device 600 shown.

[0171] for example, Figure 6 The processor 601 or 607 in the communication device 600 shown can execute the encoding method in the above method embodiment by calling computer execution instructions stored in the memory 603. Specifically, Figure 18 The function / implementation process of processor 181 in the middle can be obtained through Figure 6 The processor 601 or 607 in the communication device 600 shown calls computer execution instructions stored in memory 603 to implement the function. Figure 18 The function / implementation process of memory 182 in the middle can be achieved through Figure 6 It is implemented using memory 603.

[0172] Since the communication device 18 provided in this embodiment can execute the above encoding method, the technical effects it can achieve can be referred to the above method embodiment, and will not be repeated here.

[0173] It should be noted that one or more of the above modules or units can be implemented by software, hardware, or a combination of both. When any of the above modules or units are implemented by software, the software exists as computer program instructions and is stored in memory. The processor can be used to execute the program instructions and implement the above method flow. The processor can be built into a SoC (System-on-a-Chip) or ASIC, or it can be a separate semiconductor chip. In addition to the core that executes software instructions for computation or processing, the processor may further include necessary hardware accelerators, such as field-programmable gate arrays (FPGAs), PLDs (Programmable Logic Devices), or logic circuits that implement dedicated logic operations.

[0174] When the above modules or units are implemented in hardware, the hardware can be any one or any combination of a CPU, microprocessor, digital signal processing (DSP) chip, microcontroller unit (MCU), artificial intelligence processor, ASIC, SoC, FPGA, PLD, application-specific digital circuit, hardware accelerator, or non-integrated discrete device, which can run the necessary software or perform the above method flow independently of software.

[0175] Optionally, embodiments of this application also provide a chip system, including: at least one processor and an interface, wherein the at least one processor is coupled to a memory via the interface, and when the at least one processor executes a computer program or instructions in the memory, the method in any of the above method embodiments is executed. In one possible implementation, the communication device further includes a memory. Optionally, the chip system may be composed of chips, or may include chips and other discrete devices; embodiments of this application do not specifically limit this.

[0176] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented using software programs, implementation can be, in whole or in part, in the form of a computer program product. This computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device containing one or more servers, data centers, etc., that can be integrated with the medium. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state disks, SSDs), etc.

[0177] Although this application has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the accompanying drawings, disclosure, and appended claims, will understand and implement other variations of the disclosed embodiments in carrying out the claimed application. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0178] Although this application has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made thereto without departing from the spirit and scope of this application. Accordingly, this specification and drawings are merely exemplary illustrations of this application as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of this application. Clearly, those skilled in the art can make various alterations and modifications to this application without departing from the spirit and scope of this application. Thus, if such modifications and modifications of this application fall within the scope of the claims of this application and their equivalents, this application is also intended to include such modifications and modifications.

Claims

1. An encoding method, characterized in that, The method includes: The first bit sequence with a reliability lower than the first threshold The first bit sequence is obtained by bit mapping the source bit sequence to obtain the second bit sequence. The first bit sequence is the bit sequence obtained by bit mapping after adding cyclic redundancy check (CRC) bits to the source bit sequence. Each source bit is a bit in the source bit sequence, and the length of the first bit sequence is equal to the length of the second bit sequence. It is a positive integer; The bits in the bit sequence obtained by encoding the first bit sequence and the bits in the bit sequence obtained by encoding the second bit sequence are XORed to obtain the third bit sequence; or, the second bit sequence is encoded to obtain the third bit sequence. After rate matching of the bit sequence obtained by encoding the first bit sequence, it is segmented into M1 groups of S segments. The S segments of the x1th group are repeated. This time received There are several segments; among them, M1, S, x1 and All are positive integers, and 1 ≤ x1 ≤ M1; After rate matching of the third bit sequence, it is segmented into M1 groups of S segments, and for the x2 group of S segments, the x2 group of S segments is repeated. This time received There are segments; where x2 and All are positive integers, and 1 ≤ x2 ≤ M1; The Each segment and the aforementioned Each segment is mapped onto an orthogonal frequency division multiplexing (OFDM) symbol.

2. The method according to claim 1, characterized in that, The Each segment and the aforementioned Each segment is mapped to an OFDM symbol, including: The Each segment and the aforementioned The segments are concatenated sequentially and mapped onto the OFDM symbol, or... Divide into segments, Each segment and the aforementioned The segments are interleaved and cascaded together, and mapped onto the OFDM symbol.

3. The method according to claim 1 or 2, characterized in that, Repeat the S segments of the x1th group. This time received Each segment includes: repeating the S segments of the x1th group. This process is repeated time and again according to the corresponding segmented cyclic shift CSS parameters to obtain the desired result. Each segment; and / or Repeat the S segments of the x2th group. This time received Each segment includes: repeating the S segments of the x2th group. This process is repeated cyclically according to the corresponding CSS parameters each time, resulting in the... Each segment.

4. The method according to claim 1 or 2, characterized in that, The second bit sequence with a reliability higher than the second threshold The bits are those bits in the first bit sequence whose reliability is lower than the first threshold. Add one source bit The CRC bits are obtained, where... , and It is a positive integer.

5. The method according to claim 1 or 2, characterized in that, After rate matching of the bit sequence obtained by encoding the first bit sequence, it is segmented into M1 groups of S segments, including: After rate matching, the bit sequence obtained by encoding the first bit sequence is divided into M codewords, each codeword containing E bits; Repeat the last codeword among the M codewords multiple times, so that the number of codewords is H×M2; Divide the H×M2 codewords into M2 groups, with each group containing H codewords; For the H codewords in the x3 group, perform the following operation: The H codewords are concatenated, and the concatenated H×E bits are placed into the first circular buffer; the first B×S-H×E bits of the H codewords are concatenated to the end of the H codewords; where M, H, E, M2 and x3 are all positive integers, and 1≤x3≤M2; B represents the number of bits in each segment; B×S bits are read from the circular buffer to generate a set of S segments, each segment containing B bits.

6. The method according to claim 1 or 2, characterized in that, After rate matching of the third bit sequence, it is segmented into M1 groups of S segments, including: After rate matching, the third bit sequence is divided into M codewords, each codeword containing E bits. Repeat the last codeword among the M codewords multiple times, so that the number of codewords is H×M2; Divide the H×M2 codewords into M2 groups, with each group containing H codewords; For the H codewords in the x3 group, perform the following operation: The H codewords are concatenated, and the concatenated H×E bits are placed into the first circular buffer; the first B×S-H×E bits of the H codewords are concatenated to the end of the H codewords; where M, H, E, M2 and x3 are all positive integers, and 1≤x3≤M2; B represents the number of bits in each segment; B×S bits are read from the circular buffer to generate a set of S segments, each segment containing B bits.

7. The method according to claim 1 or 2, characterized in that, The step of rate matching the bit sequence obtained after encoding the first bit sequence includes: Bit interleaving is performed on the fourth bit sequence; wherein, the fourth bit sequence is the bit sequence obtained by sub-block interleaving and bit selection of the bit sequence obtained by encoding the first bit sequence; The step of rate matching the third bit sequence includes: Bit interleaving is performed on the fifth bit sequence; wherein the fifth bit sequence is the bit sequence obtained by sub-block interleaving and bit selection of the third bit sequence.

8. The method according to claim 1 or 2, characterized in that, The method further includes: The fourth and fifth bit sequences are placed into the second circular buffer; wherein, the fourth bit sequence is the bit sequence obtained by sub-block interleaving and bit selection of the bit sequence obtained after encoding the first bit sequence; and the fifth bit sequence is the bit sequence obtained by sub-block interleaving and bit selection of the third bit sequence. When retransmitting the source bit sequence, the bit sequence is read starting from the first bit of the fourth bit sequence or the fifth bit sequence, and the read bit sequence is bit interleaved.

9. An encoding device, characterized in that, The encoding device includes: a processor and a memory coupled to the processor; The memory is used to store programs and data; The processor is configured to execute the program stored in the memory to perform the following functions: The processor is used to process bits in the first bit sequence whose reliability is lower than a first threshold. The first bit sequence is obtained by bit mapping the source bit sequence to obtain the second bit sequence. The first bit sequence is the bit sequence obtained by bit mapping after adding cyclic redundancy check (CRC) bits to the source bit sequence. Each source bit is a bit in the source bit sequence, and the length of the first bit sequence is equal to the length of the second bit sequence. It is a positive integer; The processor is further configured to perform an XOR operation on the bits in the bit sequence obtained after encoding the first bit sequence and the bits in the bit sequence obtained after encoding the second bit sequence to obtain a third bit sequence; or, the processor is further configured to encode the second bit sequence to obtain a third bit sequence. The processor is further configured to perform rate matching on the bit sequence obtained after encoding the first bit sequence, and then segment it into M1 groups of S segments, repeating the S segments of the x1th group. This time received There are several segments; among them, M1, S, x1 and All are positive integers, and 1 ≤ x1 ≤ M1; The processor is further configured to perform rate matching on the third bit sequence, segment it into M1 groups of S segments, and repeat the S segments of the x2 group. This time received There are segments; where x2 and All are positive integers, and 1 ≤ x2 ≤ M1; The processor is also used to process the... Each segment and the aforementioned Each segment is mapped onto an orthogonal frequency division multiplexing (OFDM) symbol.

10. The encoding device according to claim 9, characterized in that, The processor is also used to process the... Each segment and the aforementioned Each segment is mapped to an OFDM symbol, including: Used to the Each segment and the aforementioned The segments are concatenated sequentially and mapped onto OFDM symbols, or, used to segment the... Each segment and the aforementioned The segments are interwoven and cascaded together, mapped onto OFDM symbols.

11. The encoding device according to claim 9 or 10, characterized in that, Repeat the S segments of the x1th group. This time received Each segment includes: repeating the S segments of the x1th group. This process is repeated time and again according to the corresponding segmented cyclic shift CSS parameters to obtain the desired result. Each segment; and / or Repeat the S segments of the x2th group. This time received Each segment includes: repeating the S segments of the x2th group. This process is repeated cyclically according to the corresponding CSS parameters each time, resulting in the... Each segment.

12. The encoding device according to claim 9 or 10, characterized in that, The second bit sequence with a reliability higher than the second threshold The bits are those bits in the first bit sequence whose reliability is lower than the first threshold. Add one source bit The CRC bits are obtained, where... , and It is a positive integer.

13. The encoding device according to claim 9 or 10, characterized in that, The processor is further configured to perform rate matching on the bit sequence obtained after encoding the first bit sequence, and then segment it into M1 groups of S segments, including: After rate matching, the bit sequence obtained by encoding the first bit sequence is divided into M codewords, each codeword containing E bits; the last codeword in the M codewords is repeated multiple times, so that the number of codewords is H×M2; the H×M2 codewords are divided into M2 groups, each group containing H codewords; For the H codewords in the x3 group, the following operations are performed: concatenate the H codewords and place the concatenated H×E bits into the memory; concatenate the first B×S-H×E bits of the H codewords to the end of the H codewords; where M, H, E, M2, and x3 are all positive integers, and 1≤x3≤M2; B represents the number of bits in each segment; read B×S bits from the memory to generate a group of S segments, where each segment contains B bits.

14. The encoding device according to claim 9 or 10, characterized in that, The processor is further configured to perform rate matching on the third bit sequence and then segment it into M1 groups of S segments, including: After rate matching of the third bit sequence, it is divided into M codewords, each codeword containing E bits; the last codeword in the M codewords is repeated multiple times, so that the number of codewords is H×M2; the H×M2 codewords are divided into M2 groups, each group containing H codewords; For the H codewords in the x3 group, the following operations are performed: concatenate the H codewords and put the concatenated H×E bits into the memory; concatenate the first B×S-H×E bits of the H codewords to the end of the H codewords; where M, H, E, M2 and x3 are all positive integers, and 1≤x3≤M2; B represents the number of bits in each segment; Used to read B×S bits from the memory to generate a set of S segments, wherein each segment contains B bits.

15. The encoding device according to claim 9 or 10, characterized in that, The processor is further configured to perform rate matching on the bit sequence obtained after encoding the first bit sequence, including: Used for bit interleaving of the fourth bit sequence; wherein, the fourth bit sequence is the bit sequence obtained by sub-block interleaving and bit selection of the bit sequence obtained after encoding the first bit sequence; The processor is further configured to perform rate matching on the third bit sequence, including: Used for bit interleaving of the fifth bit sequence; wherein, the fifth bit sequence is the bit sequence obtained after sub-block interleaving and bit selection of the third bit sequence.

16. The encoding device according to claim 9 or 10, characterized in that, The processor is further configured to place a fourth bit sequence and a fifth bit sequence into the memory; wherein the fourth bit sequence is a bit sequence obtained by sub-block interleaving and bit selection of the bit sequence obtained by encoding the first bit sequence; and the fifth bit sequence is a bit sequence obtained by sub-block interleaving and bit selection of the third bit sequence. The processor is further configured to, when retransmitting the source bit sequence, read the bit sequence starting from the first bit of the fourth bit sequence or the fifth bit sequence, and perform bit interleaving on the read bit sequence.

17. A computer-readable storage medium, characterized in that, It stores a computer program that, when executed by a computer, causes the computer to perform the method of any one of claims 1-8.

18. A computer program product containing instructions, characterized in that, When the instructions are executed on a computer, the computer performs the method of any one of claims 1-8.

19. A transmitting device, characterized in that, It includes a front-end module and an encoding device as described in any one of claims 9-16; The encoding device is used to encode the source bit sequence and map it onto OFDM symbols; The front-end module is used to convert the output of the encoding device into a wireless signal and transmit the wireless signal.

20. The transmitting end device according to claim 19, characterized in that, The transmitting end device further includes a modulation module; the front-end module is used to convert the output of the encoding device into a wireless signal and transmit the wireless signal, including: Used to modulate the output of the encoding device into a high-frequency signal via the modulation module; Used to convert the high-frequency signal into a wireless signal and transmit the wireless signal.

21. A communication system, characterized in that, It includes a receiving end device and a transmitting end device as described in claim 19 or 20; the receiving end device is configured to receive a wireless signal from the transmitting end device and recover the source bit sequence based on the wireless signal.

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