High frequency offset tolerance multi-channel signal phase measurement method and device

Abstract

The application provides a multi-channel signal phase measurement method and device with high frequency offset tolerance, and relates to the technical field of communication. The method comprises the following steps: based on each channel, a pseudo-random code PN sequence data transmitted by a phase self-calibrated digital-to-analog conversion chip is received, wherein the PN sequence data is obtained by the digital-to-analog conversion chip based on collected PN codes; for the PN sequence data received by each channel, frequency offset estimation is performed on the PN sequence data to obtain an estimated frequency offset, and the PN sequence data is compensated by using the estimated frequency offset to obtain PN sequence compensation data corresponding to the channel; for the PN sequence compensation data of each channel, the PN sequence compensation data and pre-stored local PN sequence data are subjected to sliding correlation capture, and a four-quadrant inverse tangent algorithm is combined to obtain a predicted phase. The application is suitable for high dynamic scenes with Doppler, and avoids the influence of relative motion or clock difference on the phase detection result.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a method and apparatus for measuring the phase of a multi-channel signal with high-frequency bias tolerance. Background Technology

[0002] With the increasing variety of communication services, the demand for communication capacity is constantly growing. Using multi-channel signal acquisition can improve the throughput of signal transmission, and signal combining between channels at the receiving end can bring receiver diversity gain and improve the stability of signal transmission. Therefore, multi-channel signal transmission is receiving increasing attention in research, such as Multi-Input Multi-Output (MIMO) technology.

[0003] However, during communication, the relative motion between the transmitting and receiving parties, as well as the inherent frequency deviation of their clocks, can cause Doppler frequency offset, which can severely affect communication performance. Furthermore, when combining signals acquired from multiple channels, it is necessary to ensure phase consistency between the signals. Phase differences between signals can prevent correct combining of signals from multiple channels, reducing diversity gain. Therefore, achieving phase self-calibration with high frequency offset tolerance is crucial for multi-channel combining systems.

[0004] Existing phase calibration techniques mainly include matrix inversion, Fast Fourier Transform (FFT), and rotating vector methods. In the matrix inversion method, the test piece is mounted on a precision-positioned turntable, the radiated signal is received, and the corresponding phase value is obtained by inverting the matrix. FFT does not require a device or signal and replaces matrix inversion. The rotating vector method is based on the fact that the total received field strength is the composite field strength of each channel. Changing the phase of a channel will change the total field strength, and the relative phase of that channel can be determined based on the change in the received field strength.

[0005] However, the above methods all assume that the frequency offset between channels is consistent, do not consider the impact of frequency offset on phase calibration, and require recalculation every time power is turned on, which increases the complexity of the system. Summary of the Invention

[0006] This invention provides a multi-channel signal phase measurement method and apparatus with high frequency offset tolerance, which solves the defect in the prior art that does not consider the impact of frequency offset on phase calibration, thus eliminating the impact of frequency offset in communication and eliminating the need for recalibration after each power-on.

[0007] This invention provides a multi-channel signal phase measurement method with high-frequency offset tolerance, comprising: receiving pseudo-random code (PN) sequence data sent by a phase-self-calibrated digital-to-analog converter chip for each channel, wherein the PN sequence data is obtained by the digital-to-analog converter chip based on the acquired PN code; estimating the frequency offset of the PN sequence data received for each channel to obtain a predicted frequency offset, and compensating the PN sequence data using the predicted frequency offset to obtain PN sequence compensation data for the corresponding channel; and performing sliding correlation acquisition on the PN sequence compensation data of each channel and pre-stored local PN sequence data, and combining it with a four-quadrant arctangent algorithm to obtain a predicted phase.

[0008] According to the present invention, a multi-channel signal phase measurement method with high-frequency bias tolerance is provided. The method involves performing sliding correlation capture on the PN sequence compensation data and pre-stored local PN sequence data for each channel, and combining this with a four-quadrant arctangent algorithm to obtain the predicted phase. The method includes: performing sliding correlation capture on the PN sequence compensation data and pre-stored local PN sequence data to obtain peak data; obtaining amplitude data and phase data based on the peak data; obtaining the estimated phase of each channel based on the amplitude data and the phase data using a four-quadrant arctangent algorithm; and obtaining the predicted phase based on the estimated phase of each channel.

[0009] According to the present invention, a multi-channel signal phase measurement method with high-frequency bias tolerance is provided. After obtaining the predicted phase, the method includes: obtaining the phase difference between adjacent channels based on the estimated phase of each channel; and updating the predicted phase according to the phase difference to obtain the updated predicted phase.

[0010] According to the present invention, a multi-channel signal phase measurement method with high frequency offset tolerance is provided. The frequency offset estimation of the PN sequence data includes: for the PN sequence data received by a single channel, selecting a data sequence of preset length at the beginning and end, and obtaining a phase difference value based on a conjugate algorithm; and obtaining an estimated frequency offset based on the phase difference value and the time delay between the previously acquired selected data sequences of preset length at the beginning and end.

[0011] According to the present invention, a multi-channel signal phase measurement method with high-frequency bias tolerance includes, before receiving pseudo-random code PN sequence data sent by a digital-to-analog converter chip after phase self-calibration based on each channel, the method comprises: generating a preset sequence of preset bits; supplementing the target positions of the preset sequence of preset bits based on preset values ​​to obtain a PN code; and sending the PN code to the digital-to-analog converter chip.

[0012] According to the present invention, a multi-channel signal phase measurement method with high-frequency bias tolerance is provided, wherein sending the PN code to the digital-to-analog converter chip includes: performing shaping filtering on the PN code; and sending the PN code after shaping filtering to the digital-to-analog converter chip for up-conversion processing.

[0013] The step of receiving pseudo-random code PN sequence data sent by the phase self-calibrated digital-to-analog converter chip based on each channel includes: receiving PN sequence data sent by the digital-to-analog converter chip, wherein the PN sequence data is obtained by the digital-to-analog converter chip after down-converting the received PN code; and performing matched filtering on the PN sequence data.

[0014] According to the present invention, a multi-channel signal phase measurement method with high-frequency bias tolerance is provided, wherein the phase self-calibration of the digital-to-analog converter chip is used to synchronize the local oscillator phase based on the synchronization reference signal and the synchronization clock sent by the clock chip, wherein the synchronization reference signal and the synchronization clock are obtained by the clock chip based on the received synchronization pulse.

[0015] This invention also provides a multi-channel signal phase measurement device with high-frequency offset tolerance, comprising: a data receiving module, which receives pseudo-random code PN sequence data sent by a phase self-calibrated digital-to-analog converter chip for each channel, wherein the PN sequence data is obtained by the digital-to-analog converter chip based on the acquired PN code; a frequency offset prediction and compensation module, which estimates the frequency offset of the PN sequence data received for each channel to obtain a predicted frequency offset, and uses the predicted frequency offset to compensate the PN sequence data to obtain PN sequence compensation data for the corresponding channel; and a phase detection module, which performs sliding correlation capture on the PN sequence compensation data and pre-stored local PN sequence data for each channel, and combines it with a four-quadrant arctangent algorithm to obtain a predicted phase.

[0016] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of the multi-channel signal phase measurement method with high-frequency bias tolerance as described above.

[0017] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the multi-channel signal phase measurement method with high-frequency bias tolerance as described above.

[0018] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the multi-channel signal phase measurement method with high-frequency bias tolerance as described above.

[0019] The high-frequency offset tolerance multi-channel signal phase measurement method and apparatus provided by this invention corrects the random phase introduced by the randomness of the local oscillation start-up time of the digital-to-analog converter chip by receiving PN sequence data sent by the self-calibrated digital-to-analog converter chip. This ensures that the phase of the signal acquired by the digital-to-analog converter chip remains consistent during repeated power-on processes, eliminating the need for recalibration each time. Furthermore, by estimating and compensating for the frequency offset of the PN sequence data before phase detection, it is applicable to high dynamic scenarios with Doppler, avoiding the influence of relative motion or clock difference between the FPGA platform and the digital-to-analog converter chip on the phase detection results and improving the phase detection accuracy. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0021] Figure 1 This is one of the flowcharts illustrating the multi-channel signal phase measurement method with high-frequency bias tolerance provided by the present invention;

[0022] Figure 2 This is the second flowchart of the multi-channel signal phase measurement method with high-frequency bias tolerance provided by the present invention;

[0023] Figure 3 This is a schematic diagram of the phase self-calibration process provided by the present invention;

[0024] Figure 4 This is a schematic diagram of frequency offset estimation provided by the present invention;

[0025] Figure 5 This is a schematic diagram showing the comparison between the phase estimation results and the true phase before and after using the frequency offset estimation and compensation algorithm when the phase offset θ = 30°, the frequency offset f = 1000Hz, and the sampling rate f_s = 100MHz, as provided by the present invention.

[0026] Figure 6 A schematic diagram of the phase estimation error curves of the FPGA platform provided by the present invention under different signal-to-noise ratios and frequency offsets;

[0027] Figure 7 This is a schematic diagram illustrating the measurement results of phase jitter in the signal acquired by the digital-to-analog converter chip after calibration, provided by the present invention.

[0028] Figure 8 This is a schematic diagram of the structure of the multi-channel signal phase measurement device with high-frequency bias tolerance provided by the present invention;

[0029] Figure 9 This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0031] Figure 1 A flowchart illustrating a multi-channel signal phase measurement method with high-frequency bias tolerance is shown. The method includes:

[0032] S11, based on each channel, receives pseudo-random code PN sequence data sent by the phase self-calibrated digital-to-analog converter chip respectively. The PN sequence data is obtained by the digital-to-analog converter chip based on the acquired PN code.

[0033] S12, For the PN sequence data received by each channel, the frequency offset of the PN sequence data is estimated to obtain the estimated frequency offset, and the estimated frequency offset is used to compensate the PN sequence data to obtain the PN sequence compensation data for the corresponding channel.

[0034] S13, for the PN sequence compensation data of each channel, the PN sequence compensation data and the pre-stored local PN sequence data are subjected to sliding correlation capture, and combined with the four-quadrant arctangent algorithm to obtain the predicted phase.

[0035] It should be noted that the execution entity in this manual is a Field Programmable Gate Array (FPGA) platform. S1N in this manual does not represent the sequential order of the multi-channel signal phase measurement methods for high-frequency bias tolerance. The following details will explain this in conjunction with... Figures 2-7 This invention describes a multi-channel signal phase measurement method with high-frequency bias tolerance.

[0036] Step S11: Based on each channel, receive the pseudo-random code PN sequence data sent by the phase self-calibrated digital-to-analog converter chip respectively. The PN sequence data is obtained by the digital-to-analog converter chip based on the acquired PN code.

[0037] In an optional embodiment, before receiving the pseudo-random code PN sequence data sent by the phase self-calibrated digital-to-analog converter chip based on each channel, the method includes: generating a preset sequence of preset bits; supplementing the target positions of the preset sequence of preset bits based on preset values ​​to obtain the PN code; and sending the PN code to the digital-to-analog converter chip.

[0038] It should be noted that PN codes are a type of encoded sequence composed of 0s and 1s with autocorrelation properties similar to white noise. The most common type is the m-sequence, which has excellent autocorrelation characteristics and its code phase can be determined by performing correlation operations with the local codeword. In this embodiment, the corresponding correlation operation can be determined according to the preset number of bits of the preset sequence. For example, when the preset sequence of preset bits is a 63-bit preset sequence, a 64-bit PN code can be formed by padding the end of the 63-bit m-sequence with 0s.

[0039] Further, the PN code is sent to the digital-to-analog converter chip, including: shaping and filtering the PN code; and sending the shaped and filtered PN code to the digital-to-analog converter chip for up-conversion processing. Correspondingly, based on each channel, pseudo-random code PN sequence data sent by the phase-self-calibrated digital-to-analog converter chip is received, including: receiving the PN sequence data sent by the digital-to-analog converter chip, where the PN sequence data is obtained after the digital-to-analog converter chip performs down-conversion processing on the received PN code; and performing matched filtering on the PN sequence data.

[0040] It should be added that the FPGA platform uses a continuous PN64 sequence as the raw data, which is then shaped and filtered before being sent to the digital-to-analog converter (DAC) chip for up-conversion. The DAC chip acquires this signal, down-converts it, and sends it to the FPGA platform for matched filtering to facilitate subsequent phase estimation. During the up-conversion and down-conversion processes of the DAC chip, due to the inconsistency between the DAC chip's transmit and receive local oscillator frequencies and the uncertainty of the phase, the PN signal acquired by the DAC chip and transmitted from the FPGA will have random frequency and phase offsets. Through the self-calibration of the DAC chip, the random phase offset of the received PN code can be corrected to a fixed phase offset, thus facilitating the FPGA platform to accurately estimate the fixed phase offset under the condition of frequency offset.

[0041] It should be noted that the phase self-calibration of the digital-to-analog converter (DAC) chip is used to synchronize the local oscillator phase based on the synchronization reference signal and synchronization clock sent by the clock chip. The synchronization reference signal and synchronization clock are obtained by the clock chip based on the received synchronization pulses. Through synchronization, the phase of a single-channel acquisition signal remains unchanged after each power-on, and the phase difference between multiple acquisition signals remains unchanged. Furthermore, after the DAC chip synchronizes the local oscillator phase, it establishes a communication link with the FPGA platform, achieving link synchronization, thus facilitating the transmission of its acquired data to the FPGA platform.

[0042] In other words, the self-calibration of the digital-to-analog converter (DAC) chip includes: the clock chip receiving the externally transmitted synchronization pulse to obtain the synchronization reference signal and the synchronization clock, and sending the synchronization reference signal and the synchronization clock to the DAC chip; the DAC chip receiving the synchronization reference signal and the synchronization clock, and aligning its own clock and the rising edge of the reference signal with the synchronization reference signal and the synchronization clock according to the synchronization reference signal and the synchronization clock, and setting the corresponding local oscillator phase to zero when the rising edge is acquired, thereby correcting the random phase caused by the randomness of the oscillation time of the DAC chip's local oscillator, so that the phase difference between the multi-channel signals remains unchanged without changing the connection relationship. This phase difference depends only on the transmission delay of each acquisition link. Therefore, based on the unchanged phase difference of the multi-channel signals, combined with the subsequent phase measurement algorithm, the phase synchronization of the multi-channel signals can be achieved.

[0043] It should be added that when the clock chip sends the synchronization reference signal and synchronization clock to the digital-to-analog converter chip, the clock chip also sends the synchronization reference signal and synchronization clock to the FPGA platform. This allows for the use of a low-speed synchronization reference signal and a high-speed synchronization clock to achieve link synchronization between the digital-to-analog converter chip and the FPGA platform. Furthermore, the synchronization pulse can be generated by an external pulse generator and sent to the clock chip, or it can be generated by the FPGA platform and sent to the clock chip; no further limitations are imposed here.

[0044] Step S12: For the PN sequence data received by each channel, frequency offset estimation is performed on the PN sequence data to obtain the estimated frequency offset, and the estimated frequency offset is used to compensate the PN sequence data to obtain the PN sequence compensation data for the corresponding channel.

[0045] In this embodiment, frequency offset estimation of PN sequence data includes: for PN sequence data received by a single channel, selecting data sequences of preset lengths at the beginning and end, and obtaining a phase difference value based on a conjugate algorithm; and obtaining an estimated frequency offset value based on the phase difference value and the time delay between the previously acquired selected data sequences of preset lengths at the beginning and end.

[0046] It should be noted that each channel of the FPGA platform receives PN sequence data sent by the digital-to-analog converter chip. For the PN sequence data sent by each channel, the first and last segments of the sequence are multiplied by conjugate to eliminate the original phase information and retain the phase difference between the two segments caused by frequency offset. The corresponding frequency offset is then estimated based on the phase difference, and the estimated frequency offset is used to compensate back the acquired PN sequence data. This achieves the frequency offset tolerance mentioned above, which facilitates subsequent phase detection.

[0047] Step S13: For the PN sequence compensation data of each channel, perform sliding correlation capture on the PN sequence compensation data and the pre-stored local PN sequence data, and combine it with the four-quadrant arctangent algorithm to obtain the predicted phase.

[0048] In this embodiment, for the PN sequence compensation data of each channel, sliding correlation capture is performed on the PN sequence compensation data and the pre-stored local PN sequence data, and the predicted phase is obtained by combining the four-quadrant arctangent algorithm. This includes: performing sliding correlation capture on the PN sequence compensation data and the pre-stored local PN sequence data to obtain peak data; obtaining amplitude data and phase data based on the peak data; obtaining the estimated phase of each channel based on the amplitude data and phase data and using the four-quadrant arctangent algorithm; and obtaining the predicted phase based on the estimated phase of each channel.

[0049] It should be added that, since PN sequence data has good autocorrelation, the received PN sequence data can be pre-stored locally on the FPGA using sliding correlation capture. When a correlation peak appears when the received PN sequence data is aligned with the locally stored PN sequence data, the data at the peak point is selected. This allows for the calculation of the four-quadrant arctangent of the I (amplitude) and Q (phase) path results, thus obtaining the estimated phase of the corresponding channel. Furthermore, sliding correlation capture can employ a digital matched filter (DMF).

[0050] In addition, based on the estimated phase of each channel, the predicted phase is obtained, including averaging the estimated phases of all channels to obtain the predicted phase, thereby achieving phase estimation with large frequency offset tolerance.

[0051] In one optional embodiment, after obtaining the predicted phase, since the phase offset of each channel is fixed each time, upon power-on, the process includes: obtaining the phase difference between adjacent channels based on the estimated phase of each channel; and updating the predicted phase according to the phase difference to obtain the updated predicted phase. It should be noted that by measuring the fixed phase difference between the multiple acquired signals (i.e., PN sequence data), phase self-calibration of the multiple acquired signals on the FPGA platform is achieved based on the phase self-calibration of the digital-to-analog converter chip.

[0052] Figure 2 A flowchart illustrating a multi-channel signal phase measurement method with high-frequency bias tolerance is shown. The method includes:

[0053] The digital-to-analog converter chip performs self-calibration based on the synchronization reference signal and synchronization clock sent by the clock chip, and establishes a communication link with the FPGA platform;

[0054] The FPGA platform sends the generated PN code to the digital-to-analog converter chip;

[0055] The digital-to-analog converter chip acquires the PN code, obtains the PN sequence data, and returns the PN sequence data to the FPGA platform;

[0056] The FPGA platform estimates the frequency offset of the PN sequence data received from each channel to obtain the estimated frequency offset, and uses the estimated frequency offset to compensate the corresponding PN sequence data to obtain the PN sequence compensation data for the corresponding channel.

[0057] The FPGA platform performs sliding correlation capture on the PN sequence compensation data and the pre-stored local PN sequence data, and combines it with the four-quadrant arctangent algorithm to obtain the predicted phase.

[0058] Specifically, refer to Figure 3 The digital-to-analog converter (DAC) chip performs self-calibration based on the synchronization reference signal and synchronization clock sent by the clock chip, and establishes a communication link with the FPGA platform. This includes: the clock chip receiving the synchronization pulse sent externally, obtaining the synchronization reference signal and synchronization clock, and sending the synchronization reference signal and synchronization clock to the DAC chip; the DAC chip receiving the synchronization reference signal and synchronization clock, aligning its own clock and the rising edge of the reference signal with the synchronization reference signal and synchronization clock according to the synchronization reference signal and synchronization clock, and setting the corresponding local oscillator phase to zero when the rising edge is acquired; and the DAC chip establishing a communication link with the FPGA platform.

[0059] In one alternative embodiment, reference Figure 3 It employs two clock chips, four digital-to-analog converter chips, and four FPGA platforms to achieve automatic phase calibration of four-channel signals. Based on this embodiment, it can be extended to more channels in the same way.

[0060] It should be noted that during multi-channel signal acquisition, the phase depends on the signal transmission delay and the randomness of the local oscillator start-up time. With data transmission from the FPGA platform and the connection between the FPGA platform and the digital-to-analog converter chip remaining unchanged, the signal transmission delay remains constant; the uncertainty in the signal phase stems solely from the random start-up time of the local oscillator in the digital-to-analog converter chip. This embodiment is used to correct the signal phase uncertainty caused by the local oscillator start-up time.

[0061] In the above embodiment, each clock chip provides clock signals to two digital-to-analog converter (DAC) chips and two FPGA platforms. Each DAC chip sends the acquired data to one FPGA platform for processing. Specifically, a pulse generator (PULSE_GENERATE) generates a set of synchronization pulses (SYNC_PULSE) to synchronize the clock signals of the two clock chips. Then, the clock chips provide a synchronization reference signal (REF_CLK) and a synchronization clock (LOGIC_CLK) to each DAC chip and FPGA platform. Finally, a low-speed synchronization reference signal and a high-speed synchronization clock are used to achieve phase synchronization of the DAC chips and link synchronization between the DAC chips and the FPGA platform.

[0062] Using the design described in this embodiment, assuming that the delay caused by the same signal trace length is exactly the same, ideally the local oscillator phases of the four digital-to-analog converter chips can be identical. However, in practice, due to factors such as unequal trace lengths, there will be a fixed phase difference between the local oscillators. This phase difference can be estimated and compensated using the predicted phase method described in this invention.

[0063] In one optional embodiment, the FPGA platform continuously transmits 64PN data with a 16x upsampling factor, totaling 32 PN64s in 32768 bits. The digital-to-analog converter chip acquires the 32768 bits of observation data (i.e., the PN code), performs up- and down-conversion processing on it, and then sends it to the FPGA platform. Upon receiving the PN sequence data, the FPGA platform first extracts the first 1024 bits and the last 1024 bits of the 32768 bits for frequency offset estimation and compensation; the specific estimation and compensation methods are described above. Next, the frequency offset-compensated 32768 bits are correlated with the original PN64 data using a sliding correlation capture. Since the 32768 bits contain 32 PN64s, 32 correlation peaks will appear. Assuming the data at the 32 peaks are I1+Q1, I2+Q2, ..., I... 32 +Q 32 For the peak data I1+Q1, the phase calculation result (degrees) is: The final phase calculation result (in degrees) is obtained by averaging the 32 peak values.

[0064] Further, refer to Figure 4 The observation window contains 32768 bits, and the collected data is 64PN with a 16x upsampling rate, meaning each data segment is 1024 bits long. Assume the transmitted data is s, the received signal phase offset is θ, the frequency offset is f, and the receiving sampling rate is f. s Let the first 1024 bits be s1 and the last 1024 bits be s2. Let the time interval between s1 and s2 be τ. Then s1 = s(t)e j(θ+ft) ,s2=s(t)e j(θ+f(t+τ)) , Multiplying the conjugates of s2 and s1 together yields s2. * ×s1=s(t) 2 e jfτ Therefore, fτ=tan -1 (s2 * ×s1). Therefore, the frequency offset is calculated. During compensation, the received data is multiplied by e. -jft That's all.

[0065] Figure 5The comparison between the phase estimation results before and after the frequency offset estimation and compensation algorithms is presented under the conditions of phase offset θ = 30°, frequency offset f = 1000Hz, and sampling rate f_s = 100MHz. Whether or not frequency offset is compensated has little impact on the correlation peak, but if a frequency offset exists during phase calculation, the measured phase will continuously change and gradually deviate from the true phase value.

[0066] Figure 6 The figures show the phase estimation error curves of the FPGA platform of this invention under different signal-to-noise ratios and frequency offsets. The measurement method has a measurement error of <1° when SNR = 0dB and frequency offset ≤1500Hz.

[0067] Figure 7 To measure the phase jitter of the signals acquired by the calibrated digital-to-analog converter (DAC) chips, the phase measurement and processing unit of this invention was used to measure the phase jitter of the signals acquired by the DAC chips after self-calibration. Three different DAC chips were measured, with each chip powered on three times and measured three times each time, for a total of nine measurements. It can be seen that after multiple power-ups and repeated measurements, the phase of the signals acquired by each DAC chip remained essentially unchanged. The measurement results with the largest jitter were selected for analysis, and the jitter error was <4°.

[0068] In summary, this embodiment of the invention receives PN sequence data sent by a self-calibrated digital-to-analog converter (DAC) chip to correct the random phase introduced by the randomness of the local oscillation start-up time of the DAC chip receiver. This ensures that the phase of the signal acquired by the DAC chip receiver remains consistent during repeated power-ups, eliminating the need for recalibration each time. Furthermore, by estimating and compensating for the frequency offset of the PN sequence data before phase detection, it is made suitable for high-dynamic scenarios with Doppler interference. This avoids the influence of relative motion or clock bias between the FPGA platform and the DAC chip on the phase detection results, thereby improving phase detection accuracy.

[0069] The high-frequency bias tolerance multi-channel signal phase measurement device provided by the present invention is described below. The high-frequency bias tolerance multi-channel signal phase measurement device described below and the high-frequency bias tolerance multi-channel signal phase measurement method described above can be referred to in correspondence.

[0070] Figure 8 A schematic diagram of a multi-channel signal phase measurement device with high-frequency bias tolerance is shown. The device includes:

[0071] The data receiving module 81 receives pseudo-random code PN sequence data sent by the phase self-calibrated digital-to-analog converter chip through each channel. The PN sequence data is obtained by the digital-to-analog converter chip based on the acquired PN code.

[0072] The frequency offset prediction and compensation module 82 estimates the frequency offset of the PN sequence data received by each channel to obtain the estimated frequency offset, and uses the estimated frequency offset to compensate the PN sequence data to obtain the PN sequence compensation data for the corresponding channel.

[0073] The phase detection module 83 performs sliding correlation capture on the PN sequence compensation data and the pre-stored local PN sequence data for each channel, and combines it with the four-quadrant arctangent algorithm to obtain the predicted phase.

[0074] In an optional embodiment, the device further includes: a sequence generation module, which generates a preset sequence of preset bits before receiving pseudo-random code PN sequence data sent by the phase self-calibrated digital-to-analog converter chip based on each channel; a supplementation module, which supplements the target position of the preset sequence of preset bits based on preset values ​​to obtain a PN code; and a transmission module, which sends the PN code to the digital-to-analog converter chip.

[0075] Furthermore, the transmitting module includes: a shaping and filtering unit for shaping and filtering the PN code; and a transmitting unit for sending the PN code after shaping and filtering to a digital-to-analog converter chip for up-conversion processing.

[0076] Accordingly, the data receiving module includes: a receiving unit for receiving PN sequence data sent by the digital-to-analog converter chip, wherein the PN sequence data is obtained by the digital-to-analog converter chip performing down-conversion processing on the received PN code; and a matched filtering unit for performing matched filtering on the PN sequence data.

[0077] It should be noted that the phase self-calibration of the digital-to-analog converter (DAC) chip is used to synchronize the local oscillator phase based on the synchronization reference signal and synchronization clock sent by the clock chip. The synchronization reference signal and synchronization clock are obtained by the clock chip based on the received synchronization pulses. Through synchronization, the phase of a single-channel acquisition signal remains unchanged after each power-on, and the phase difference between multiple acquisition signals remains unchanged. Furthermore, after the DAC chip synchronizes the local oscillator phase, it establishes a communication link with the FPGA platform, achieving link synchronization, thus facilitating the transmission of its acquired data to the FPGA platform.

[0078] In an optional embodiment, the device further includes a signal synchronization module that receives a synchronization reference signal and a synchronization clock sent by a clock chip. In this case, the clock chip also sends the synchronization reference signal and the synchronization clock to a digital-to-analog converter chip.

[0079] The frequency offset prediction and compensation module 82 includes: a difference estimation unit, which selects a data sequence of preset length at the beginning and end for the PN sequence data received by a single channel, and obtains the phase difference based on the conjugate algorithm; and a frequency offset estimation unit, which obtains the predicted frequency offset based on the phase difference and the time delay between the previously acquired selected data sequences of preset length at the beginning and end.

[0080] The phase detection module 83 includes: a sliding correlation capture unit, which performs sliding correlation capture on PN sequence compensation data and pre-stored local PN sequence data to obtain peak data; a data acquisition unit, which obtains amplitude data and phase data based on the peak data; a phase estimation unit, which obtains the estimated phase of each channel based on the amplitude data and phase data and using a four-quadrant arctangent algorithm; and a phase prediction unit, which obtains the predicted phase based on the estimated phase of each channel.

[0081] In addition, the phase prediction unit includes a phase prediction subunit, which averages the estimated phases of all channels to obtain the predicted phase, thereby achieving phase estimation with large frequency offset tolerance.

[0082] In an optional embodiment, the device further includes: a phase difference acquisition module, which, after obtaining the predicted phase, obtains the phase difference between adjacent channels based on the estimated phase of each channel after power-on, since the phase offset of each channel is fixed each time; and a phase adjustment module, which updates the predicted phase according to the phase difference to obtain the updated predicted phase.

[0083] In an optional embodiment, a multi-channel signal phase measurement device with high-frequency offset tolerance is also disclosed, including a clock chip, a digital-to-analog converter chip, and an FPGA platform, wherein: the digital-to-analog converter chip performs self-calibration based on the synchronization reference signal and synchronization clock sent by the clock chip, and establishes a communication link with the FPGA platform; the FPGA platform sends the generated PN code to the digital-to-analog converter chip; the digital-to-analog converter chip acquires the PN code, obtains PN sequence data, and returns the PN sequence data to the FPGA platform; the FPGA platform performs frequency offset estimation on the PN sequence data received by each channel to obtain the estimated frequency offset, and uses the estimated frequency offset to compensate the corresponding PN sequence data to obtain the PN sequence compensation data for the corresponding channel; the FPGA platform performs sliding correlation capture on the PN sequence compensation data and the pre-stored local PN sequence data, and combines it with the four-quadrant arctangent algorithm to obtain the predicted phase.

[0084] In summary, this embodiment of the invention corrects the random phase introduced by the randomness of the local oscillation start-up time of the digital-to-analog converter (DAC) chip by receiving PN sequence data after self-calibration. This ensures that the phase of the signal acquired by the DAC chip during repeated power-ups remains consistent, eliminating the need for recalibration each time. Furthermore, by estimating and compensating for the frequency offset of the PN sequence data before phase detection, it is made suitable for high-dynamic scenarios with Doppler interference. This avoids the influence of relative motion or clock bias between the FPGA platform and the DAC chip on the phase detection results, thereby improving phase detection accuracy.

[0085] Figure 9 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 9 As shown, the electronic device may include a processor 91, a communication interface 92, a memory 93, and a communication bus 94. The processor 91, communication interface 92, and memory 93 communicate with each other via the communication bus 94. The processor 91 can call logic instructions in the memory 93 to execute a multi-channel signal phase measurement method with high-frequency bias tolerance. This method includes: receiving pseudo-random code (PN) sequence data sent by a phase-self-calibrated digital-to-analog converter chip for each channel, wherein the PN sequence data is obtained by the digital-to-analog converter chip based on the acquired PN code; estimating the frequency bias of the PN sequence data received for each channel to obtain a predicted frequency bias, and using the predicted frequency bias to compensate the PN sequence data to obtain PN sequence compensation data for the corresponding channel; and performing sliding correlation capture on the PN sequence compensation data of each channel and pre-stored local PN sequence data, combined with a four-quadrant arctangent algorithm, to obtain a predicted phase.

[0086] Furthermore, the logical instructions in the aforementioned memory 93 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0087] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the multi-channel signal phase measurement method with high frequency offset tolerance provided by the above methods. The method includes: receiving pseudo-random code PN sequence data sent by a phase self-calibrated digital-to-analog converter chip for each channel, wherein the PN sequence data is obtained by the digital-to-analog converter chip based on the acquired PN code; estimating the frequency offset of the PN sequence data received for each channel to obtain a predicted frequency offset, and using the predicted frequency offset to compensate the PN sequence data to obtain PN sequence compensation data for the corresponding channel; and performing sliding correlation capture on the PN sequence compensation data and pre-stored local PN sequence data for each channel, and combining it with a four-quadrant arctangent algorithm to obtain a predicted phase.

[0088] In another aspect, the present invention also provides a non-transitory computer-readable storage medium storing a computer program thereon. When executed by a processor, the computer program implements a multi-channel signal phase measurement method with high-frequency offset tolerance provided by the methods described above. The method includes: receiving pseudo-random code PN sequence data sent by a phase self-calibrated digital-to-analog converter chip for each channel, wherein the PN sequence data is obtained by the digital-to-analog converter chip based on the acquired PN code; estimating the frequency offset of the PN sequence data received for each channel to obtain a predicted frequency offset, and compensating the PN sequence data using the predicted frequency offset to obtain PN sequence compensation data for the corresponding channel; and performing sliding correlation capture on the PN sequence compensation data and pre-stored local PN sequence data for each channel, and combining it with a four-quadrant arctangent algorithm to obtain a predicted phase.

[0089] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0090] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0091] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for measuring the phase of a multi-channel signal with high-frequency bias tolerance, characterized in that, include: Based on each channel, pseudo-random code PN sequence data sent by the phase self-calibrated digital-to-analog converter chip is received respectively. The PN sequence data is obtained by the digital-to-analog converter chip based on the acquired PN code. For the PN sequence data received by each channel, frequency offset estimation is performed on the PN sequence data to obtain the estimated frequency offset, and the estimated frequency offset is used to compensate the PN sequence data to obtain the PN sequence compensation data for the corresponding channel. For the PN sequence compensation data of each channel, the PN sequence compensation data and the pre-stored local PN sequence data are subjected to sliding correlation capture, and combined with the four-quadrant arctangent algorithm to obtain the predicted phase; The PN sequence compensation data for each of the aforementioned channels involves performing sliding correlation capture on the PN sequence compensation data and pre-stored local PN sequence data, and combining this with a four-quadrant arctangent algorithm to obtain the predicted phase, including: The peak data is obtained by performing sliding correlation capture on the PN sequence compensation data and the pre-stored local PN sequence data; Based on the peak data, amplitude data and phase data are obtained; Based on the amplitude data and the phase data, and using the four-quadrant arctangent algorithm, the estimated phase of each channel is obtained; The predicted phase is obtained based on the estimated phase of each channel; Based on the estimated phase of each of the aforementioned channels, the predicted phase is obtained, including: The predicted phase is obtained by averaging the estimated phases of all channels.

2. The multi-channel signal phase measurement method with high-frequency bias tolerance according to claim 1, characterized in that, After obtaining the predicted phase, the process includes: Based on the estimated phase of each channel, the phase difference between adjacent channels is obtained; The predicted phase is updated based on the phase difference to obtain the updated predicted phase.

3. The multi-channel signal phase measurement method with high-frequency bias tolerance according to claim 1, characterized in that, The frequency offset estimation of the PN sequence data includes: For PN sequence data received by a single channel, a data sequence of preset lengths at the beginning and end is selected, and the phase difference is obtained based on the conjugate algorithm; The estimated frequency offset is obtained based on the phase difference value and the time delay between the previously acquired selected data sequences of preset lengths.

4. The multi-channel signal phase measurement method with high-frequency bias tolerance according to claim 1, characterized in that, Before receiving the pseudo-random code PN sequence data sent by the phase-self-calibrated digital-to-analog converter chip based on each channel, the process includes: Generate a preset sequence of preset bits; Based on preset values, the target positions of the preset sequence of preset bits are supplemented to obtain the PN code; The PN code is sent to the digital-to-analog converter chip.

5. The multi-channel signal phase measurement method with high-frequency bias tolerance according to claim 4, characterized in that, Sending the PN code to the digital-to-analog converter chip includes: The PN code is subjected to shaping filtering; The PN code, after being shaped and filtered, is sent to the digital-to-analog converter chip for up-conversion processing. The process of receiving pseudo-random code PN sequence data from the phase-self-calibrated digital-to-analog converter chip via each channel includes: The digital-to-analog converter receives PN sequence data sent by the digital-to-analog converter chip, wherein the PN sequence data is obtained by the digital-to-analog converter chip after performing down-conversion processing on the received PN code; The PN sequence data is subjected to matched filtering.

6. The multi-channel signal phase measurement method with high-frequency bias tolerance according to claim 1, characterized in that, The phase self-calibration of the digital-to-analog converter chip is achieved by synchronizing the local oscillator phase based on the synchronization reference signal and synchronization clock sent by the clock chip. The synchronization reference signal and synchronization clock are obtained by the clock chip based on the received synchronization pulse.

7. A multi-channel signal phase measurement device with high-frequency bias tolerance, characterized in that, include: The data receiving module receives pseudo-random code PN sequence data sent by the phase self-calibrated digital-to-analog converter chip through each channel. The PN sequence data is obtained by the digital-to-analog converter chip based on the acquired PN code. The frequency offset prediction and compensation module estimates the frequency offset of the PN sequence data received by each channel to obtain the estimated frequency offset, and uses the estimated frequency offset to compensate the PN sequence data to obtain the PN sequence compensation data for the corresponding channel. The phase detection module performs sliding correlation capture on the PN sequence compensation data and pre-stored local PN sequence data for each channel, and combines it with the four-quadrant arctangent algorithm to obtain the predicted phase. The phase detection module includes: The sliding correlation capture unit performs sliding correlation capture on the PN sequence compensation data and the pre-stored local PN sequence data to obtain peak data; The data acquisition unit obtains amplitude data and phase data based on the peak data; The phase prediction unit obtains the predicted phase of each channel based on the amplitude data and the phase data, using the four-quadrant arctangent algorithm. The phase prediction unit obtains the predicted phase based on the estimated phase of each channel; The phase prediction unit includes: The phase prediction subunit averages the estimated phases of all channels to obtain the predicted phase.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the steps of the multi-channel signal phase measurement method with high-frequency bias tolerance as described in any one of claims 1 to 6.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the multi-channel signal phase measurement method with high-frequency bias tolerance as described in any one of claims 1 to 6.

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