Method and apparatus for controlling communication link, storage medium and electronic device

Abstract

Embodiments of the present application provide a communication link control method and device, a storage medium and an electronic device, wherein the method comprises: in the process that a first server transmits data to a second server through a target chip, performing target electrostatic test on a first communication link between the first server and the target chip to obtain a target test result; obtaining a target reduction frequency included in the target test result; in the case that a preset target abnormal condition is met between the target reduction frequency and a preset reduction frequency threshold, adjusting a transmission rate of the first communication link between the first server and the target chip to a reference transmission rate. Through the embodiments of the present application, the problem of low control efficiency of the communication link is solved, and the effect of improving the control efficiency of the communication link is achieved.

Description

Technical Field

[0001] This application relates to the field of computers, and more specifically, to a method and apparatus for controlling a communication link, a storage medium, and an electronic device. Background Technology

[0002] During electrostatic discharge testing of communication links between servers, a strong electromagnetic field is generated in the space at the moment of electrostatic discharge. This electromagnetic field can interfere with the transmission of high-speed signals, often leading to problems such as reduced transmission speed and server crashes in the communication links between servers.

[0003] In related technologies, reinforced grounding is often used to address issues such as speed reduction and system crashes caused by electromagnetic interference. Reinforced grounding reduces the bridging impedance between server components and between metal parts. However, this method cannot solve the strong interference of the spatial field generated by electrostatic discharge on the communication link, and therefore cannot effectively control the transmission rate of the communication link.

[0004] No effective solution has yet been proposed to address the technical problem of low control efficiency in communication links in related technologies. Summary of the Invention

[0005] This application provides a method and apparatus for controlling a communication link, a storage medium, and an electronic device to at least solve the problem of low control efficiency of communication links in related technologies.

[0006] According to one embodiment of this application, a method for controlling a communication link is provided, comprising: during the process of a first server transmitting data to a second server through a target chip, performing a target electrostatic discharge (ESD) test on a communication link with low control efficiency of a first communication link between the first server and the target chip, and obtaining a target test result, wherein the first communication link is configured to transmit data at a reference transmission rate, and the target test result includes a target reduction number, which is the number of times the transmission rate of the first communication link is lower than the reference transmission rate during the target ESD test of the first communication link; acquiring the target reduction number included in the target test result; and, if a preset target abnormality condition is met between the target reduction number and a preset reduction number threshold, adjusting the transmission rate of the first communication link between the first server and the target chip to the reference transmission rate.

[0007] Optionally, before obtaining the target reduction count included in the target test result, the method further includes: after performing a target electrostatic discharge (ESD) test on the first communication link between the first server and the target chip, reading the value of a first register in the substrate management controller (BMC), wherein the value of the first register represents the target reduction count, and the first register is used to record the number of times the transmission rate of the first communication link is lower than the reference transmission rate during the target ESD test on the first communication link; and determining the target test result as including the target reduction count represented by the read value of the first register.

[0008] Optionally, the method further includes: during the target electrostatic test of the first communication link, detecting whether a level change event occurs, wherein the level change event indicates that the handshake signal between the target chip and the first server switches from a high level to a low level, the handshake signal is used to control the transmission rate of the first communication link, and when the handshake signal is at a high level, the transmission rate of the first communication link is set to the reference transmission rate, and when the handshake signal is at a low level, the transmission rate of the first communication link is set to be lower than the reference transmission rate; wherein the high level is a preset first level, the low level is a preset second level, the first level is greater than the second level, or the high level is a preset first level. The level is within a preset second level range, where the low level is within the first level range and the minimum level within the first level range is greater than the maximum level within the second level range. Upon detecting a level change event, the duration of the handshake signal switching from the high level to the low level is obtained. If the duration satisfies a preset matching condition, it is determined that the transmission rate of the first communication link has been lower than the reference transmission rate once. The value of the first register in the BMC is updated to increase the number of times the transmission rate of the first communication link has been lower than the reference transmission rate by one. The first register is used to record the number of times the transmission rate of the first communication link has been lower than the reference transmission rate during the target electrostatic test of the first communication link.

[0009] Optionally, if a preset target anomaly condition is met between the target reduction number and a preset reduction number threshold, the transmission rate of the first communication link between the first server and the target chip is adjusted to the reference transmission rate. This includes: adjusting the transmission rate between the first server and the target chip to the reference transmission rate if the target reduction number is greater than or equal to the reduction number threshold; or adjusting the transmission rate between the first server and the target chip to the reference transmission rate if the target reduction number is greater than or equal to the reduction number threshold and the N historical reduction numbers included in the N historical test results are all greater than or equal to the reduction number threshold. The N historical test results include the test results obtained from N electrostatic discharge tests performed on the first communication link before the target electrostatic discharge test. The N electrostatic discharge tests and the target electrostatic discharge test are N+1 consecutive electrostatic discharge tests, where N is a positive integer greater than or equal to 1.

[0010] Optionally, adjusting the transmission rate of the first communication link between the first server and the target chip to the reference transmission rate includes: obtaining an adjustment instruction sent by the BMC to the target chip, wherein the adjustment instruction is used to adjust the value of a second register in the target chip, and the value of the second register is used to control the handshake signal between the target chip and the first server; responding to the adjustment instruction, controlling the target chip to adjust the value of the second register from a first value to a second value, wherein when the value of the second register is the first value, the handshake signal is set to a low level, and when the value of the second register is the second value, the handshake signal is set to a high level.

[0011] Optionally, when a first voltage is applied to the first test position of the high-speed serial computer expansion bus standard PCIe connector where the target chip is located, the first test position is discharged a first preset number of times within a first test duration; and when a second voltage is applied to the first test position, the first test position is discharged a second preset number of times within a second test duration, wherein the first voltage is a positive voltage and the second voltage is a negative voltage; and / or when a third voltage is applied to the second test position of the communication cable carrying the first communication link, the second test position is discharged a third preset number of times within a third test duration; and when a fourth voltage is applied to the second test position, the second test position is discharged a fourth preset number of times within a fourth test duration, wherein the third voltage is a positive voltage and the fourth voltage is a negative voltage.

[0012] Optionally, the method further includes: if the target abnormality condition is met between the target reduction number and the reduction number threshold, adjusting the transmission rate of the second communication link between the second server and the target chip to the reference transmission rate.

[0013] According to another embodiment of this application, a control device for a communication link is provided, comprising: a testing module, configured to perform a target electrostatic discharge (ESD) test on a first communication link between the first server and the target chip during the process of a first server transmitting data to a second server via a target chip, and obtain a target test result, wherein the first communication link is configured to transmit data at a reference transmission rate, and the target test result includes a target reduction number, which is the number of times the transmission rate of the first communication link is lower than the reference transmission rate during the target ESD test; a first acquisition module, configured to acquire the target reduction number included in the target test result; and a first adjustment module, configured to adjust the transmission rate of the first communication link between the first server and the target chip to the reference transmission rate when a preset target abnormality condition is met between the target reduction number and a preset reduction number threshold.

[0014] According to yet another embodiment of this application, a computer-readable storage medium is also provided, wherein a computer program is stored in the computer program, and the computer program is configured to execute the steps in any of the above-described embodiments of the communication link control method when it is run.

[0015] According to yet another embodiment of this application, an electronic device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform the steps in any of the above-described embodiments of the communication link control method.

[0016] Through the embodiments of this application, when the number of times the transmission rate of the communication link is lower than the reference transmission rate meets a preset abnormal condition, it can be indicated that the frequent reduction in the transmission rate of the communication link may be caused by electrostatic testing. In such cases, the transmission rate of the communication link is automatically adjusted to the reference transmission rate before the rate reduction. Therefore, the problem of low control efficiency of the communication link can be solved, thereby improving the control efficiency of the communication link. Attached Figure Description

[0017] Figure 1 This is a hardware structure block diagram of a mobile terminal for a communication link control method according to an embodiment of this application;

[0018] Figure 2This is a flowchart of a communication link control method according to an embodiment of this application;

[0019] Figure 3 This is a schematic diagram illustrating an optional CPU server and GPU server connection according to an embodiment of this application;

[0020] Figure 4 This is a schematic diagram illustrating the connection between an optional target chip and a first server and a second server according to an embodiment of this application;

[0021] Figure 5 This is a schematic diagram of discharge in an optional electrostatic test according to an embodiment of this application;

[0022] Figure 6 This is a schematic diagram of an optional contact discharge current waveform according to an embodiment of this application;

[0023] Figure 7 This is a schematic diagram of an optional communication link control method according to an embodiment of this application;

[0024] Figure 8 This is a structural block diagram of a control device for a communication link according to an embodiment of this application. Detailed Implementation

[0025] The embodiments of this application will be described in detail below with reference to the accompanying drawings and examples.

[0026] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of the embodiments of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0027] The methods and embodiments provided in this application can be executed on a mobile terminal, computer terminal, or similar computing device. Taking running on a mobile terminal as an example, Figure 1 This is a hardware structure block diagram of a mobile terminal for a communication link control method according to an embodiment of this application. Figure 1 As shown, a mobile terminal may include one or more ( Figure 1 Only one is shown in the diagram. A processor 102 (which may include, but is not limited to, a microprocessor MCU or a programmable logic device FPGA, etc.) and a memory 104 for storing data are also shown. The mobile terminal may further include a transmission device 106 for communication functions and an input / output device 108. Those skilled in the art will understand that... Figure 1 The structure shown is for illustrative purposes only and does not limit the structure of the mobile terminal described above. For example, the mobile terminal may also include components that are more... Figure 1 The more or fewer components shown, or having the same Figure 1The different configurations shown.

[0028] The memory 104 can be used to store computer programs, such as application software programs and modules, like the computer program corresponding to the communication link control method in this embodiment. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, thus implementing the aforementioned method. The memory 104 may include high-speed random access memory and non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor 102, and these remote memories can be connected to the mobile terminal via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0029] The transmission device 106 is used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by the mobile terminal's communication provider. In one example, the transmission device 106 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 106 may be a Radio Frequency (RF) module used for wireless communication with the Internet.

[0030] This embodiment provides a control method for the communication link operating on the aforementioned mobile terminal. Figure 2 This is a flowchart of a communication link control method according to an embodiment of this application, such as... Figure 2 As shown, the process includes the following steps:

[0031] Step S202: During the process of the first server transmitting data to the second server through the target chip, a target electrostatic discharge test is performed on the first communication link between the first server and the target chip to obtain the target test result. The first communication link is set to transmit data at a reference transmission rate. The target test result includes the number of target reductions, which is the number of times the transmission rate of the first communication link is lower than the reference transmission rate during the target electrostatic discharge test.

[0032] Step S204: Obtain the target reduction count, which is included in the target test results;

[0033] Step S206: If the preset target abnormality condition is met between the target reduction number and the preset reduction number threshold, the transmission rate of the first communication link between the first server and the target chip is adjusted to the reference transmission rate.

[0034] By following the steps described above, if the number of times the communication link's transmission rate falls below the reference transmission rate meets the preset abnormal conditions, it indicates that electrostatic discharge (ESD) testing may be causing the frequent drops in the communication link's transmission rate. In such cases, the communication link's transmission rate is automatically adjusted back to the reference transmission rate before the rate reduction. Therefore, the problem of low control efficiency in the communication link can be solved, thereby improving the control efficiency of the communication link.

[0035] The entity performing the above steps can be a terminal, but is not limited to this.

[0036] In the technical solution provided in step S202 above, with the development of the field of artificial intelligence, the data processing behind artificial intelligence is increasingly testing the data processing capabilities of AI (Artificial Intelligence) servers in data centers. The collection and organization of various data in fields such as big data, cloud computing, and artificial intelligence require AI servers of various heterogeneous forms. The extensive application of computing units satisfies the server's ability to perform intensive data operations. In order to improve the diversity of server resource configuration, improve energy utilization, and reduce economic costs, AI servers may include, but are not limited to, a first server and a second server connected by high-speed interconnect cables of a target communication protocol, with the first server and the second server cascaded. More specifically, AI servers may exist in the data center's server room in a combination of a first server and a second server, but are not limited to. For example, the first and second servers can be connected via, but are not limited to, PCIe (Peripheral Component Interconnect Express) 5.0 super-high-speed interconnect cables or PCIe 4.0 high-speed interconnect cables. Optionally, the first server can be, but is limited to, a server providing processor resources, and the second server can be, but is limited to, a server providing computing power resources. The first server can be, but is not limited to, a CPU (Central Processing Unit) server, and the second server can be, but is limited to, a GPU (Graphics Processing Unit) server. In this case, the specific form of the AI ​​server is a CPU server cascaded with a GPU server. This cascading method can maximize the optimization of the AI ​​server configuration.

[0037] In this embodiment, the first server is a CPU server and the second server is a GPU server, as an example. Figure 3 This is a schematic diagram illustrating an optional CPU server and GPU server connection according to an embodiment of this application, as shown below. Figure 3 As shown, the CPU server includes PCIe interfaces 1 to 8, and the GPU server includes PCIe interfaces 1 to 8. The CPU server's PCIe interfaces 1 to 8 are connected to the GPU server's PCIe interfaces 1 to 8, respectively. The connection method can be, but is not limited to, using high-speed interconnect cables. The communication protocol is PCIe 5.0. PCIe is a bus standard. A bus is a common communication trunk for transmitting information between computer components, providing data transmission and control logic to each component in a general way. In the PCIe standard, the line used to transmit data is called a "lane." ×1 indicates that the interface has one PCIe lane, ×4 indicates four lanes, and so on; each lane has the same speed and can be stacked. The GPU server has indicator lights 1 to 8. Under normal conditions or when the PCIe communication link does not experience a speed reduction, the indicator lights will be constantly lit, and the indicator lights can be, but are not limited to, green. When the transmission bandwidth of the PCIe link decreases, the status indicator lights change from constantly lit to flashing at a frequency of 2Hz.

[0038] Optionally, in this embodiment, the CPU of the data processing center of the first server is connected to the PCIe interface of the second server via a high-speed interconnect cable. Since the high-speed interconnect cable is relatively long and cannot guarantee signal integrity, signal integrity can be achieved, but is not limited to, through a target chip. The target chip can be, but is not limited to, a Retimer chip, etc. Figure 4 This is a schematic diagram illustrating the connection between an optional target chip and a first server and a second server according to an embodiment of this application, as shown below. Figure 4 As shown, the CPU server is connected to the Retimer chip, and the Retimer chip is connected to the GPU server through the PCIe interface, which realizes the signal integrity of the PCIe 5.0 protocol. The PCIe 5.0 is ultimately connected to the GPU server.

[0039] Optionally, in this embodiment, the transmission rate of the communication link may include, but is not limited to, the communication link bandwidth, the communication protocol used by the communication link, etc. On the PCIe communication link, the main point of interference from electrostatic discharge (ESD) is the Retimer chip. When this chip is interfered with, the communication bandwidth will be reduced to ensure the normal operation of the communication link; for example, from PCIe 5.0 to PCIe 4.0. However, the communication bandwidth of PCIe 4.0 is only half the performance of PCIe 5.0, i.e., 64GB / s. It is understandable that the PCIe communication link (equivalent to the first communication link) may experience a speed reduction problem during ESD testing, for example, the communication protocol may be reduced from PCIe 5.0 to PCIe 4.0. Since the communication link bandwidth of PCIe 4.0 reaches 16Gb / s, while the communication bandwidth of PCIe x16 is 64GB / s, such performance degradation is generally unacceptable.

[0040] In one exemplary embodiment, a target electrostatic discharge test can be performed on the first communication link between the first server and the target chip in the following manner, but not limited to: when a first voltage is applied to a first test position on the high-speed serial computer expansion bus standard PCIe connector where the target chip is located, the first test position is discharged a first preset number of times within a first test duration; and when a second voltage is applied to the first test position, the first test position is discharged a second preset number of times within a second test duration, wherein the first voltage is a positive voltage and the second voltage is a negative voltage; and / or when a third voltage is applied to a second test position on the communication cable carrying the first communication link, the second test position is discharged a third preset number of times within a third test duration; and when a fourth voltage is applied to the second test position, the second test position is discharged a fourth preset number of times within a fourth test duration, wherein the third voltage is a positive voltage and the fourth voltage is a negative voltage.

[0041] Optionally, in this embodiment, the target electrostatic test may include, but is not limited to, contact discharge and air discharge methods. Contact discharge primarily targets areas that the user's fingers can directly touch when using the device. Air discharge primarily tests the insulation of the device.

[0042] Optionally, in this embodiment, in the PCIE communication link, the PCIE high-speed interconnect cable (equivalent to a communication cable) is wrapped with a braided shield, with a braiding density controlled at over 90%. The shield is wrapped with a nylon mesh, which can, but is not limited to, an air discharge mode for electrostatic discharge of the high-speed interconnect cable. The third test duration can, but is not limited to, be the same as or different from the fourth test duration. The voltage values ​​of the third and fourth voltages can, but are not limited to, be the same. For example, both the third and fourth voltage values ​​can be preset voltage values, such as 8KV, in which case the third voltage is positive 8KV (positive polarity) and the fourth voltage is negative 8KV (negative polarity). During electrostatic discharge testing, a positive or negative electrostatic discharge can be performed at the second test position on the communication cable every preset time interval (e.g., 1 second, 2 seconds, etc.). The third and fourth preset number of discharges can, but are not limited to, be the same or different, for example, 25 discharges for each polarity.

[0043] Optionally, in this embodiment, the voltage values ​​of the first voltage and the second voltage may be the same or different, the first preset number of tests and the second preset number of tests may be the same or different, and the first test duration may be the same or different from the second test duration. During electrostatic discharge testing, a positive or negative electrostatic discharge may be performed at the first test position on the PCIe connector where the target chip is located every preset time interval (e.g., 1 second, 2 seconds, etc.). The voltage values ​​of the first voltage and the second voltage may be the same, for example, if both the first and second voltages are 4KV, then the first voltage is positive 4KV (positive polarity) and the second voltage is negative 4KV (negative polarity). During the electrostatic discharge test, 30 positive and 30 negative discharges may be performed at the first test position.

[0044] Figure 5 This is a schematic diagram of discharge in an optional electrostatic test according to an embodiment of this application, such as... Figure 5 As shown, electrostatic discharge (ESD) testing can be performed on the first communication link between the first server and the second server within 60 seconds, but is not limited to. During the ESD testing, positive or negative ESD discharge can be performed once every 1 second at the first test position on the PCIe connector where the target chip is located. The first voltage is positive 4KV (positive polarity) and the second voltage is negative 4KV (negative polarity), that is, the voltage values ​​of the second voltage and the first voltage are 4kV. Figure 6 This is a schematic diagram of an optional contact discharge current waveform according to an embodiment of this application, such as... Figure 6As shown, during the electrostatic discharge test, a strong electromagnetic field is formed in the space at the instant of electrostatic discharge. The waveform of the current can be, but is not limited to, a rapid increase followed by a rapid decrease, then a slow increase followed by a slow decrease.

[0045] In the technical solution provided in step S204 above, the target test result can be obtained, but is not limited to, the number of times the transmission rate of the first communication link is lower than the reference transmission rate during the target electrostatic test of the first communication link. For example, the reference transmission rate is the transmission rate corresponding to PCIe 5.0. Thus, the number of times the target reduction occurs can be, but is not limited to, the number of times the transmission rate of the first communication link is lower than the transmission rate corresponding to PCIe 5.0 during the target electrostatic test.

[0046] In one exemplary embodiment, the target test result may be obtained, but is not limited to, by the following method: after performing a target electrostatic discharge (ESD) test on the first communication link between the first server and the target chip, the value of a first register in the substrate management controller (BMC) is read, wherein the value of the first register represents the number of target reductions, and the first register is used to record the number of times the transmission rate of the first communication link is lower than the reference transmission rate during the target ESD test on the first communication link; the target test result is determined to include the number of target reductions represented by the read value of the first register.

[0047] Optionally, in this embodiment, the first register in the Baseboard Management Controller (BMC) can be obtained through the address of the first register, and the value of the first register can be obtained. For example, the address of the first register can be, but is not limited to, 0x22.

[0048] Optionally, in this embodiment, the value of the first register may be, but is not limited to, the number of times the transmission rate of the first communication link is lower than the reference transmission rate during the electrostatic test.

[0049] In an exemplary embodiment, the method further includes: during the target electrostatic test of the first communication link, detecting whether a level change event occurs, wherein the level change event indicates that the handshake signal between the target chip and the first server switches from a high level to a low level, the handshake signal is used to control the transmission rate of the first communication link, wherein when the handshake signal is at the high level, the transmission rate of the first communication link is set to the reference transmission rate, and when the handshake signal is at the low level, the transmission rate of the first communication link is set to be lower than the reference transmission rate; wherein the high level is a preset first level, the low level is a preset second level, the first level is greater than the second level, or the high level is a preset third level. The first communication link is defined as follows: a level within a certain level range, wherein the low level is a level within a preset second level range, and the minimum level within the first level range is greater than the maximum level within the second level range; upon detecting a level change event, the duration of the handshake signal switching from the high level to the low level is obtained; if the duration satisfies a preset matching condition, it is determined that the transmission rate of the first communication link has been lower than the reference transmission rate; the value of the first register in the BMC is updated to increase the number of times the transmission rate of the first communication link has been lower than the reference transmission rate by one, wherein the first register is used to record the number of times the transmission rate of the first communication link has been lower than the reference transmission rate during the target electrostatic test of the first communication link.

[0050] Optionally, in this embodiment, if the duration of the handshake signal after switching from high level to low level is greater than or equal to a preset duration threshold, or if the duration of the handshake signal after switching from high level to low level is less than the preset duration threshold and the difference between the duration of the handshake signal after switching from high level to low level and the preset duration threshold is less than or equal to the difference threshold, it is determined that the transmission rate of the first communication link is lower than the reference transmission rate.

[0051] Optionally, in this embodiment, when a level change event is detected, the duration of the handshake signal switching from high level to low level is obtained; if the duration does not meet the preset matching conditions, it is determined that the transmission rate of the first communication link is not lower than the reference transmission rate. In this way, the accuracy of the first communication link's transmission rate being lower than the reference transmission rate is improved.

[0052] Optionally, in this embodiment, the method further includes: during the target electrostatic test of the first communication link, detecting whether a level change event occurs, wherein the level change event indicates that the handshake signal between the target chip and the first server switches from a high level to a low level, the handshake signal is used to control the transmission rate of the first communication link, and when the handshake signal is at a high level, the transmission rate of the first communication link is set to the reference transmission rate, and when the handshake signal is at a low level, the transmission rate of the first communication link is set to be lower than the reference transmission rate; wherein the high level is a preset first level, the low level is a preset second level, the first level is greater than the second level, or the high level is within a preset first level range, and the low level is within a preset second level range. The minimum level within the first level range is greater than the maximum level within the second level range; when P consecutive level change events are detected, the duration of the handshake signal switching from the high level to the low level in each of the P level change events is obtained, resulting in P durations, where P is a positive integer greater than or equal to 2; if all P durations satisfy a preset matching condition, it is determined that the transmission rate of the first communication link is lower than the reference transmission rate once; the value of the first register in the BMC is updated to increase the number of times the transmission rate of the first communication link is lower than the reference transmission rate by one, wherein the first register is used to record the number of times the transmission rate of the first communication link is lower than the reference transmission rate during the target electrostatic test of the first communication link.

[0053] Optionally, in this embodiment, the method further includes: during the target electrostatic test of the first communication link, detecting whether a level change event occurs, wherein the level change event indicates that the handshake signal between the target chip and the first server switches from a high level to a low level, the handshake signal is used to control the transmission rate of the first communication link, and when the handshake signal is at a high level, the transmission rate of the first communication link is set to the reference transmission rate, and when the handshake signal is at a low level, the transmission rate of the first communication link is set to be lower than the reference transmission rate; wherein the high level is a preset first level, the low level is a preset second level, the first level is greater than the second level, or the high level is within a preset first level range, and the low level is within a preset second level range. The minimum level within the first level range is greater than the maximum level within the second level range; when P consecutive level change events are detected, the duration of the handshake signal switching from the high level to the low level in each of the P level change events is obtained, resulting in P durations, where P is a positive integer greater than or equal to 2; when all P durations satisfy a preset matching condition, it is determined that the transmission rate of the first communication link is lower than the reference transmission rate P times; the value of the first register in the BMC is updated to increase the number of times the transmission rate of the first communication link is lower than the reference transmission rate by P times, wherein the first register is used to record the number of times the transmission rate of the first communication link is lower than the reference transmission rate during the target electrostatic test of the first communication link.

[0054] In the technical solution provided in step S206 above, if the preset target abnormality condition is met between the target reduction number and the preset reduction number threshold, it can be indicated that the reduction in the transmission rate of the first communication link is caused by electrostatic discharge (ESD) testing. In this case, the transmission rate of the first communication link between the first server and the target chip can be automatically adjusted to the reference transmission rate, but is not limited to automatic adjustment. In this way, intelligent identification of the speed reduction event generated by the server during ESD testing is achieved. After confirming the speed reduction event, the transmission rate (e.g., transmission bandwidth) of the PCIe communication link can be automatically restored. On the one hand, this improves the success rate of the server passing ESD testing; on the other hand, it ensures the normal operation of the server in a real data center environment, avoiding performance degradation due to ESD issues and improving the stability of server performance.

[0055] In one exemplary embodiment, the transmission rate of the first communication link between the first server and the target chip can be adjusted to a reference transmission rate in, but is not limited to, the following ways: If the number of target reductions is greater than or equal to the reduction number threshold, the transmission rate between the first server and the target chip is adjusted to the reference transmission rate; or if the number of target reductions is greater than or equal to the reduction number threshold, and the number of reductions in the N historical test results is greater than or equal to the reduction number threshold, the transmission rate between the first server and the target chip is adjusted to the reference transmission rate, wherein the N historical test results include test results obtained from N electrostatic tests performed on the first communication link before the target electrostatic test, and the N electrostatic tests and the target electrostatic test are N+1 consecutive electrostatic tests, where N is a positive integer greater than or equal to 1.

[0056] Optionally, in this embodiment, before performing the target electrostatic discharge test, the first communication link may be subjected to N historical electrostatic discharge tests, resulting in N historical test results. The N historical electrostatic discharge tests and the target electrostatic discharge test are performed consecutively. One of the N historical reduction counts may be, but is not limited to, the number of times the transmission rate of the first communication link is lower than the reference transmission rate during one historical electrostatic discharge test of the first communication link.

[0057] Optionally, in this embodiment, it can be understood that, in cases where the target reduction number is greater than or equal to the reduction number threshold, and the N historical reduction numbers included in the N historical test results are all greater than or equal to the reduction number threshold, the number of times the transmission rate of the first communication link is lower than the reference transmission rate in each of the multiple electrostatic discharge tests performed on the first communication link is greater than or equal to the reduction number threshold. In this way, the results of multiple electrostatic discharge tests are used to determine whether the preset target abnormal conditions are met, thereby improving the accuracy of the transmission rate of the first communication link between the first server and the target chip.

[0058] In one exemplary embodiment, the transmission rate of the first communication link between the first server and the target chip can be adjusted to a reference transmission rate by, but is not limited to, the following: obtaining an adjustment instruction sent by the BMC to the target chip, wherein the adjustment instruction is used to adjust the value of a second register in the target chip, the value of the second register being used to control the handshake signal between the target chip and the first server; responding to the adjustment instruction, controlling the target chip to adjust the value of the second register from a first value to a second value, wherein when the value of the second register is the first value, the handshake signal is set to a low level, and when the value of the second register is the second value, the handshake signal is set to a high level.

[0059] Optionally, in this embodiment, the second register in the target chip can be accessed through the register address of the second register, for example, the register address of the second register is 0x00, and the first value and the second value can be, but are not limited to, preset values, for example, the first value is 0x02, the second value is 0x0, etc.

[0060] In one exemplary embodiment, the method further includes: if the target abnormality condition is met between the target reduction number and the reduction number threshold, adjusting the transmission rate of the second communication link between the second server and the target chip to the reference transmission rate.

[0061] Optionally, in this embodiment, the transmission rate of the second communication link between the second server and the target chip can be adjusted to a reference transmission rate in the following ways, but not limited to: obtaining a switching instruction sent by the BMC to the second server, wherein the switching instruction is used to adjust the transmission rate of the second communication link between the target chip and the second server to a reference transmission rate; responding to the switching instruction, controlling the handshake signal between the second server and the target chip to switch from a low level to a high level, wherein the high level is a preset third level, the low level is a preset fourth level, the third level is greater than the fourth level, or the high level is a level within a preset third level range, the low level is a level within a preset fourth level range, the minimum level within the third level range is greater than the maximum level within the fourth level range. When the handshake signal between the second server and the target chip is at a high level, the transmission rate of the second communication link is set to the reference transmission rate; when the handshake signal between the second server and the target chip is at a low level, the transmission rate of the second communication link is set to a rate lower than the reference transmission rate.

[0062] To better understand the communication link control method in the embodiments of this application, the following explanation and description of the communication link control method in the embodiments of this application will be provided in conjunction with optional embodiments, which may be applied to, but are not limited to, the embodiments of this application.

[0063] The target chip's pins are connected to the first server's pins to form a handshake mechanism. For example, the Retimer chip's FJ6 pin (GPIO0 pin) is connected to the CPU's 1086 pin (GPIO pin) to form a handshake mechanism. The handshake is successful when the Retimer chip's FJ6 pin (GPIO0 pin) remains high. A high handshake signal corresponds to the PCIe 5.0 transfer rate (equivalent to a reference transfer rate). A low handshake signal corresponds to the PCIe 4.0 transfer rate.

[0064] Figure 7 This is a schematic diagram of an optional communication link control method according to an embodiment of this application, such as... Figure 7 As shown, the communication link control method of this application embodiment can be implemented through, but is not limited to, the following steps:

[0065] Step S701: Perform an electrostatic test.

[0066] Step S702: Determine if a speed reduction has occurred, specifically whether the communication link between the Retimer chip and the CPU server has experienced a speed reduction. In detail, the handshake signal between the Retimer chip and the CPU server may be interrupted (i.e., a high-level output interruption; if there is no high-level output during the handshake connection, it will become a low level 0V). If the duration of the interruption exceeds a threshold (e.g., 1500ms), the PCIe communication link between the Retimer chip and the CPU server will be reduced to PCIe 4.0. In this case, it can be confirmed that the transmission rate of the first communication link has been lower than the reference transmission rate, and the indicator light deployed on the GPU server will flash. If no speed reduction is confirmed, the indicator light deployed on the GPU server will remain constantly lit.

[0067] In step S703, the BMC continuously detects whether the number of reset actions has reached 30 times within 60 seconds. If it has reached 30 times, step S704 is executed; otherwise, step S705 is executed.

[0068] Step S704: The PCIe link speed reduction is determined to be caused by electrostatic discharge (ESD) testing. Specifically, if the ESD test does not stop, this reset action will repeat multiple times. The ESD test will complete within 50 seconds. If the BMC detects 30 such reset actions within 60 seconds (calculated from the first restoration of the PCIe 5.0 connection between the Retimer chip and the CPU), it can be determined that the PCIe communication link speed reduction is caused by ESD testing. In this case, step S706 is executed.

[0069] Step S705: Feedback information to the CPU server for communication exception handling.

[0070] In step S706, the Retimer chip restores the PCIe link communication speed to PCIe 5.0. Specifically, after 50 seconds, the GPU server and the Retimer chip, as well as the Retimer chip and the CPU server, will be reconnected to PCIe 5.0.

[0071] The Retimer chip's internal register (equivalent to a second register) assigns a value based on the handshake signal. The register address can be, but is not limited to, 0x00. When the level is high, the register value can be, but is not limited to, 0x01; when the level is low, the register value can be, but is not limited to, 0x02. Simultaneously, the handshake signal is connected to the 568-pin (GPIO pin) of the BMC control chip via a voltage divider resistor. When the level of the BMC chip's 568-pin changes from high to low, it can be understood that after the connection between the Retimer chip and the CPU chip changes from PCIe 5.0 to PCIe 4.0, it requires the PCIe connection between the Retimer and the CPU to be reconnected to PCIe 5.0.

[0072] The specific implementation process is as follows: The GPIO pin 569 of the BMC chip is connected to the GPIO pin FJ7 of the Retimer chip, and the GPIO pin 570 of the BMC chip is connected to the GPIO pin 1087 of the CPU. When the BMC chip performs a high-to-low and then-high transition for pins 569 and 570, the PCIe interconnect between the Retimer chip and the CPU is reset to PCIe 5.0. Simultaneously, the value of the BMC internal register (equivalent to the first register), at register address 0x22, begins to accumulate.

[0073] The BMC chip's GPIO pin 571 is connected to the GPU's GPIO pin 878. When the BMC chip performs a high-to-low and then-high transition on pin 571, the PCIe interconnect between the Retimer chip and the GPU server resets to PCIe 5.0. This is to ensure the correctness and stability of the entire communication link. After the PCIe communication link is restored to PCIe 5.0, the status indicator light on the GPU server returns to a constant on state.

[0074] Through the above steps, on the one hand, when the AI ​​server experiences interconnect speed reduction during electrostatic discharge testing, the automatic recovery to PCIe 5.0 communication protocol can be adjusted by setting a Retimer chip on the CPU server, thereby improving the recovery efficiency of the communication link. On the other hand, when interconnect speed reduction occurs during electrostatic discharge testing of the AI ​​server, the indicator light below the interconnect interface can indicate to the end user whether there is a speed reduction problem, thus improving the user experience.

[0075] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solutions of the embodiments of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0076] This embodiment also provides a communication link control device for implementing the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0077] Figure 8 This is a structural block diagram of a control device for a communication link according to an embodiment of this application, such as... Figure 8 As shown, the device includes:

[0078] Test module 802 is used to perform a target electrostatic discharge test on a first communication link between the first server and the target chip during the process of the first server transmitting data to the second server through the target chip, and obtain a target test result. The first communication link is set to transmit data at a reference transmission rate. The target test result includes the number of target reductions, which is the number of times the transmission rate of the first communication link is lower than the reference transmission rate during the target electrostatic discharge test of the first communication link.

[0079] The first acquisition module 804 is used to acquire the number of times the target was reduced, which is included in the target test results;

[0080] The first adjustment module 806 is used to adjust the transmission rate of the first communication link between the first server and the target chip to the reference transmission rate when the preset target abnormality condition is met between the target reduction number and the preset reduction number threshold.

[0081] Optionally, the device further includes:

[0082] The reading module is configured to read the value of a first register in the substrate management controller (BMC) after performing a target electrostatic discharge (ESD) test on the first communication link between the first server and the target chip, before obtaining the target reduction count included in the target test results. The value of the first register represents the target reduction count, and the first register is used to record the number of times the transmission rate of the first communication link is lower than the reference transmission rate during the target ESD test on the first communication link.

[0083] The first determining module is used to determine the target test result as including the number of times the target is reduced, represented by the value of the first register read.

[0084] Optionally, the device further includes:

[0085] The detection module is used to detect whether a level change event occurs during the target electrostatic test of the first communication link. The level change event indicates that the handshake signal between the target chip and the first server switches from a high level to a low level. The handshake signal controls the transmission rate of the first communication link. When the handshake signal is at a high level, the transmission rate of the first communication link is set to a reference transmission rate; when the handshake signal is at a low level, the transmission rate of the first communication link is set to a level lower than the reference transmission rate. The high level is a preset first level, and the low level is a preset second level, where the first level is greater than the second level. Alternatively, the high level is within a preset first level range, and the low level is within a preset second level range, where the minimum level within the first level range is greater than the maximum level within the second level range.

[0086] The second acquisition module is used to acquire the duration of the handshake signal after it switches from the high level to the low level when the level change event is detected;

[0087] The second determining module is used to determine, when the duration meets the preset matching conditions, that there has been a time when the transmission rate of the first communication link is lower than the reference transmission rate.

[0088] An update module is used to update the value of the first register in the BMC to increase the number of times the transmission rate of the first communication link is lower than the reference transmission rate by one. The first register is used to record the number of times the transmission rate of the first communication link is lower than the reference transmission rate during the target electrostatic test of the first communication link.

[0089] Optionally, the first adjustment module includes:

[0090] The first adjustment unit is configured to adjust the transmission rate between the first server and the target chip to the reference transmission rate when the target reduction number is greater than or equal to the reduction number threshold; or

[0091] The second adjustment unit is configured to adjust the transmission rate between the first server and the target chip to the reference transmission rate when the target reduction number is greater than or equal to the reduction number threshold and the N historical test results include N historical reduction numbers that are all greater than or equal to the reduction number threshold. The N historical test results include test results obtained from N electrostatic tests performed on the first communication link before the target electrostatic test. The N electrostatic tests and the target electrostatic test are N+1 consecutive electrostatic tests, where N is a positive integer greater than or equal to 1.

[0092] Optionally, the first adjustment module includes:

[0093] The acquisition unit is used to acquire the adjustment instruction sent by the BMC to the target chip, wherein the adjustment instruction is used to adjust the value of the second register in the target chip, and the value of the second register is used to control the handshake signal between the target chip and the first server.

[0094] The control unit is configured to respond to the adjustment command and control the target chip to adjust the value of the second register from a first value to a second value, wherein when the value of the second register is the first value, the handshake signal is set to a low level, and when the value of the second register is the second value, the handshake signal is set to a high level.

[0095] Optionally, the test module includes:

[0096] The first test unit, when a first voltage is applied to a first test position on the high-speed serial computer expansion bus standard PCIe connector where the target chip is located, discharges the first test position a first preset number of times within a first test duration; and when a second voltage is applied to the first test position, discharges the first test position a second preset number of times within a second test duration, wherein the first voltage is a positive voltage and the second voltage is a negative voltage; and / or

[0097] The second test unit, when a third voltage is applied to a second test position on the communication cable carrying the first communication link, discharges the second test position a third preset number of times within a third test duration, and when a fourth voltage is applied to the second test position, discharges the second test position a fourth preset number of times within a fourth test duration, wherein the third voltage is a positive voltage and the fourth voltage is a negative voltage.

[0098] Optionally, the device further includes:

[0099] The second adjustment module is used to adjust the transmission rate of the second communication link between the second server and the target chip to the reference transmission rate when the target abnormal condition is met between the target reduction number and the reduction number threshold.

[0100] It should be noted that the above modules can be implemented by software or hardware. For the latter, they can be implemented in the following ways, but are not limited to: all the above modules are located in the same processor; or, the above modules are located in different processors in any combination.

[0101] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above method embodiments when run.

[0102] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0103] Embodiments of this application also provide an electronic device including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0104] In one exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0105] Specific examples in this embodiment can be found in the examples described in the above embodiments and exemplary implementations, and will not be repeated here.

[0106] Obviously, those skilled in the art should understand that the modules or steps of the embodiments of this application described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented here, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, the embodiments of this application are not limited to any particular combination of hardware and software.

[0107] The above description is merely a preferred embodiment of this application and is not intended to limit the embodiments of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the principles of the embodiments of this application should be included within the protection scope of the embodiments of this application.

Claims

1. A control method for a communication link, characterized in that, include: During the process of the first server transmitting data to the second server through the target chip, a target electrostatic discharge (ESD) test is performed on the first communication link between the first server and the target chip to obtain the target test result. The first communication link is set to transmit data at a reference transmission rate. The target test result includes the number of target reductions, which is the number of times the transmission rate of the first communication link is lower than the reference transmission rate during the ESD test. The number of times the target was reduced is included in the target test results; If a preset target anomaly condition is met between the target reduction number and the preset reduction number threshold, the transmission rate of the first communication link between the first server and the target chip is adjusted to the reference transmission rate.

2. The method according to claim 1, characterized in that, Before obtaining the target reduction count included in the target test results, the method further includes: After performing a target electrostatic discharge (ESD) test on the first communication link between the first server and the target chip, the value of the first register in the substrate management controller (BMC) is read. The value of the first register represents the number of times the target reduction occurs. The first register is used to record the number of times the transmission rate of the first communication link is lower than the reference transmission rate during the target ESD test on the first communication link. The target test result is determined as the number of times the target is reduced, including the value read from the first register.

3. The method according to claim 1, characterized in that, The method further includes: During the electrostatic discharge test of the first communication link, a level change event is detected. This level change event indicates that the handshake signal between the target chip and the first server has switched from a high level to a low level. The handshake signal controls the transmission rate of the first communication link. When the handshake signal is at a high level, the transmission rate of the first communication link is set to a reference transmission rate. When the handshake signal is at a low level, the transmission rate of the first communication link is set to a level lower than the reference transmission rate. The high level is a preset first level, and the low level is a preset second level, where the first level is greater than the second level. Alternatively, the high level is within a preset first level range, and the low level is within a preset second level range, where the minimum level within the first level range is greater than the maximum level within the second level range. In the event of detecting the level change event, the duration of the handshake signal after it switches from the high level to the low level is obtained; If the duration meets the preset matching conditions, it is determined that there has been a time when the transmission rate of the first communication link is lower than the reference transmission rate. The value of the first register in the BMC is updated to increase the number of times the transmission rate of the first communication link is lower than the reference transmission rate by one. The first register is used to record the number of times the transmission rate of the first communication link is lower than the reference transmission rate during the target electrostatic test of the first communication link.

4. The method according to claim 1, characterized in that, If a preset target anomaly condition is met between the target reduction number and a preset reduction number threshold, the transmission rate of the first communication link between the first server and the target chip is adjusted to the reference transmission rate, including: If the number of reductions is greater than or equal to the reduction threshold, the transmission rate between the first server and the target chip is adjusted to the reference transmission rate; or If the target reduction number is greater than or equal to the reduction number threshold, and the N historical test results include N historical reduction numbers that are all greater than or equal to the reduction number threshold, the transmission rate between the first server and the target chip is adjusted to the reference transmission rate. The N historical test results include the test results obtained from N electrostatic tests performed on the first communication link before the target electrostatic test. The N electrostatic tests and the target electrostatic test are N+1 consecutive electrostatic tests, where N is a positive integer greater than or equal to 1.

5. The method according to claim 3, characterized in that, Adjusting the transmission rate of the first communication link between the first server and the target chip to the reference transmission rate includes: Obtain the adjustment instruction sent by BMC to the target chip, wherein the adjustment instruction is used to adjust the value of the second register in the target chip, and the value of the second register is used to control the handshake signal between the target chip and the first server; In response to the adjustment command, the target chip is controlled to adjust the value of the second register from the first value to the second value. When the value of the second register is the first value, the handshake signal is set to the low level, and when the value of the second register is the second value, the handshake signal is set to the high level.

6. The method according to claim 1, characterized in that, The electrostatic discharge (ESD) test performed on the first communication link between the first server and the target chip includes: When a first voltage is applied to a first test position on the high-speed serial computer expansion bus standard PCIe connector where the target chip is located, the first test position is discharged a first preset number of times within a first test duration; and when a second voltage is applied to the first test position, the first test position is discharged a second preset number of times within a second test duration, wherein the first voltage is a positive voltage and the second voltage is a negative voltage; and / or When a third voltage is applied to the second test position of the communication cable carrying the first communication link, the second test position is discharged a third preset number of times within a third test duration. When a fourth voltage is applied to the second test position, the second test position is discharged a fourth preset number of times within a fourth test duration. The third voltage is a positive voltage and the fourth voltage is a negative voltage.

7. The method according to any one of claims 1 to 6, characterized in that, The method further includes: If the target abnormal condition is met between the target reduction number and the reduction number threshold, the transmission rate of the second communication link between the second server and the target chip is adjusted to the reference transmission rate.

8. A control device for a communication link, characterized in that, include: The testing module is used to perform a target electrostatic discharge (ESD) test on a first communication link between the first server and the target chip during the process of the first server transmitting data to the second server through the target chip, and to obtain a target test result. The first communication link is configured to transmit data at a reference transmission rate. The target test result includes the number of target reductions, which is the number of times the transmission rate of the first communication link is lower than the reference transmission rate during the process of performing the target ESD test on the first communication link. The first acquisition module is used to acquire the number of times the target was reduced, which is included in the target test results; The first adjustment module is used to adjust the transmission rate of the first communication link between the first server and the target chip to the reference transmission rate when the preset target abnormality condition is met between the target reduction number and the preset reduction number threshold.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the method described in any one of claims 1 to 7.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method described in any one of claims 1 to 7.

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