An embedded flash memory device and a method of fabricating the same

Abstract

The application provides an embedded flash memory device and a manufacturing method thereof. The embedded flash memory device comprises a P-type substrate, an N-well, a P-well, a gate, a P-type source region and a P-type drain region. The P-type substrate comprises a high-voltage region. The N-well and the P-well are located in the high-voltage region, and the P-well is located in the N-well. The gate is located above the N-well and extends to above the P-well. The gate comprises a first gate dielectric layer, an N-type floating gate layer, a second gate dielectric layer and an N-type logic gate layer which are stacked in sequence from bottom to top. The N-type logic gate layer is electrically connected with the N-type floating gate layer. The P-type source region and the P-type drain region are located in the N-well and the P-well respectively, and the P-type source region and the P-type drain region are arranged on the two sides of the gate. The high-voltage region of the embedded flash memory device has an LDPMOS. Compared with a conventional embedded flash memory device, the overall withstand voltage performance can be improved to meet the high-voltage flash memory requirement, the production cost is reduced, and in the overall manufacturing process of the device, one mask process can be saved, and the production cost is reduced.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device structure and manufacturing technology, and relates to an embedded flash memory device and its manufacturing method. Background Technology

[0002] Flash memory has become a widely used non-volatile memory element in personal computers and electronic devices because it can perform multiple data write, read, and erase operations, and the stored data will not be lost after power is turned off.

[0003] Please see Figure 1 The diagram shows a cross-sectional view of a typical flash memory cell structure 100. A typical flash memory cell structure 100 includes a storage region 101, a high-voltage region 102, and a low-voltage region 103. The storage region 101 includes control transistors and selection transistors. The selection transistors select the cell structure to be used for storage operations. After selection, data writing or erasing operations are performed on the control transistor corresponding to the selection transistor. The selection transistor includes a selected gate (SG), and the control transistor includes a floating gate (FG) and a control gate (CG) located above the floating gate. Electrical isolation is achieved between the floating gate and the substrate, and between the floating gate and the control gate, using an isolation layer. When data is written to or erased from the flash memory cell, the voltage across the control gate, source, drain, and erase gate allows electrons to be injected into or pulled out of the floating gate. The high-voltage region 102 (containing multiple high-voltage transistors) and the low-voltage region 103 (containing multiple low-voltage transistors) are used to implement driving functions. When a memory cell device is erased or programmed, a positive or negative high voltage is applied to the SG, respectively. Therefore, the thickness of the gate oxide layer of the transistor in the memory area is usually controlled to meet the high voltage performance requirements of the SG. However, even if the thickness of the gate oxide layer of the transistor in the memory area is controlled, the improvement effect on the overall voltage withstand performance of the flash memory device is limited and still cannot meet the performance requirements of high voltage flash memory.

[0004] Therefore, how to provide an embedded flash memory device and its fabrication method to further improve the overall voltage withstand performance of the embedded flash memory device by improving the transistor structure in the high voltage region has become an important technical problem that needs to be solved by those skilled in the art.

[0005] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an embedded flash memory device and a method for manufacturing the same, so as to solve the problem that the overall withstand voltage performance of embedded flash memory devices in the prior art needs to be improved.

[0007] To achieve the above and other related objectives, the present invention provides an embedded flash memory device, comprising:

[0008] P-type substrate, including the high-voltage region;

[0009] The N-well and P-well are located in the P-type substrate, and both the N-well and P-well are located in the high-voltage region, with the P-well located inside the N-well.

[0010] A gate is located on the P-type substrate, the gate is located above the N-well and the gate also extends above the P-well. The gate includes a first gate dielectric layer, an N-type floating gate layer, a second gate dielectric layer and an N-type logic gate layer stacked sequentially from bottom to top. The N-type logic gate layer is electrically connected to the N-type floating gate layer.

[0011] The P-type source region and the P-type drain region are located in the P-type substrate. The P-type source region is located in the N-well, and the P-type drain region is located in the P-well. The P-type source region and the P-type drain region are located on opposite sides of the gate.

[0012] Optionally, the N-type floating gate layer includes an N-type doped polysilicon layer, and the N-type logic gate layer includes an N-type doped polysilicon layer.

[0013] Optionally, the first gate dielectric layer includes a silicon oxide layer, and the second gate dielectric layer includes a silicon oxide-silicon nitride-silicon oxide stacked structure.

[0014] Optionally, the N-type logic gate layer extends through at least a portion of the second gate dielectric layer to be electrically connected to the N-type floating gate layer.

[0015] Optionally, it further includes a first shallow trench isolation structure and a second shallow trench isolation structure spaced apart, wherein the first shallow trench isolation structure is located on opposite sides of the N-well, and the second shallow trench isolation structure is located within the P-well and below the gate.

[0016] Optionally, it further includes a P-type doped layer, which is located on the upper surface of the N-well and between the P-type source region and the P-type drain region, wherein the doping concentration of the P-type doped layer is lower than that of the P-type source region.

[0017] Optionally, the substrate further includes a storage region and a low-voltage region, wherein the high-voltage region and the low-voltage region are both located around the storage region, wherein the storage region is formed with a storage device, and the low-voltage region is formed with a low-voltage device.

[0018] This invention also provides a method for manufacturing an embedded flash memory device, comprising the following steps:

[0019] A P-type substrate is provided, the P-type substrate including a high voltage region;

[0020] An N-well and a P-well are formed in the P-type substrate, wherein both the N-well and the P-well are located in the high-voltage region and the P-well is located within the N-well;

[0021] A gate is formed on the P-type substrate. The gate is located above the N-well and extends above the P-well. The gate includes a first gate dielectric layer, an N-type floating gate layer, a second gate dielectric layer, and an N-type logic gate layer stacked sequentially from bottom to top. The N-type logic gate layer is electrically connected to the N-type floating gate layer.

[0022] A P-type source region and a P-type drain region are formed in the P-type substrate. The P-type source region is located in the N-well, and the P-type drain region is located in the P-well. The P-type source region and the P-type drain region are arranged on both sides of the gate.

[0023] Optionally, the method further includes the step of forming a P-type doped layer, wherein the P-type doped layer is located on the upper surface of the N-well and between the P-type source region and the P-type drain region, and the doping concentration of the P-type doped layer is lower than the doping concentration of the P-type source region.

[0024] Optionally, the P-type substrate further includes a storage region and a low-voltage region, wherein the high-voltage region and the low-voltage region are both located around the storage region, and the substrate further includes the steps of forming a storage device in the storage region and forming a low-voltage device in the storage region.

[0025] As described above, the embedded flash memory device of the present invention has an LDPMOS in the high-voltage region, which effectively improves the overall withstand voltage capability compared to conventional embedded flash memory devices, meeting the requirements of high-voltage flash memory. Furthermore, it saves one mask process during the overall manufacturing process, reducing production costs. The manufacturing method of the embedded flash memory device of the present invention can produce an embedded flash memory device with an LDPMOS in the high-voltage region, effectively improving the overall withstand voltage capability. The manufacturing process is simple and easy to achieve large-scale, low-cost production. Attached Figure Description

[0026] Figure 1 The diagram shows a cross-sectional view of a typical flash memory.

[0027] Figure 2 The diagram shows a partial cross-sectional view of the embedded flash memory device of the present invention in a first direction.

[0028] Figure 3 The diagram shows a partial cross-sectional view of the embedded flash memory device of the present invention in the second direction.

[0029] Figure 4 The diagram shows the steps of a method for manufacturing an embedded flash memory device according to the present invention.

[0030] Figure 5 The diagram shown is a cross-sectional view of the structure obtained after forming an etched window in the method for manufacturing the embedded flash memory device of the present invention.

[0031] Figure 6 The diagram shown is a cross-sectional view of the structure obtained after forming a shallow trench structure in the method for manufacturing the embedded flash memory device of the present invention.

[0032] Figure 7 The diagram shown is a cross-sectional view of the structure obtained after forming the first shallow trench isolation structure and the second shallow trench isolation structure in the method for manufacturing the embedded flash memory device of the present invention.

[0033] Figure 8 The diagram shown is a cross-sectional view of the structure obtained after forming the N-well and P-well in the method for manufacturing the embedded flash memory device of the present invention.

[0034] Figure 9 The diagram shown is a cross-sectional view of the structure obtained after forming an N-type floating gate layer in the method for manufacturing the embedded flash memory device of the present invention.

[0035] Figure 10 The diagram shown is a cross-sectional view of the structure obtained after forming an N-type logic gate layer in the method for manufacturing the embedded flash memory device of the present invention.

[0036] Figure 11 The diagram shown is a cross-sectional view of the structure obtained after forming the gate sidewall in the method for manufacturing the embedded flash memory device of the present invention.

[0037] Component labeling: 100 Flash memory device, 101 Storage region, 102 High voltage region, 102a PMOS located in HVNW, 102b NMOS located in HVPW, 102c NMOS located in TW, 103 Low voltage region, 1P-type substrate, 10 High voltage region, 11 First shallow trench isolation structure, 12 Second shallow trench isolation structure, 13 N-well, 14 P-well, 15 Gate, 151 First gate dielectric layer, 152 N-type floating gate layer, 153 Second gate dielectric layer, 154 N-type logic gate layer, 16 Gate sidewall, 17 P-type source region, 18 P-type drain region, Steps S1 to S4. Detailed Implementation

[0038] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0039] Please see Figures 2 to 11 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0040] Based on the analysis and experiments conducted on the problem described in the background technology that simply improving the gate oxide layer thickness of the select transistor still cannot meet the performance requirements of high-voltage flash memory, it was found that during the operation of flash memory devices, in addition to the high voltage applied to the select transistor, high voltage also needs to be transmitted to the SG before the erase and programming operations. Therefore, the devices in the peripheral circuits (such as decoding circuits and driving circuits) related to the SG also need to have high voltage withstand capability. Therefore, the overall voltage withstand performance of embedded flash memory devices can be improved by improving the transistor structure in the high voltage region. The specific technical solution is as follows.

[0041] Example 1

[0042] This embodiment provides an embedded flash memory device; please refer to [link / reference]. Figure 2 The diagram shows a partial cross-sectional view of the embedded flash memory device in the first direction (corresponding to the LDPMOS), specifically including a P-type substrate 1 ( Figure 2 (Not shown in the image), N-well 13, P-well 14, gate 15, P-type source region 17, and P-type drain region 18. Please refer to the relevant documentation. Figure 3 The diagram shows a partial cross-sectional view of the embedded flash memory device in a second direction (the second direction is perpendicular to the first direction).

[0043] Specifically, the P-type substrate 1 includes a high-voltage region 10; the N-well 13 and the P-well 14 are both located in the high-voltage region 10 of the P-type substrate 1, and the P-well 14 is located within the N-well 13; the gate 15 is located on the P-type substrate 1, the gate 15 is located above the N-well 13 and the gate 15 also extends above the P-well 14, the gate 15 includes a first gate dielectric layer 151, an N-type floating gate layer 152, a second gate dielectric layer 153 and an N-type logic gate layer 154 stacked sequentially from bottom to top, the N-type logic gate layer 154 is electrically connected to the N-type floating gate layer 152; the P-type source region 17 and the P-type drain region 18 are both located in the P-type substrate 1, the P-type source region 17 is located in the N-well 13, the P-type drain region 18 is located in the P-well 14, and the P-type source region 17 and the P-type drain region 18 are respectively arranged on both sides of the gate 15.

[0044] Specifically, in this embodiment, an LDPMOS is added to the structure of a conventional embedded flash memory device. Figure 2 The structure shown can utilize the high breakdown voltage of LDPMOS to simplify the circuit design during erase operations. This is because selecting memory cells requires a higher voltage, resulting in higher voltage withstand capability. The LDPMOS with a higher breakdown voltage or other transistors with slightly lower breakdown voltages can be selected as needed. Furthermore, the addition of LDPMOS improves the characteristics of the memory cells, specifically reducing erase disturbance. Erase disturbance refers to the following: during the erase operation, the substrate is connected to a high voltage (e.g., 20V), causing the bit lines to float. The gate of the selected control gate transistor is connected to 0V, while the unselected control gate transistors are floated and connected to a high voltage to prevent the selected cell from being erased. However, if leakage occurs during the erase / write process, the instantaneous current may cause the unselected block to be erased.

[0045] As an example, the N-type floating gate layer 152 includes an N-type doped polysilicon layer, and the N-type logic gate layer 154 includes an N-type doped polysilicon layer, meaning that the materials of the floating gate layer and the logic gate layer of the gate 15 both include polysilicon.

[0046] As an example, the first gate dielectric layer 151 includes a silicon oxide layer, and the second gate dielectric layer 153 includes a silicon oxide layer-silicon nitride layer-silicon oxide stacked structure (ONO layer).

[0047] As an example, the N-type logic gate layer 154 penetrates at least a portion of the second gate dielectric layer 153 to be electrically connected to the N-type floating gate layer 152. That is, before forming the N-type logic gate layer 154, etching is performed to form contact vias that at least penetrate the second gate dielectric layer 153. Figure 2(Not marked in the text) Subsequently, during the formation of the N-type logic gate layer 154, the N-type logic gate layer 154 fills into the contact hole and connects with the N-type floating gate layer 152. In this embodiment, the contact hole also penetrates at least a portion of the N-type floating gate layer 152. In other embodiments, the contact hole may only penetrate the second gate dielectric layer 153 to expose a portion of the N-type floating gate layer 152. Under the premise of ensuring that the N-type logic gate layer 154 and the N-type floating gate layer 152 are electrically connected, the width and depth of the contact hole can be reasonably set according to actual needs.

[0048] As an example, the embedded flash memory device further includes a first shallow trench isolation structure 11 and a second shallow trench isolation structure 12 spaced apart. The first shallow trench isolation structure 11 is located on opposite sides of the N-well 13, and the second shallow trench isolation structure 12 is located within the P-well 14 and below the gate 15. The first shallow trench isolation structure 11 serves to isolate the LDPMOS from other regions in the P-type substrate 1, and the second shallow trench isolation structure 12 acts as a breakdown voltage structure to further improve the breakdown voltage performance of the device.

[0049] As an example, the embedded flash memory device also includes a P-type doped layer ( Figure 2 (Not shown in the image), the P-type doped layer is located on the upper surface of the N-well 13 and is situated between the P-type source region 17 and the P-type drain region 18. The doping concentration of the P-type doped layer is lower than that of the P-type source region 17. The P-type doped layer serves as a buried channel, meaning that in this embodiment, the transistor structure formed in the high-voltage region 10 is an LDPMOS with a P-type buried channel.

[0050] As an example, please refer to [the relevant documentation / reference]. Figure 1 The substrate further includes a storage region and a low-voltage region, wherein the high-voltage region 10 (equivalent to...) Figure 1 As shown in Figure 102), both the low-voltage region and the high-voltage region are located around the memory region. The memory region contains memory devices (including select transistors and control transistors), and the low-voltage region contains low-voltage devices (including low-voltage PMOS and low-voltage NMOS). Similarly, the high-voltage region 10 includes high-voltage PMOS (PMOS located within HVNW, such as...). Figure 1 As shown in Figure 102a), and high-voltage NMOS (including NMOS located within HVPW and NMOS located within TW, such as...) Figure 1As shown in Figures 102b and 102c, the storage region is used for data storage, writing, and erasing. The high-voltage region 10 is used to form a storage cell control circuit to control the writing and erasing of storage transistors within the storage region. The NMOS located in the TW (triple well, with a P-substrate as the first well, a deep N-well within the P-substrate as the second well, and a P-well within the deep N-well as the third well) is used to apply a negative voltage. Due to its three well regions, the negative voltage applied between the P-type substrate and the HVPW prevents leakage current from occurring between the NMOS and the P-type substrate due to the presence of the HVNW. The low-voltage region serves as the main logic circuit; that is, the high-voltage region 10 and the low-voltage region serve as the peripheral circuitry of the storage region, providing driving force for the storage region. Furthermore, the gates 15 of each transistor within the storage region and the high-voltage region 10 are all stacked gate structures (i.e., including a floating gate layer and a logic gate layer).

[0051] Specifically, typically, the high-voltage region 10 includes an NMOS located within the TW (Transmission Wavelength W). This NMOS has a surface channel, and the difference in work function between its floating gate layer and the channel region means that the threshold voltage of this NMOS cannot meet the actual performance requirements. Therefore, an ion implantation process is needed to adjust the threshold voltage by targeting the outermost surface of the channel region. During the ion implantation process to adjust the threshold voltage, a mask is required to define the implantation area. However, in this embodiment, because an LDPMOS is fabricated in the high-voltage region 10 and N+ implantation is performed on its floating gate layer and logic gate layer, the resulting transistor directly meets the threshold voltage range. Furthermore, the overall voltage withstand capability of the flash memory device is effectively improved, meeting the requirements of high-voltage flash memory. Compared with conventional technology, the step of adjusting the threshold voltage can be omitted, which can save manufacturing costs. In addition, since ion implantation of different conductivity types is also required when fabricating transistors in other areas of the memory device (memory area and / or low-voltage area), although the doping elements of the floating gate layer and the source / drain region have opposite electrical properties, since the fabrication process of the entire embedded flash memory device also includes N+ implantation of other transistors, no additional mask is added when ion implanting the floating gate layer and the logic gate layer, thus not increasing the additional manufacturing cost.

[0052] The embedded flash memory device in this embodiment has an LDPMOS in the high voltage region, which effectively improves the overall voltage withstand capability compared to conventional embedded flash memory devices, meeting the requirements of high voltage flash memory. Furthermore, the overall manufacturing process can reduce one mask process, thus lowering production costs.

[0053] Example 2

[0054] This embodiment provides a method for fabricating an embedded flash memory device. Please refer to [link / reference]. Figure 4 The flowchart shows the steps of this production method, which specifically include the following steps:

[0055] S1: A P-type substrate is provided, wherein the P-type substrate includes a high-voltage region;

[0056] S2: An N-well and a P-well are formed in the P-type substrate, wherein both the N-well and the P-well are located in the high-voltage region and the P-well is located within the N-well;

[0057] S3: A gate is formed on the P-type substrate. The gate is located above the N-well and extends above the P-well. The gate includes a first gate dielectric layer, an N-type floating gate layer, a second gate dielectric layer, and an N-type logic gate layer stacked sequentially from bottom to top. The N-type logic gate layer is electrically connected to the N-type floating gate layer.

[0058] S4: A P-type source region and a P-type drain region are formed in the P-type substrate, wherein the P-type source region is located in the N-well, the P-type drain region is located in the P-well, and the P-type source region and the P-type drain region are arranged on both sides of the gate.

[0059] Please see Figure 5 Step S1 is executed, providing a P-type substrate 1, wherein the P-type substrate 1 includes a high voltage region 10;

[0060] As an example, the P-type substrate 1 further includes a storage region and a low-voltage region. The high-voltage region 10 and the low-voltage region are both located around the storage region. The storage region is used to fabricate storage devices, and the low-voltage region is used to fabricate low-voltage devices.

[0061] For example, please refer to Figure 5 and Figure 7 It also includes the steps of forming a first shallow trench isolation structure 11 and a second shallow trench isolation structure 12. The first shallow trench isolation structure 11 and the second shallow trench isolation structure 12 can be manufactured simultaneously or in stages. In this embodiment, the first shallow trench isolation structure 11 and the second shallow trench isolation structure 12 are manufactured simultaneously, which can save process steps. Figure 5 As shown, an oxide pad layer is formed sequentially. Figure 5 (not marked in the text), hard mask layer ( Figure 5 (not marked in the text) and photoresist layer ( Figure 5 (Not identified in the text) is applied to the surface of the P-type substrate 1, and the photoresist layer is patterned to form multiple etching windows ( Figure 5 (not marked in the text); such as Figure 6 As shown, the P-type substrate 1 is etched based on the etching window to obtain multiple shallow trench structures and the patterned photoresist layer is removed; as Figure 7 As shown, an isolation layer is formed ( Figure 7 (Not identified in the text) is placed on the P-type substrate 1, and the isolation layer is further filled into the shallow trench; the isolation layer is planarized so that the upper surface of the isolation layer is flush with the hard mask layer (not identified in the text) on the P-type substrate 1. Figure 7 The upper surface of the (not shown) is flush with the hard mask layer and the oxide pad layer after etching to obtain a shallow trench isolation structure. The shallow trench isolation structure includes a first shallow trench isolation structure 11 and a second shallow trench isolation structure 12. The first shallow trench isolation structure 11 is located on opposite sides of the subsequently formed N-well 13, and the second shallow trench isolation structure 12 is located in the subsequently formed P-well 14 and below the subsequently formed gate 15.

[0062] Please see Figure 8 Step S2 is executed to form an N-well 13 and a P-well 14 in the P-type substrate 1. Both the N-well 13 and the P-well 14 are located in the high-voltage region 10, and the P-well 14 is located within the N-well 13. With the first shallow trench isolation structure 1111 and the second shallow trench isolation structure 12 formed, ion implantation is performed on the region between the two first shallow trench isolation structures 11 to form the N-well 13, based on the two first shallow trench isolation structures 11. It should be noted that when forming the P-well 14 by ion implantation, the arrangement of the second shallow trench isolation structure 12 will have a certain impact on the formation of the P-well 14. Therefore, it is necessary to control the dose and energy during ion implantation to form the P-well 14 so that the second shallow trench isolation structure 12 is completely located within the P-well 14, avoiding adverse effects on the conductive channel between the source and drain.

[0063] As an example, the fabrication method further includes the step of forming a P-type doped layer (not shown in the figure), which is located on the upper surface of the N-well 13 and between the P-type source region 17 and the P-type drain region 18, wherein the doping concentration of the P-type doped layer is lower than the doping concentration of the P-type source region 17.

[0064] Please see Figures 9 to 11 Step S3 is executed to form a gate 15 on the P-type substrate 1. The gate 15 is located above the N-well 13 and extends above the P-well 14. The gate 15 includes a first gate dielectric layer 151, an N-type floating gate layer 152, a second gate dielectric layer 153 and an N-type logic gate layer 154 stacked sequentially from bottom to top. The N-type logic gate layer 154 is electrically connected to the N-type floating gate layer 152.

[0065] As an example, the N-type logic gate layer 154 extends through at least a portion of the second gate dielectric layer 153 to be electrically connected to the N-type floating gate layer 152.

[0066] like Figure 9As shown, a first dielectric layer is formed on the upper surface of the P-type substrate, and a first N-type polysilicon layer is formed on the first dielectric layer using a self-aligned process. The first N-type polysilicon layer and the first dielectric layer are etched to form a first gate dielectric layer 151 and the N-type floating gate layer 152; Figure 10 As shown, a second dielectric layer is formed, which covers the N-type floating gate layer 152 and at least a portion of the upper surface of the P-type substrate 1; a contact hole is formed in the second dielectric layer, the contact hole penetrating the second dielectric layer to expose at least a portion of the N-type floating gate layer 152; a second polysilicon layer is formed above the second dielectric layer, the second polysilicon layer also filling the contact hole and connecting to the N-type floating gate layer 152; etching is performed and N-type ion implantation is performed on the second polysilicon layer to form the second gate dielectric layer 153 and the N-type logic gate layer 154.

[0067] For example, please refer to Figure 11 It also includes the step of forming a gate sidewall 16, which is located on opposite sides of the gate 15. The gate sidewall 16 can provide a mask for the subsequent ion implantation to form the source and drain regions, preventing dopant elements from entering the channel region and affecting the electrical performance of the device.

[0068] Please see again Figure 2 Step S4 is executed to form a P-type source region 17 and a P-type drain region 18 in the P-type substrate 1. The P-type source region 17 is located in the N-well 13, and the P-type drain region 18 is located in the P-well 14. The P-type source region 17 and the P-type drain region 18 are respectively located on both sides of the gate 15. That is, after the P-type source region 17 and the P-type drain region 18 are formed, the gate 15 spans between the P-type source region 17 and the P-type drain region 18 to form a conductive channel through voltage regulation.

[0069] As an example, the fabrication method further includes the steps of forming a memory device in the memory region and forming a low-voltage device in the memory region, with the fabrication of the memory device and the low-voltage device being carried out simultaneously with the fabrication of the LDPMOS described above.

[0070] The method for fabricating embedded flash memory devices in this embodiment can produce embedded flash memory devices with LDPMOS in the high-voltage region, effectively improving the overall withstand voltage capability, meeting the high-voltage performance requirements, and saving a mask process in the overall device fabrication process, effectively reducing the manufacturing cost.

[0071] In summary, the embedded flash memory device of this invention features an LDPMOS transistor in its high-voltage region. Compared to conventional embedded flash memory devices, this effectively improves the overall voltage withstand capability, meeting the requirements of high-voltage flash memory. Furthermore, the overall manufacturing process reduces one masking step, lowering production costs. The method for manufacturing the embedded flash memory device of this invention can produce embedded flash memory devices with LDPMOS transistors in the high-voltage region, effectively improving the overall voltage withstand capability. The manufacturing process is simple and easily achievable for large-scale, low-cost production. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and possesses high industrial applicability.

[0072] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An embedded flash memory device, characterized in that, include: P-type substrate, including the high-voltage region; The N-well and P-well are located in the P-type substrate, and both the N-well and P-well are located in the high-voltage region, with the P-well located inside the N-well. A gate is located on the P-type substrate, the gate is located above the N-well and the gate also extends above the P-well. The gate includes a first gate dielectric layer, an N-type floating gate layer, a second gate dielectric layer and an N-type logic gate layer stacked sequentially from bottom to top. The N-type logic gate layer is electrically connected to the N-type floating gate layer. The P-type source region and the P-type drain region are located in the P-type substrate. The P-type source region is located in the N-well, and the P-type drain region is located in the P-well. The P-type source region and the P-type drain region are located on opposite sides of the gate.

2. The embedded flash memory device according to claim 1, characterized in that: The N-type floating gate layer includes an N-type doped polysilicon layer, and the N-type logic gate layer includes an N-type doped polysilicon layer.

3. The embedded flash memory device according to claim 2, characterized in that: The first gate dielectric layer includes a silicon oxide layer, and the second gate dielectric layer includes a silicon oxide layer-silicon nitride layer-silicon oxide stacked structure.

4. The embedded flash memory device according to claim 1, characterized in that: The N-type logic gate layer penetrates at least a portion of the second gate dielectric layer to be electrically connected to the N-type floating gate layer.

5. The embedded flash memory device according to claim 1, characterized in that: It also includes a first shallow trench isolation structure and a second shallow trench isolation structure spaced apart, the first shallow trench isolation structure being located on opposite sides of the N-well, and the second shallow trench isolation structure being located within the P-well and below the gate.

6. The embedded flash memory device according to claim 1, characterized in that: It also includes a P-type doped layer, which is located on the upper surface of the N-well and between the P-type source region and the P-type drain region. The doping concentration of the P-type doped layer is lower than that of the P-type source region.

7. The embedded flash memory device according to claim 1, characterized in that: The substrate further includes a storage region and a low-voltage region, both of which are located around the storage region. The storage region is formed with a storage device, and the low-voltage region is formed with a low-voltage device.

8. A method for fabricating an embedded flash memory device, characterized in that, Includes the following steps: A P-type substrate is provided, the P-type substrate including a high voltage region; An N-well and a P-well are formed in the P-type substrate, wherein both the N-well and the P-well are located in the high-voltage region and the P-well is located within the N-well; A gate is formed on the P-type substrate. The gate is located above the N-well and extends above the P-well. The gate includes a first gate dielectric layer, an N-type floating gate layer, a second gate dielectric layer, and an N-type logic gate layer stacked sequentially from bottom to top. The N-type logic gate layer is electrically connected to the N-type floating gate layer. A P-type source region and a P-type drain region are formed in the P-type substrate. The P-type source region is located in the N-well, and the P-type drain region is located in the P-well. The P-type source region and the P-type drain region are arranged on both sides of the gate.

9. The method for manufacturing an embedded flash memory device according to claim 8, characterized in that: It also includes the step of forming a P-type doped layer, wherein the P-type doped layer is located on the upper surface of the N-well and between the P-type source region and the P-type drain region, and the doping concentration of the P-type doped layer is lower than the doping concentration of the P-type source region.

10. The method for manufacturing an embedded flash memory device according to claim 8, characterized in that: The P-type substrate further includes a storage region and a low-voltage region, both of which are located around the storage region. The substrate also includes the steps of forming a storage device in the storage region and forming a low-voltage device in the storage region.

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