Memory devices and methods of manufacturing memory devices

Abstract

The present disclosure relates to a memory device and a method of manufacturing a memory device. The memory device according to one embodiment includes a stack structure including gate lines separated from each other and stacked on top of each other, a main plug formed in a vertical direction of the stack structure, a plug separation pattern separating the main plug into a first sub-plug and a second sub-plug, a gap formed in the plug separation pattern, and a separation layer surrounding the gap.

Description

Technical Field

[0001] Various embodiments of this disclosure generally relate to a memory device and a method of manufacturing a memory device, and more specifically, to a three-dimensional memory device and a method of manufacturing a three-dimensional memory device. Background Technology

[0002] Memory devices can be divided into volatile memory devices that lose stored data when power is interrupted and non-volatile memory devices that retain stored data even when power is interrupted.

[0003] Non-volatile memory devices may include NAND flash memory, NOR flash memory, resistive random access memory (ReRAM), phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), and spin-transfer torque random access memory (STT-RAM).

[0004] A NAND flash memory system may include a memory device configured to store data and a controller configured to control the memory device. The memory device may include an array of memory cells for storing data and peripheral circuitry configured to perform programming, reading, or erasing operations in response to commands transmitted from the controller.

[0005] A memory cell array can include multiple memory blocks. Each memory block can include multiple memory cells.

[0006] As the integration density of memory devices increases, there is a growing need for memory devices capable of storing large amounts of data, along with simplified manufacturing processes. Summary of the Invention

[0007] According to one embodiment, a memory device may include: a stacked structure including gate lines, wherein the gate lines are stacked in a vertical direction and wherein the gate lines are separated from each other; a main plug included in the stacked structure, the main plug extending in a vertical direction of the stacked structure; a plug separation pattern that separates the main plug into a first sub-plug and a second sub-plug; a gap included in the plug separation pattern; and a separation layer surrounding the gap.

[0008] According to one embodiment, a method of manufacturing a memory device may include: forming a stacked structure, wherein a first material layer and a second material layer are alternately stacked on a lower structure; forming main plugs spaced apart from each other and arranged in a vertical direction of the stacked structure; forming slits through the stacked structure and separation holes for separating the main plugs; forming a first separation layer on the inner surface of each of the separation holes; forming a second separation layer on the inner surface of the first separation layer; forming a third separation layer on the inner surface of the second separation layer; and forming a gap in the third separation layer. Attached Figure Description

[0009] Figure 1 This is a diagram illustrating a memory device according to one embodiment of the present disclosure;

[0010] Figure 2 It is a diagram showing the arrangement of the memory cell array and peripheral circuitry;

[0011] Figure 3 This is a diagram showing the structure of a memory cell array;

[0012] Figure 4 This is a diagram showing the layout of a memory device according to one embodiment of the present disclosure;

[0013] Figure 5 This is a layout diagram showing the structure of the plug region 41 according to one embodiment of the present disclosure;

[0014] Figure 6 This is a cross-sectional view showing the structure of a single plug region 42 according to one embodiment of the present disclosure;

[0015] Figure 7 This is a cross-sectional view showing the structure of the plug separation pattern region 43 according to one embodiment of the present disclosure;

[0016] Figure 8 This is a layout diagram showing the structure of the plug region 61 adjacent to the source line according to one embodiment of the present disclosure;

[0017] Figure 9 This is a perspective view showing the structure of a slit and a storage block according to one embodiment of the present disclosure;

[0018] Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 10E , Figure 10F , Figure 10G , Figure 10H , Figure 10I , Figure 10J , Figure 10K , Figure 10L , Figure 10M , Figure 10N , Figure 10O , Figure 10P and Figure 10Q This is a layout diagram illustrating a method of manufacturing a memory device according to one embodiment of the present disclosure;

[0019] Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 11E , Figure 11F , Figure 11G , Figure 11H , Figure 11I , Figure 11J , Figure 11K , Figure 11L , Figure 11M , Figure 11N , Figure 11O , Figure 11P and Figure 11Q This is a cross-sectional view illustrating a method of manufacturing a memory device according to one embodiment of the present disclosure;

[0020] Figure 12 This is a diagram illustrating a solid-state drive (SSD) applied to a memory device according to the present disclosure; and

[0021] Figure 13 This is a diagram illustrating a memory card system using a memory device according to one embodiment of the present disclosure. Detailed Implementation

[0022] The specific structural or functional descriptions illustrating examples of embodiments of the concepts disclosed in this specification are for illustrative purposes only and may be implemented in various forms, but the descriptions are not limited to the examples of embodiments described in this specification.

[0023] Various implementations relate to memory devices that can improve the reliability of memory devices and methods of manufacturing memory devices.

[0024] Figure 1 This is a diagram illustrating a memory device 100 according to one embodiment of the present disclosure.

[0025] Reference Figure 1 The memory device 100 may include peripheral circuitry 190 and a memory cell array 110.

[0026] The peripheral circuitry 190 can perform programming and verification operations to store data in the memory cell array 110, read operations to output data stored in the memory cell array 110, or erase operations to erase data stored in the memory cell array 110. The peripheral circuitry 190 may include a voltage generator 130, a row decoder 120, a source line driver 140, control circuitry 150, a page buffer 160, a column decoder 170, and input / output circuitry 180.

[0027] The memory cell array 110 may include a plurality of memory cells for storing data. According to one embodiment, the memory cell array 110 may include a three-dimensional memory cell array. Depending on the programming method, the plurality of memory cells may store one bit of data or multi-bit data consisting of two or more bits. The plurality of memory cells may form multiple strings. The memory cells included in each string may be electrically interconnected with each other via channels. The channels included in the strings may be connected to the page buffer 160 via bit lines BL.

[0028] Voltage generator 130 can generate various operating voltages Vop for programming, reading, or erasing operations in response to the operation signal OP_S. For example, voltage generator 130 can selectively generate and output various operating voltages Vop, including programming voltage, verification voltage, pass voltage, read voltage, and erase voltage.

[0029] The row decoder 120 can be connected to the memory cell array 110 via multiple drain select lines DSL, multiple word lines WL, and multiple source select lines SSL. The row decoder 120 can transmit the operating voltage Vop to the multiple drain select lines DSL, multiple word lines WL, and multiple source select lines SSL in response to the row address RADD.

[0030] The source line driver 140 can transfer the source voltage Vsl to the memory cell array 110 in response to the source line signal SL_S. For example, the source voltage Vsl can be transferred to a source line connected to the memory cell array.

[0031] Control circuit 150 can output operation signal OP_S, row address RADD, source line control signal SL_S, page buffer control signal PB_S, and column address CADD in response to command CMD and address ADD.

[0032] Page buffer 160 can be connected to memory cell array 110 via bit lines BL. Page buffer 160 can store data DATA received via multiple bit lines BL in response to page buffer control signal PB_S. Page buffer 160 can sense voltage or current in multiple bit lines BL during read operations.

[0033] In response to the column address CADD, the column decoder 170 can transfer data DATA input from the input / output circuit 180 to the page buffer 160, or can transfer data DATA stored in the page buffer 160 to the input / output circuit 180. The column decoder 170 can exchange data DATA with the input / output circuit 180 via the column line CLL, and can exchange data DATA with the page buffer 160 via the data line DTL.

[0034] The input / output circuit 180 can transmit commands CMD and addresses ADD from an external device (e.g., a controller) connected to the memory device 100 to the control circuit 150, and can output data DATA received from the column decoder 170 to the external device.

[0035] Figure 2 This is a diagram showing the arrangement of the memory cell array 110 and the peripheral circuitry 190.

[0036] Reference Figure 2 The memory cell array 110 can be stacked on top of the peripheral circuitry 190. For example, when a substrate is formed in the XY plane, the peripheral circuitry 190 can be stacked from the substrate along the Z direction, and the memory cell array 110 can be stacked on top of the peripheral circuitry 190.

[0037] Figure 3 This is a diagram showing the structure of the memory cell array 110.

[0038] Reference Figure 3 The memory cell array 110 may include first memory blocks BLK1 to BLKi, where i is a positive integer. First memory blocks BLK1 to BLKi may be spaced apart from each other in the Y direction and are jointly connected to first bit lines BL1 to BLj. For example, first bit lines BL1 to BLj may extend in the Y direction and be spaced apart from each other in the X direction. First memory blocks BLK1 to BLKi may be separated from each other by a slit SLT.

[0039] Figure 4 This is a diagram illustrating the layout of a memory device according to one embodiment of the present disclosure.

[0040] Reference Figure 4The (n-1)th memory block BLK(n-1), the nth memory block BLKn, and the (n+1)th memory block BLK(n+1) in the memory device may be spaced apart from each other in the Y direction. The (n-1)th memory block BLK(n-1), the nth memory block BLKn, and the (n+1)th memory block BLK(n+1) may have the same configuration and may be separated from each other by a slit SLT. Each slit SLT may include a slit isolation layer IS and a source contact SC. The slit isolation layer IS can electrically isolate the memory blocks from each other. The source contact SC can contact a source line (not shown) formed under the memory block and can transmit the source line voltage generated by the voltage generator 130 to the source line.

[0041] Since the (n-1)th storage block BLK(n-1), the nth storage block BLKn, and the (n+1)th storage block BLK(n+1) can have the same configuration, the nth storage block BLKn is described below as an example.

[0042] The nth memory block BLKn may include multiple main plugs Pm. Each main plug Pm may include a first sub-plug 1Ps and a second sub-plug 2Ps separated by a plug separation pattern SP. Each of the first sub-plug 1Ps and the second sub-plug 2Ps may include multiple memory cells. Figure 4 The diagram illustrates how each of two main plugs Pm is separated into a first sub-plug 1Ps and a second sub-plug 2Ps by a plug separation pattern SP. However, the number of main plugs Pm separated by a plug separation pattern SP is not limited to... Figure 4 The quantities shown are as follows. For example, a main plug Pm can be separated into a first sub-plug 1Ps and a second sub-plug 2Ps by a plug separation pattern SP. Each of the three main plugs Pm can be separated into a first sub-plug 1Ps and a second sub-plug 2Ps by a plug separation pattern SP. In the following, an implementation of separating each of two main plugs Pm into a first sub-plug 1Ps and a second sub-plug 2Ps by a plug separation pattern SP will be described.

[0043] Since different bit lines BL are connected to the first sub-plug 1Ps and the second sub-plug 2Ps, the memory cells included in the first sub-plug 1Ps and the second sub-plug 2Ps can form different strings. For example, the first sub-plug 1Ps can be connected to the first bit line BL1 through the bit line contact BLC, and the second sub-plug 2Ps can be connected to the second bit line BL2 through the bit line contact BLC.

[0044] The nth memory block BLKn may include source select lines, word lines, and drain select lines stacked on top of each other. For example, word lines may be formed above source select lines, and drain select lines may be formed above word lines.

[0045] Since memory blocks (n-1) to (n+1) are separated by a slit SLT, gate lines included in different memory blocks can be separated from each other by the slit SLT. For example, gate lines included in memory block (n-1) and gate lines included in memory block (n+1) can be separated from each other by the slit SLT.

[0046] According to one embodiment of this disclosure, the plug separation pattern SP can be separated from the slit SLT at predetermined intervals in the Y-axis direction. Furthermore, the plug separation patterns SP can be spaced apart from each other in the Y-axis direction at the same interval as the interval of the slit SLT. For example, the plug separation pattern SP can be separated from the slit SLT in the Y-axis direction at a first interval T1. The term "predetermined" (e.g., predetermined interval) as used herein with respect to parameters indicates that the value of the parameter is determined before the parameter is used in a process or algorithm. In some embodiments, the value of the parameter is determined before the process or algorithm begins. In other embodiments, the value of the parameter is determined during the process or algorithm, but before the parameter is used in the process or algorithm.

[0047] Each plug separation pattern SP may include a barrier pattern PP, an air gap (not shown), and a separation layer SM. The barrier pattern may be surrounded by the separation layer above the air gap. The separation layer SM and the barrier pattern PP prevent the air gap from exchanging material with the outside. Therefore, the air gap may be formed below the barrier pattern PP in the Z-axis direction. (Refer to the following...) Figure 6 Describe the separation layer SM and the air gap. The separation layer SM can have various shapes and is not limited to these. Figure 4 The shape shown. For example, the separation layer SM can have an elliptical shape, a circular shape, a rectangular shape, etc.

[0048] The plug region 41, which includes memory cells, will be described below.

[0049] Figure 5 This is a layout diagram showing the structure of the plug region 41 according to one embodiment of the present disclosure.

[0050] Reference Figure 5 A first main plug 1Pm, a second main plug 2Pm, and a plug separation pattern SP may be included in the plug region 41. The first main plug 1Pm and the second main plug 2Pm may be spaced apart from each other in the X-axis direction and extend in the Y-axis direction. The plug separation pattern SP may extend in the X-axis direction to separate the first main plug 1Pm and the second main plug 2Pm in the Y-axis direction.

[0051] The first main plug 1Pm may include a first sub-plug 1Ps and a second sub-plug 2Ps separated by the plug separation pattern SP. The second main plug 2Pm may include a third sub-plug 3Ps and a fourth sub-plug 4Ps separated by the plug separation pattern SP. The third sub-plug 3Ps may have the same structure as the first sub-plug 1Ps. The fourth sub-plug 4Ps may have the same structure as the second sub-plug 2Ps. Based on the plug separation pattern SP, the structure of the first sub-plug 1Ps may be symmetrical with the structure of the second sub-plug 2Ps. Based on the plug separation pattern SP, the structure of the third sub-plug 3Ps may be symmetrical with the structure of the fourth sub-plug 4Ps.

[0052] Since the first sub-plug 1Ps to the fourth sub-plug 4Ps have similar structures, the structure of the first sub-plug 1Ps will be described below as an example.

[0053] The first sub-plug 1Ps may include a capping layer CAP, a channel layer CH, a tunnel isolation layer TO, a charge trapping layer CT, and a blocking layer BX. The capping layer CAP may be disposed on top of the first sub-plug 1Ps extending vertically from the substrate, and in one embodiment, may be configured to improve the electrical characteristics of the drain-select transistor. For example, the capping layer CAP may include a conductive material. For example, the capping layer CAP may include a doped polysilicon layer. Although in Figure 5 Not shown, but a core pillar CP may be formed below the capping layer CAP. For example, the core pillar CP may include an insulating or conductive material. A channel layer CH may surround the capping layer CAP and the core pillar CP and may include a conductive material. For example, the channel layer CH may include a polysilicon layer. A tunnel isolation layer TO may surround the channel layer CH and include an insulating material. For example, the tunnel isolation layer TO may include an oxide layer or a silicon oxide layer. A charge trapping layer CT may surround the surface of the tunnel isolation layer TO and may include a material capable of trapping charges. For example, the charge trapping layer CT may include a nitride layer. A barrier layer BX may surround the charge trapping layer CT and include an insulating material. For example, the barrier layer BX may include an oxide layer or a silicon oxide layer.

[0054] Despite Figure 5 Although not shown in the diagram, the first sub-plugs 1Ps to the fourth sub-plugs 4Ps can be electrically connected to different bit lines through different bit line contacts. For example, the channel layer CH of the first sub-plug 1Ps can be connected to the first bit line through the bit line contact, the channel layer CH of the second sub-plug 2Ps can be connected to the second bit line through the bit line contact, the channel layer CH of the third sub-plug 3Ps can be connected to the third bit line through the bit line contact, and the channel layer CH of the fourth sub-plug can be connected to the fourth bit line through the bit line contact BLC.

[0055] Despite Figure 5The air gap is not shown, but it may extend in the Z-axis direction of the blocking pattern PP. The plug separation pattern SP may include the blocking pattern PP, the air gap, and a separation layer SM surrounding the air gap and the blocking pattern PP. The separation layer SM may include sub-separation regions SMs corresponding to the portions of the separation layer SM that contact the first sub-plugs 1Ps to the fourth sub-plugs 4Ps. Similarly, for the first sub-plugs 1Ps to the fourth sub-plugs 4Ps having similar configurations, the sub-separation regions SMs that contact the first sub-plugs 1Ps to the fourth sub-plugs 4Ps respectively may have similar configurations. Furthermore, similar to the first sub-plugs 1Ps to the fourth sub-plugs 4Ps that are symmetrical about the plug separation pattern SP, each of the sub-separation regions SMs that contact the first sub-plugs 1Ps to the fourth sub-plugs 4Ps respectively may be symmetrical about the plug separation pattern SP.

[0056] The separation layer SM may include a first separation layer 1SM to a third separation layer 3SM. The first separation layer 1SM may surround the outermost edge of the separation layer SM. A second separation layer 2SM may be formed on the inner wall of the first separation layer 1SM. A third separation layer 3SM may be formed along the inner wall of the second separation layer 2SM. The first separation layer 1SM may include an insulating material, such as an oxide layer or a silicon oxide layer. In one embodiment, the first separation layer 1SM may protect against [transmission / damage]. Figure 11E The layer exposes the side surface of the separation hole SH, and can electrically disconnect the second separation layer 2SM and the first sub-plugs 1Ps to the fourth sub-plugs 4Ps from each other before the complete separation layer SM is formed. Furthermore, in one embodiment, the first separation layer 1SM can prevent source line conductive material from being introduced into the memory cell during the source line formation process to be performed in a subsequent process.

[0057] The second separation layer 2SM may include a low-k material. A low-k material is one with a relatively small permittivity (k) relative to silicon dioxide (SiO2). For example, the second separation layer 2SM may include a SiCN layer. To control the capacitance of the memory cell, the carbon (C) content can be adjusted when the second separation layer 2SM is formed. In one embodiment, the second separation layer 2SM may be configured to reduce interference between memory cells facing each other and interposed therebetween. For example, the capacitance of the second separation layer 2SM may be proportional to the concentration of carbon (C) included in the second separation layer 2SM. Furthermore, in one embodiment, the second separation layer 2SM, together with the first separation layer 1SM, may prevent source line conductive material from being introduced into the memory cell during a subsequent source line formation process. A third separation layer 3SM may surround the barrier pattern PP. The third separation layer 3SM may include an insulating material, such as a silicon nitride layer or an oxide layer.

[0058] Furthermore, the third separation layer 3SM, together with the first separation layer 1SM and the second separation layer 2SM, can prevent source line conductive material from being introduced into the memory cell during the source line formation process to be performed in subsequent processes. For example... Figure 5 As shown, the separation layer SM may include a third separation layer 3SM, a second separation layer 2SM, and a first separation layer 1SM. However, the separation layer SM may have another configuration. For example, sub-separation regions SMs may include a first separation layer 1SM and a second separation layer 2SM. Furthermore, as... Figure 5 As shown, the third separation layer 3SM, the second separation layer 2SM, and the first separation layer 1SM can have the same thickness. However, this disclosure is not limited to this. For example, when the separation layer SM includes the first separation layer 1SM and the second separation layer 2SM, the second separation layer 2SM can have a greater thickness than the first separation layer 1SM.

[0059] Reference Figure 6 Describe the structure of the first sub-plug 1Ps, the second sub-plug 2Ps, and the plug separation pattern SP.

[0060] Figure 6 This is a layout diagram showing the structure of a single plug region 42 according to one embodiment of the present disclosure.

[0061] Figure 6 The image shown is taken along the A1-A2 direction. Figure 5 The cross-section of the first sub-plug 1Ps and the second sub-plug 2Ps.

[0062] The first sub-plugs 1Ps and the second sub-plugs 2Ps, along with the plug separation pattern SP, can extend in a direction perpendicular to the source line SL. The plug separation pattern SP can include an air gap AG, a barrier pattern PP, and a separation layer SM. The lower surface of the separation layer SM of the plug separation pattern SP can contact the source line SL. The barrier pattern PP can be formed on top of the air gap AG. Furthermore, the lower surface of the barrier pattern PP can have the same width as the top of the air gap AG. The barrier pattern PP can prevent the air gap AG from exchanging material with the outside. In one embodiment, the air gap AG can be a gap filled with gas, not limited to air. For example, the air gap AG can contain gas or a combination of gas and air.

[0063] The plug separation pattern SP can pass through the core pillar CP, channel layer CH, tunnel isolation layer TO, charge trapping layer CT, and barrier layer BX. The main plug Pm can be divided into a first sub-plug 1Ps and a second sub-plug 2Ps by the plug separation pattern SP. The gate line GL can surround the first sub-plug 1Ps, the second sub-plug 2Ps, and the plug separation pattern SP, and be spaced apart from each other in the Z-axis direction. The lower part of the channel layer CH can contact the source line SL, and the upper part of the channel layer CH can contact the bit line contact BLC.

[0064] In the gate line GL, the line formed below the word line WL can be used as the source select line SSL. The line above the word line WL can be used as the drain select line DSL. The word line WL can be connected to the gate of the memory cell MC. The source select line SSL can be connected to the gate of the source select transistor SST. The drain select line DSL can be connected to the gate of the drain select transistor DST. The source select transistor SST can be configured to electrically connect the source line SL to the channel layer CH in the string or to disconnect the source line SL from the channel layer CH in the string. The drain select transistor DST can be configured to electrically connect the bit line to the channel layer CH in the string or to disconnect the bit line from the channel layer CH in the string.

[0065] Bit line contact portion BLC can be formed on the channel layer CH of the first sub-plug 1Ps. Bit line BL can be formed above bit line contact portion BLC.

[0066] Figure 7 This is a cross-sectional view showing the structure of the plug separation pattern region 43 according to one embodiment of the present disclosure.

[0067] Figure 7 The image shown is taken along the B1-B2 direction. Figure 5 The diagram shows a cross-section of the plug separation pattern SP. The plug separation pattern SP may include a barrier pattern PP, an air gap AG, and a separation layer SM. The barrier pattern PP may be formed on top of the air gap AG. The bottom surface of the separation layer SM may contact the source line SL. In the plug separation pattern region 43 other than the plug region 61 that contacts the source line SL, the separation layer SM may include a first separation layer 1SM, a second separation layer 2SM, and a third separation layer 3SM. However, a sub-separation region (not shown) in the plug region 61 corresponding to the portion of the separation layer SM that contacts the plug may include the first separation layer 1SM, the second separation layer 2SM, and the third separation layer 3SM. Other portions of the separation layer SM may include the second separation layer 2SM and the third separation layer 3SM.

[0068] The structure of the plug region 61 of the contact source line SL will be described below.

[0069] Figure 8 This is a layout diagram showing the structure of the plug region 61 in contact with the source line SL according to one embodiment of the present disclosure.

[0070] Reference Figure 5 and Figure 8The first main plug 1Pm, the second main plug 2Pm, and the plug separation pattern SP can be located in the plug region 61 of the contact source line SL. The plug separation pattern SP can include an air gap AG and a separation layer SM. The separation layer SM can include sub-separation regions SMs that contact the first sub-plugs 1Ps to the fourth sub-plugs 4Ps. The sub-separation regions SMs can include a third separation layer 3SM, a second separation layer 2SM, and a first separation layer 1SM. The second separation layer 2SM and the third separation layer 3SM can be included in the region of the separation layer SM other than the sub-separation regions SMs. However, this is limited to the plug region 61 of the contact source line SL. For example, in the plug region of the contact source line SL, the separation layer SM other than the sub-separation regions SMs can include both the second separation layer 2SM and the third separation layer 3SM other than the first separation layer 1SM. In other regions, the separation layer SM can include all of the first separation layer 1SM, the second separation layer 2SM, and the third separation layer 3SM. In other words, in the sub-separation regions SMs, the first separation layer 1SM overlaps with the first sub-plug 1Ps and the second sub-plug 2Ps.

[0071] Figure 9 This is a perspective view showing the structure of a slit and a storage block according to one embodiment of the present disclosure.

[0072] Reference Figure 9 The nth memory block BLKn with a three-dimensional structure may include a plurality of sub-plugs 1Ps to 4Ps extending vertically to a substrate (not shown). For example, the first sub-plug 1Ps and the second sub-plug 2Ps may be separated from each other by a plug separation pattern SP, and the third sub-plug 3Ps and the fourth sub-plug 4Ps may also be separated from each other by a plug separation pattern SP.

[0073] The slot SLT formed between memory blocks can extend in a direction perpendicular to the substrate (not shown) and in the X direction. The slot SLT may include a source contact SC and a slot isolation layer IS.

[0074] Figures 10A to 10Q This is a layout diagram illustrating a method for manufacturing a memory device according to one embodiment of the present disclosure. Figures 11A to 11Q This is a cross-sectional view illustrating a method for manufacturing a memory device according to one embodiment of the present disclosure.

[0075] Figures 11A to 11Q These are shown separately along Figures 10A to 10Q The layout diagram of the cross section taken from line C1-C2.

[0076] Reference Figure 10A and Figure 11AA first source layer 1S, a sacrificial layer SF, and a second source layer 2S may be stacked on a lower structure (not shown). The lower structure (not shown) may include a substrate or peripheral circuitry. The first source layer 1S may serve as a source line and includes a conductive material. The second source layer 2S may have the same material as the first source layer 1S. For example, the first source layer 1S and the second source layer 2S may include conductive materials such as polysilicon, tungsten, or nickel. The sacrificial layer SF may include a material that has etch selectivity relative to the first source layer 1S. An etch stop layer ST may be formed in a portion of the sacrificial layer SF. During an etching process for forming a slit hole SLH in a slit region, the etch stop layer ST may be provided to prevent or mitigate over-etching. The etch stop layer ST may include a conductive material such as tungsten. During subsequent processes, to protect the first source layer 1S and the second source layer 2S, buffer layers may be further formed between the first source layer 1S and the sacrificial layer SF, and between the second source layer 2S and the sacrificial layer SF. For example, the buffer layer may include an oxide layer.

[0077] Reference Figure 10B and Figure 11B The first material layer 1M and the second material layer 2M can be alternately stacked over the second source layer 2S. For example, when the first material layer 1M is formed over the second source layer 2S, the second material layer 2M can be formed over the first material layer 1M, and the first material layer 1M can be formed over the second material layer 2M. The first material layer 1M may include an insulating material. For example, the first material layer 1M may include an oxide layer or a silicon oxide layer. The second material layer 2M may include a material that can be removed during subsequent processes. Therefore, the second material layer 2M may include a material with a different etch selectivity than the first material layer 1M. For example, the second material layer 2M may include a nitride layer. The first material layer 1M can be formed on both the top and bottom of a structure in which the first material layer 1M and the second material layer 2M are stacked.

[0078] Reference Figure 10C and Figure 11CA vertical via VH can be formed in the cell region of the memory block, exposing the first source layer 1S through the vertical via VH. For example, an etching process can be performed to remove a portion of the first material layer 1M, a portion of the second material layer 2M, a portion of the second source layer 2S, a portion of the sacrificial layer SF, and a portion of the first source layer 1S. As an etching process, a dry etching process can be performed, thereby forming the vertical via VH in a direction perpendicular to the substrate. The vertical via VH can be formed in the region used to form the main plug. The major axis of the vertical via VH can represent the Y direction and its minor axis can represent the X direction. When the etching process used to form the vertical via VH is terminated, the first source layer 1S can be exposed through the lower surface of the vertical via VH, and the first material layer 1M, the second material layer 2M, the second source layer 2S, and the sacrificial layer SF can be exposed through the side surfaces of the vertical via VH.

[0079] Reference Figure 10D and Figure 11D A main plug Pm can be formed in a vertical via VH. The main plug Pm may include a barrier layer BX, a charge trapping layer CT, a tunneling isolation layer TO, a channel layer CH, a core pillar CP, and a capping layer CAP. For example, the barrier layer BX can be formed along the inner surface of a vertical via VH having a cylindrical shape. The cylindrical shape of the barrier layer BX can be defined to fill a portion of the interior of the vertical via VH. The charge trapping layer CT can have a cylindrical shape along the inner surface of the barrier layer BX. The tunneling isolation layer TO can have a cylindrical shape along the inner surface of the charge trapping layer CT. The channel layer CH can have a cylindrical shape along the inner surface of the tunneling isolation layer TO. The core pillar CP can fill the interior surrounded by the channel layer CH. After forming the core pillar CP, an etching process can be performed to remove a portion of the upper region of the core pillar CP. The capping layer CAP can be formed in the region where the core pillar CP has been removed.

[0080] Reference Figure 10E and Figure 11E A separation hole SH can be formed to separate the main plug Pm in the Y-axis direction. The separation hole SH can be formed by an etching process that removes a portion of the main plug Pm. The etching process can be performed until the first source layer 1S in the cell region is exposed, thereby separating the channel layer CH included in the main plug Pm. When the etching process for forming the separation hole SH terminates, the first source layer 1S is exposed through the bottom surface of the separation hole SH, and the barrier layer BX, charge trapping layer CT, tunnel isolation layer TO, channel layer CH, core pillar CP, and capping layer CAP are exposed through the side surfaces of the separation hole SH. As an etching process, a dry etching process can be performed, thereby forming the separation hole SH in a direction perpendicular to the substrate. The main plug Pm can be divided into a first sub-plug 1Ps and a second sub-plug 2Ps through the separation hole SH.

[0081] Figures 10F to 10H and Figures 11F to 11H These are layout and cross-sectional views illustrating a method for manufacturing a separation layer SM according to one embodiment of the present disclosure.

[0082] Reference Figure 10F and Figure 11F A first separation layer 1SM can be formed in the separation hole SH. The first separation layer 1SM can have curved sidewalls. The first separation layer 1SM can have a cylindrical shape along the inner wall of the separation hole SH, without filling the separation hole SH. The first separation layer 1SM can include an insulating material, such as an oxide layer or a silicon oxide layer. In one embodiment, the first separation layer 1SM can protect the layers exposed through the side surface of the separation hole SH and can provide electrical resistance between the second separation layer 2SM and the first sub-plugs 1Ps to the fourth sub-plugs 4Ps. Furthermore, in one embodiment, the first separation layer 1SM can prevent source line conductive material from being introduced into the memory cell during the source line formation process to be performed in a subsequent process.

[0083] Reference Figure 10G and Figure 11G A second separation layer 2SM can be formed along the inner wall of the separation hole SH where the first separation layer 1SM is formed. The second separation layer 2SM may include a low-k material, such as a SiCN layer. To control the capacitance of the memory cell, the carbon (C) content of the second separation layer 2SM can be adjusted. For example, the capacitance of the second separation layer 2SM may be proportional to the concentration of carbon (C) included in the second separation layer 2SM. In one embodiment, the second separation layer 2SM can be configured to reduce interference between memory cells that are opposite each other and in which the separation layers SM are interposed. In one embodiment, the second separation layer 2SM, together with the first separation layer 1SM, can prevent source line conductive material from being introduced into the memory cell during the source line formation process to be performed in a subsequent process.

[0084] Reference Figure 10H and Figure 11H A third separation layer 3SM can be formed in the separation hole SH where the second separation layer 2SM is formed. The third separation layer 3SM can have curved sidewalls. The third separation layer 3SM can have a cylindrical shape along the inner wall of the second separation layer 2SM that does not fill the separation hole SH. The third separation layer 3SM can include an insulating material. For example, the third separation layer 3SM can include a silicon oxide layer or an oxide layer. In one embodiment, the third separation layer 3SM, together with the first separation layer 1SM and the second separation layer 2SM, can prevent source line conductive material from being introduced into the memory cell during the source line formation process to be performed in a subsequent process.

[0085] Reference Figure 10I and Figure 11IA barrier pattern PP can be formed over the entire structure. The barrier pattern PP can include a material with high step coverage to cover the top of the slit hole SLH and the top of the third separation layer 3SM before the interior of the separation holes SH and slit holes SLH, which are filled with the third separation layer 3SM, is filled. The barrier pattern PP can have an oxide layer with a step coverage higher than that of the first material layer 1M. Because materials with high step coverage have a faster deposition rate than ordinary materials, the top openings of the separation holes SH and the top openings of the slit holes SLH, which are filled with the third separation layer 3SM, can be sealed before deep holes such as the slit holes SLH and the separation holes SH are filled.

[0086] Reference Figure 10J and Figure 11J An etching process can be performed such that the barrier pattern PP formed in other areas is removed while retaining the barrier pattern PP in the top portion of the separation hole SH filled with the third separation layer 3SM. For example, a planarization process can be performed until the first material layer 1M or the capping layer CAP is exposed. When performing the planarization process, the barrier pattern PP can be removed from the top of the slot hole SLH, the top of the first material layer 1M, the top of the first sub-plugs 1Ps, and the top of the second sub-plugs 2Ps, and the barrier pattern PP can be retained in the separation hole SH filled with the third separation layer 3SM. As a result, the etch stop layer ST, the first material layer 1M, and the second material layer 2M can be exposed through the slot hole SLH.

[0087] Reference Figure 10K and Figure 11K An etching process can be performed to remove the etch stop layer ST exposed through the slit hole SLH. Since the sacrificial layer SF is exposed through the slit hole SLH after the etch stop layer ST is removed, an etching process can be performed to remove the sacrificial layer SF. When the sacrificial layer SF is removed, the barrier layer BX can be exposed between the first source layer 1S and the second source layer 2S. When the barrier layer BX is exposed, a wet etching process can be performed to remove the barrier layer BX, charge trapping layer CT, and tunnel isolation layer TO exposed between the first source layer 1S and the second source layer 2S through the slit hole SLH. An etching process for removing the charge trapping layer CT and the tunnel isolation layer TO can be performed until the channel layer CH is removed. Because a wet etching process is performed, the first separation layer 1SM exposed between the first source layer 1S and the second source layer 2S can be removed along with the barrier layer BX. However, since the first separation layer 1SM is protected by the first sub-plugs 1Ps to the fourth sub-plugs 4Ps, the first separation layer 1SM in the sub-separation regions SMs can be left unremoved.

[0088] Reference Figure 10L and Figure 11LA third source layer 3S can be formed in the region where the sacrificial layer SF, charge trapping layer CT, tunnel isolation layer TO, and first separation layer 1SM exposed through the slit hole SLH have been removed. The third source layer 3S can contact the channel layer CH at the bottom surface of the main plug Pm. The third source layer 3S can comprise the same material as the first source layer 1S or the second source layer 2S. For example, the third source layer 3S can comprise a conductive material such as polysilicon, tungsten, or nickel. Therefore, a source line SL consisting of the first source layer 1S to the third source layer 3S can be formed. The first separation layer 1SM to the third separation layer 3SM can be used to prevent the conductive material of the source line from being introduced into the memory cell.

[0089] Reference Figure 10M and Figure 11M An etching process can be performed to remove the second material layer 2M through a slit hole SLH. As an etching process, a wet etching process using an etchant for selective removal can be performed, so that the first material layer 1M can be retained while the second material layer 2M is removed.

[0090] Reference Figure 10N and Figure 11N A third material layer 3M can be formed in the region where the second material layer 2M has been removed. Since the third material layer 3M serves as the gate line GL, it can include a conductive material. For example, the third material layer 3M can include tungsten (W), cobalt (Co), nickel (Ni), molybdenum (Mo), silicon (Si), and polysilicon (Poly-Si). When the third material layer 3M is formed between the first material layers 1M, a stacked structure including the first material layers 1M and the third material layer 3M can be formed. When the third material layer 3M is formed between the first material layers 1M, it can also be formed on the surface of the slit hole SLH.

[0091] Reference Figure 10O and Figure 11O An etching process can be performed to remove the third material layer 3M formed on the surface of the slit hole SLH. An etching process can be performed to remove the third material layer 3M from the surface of the slit hole SLH. However, a portion of the third material layer 3M adjacent to the slit hole SLH between the first material layers 1M can also be removed.

[0092] Reference Figure 10P and Figure 11PA slot isolation layer IS can be formed on the surface of the slot hole SHL. The slot isolation layer IS may include an oxide layer or a silicon oxide layer. The slot isolation layer IS can be formed to cover the entire third material layer 3M exposed through the side surface of the slot hole SLH. The slot isolation layer IS can be formed at the bottom surface of the slot hole SLH. After forming the slot isolation layer IS, an etching process can be performed to expose the third source layer 3S through the bottom surface of the slot hole SLH. As the etching process, a dry etching process can be performed so that the slot isolation layer IS formed on the side surface of the slot hole SLH can be retained, and the slot isolation layer IS formed on the bottom surface of the slot hole SLH can be selectively removed.

[0093] Reference Figure 10Q and Figure 11Q A deposition process can be performed to form a source contact SC in the slit hole SLH. The source contact SC may include a conductive material. For example, the source contact SC may include doped polysilicon or tungsten. A slit isolation layer IS can be formed between the third material layer 3M for the gate line GL and the source contact SC. Therefore, the gate line GL included in the (n-1)th memory block BLK(n-1) and the nth memory block BLKn can be separated from each other.

[0094] Figure 12 This is a block diagram illustrating a solid-state drive (SSD) system 4000 of a memory device according to one embodiment of the present disclosure.

[0095] Reference Figure 12 The SSD system 4000 may include a host 4100 and an SSD 4200. The SSD 4200 can exchange signals with the host 4100 through a signal connector 4001 and can receive power through a power connector 4002. The SSD 4200 may include a controller 4210, multiple flash memory units 4221 to 422n, an auxiliary power supply 4230, and a buffer memory 4240.

[0096] The controller 4210 can control multiple flash memory devices 4221 to 422n in response to signals received from the host 4100. In one embodiment, the signals can be based on the interface between the host 4100 and the SSD 4200. For example, the signals can be defined by at least one of a variety of interfaces such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), Fast PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), WiFi, Bluetooth, and Non-Volatile Memory Fast (NVMe) interface.

[0097] Auxiliary power supply 4230 can be connected to host 4100 via power connector 4002. Auxiliary power supply 4230 can be supplied with or charged with power from host 4100. When power cannot be stably supplied from host 4100, auxiliary power supply 4230 can supply power to SSD 4200. In one embodiment, auxiliary power supply 4230 can be located inside or outside SSD 4200. For example, auxiliary power supply 4230 can be located in the motherboard and provide auxiliary power to SSD 4200.

[0098] Buffer memory 4240 can be used as a buffer memory for SSD 4200. For example, buffer memory 4240 can temporarily store data received from host 4100 or data received from multiple flash memories 4221 to 422n, or it can store metadata (e.g., a mapping table) of flash memories 4221 to 422n. Buffer memory 4240 can include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0099] Figure 13 This is a diagram illustrating a memory system 70000 using a memory device according to one embodiment of the present disclosure.

[0100] Reference Figure 13 The memory system 70000 may include a memory card or a smart card. The memory system 70000 may include a memory device 1100, a controller 1200, and a card interface 7100.

[0101] Memory device 1100 can be used with the above Figure 1 The memory device 100 shown is configured in the same manner.

[0102] The controller 1200 can control the data exchange between the memory device 1100 and the card interface 7100. According to one embodiment, the card interface 7100 may be, but is not limited to, a Secure Digital (SD) card interface or a Multimedia Card (MMC) interface.

[0103] Card interface 7100 can interface for data exchange between host 60000 and controller 1200 according to the protocol of host 60000. According to one embodiment, card interface 7100 can support Universal Serial Bus (USB) protocol and IC-USB protocol. Card interface 7100 can refer to hardware capable of supporting the protocol used by host 60000, software installed in the hardware, or signal transmission method.

[0104] When the memory system 70000 is connected to the host interface 6200 of the host 60000 (e.g., PC, tablet PC, digital camera, digital audio player, cellular phone, console video game hardware, or digital set-top box), the host interface 6200 can perform data communication with the memory device 1100 through the card interface 7100 and the controller 1200 in response to the control of the microprocessor 6100.

[0105] According to one implementation, the reliability of the memory device can be improved.

[0106] It will be apparent to those skilled in the art that various modifications can be made to the above-described examples of the embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is intended to cover all such modifications, provided they fall within the scope of the appended claims and their equivalents.

[0107] Cross-reference of related applications

[0108] This application claims priority to Korean Patent Application No. 10-2022-0063382, filed on May 24, 2022, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A memory device, the memory device comprising: A stacked structure including gate lines, wherein the gate lines are stacked in a vertical direction and wherein the gate lines are separated from each other; A main plug, which is included in the stacked structure and extends in the vertical direction of the stacked structure; A plug separation pattern, wherein the plug separation pattern separates the main plug into a first sub-plug and a second sub-plug; A gap, the gap being included in the plug separation pattern; and Separation layer, the separation layer surrounding the gap, The separation layer includes a first separation layer, a second separation layer, and a third separation layer.

2. The memory device according to claim 1, wherein, The gap is surrounded by the third separation layer, which has curved sidewalls. The second separation layer surrounds the curved sidewall of the third separation layer to have a curved sidewall, and The first separation layer surrounds the curved sidewall of the second separation layer.

3. The memory device according to claim 1, wherein, Each of the first separation layer and the third separation layer includes an insulating material.

4. The memory device according to claim 1, wherein, The second separation layer comprises a low-k material.

5. The memory device according to claim 4, wherein, The low-k material includes SiCN.

6. The memory device according to claim 5, wherein, The capacitance of the second separation layer is controlled by the concentration of carbon C included in the SiCN.

7. The memory device according to claim 1, wherein, The main plug includes a core post, a channel layer, a tunnel isolation layer, a charge trapping layer, and a barrier layer extending in the stacked structure.

8. The memory device according to claim 1, wherein, The first sub-plug and the second sub-plug are symmetrical about each other with respect to the plug separation pattern.

9. The memory device according to claim 1, wherein, The plug separation pattern extends in the main plug and the stacked structure.

10. The memory device according to claim 1, wherein, The gap and the first to the third separation layers are formed in the plug separation pattern to extend in the main plug and the stacked structure.

11. The memory device according to claim 1, wherein, The plug separation pattern includes a blocking pattern surrounded by the separation layer above the gap.

12. The memory device according to claim 1, wherein, The separation layer includes a sub-separation region that contacts the first sub-plug and the second sub-plug.

13. The memory device according to claim 12, wherein, Apart from the sub-separation region, the second separation layer is in direct contact with the source electrode line.

14. The memory device according to claim 13, wherein, The first separation layer overlaps with the first sub-plug and the second sub-plug.

15. The memory device according to claim 1, wherein, The gap constitutes an air gap.

16. The memory device according to claim 1, wherein, The gap contains gas.

17. A method of manufacturing a memory device, the method comprising the steps of: A layered structure is formed, wherein a first material layer and a second material layer are alternately layered in a vertical direction above a lower structure; A main plug is formed in the stacked structure, the main plugs being spaced apart from each other and arranged along the vertical direction of the stacked structure; Forming a slit through the stacked structure and a separation hole for separating the main plug; A first separation layer is formed on the inner surface of each of the separation holes; A second separation layer is formed on the inner surface of the first separation layer; A third separation layer is formed on the inner surface of the second separation layer; and A gap is formed in the third separation layer.

18. The method of claim 17, further comprising the step of: Remove the sacrificial layer exposed through the slit hole; The portion of the sacrificial layer that was removed was filled with a third material layer; Remove the second material layer exposed through the slit hole; A conductive layer is formed in the portion in which the second material layer has been removed; An insulating layer is formed on the side surface of the slit hole; as well as A source contact is formed in the slit hole where the insulating layer is formed.

19. The method of claim 17, wherein, The step of forming the gap includes the following steps: A blocking pattern is formed over the entire top of the stacked structure; and Remove the blocking pattern except for the blocking pattern formed above the third separation layer.

20. The method of claim 17, wherein, The first material layer includes an oxide layer, and The second material layer includes an oxide layer.

21. The method according to claim 17, wherein, The steps for forming the main plug include the following: Forming vertical holes through the first material layer and the second material layer; and A barrier layer, a charge trapping layer, a tunnel isolation layer, a channel layer, and a core pillar are formed along the inner wall of each of the vertical holes.

22. The method according to claim 17, wherein, Each of the first separation layer and the third separation layer includes an insulating material.

23. The method according to claim 17, wherein, The second separation layer comprises a low-k material.

24. The method according to claim 23, wherein, The low-k material includes SiCN.

25. The method according to claim 24, wherein, The capacitance of the second separation layer is controlled by the concentration of carbon C included in the SiCN.

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