Data processing system

Abstract

A data processing system comprises processing units 1, 2, 3, 10 and a communication bus 5 over which bus transactions can be performed that access a memory 6. The system comprises a codec 20 and the processing units 1, 2, 3, 10 can initiate bus transactions over the communication bus 5 that include the codec 20 accessing the memory 6.

Description

Technical Field

[0001] The techniques described herein relate to data processing systems, and more specifically to compression and decompression in data processing systems such as graphics processing systems. Background Technology

[0002] A graphics processing unit (GPU) typically performs graphics processing operations by processing data in an uncompressed form. When such an operation has produced specific output (e.g., a frame), the output data can be written to memory for storage before being further processed by the GPU.

[0003] To reduce the amount of data that needs to be transferred to and from memory, and the associated power costs of moving such data back and forth, the data can be compressed before being written to memory. This allows the data to be stored in a compressed format. Then, when the graphics processor needs the data for further processing, the compressed data is read from memory and decompressed, so that the data is then in a suitable format for the graphics processor to process.

[0004] The applicant believes there is still room for improvement regarding the compression and decompression arrangements in the graphics processing system. Summary of the Invention

[0005] In a first aspect, this application relates to a data processing system comprising: a processing unit; a codec operable to compress and decompress data; and a communication bus through which bus transactions for accessing memory are performed; wherein the processing unit is operable to initiate a bus transaction including the codec accessing the memory via the communication bus by: issuing a bus transaction request on the communication bus, the bus transaction request including a signal instructing the codec to access the memory; and the codec is operable to, in response to receiving the bus transaction request via the communication bus, determine whether to access the memory based on whether the bus transaction request includes a signal instructing the codec to access the memory, and when it is determined that the memory should be accessed, access the memory via the communication bus.

[0006] In a second aspect, this application relates to a codec operable to compress and decompress data, the codec comprising: a bus transaction initiation circuit configured to initiate a bus transaction via a communication bus to access memory; and a processing circuit configured to, in response to receiving a bus transaction request via the communication bus, determine whether to access the memory based on whether the bus transaction request includes a signal instructing the codec to access the memory, and, when it is determined that the memory should be accessed, cause the bus transaction initiation circuit to initiate a bus transaction via the communication bus to access the memory.

[0007] In a third aspect, this application relates to a method of operating a data processing system, the data processing system comprising: a processing unit; a codec operable to compress and decompress data; and a communication bus through which bus transactions for accessing memory are performed; wherein the processing unit is operable to initiate a bus transaction including the codec accessing the memory via the communication bus by: issuing a bus transaction request on the communication bus, the bus transaction request including a signal instructing the codec to access the memory; and the codec is operable to, in response to receiving a bus transaction request via the communication bus, determine whether the bus transaction request includes an instruction that the codec should access the memory. The method comprises: the processing unit initiating a bus transaction for the codec to access the memory via the communication bus by issuing a bus transaction request on the communication bus, the bus transaction request including a signal indicating that the codec should access the memory; and the codec, in response to receiving the bus transaction request via the communication bus, determining whether to access the memory based on whether the bus transaction request includes the signal indicating that the codec should access the memory, and accessing the memory via the communication bus when it is determined to access the memory.

[0008] In a fourth aspect, this application relates to a method of operating a codec capable of compressing and decompressing data, wherein the codec includes a bus transaction initiation circuit configured to initiate a bus transaction via a communication bus to access memory; the method includes: in response to receiving a bus transaction request via the communication bus, determining whether to access the memory based on whether the bus transaction request includes a signal indicating that the codec should access the memory, and when it is determined that the memory should be accessed, causing the bus transaction initiation circuit to initiate a bus transaction via the communication bus to access the memory.

[0009] In a fifth aspect, this application relates to a computer program product comprising computer software code that, when run on a data processing device, executes the methods described in accordance with the foregoing aspects. Attached Figure Description

[0010] Implementations of the technology described herein will now be described by way of example only, with reference to the accompanying drawings, wherein: Figure 1 A data processing system according to one embodiment of the technology described herein is shown; Figure 2 A data processing system operating according to various embodiments of the technology described herein is illustrated schematically; Figure 3A , Figure 3B and Figure 3C The memory layout of various embodiments according to the technology described herein is illustrated schematically; Figure 4A and Figure 4B A compressed data read transaction according to one embodiment of the technology described herein is illustrated schematically; Figure 5A and Figure 5B A compressed data write transaction is illustrated schematically according to one embodiment of the technology described herein; Figure 6A and Figure 6B A data processing system according to various embodiments of the technology described herein is illustrated schematically; and Figure 7 A codec unit according to one embodiment of the technology described herein is illustrated schematically.

[0011] Where appropriate in the accompanying drawings, similar reference numerals are used for similar parts. Detailed Implementation

[0012] A first embodiment of the technology described herein includes a data processing system, the data processing system comprising: Processing unit; Codec; and A communication bus through which bus transactions for accessing memory can be performed; The processing unit is operable to initiate bus transactions via the communication bus, including access to the memory by the codec; and The codec is operable to access the memory in response to the processing unit initiating such a bus transaction via the communication bus.

[0013] A second embodiment of the technology described herein includes a method for operating a data processing system, the data processing system comprising: Processing unit; Codec; and A communication bus through which bus transactions for accessing memory can be performed; The processing unit is operable to initiate bus transactions via the communication bus, including access to the memory by the codec; and The codec is operable to access the memory in response to the processing unit initiating such a bus transaction via the communication bus; The method includes: The processing unit initiates a bus transaction via the communication bus, during which the codec accesses the memory; and In response to the processing unit initiating the bus transaction via the communication bus, the codec accesses the memory.

[0014] The technology described herein relates to a data processing system, such as, and in one embodiment, a graphics processing system, which includes a codec unit capable of operating to compress and decompress data.

[0015] The system includes a processing unit, such as, and in one embodiment, a central processing unit (CPU) or a graphics processing unit (GPU), i.e., in one embodiment, capable of accessing memory via a communication bus (interconnect) by initiating bus transactions on the bus (interconnect). Therefore, the processing unit may, and in one embodiment, be capable of operating as a bus master. The bus transactions that the processing unit can initiate may, and in one embodiment, indeed include bus transactions in which the processing unit accesses the memory of the data processing system to read or write uncompressed data in the memory.

[0016] In the techniques described herein, in addition to initiating such "direct" bus transactions, for example, involving uncompressed data read or written by a processing unit, the processing unit is also able to initiate bus transactions where a (compressed) codec will access memory. As will be discussed in more detail below, these "codec bus transactions" may, and in one embodiment do, include codec access to memory to read or write compressed data in memory, or to read or write metadata associated with compressed data in memory.

[0017] Specifically, during a “codec” bus transaction triggered by the processing unit, the codec may, and in one implementation, perform: compressing the data provided by the processing unit and writing the compressed data to memory; or reading the compressed data from memory, decompressing the compressed data, and providing the decompressed data to the processing unit.

[0018] The applicant has recognized that it is possible to configure the data processing system such that processing units, such as CPUs and / or GPUs, can use bus transactions to communicate with and control the codecs. By using bus transactions to control the codecs, the codec units need to be accessible only via the communication bus, and therefore the integration with the processing units (or units) that require compression and decompression operations may not be as tight.

[0019] This allows for a more flexible arrangement of compression and decompression in data processing systems. For example, in the techniques described herein, multiple different processing units may, and in one implementation, use bus transactions to control the same single (e.g., external) codec, and similarly, a single processing unit may, and in one implementation, control multiple different (e.g., external) codecs that, for example, implement different encoding (compression) schemes in one implementation.

[0020] Furthermore, using bus transactions in the manner described herein provides this flexibility in a particularly straightforward and efficient way. For example, the applicant has recognized that relatively minor modifications to existing bus protocols such as AXI can enable the use of bus transactions to control codecs in the manner described herein.

[0021] Furthermore, in the techniques described herein, the processing unit may, and in one embodiment, control the codec via the same bus interface it uses for other, such as "direct" bus transactions. The processing unit may therefore be able, and in one embodiment, access compressed data in memory in substantially the same manner as it accesses uncompressed data in memory (e.g., in one embodiment, in a "random access" manner). Similarly, via the same single bus interface, the processing unit may be able to control multiple different codec units.

[0022] This means, for example, that the techniques described herein can reduce the overall hardware / silicon costs associated with performing compression and decompression operations in data processing systems. Furthermore, the overall power consumption of the system during compression and decompression operations can be reduced. This is generally advantageous, but can be particularly advantageous in resource-constrained contexts, such as in portable devices like mobile phones and tablets.

[0023] Therefore, it should be understood that the techniques described herein provide improved data processing systems.

[0024] The processing unit can be any suitable processing unit. For example, and in one embodiment, it can be a central processing unit (CPU), a graphics processing unit (GPU), a video processor, a sound processor, an image signal processor (ISP), a digital signal processor (DSP), a neural network processor, or a display controller. Other processing units are possible.

[0025] The processing unit can initiate bus transactions to access the memory (of the data processing system) via the communication bus. In one embodiment, the processing unit includes a bus interface (bus adapter) that communicates with the communication bus (interconnector), and via this bus interface, the processing unit can initiate bus transactions on the bus (interconnector). The processing unit should, and in one embodiment, be operable to: initiate a bus transaction by issuing a bus transaction request on the communication bus (interconnector); and in one embodiment, control the bus transactions initiated by the request. Therefore, the processing unit should, and in one embodiment, be operable to act as a bus master. Furthermore, the system should, and in one embodiment, indeed include memory accessible via the communication bus.

[0026] The memory can be any suitable and desired memory for storing any suitable (e.g., compressed and / or uncompressed (no compression)) data used and / or generated by the data processing system, such as and in one embodiment, image data, texture data, graphics processing fragments or vertex data, video data, sound data, neural network data, etc.

[0027] There may be one or more (e.g., many) different memories that can be accessed via a communication bus. In one embodiment, the memory is external memory (e.g., not located on the same chip as the processing unit and / or codec). For example, in one embodiment, the memory is the main (system) memory of the data processing system that can be accessed by the codec (and processing unit) via the same (system) bus.

[0028] The system may include a memory management unit (MMU) associated with the memory, which is operable to appropriately translate memory addresses (between logical and physical memory addresses).

[0029] A communication bus can be any suitable and desirable interconnect through which bus transactions for accessing (e.g., main) memory can be performed. The bus may be able to (during bus transactions) travel to and from (at least) memory to perform any suitable signal and data transfers, and for these purposes may include any suitable set of channels.

[0030] For example, a communication bus may include one or more channels for transmitting control data, and / or address data, and / or reading data, and / or writing data (data to be written). There may be separate (independent) channels for control data, address data, and "user" data, or the same channel may be used for two or more types of data, including control data, address data, and "user" data. Similarly, there may be separate (independent) channels for reading transactions and writing transactions, or the same channel may be used for both reading and writing transactions.

[0031] In one implementation, the communication bus includes a read address channel, a read data channel, a write address channel, a write data channel, and a write response channel, for example, and in one implementation, according to the Advanced Extensible Interface (AXI), as described in the AMBA (Advanced Microcontroller Bus Architecture) specification. Other channel arrangements are possible.

[0032] The system should be configured accordingly, and in one implementation, to perform bus transactions according to a bus protocol such as AXI. Processing units, buses, memory, codecs, etc., should be appropriately configured accordingly, and in one implementation, to operate according to the bus protocol (of the data processing system in question).

[0033] The codec can be any suitable encoder / decoder unit capable of compressing and decompressing data. The codec should, and in one embodiment, include encoder and decoder circuitry configured to compress and decompress data. The encoder and decoder circuitry may include encoder and decoder circuitry, and may include separate circuitry or may be formed at least partially by shared processing circuitry. The (compression) codec (of its encoder and decoder circuitry) should, and in one embodiment, be configured to compress and decompress data according to a suitable encoding scheme (or multiple encoding schemes). For example, the encoding scheme implemented by the codec can be lossless or lossy, where appropriate and desired.

[0034] Encoding schemes may include, for example, adaptive scalable texture compression (ASTC), as described in US 2012 / 0281007, the entire contents of which are incorporated herein by reference; or ARM framebuffer compression (AFBC), as described in US 2013 / 0036290 and US 2013 / 0198485, the entire contents of which are incorporated herein by reference.

[0035] In one implementation, as will be discussed in more detail below, the processing unit may instruct the codec, for example, on the encoding scheme and / or options that the codec should use, via a communication bus. Therefore, in one implementation, the codec (its encoder and decoder circuitry) is configurable via the communication bus.

[0036] The codec may reside outside the processing unit (e.g., not on the same chip as the processing unit). However, in one embodiment, the codec is provided on the same chip as the processing unit. Positioning the codec and processing chip on the same chip can reduce power consumption. The codec unit and the processing unit may be able to communicate via a communication bus (interconnect). In one embodiment (logically), the codec is located between the processing unit and (e.g., main) memory, for example, and in one embodiment, the codec is such that it can intercept bus transaction communication between the processing unit and the memory.

[0037] The codec can (logically) reside between the processing unit and the memory management unit, in which case the codec can access memory using logical memory addresses. Alternatively, the codec can (logically) reside between the memory and the memory management unit, in which case the codec can access memory using physical memory addresses.

[0038] The codec can be a standalone module connected to a bus (interconnector) via, for example, a bus interface. Alternatively, the codec can be integrated into the bus (interconnector).

[0039] In one embodiment, the codec (and the processing unit in one embodiment) includes bus transaction initiation circuitry (e.g., a bus interface) configured to initiate bus transactions via a communication bus to access memory. In one embodiment, the codec is operable to access memory in such a way that the codec's bus transaction initiation circuitry initiates a bus transaction to access memory via the communication bus. Therefore, in one embodiment, this arrangement effectively enables the codec to initiate a (second) bus transaction to access memory in response to receiving a (first) bus transaction initiated by the processing unit.

[0040] It is believed that the very concept of a codec being able to initiate bus transactions in this manner could be novel and inventive.

[0041] Therefore, another embodiment of the technology described herein includes a codec comprising: A bus transaction initiation circuit, configured to initiate a bus transaction via a communication bus to access memory; and A processing circuit configured to, in response to receiving a request via the communication bus for the codec to access the memory, cause the bus transaction initiation circuit to initiate a bus transaction via the communication bus to access the memory.

[0042] Another embodiment of the technology described herein includes a method for operating a codec, the codec including a bus transaction initiation circuit configured to initiate a bus transaction via a communication bus to access memory; the method includes: In response to receiving a request via the communication bus for the codec to access the memory, the bus transaction initiation circuit initiates a bus transaction via the communication bus to access the memory.

[0043] These implementations may include, as appropriate, one or more or all of the optional features described herein. For example, in one implementation, the codec is configurable via a communication bus. Thus, in one implementation, and as will be discussed in more detail below, in response to the request, the codec (its encoder and decoder circuitry) is configured (processing circuitry) to compress or decompress data, for example, and in one implementation, according to (encoding) parameters and / or attributes indicated by the request. In one implementation, memory access includes: reading compressed data to be decompressed, or writing already compressed data.

[0044] As discussed above, providing a codec that can be controlled via bus transactions facilitates the control of the same single codec by multiple different processing units, as well as the control of multiple different codecs by a single processing unit. Therefore, in one embodiment, the system includes one or more processing units, and in another embodiment, it includes a plurality of processing units, each of which can trigger a codec to access memory in the manner described herein. In one embodiment, the system includes one or more codecs, and in another embodiment, it includes a plurality of codecs, each of which can be triggered by one or more processing units to access memory in the manner described herein. In the case of multiple codecs, each codec unit in one embodiment is configured to compress and decompress data in different ways, for example, according to different encoding schemes.

[0045] As discussed above, in one embodiment, the processing unit is also capable of initiating bus transactions via the communication bus, including processing unit access to memory (while the codec does not access memory), such as direct memory access (DMA) transactions, in one embodiment by issuing an appropriate bus transaction request on the communication bus (e.g., the control or address channel of the communication bus). (The processing unit should therefore be, and in one embodiment, capable of, accessing memory via the communication bus (during a bus transaction).) In one embodiment, such a “direct” bus transaction includes: the processing unit accessing memory to write data to memory; and / or the processing unit accessing memory to read data from memory. In this case, the data read from or written to memory is in an uncompressed form in one embodiment.

[0046] The processing unit is also operable to initiate bus transactions via the communication bus, including codec access to memory. In one embodiment, the bus transaction is initiated by issuing an appropriate bus transaction request on the communication bus (e.g., the control or address channel of the communication bus) that triggers appropriate action (operation) of the codec. In other words, in one embodiment, the codec can be triggered to access memory by (receiving) an appropriate bus transaction request issued by the processing unit. Therefore, the codec unit may be, and in one embodiment, operable to act as a bus slave device. Furthermore, the codec should be, and in one embodiment, operable to access memory (during a bus transaction) via the communication bus.

[0047] In one implementation, the processing unit may (at least) initiate a "codec" bus transaction (wherein, in response to a bus transaction request from the processing unit, the codec accesses memory), the "codec" bus transaction including: the codec accessing memory to write data to memory; and / or the codec accessing memory to read data from memory. In this case, the data read from or written to memory is in compressed form in one implementation.

[0048] In one implementation, and as will be discussed in more detail below, the processing unit may also or alternatively (and in one implementation as well) initiate a “codec bus transaction” that includes codec accessing memory to read (only) metadata from memory; and / or (only) writing metadata to memory (in one implementation, regarding and for metadata associated with compressed data).

[0049] Therefore, in one embodiment, the processing unit is operable to initiate (“direct”) bus transactions including processing unit access to memory, in one embodiment to read or write uncompressed data, and to initiate (“codec”) bus transactions including codec access to memory, in one embodiment to read or write compressed data and / or metadata associated with the compressed data.

[0050] The processing unit can initiate “codec” bus transactions in any appropriate and desired manner. In one embodiment, the processing unit may issue an indication that the bus transaction involves compressed data (and therefore should include codec access to memory), and in another embodiment, the codec appropriately responds to such indication (by appropriately accessing memory during the bus transaction).

[0051] Such "compressed data" instructions issued by the processing unit can take any suitable form. For example, a bus transaction request initiating a "codec" bus transaction may include an instruction that the request pertains to compressed data, and the codec may respond appropriately on that basis.

[0052] In one implementation, the processing unit may issue a specific (in one selected implementation, in a predetermined implementation) signal indicating that the associated bus transaction involves compressed data (and therefore should include codec access to memory). Correspondingly, in one implementation, in response to receiving such a “compressed data” signal from the processing unit, the codec responds appropriately (accesses memory).

[0053] Such “compressed data” signals should be, and in one implementation, appropriately defined in the bus protocol. “Compressed data” signals may, for example, be issued and transmitted on and through any appropriate channel of the communication bus (such as the control or address channel of the communication bus), along with other control information.

[0054] In one implementation, the processing unit may instruct whether a bus transaction request should trigger a codec to access memory. The processing unit may, for example, issue a "compressed data" signal when the bus transaction request involves compressed data, and not issue such a signal (and, for example, issue a different signal) when the bus transaction request does not involve compressed data (e.g., when it involves uncompressed data). Furthermore, in cases where many different codecs may exist, the "compressed data" signal may indicate the specific codec that should be triggered to access memory.

[0055] Correspondingly, in one embodiment, the codec determines whether it should access memory in response to a received bus transaction request, based on whether the request instructs (e.g., by including appropriate signals) that the codec should do so (e.g., whether the request is indicated to be related to compressed data). In one embodiment, when it is determined that the codec should access memory in response to a received bus transaction request, the codec accesses memory as appropriate.

[0056] However, in one implementation, the codec does not access memory when it has not yet been determined (as opposed to determining) that the codec should access memory. The codec may (completely) not respond to bus transaction requests that do not indicate that the codec should respond (not indicated as being related to compressed data). However, in one implementation, the codec is capable of operating to forward (via the communication bus) any bus transaction request that does not indicate that the codec should respond (e.g., not indicated as being related to compressed data), for example, and in one implementation, such that the forwarded request can, via the communication bus (interconnector), appropriately reach and trigger other codecs (if present) or other components of the system.

[0057] Therefore, in one embodiment, a codec includes bypass circuitry capable of operating to forward (via the communication bus) received bus transaction requests that do not instruct the codec to respond to (e.g., are not indicated to be related to compressed data). However, in other embodiments, the system may be configured such that the codec only receives bus transaction requests to which the codec should respond, for example, allowing requests not intended for the codec to bypass the codec.

[0058] In one implementation, the codec is operable to: determine whether the codec should access memory in response to a received bus transaction request; access memory when it is determined that the codec should access memory in response to a received bus transaction request; and forward the received bus transaction request (through the communication bus) without accessing memory when it is not determined that the codec should access memory in response to a received bus transaction request.

[0059] In addition to being able to indicate that a bus transaction should involve a codec, the processing unit should be able, and in one embodiment, be able to, via the communication bus to instruct the codec to perform operations during a bus transaction, such as, in one embodiment, instructing the codec to read or write data. Correspondingly, as already stated, the codec should, and in one embodiment, be configurable via the communication bus.

[0060] Whether the codec should read or write data can be indicated by the processing unit in any appropriate and desired manner. For example, when the codec is about to read data, the processing unit may issue a "compressed data" signal on the communication bus, and when the codec is about to write data, a different "compressed data" signal may be issued on the communication bus. In one embodiment, the communication bus includes separate read and write channels, and when the codec is about to read compressed data, the processing unit issues a "compressed data" signal on the read (e.g., control or address) channel, and when the codec is about to write compressed data, the processing unit issues a "compressed data" signal on the write (e.g., control or address) channel (and the codec is configured to respond accordingly).

[0061] In one embodiment, as described above, when the processing unit instructs the codec to read compressed data from memory, in response, the codec reads the compressed data from memory, decompresses the read compressed data to produce decompressed data, and provides the decompressed data to the processing unit via the communication bus. Therefore, in one embodiment, the processing unit is operable to initiate a (“codec”) bus transaction, which includes the codec reading compressed data from memory, decompressing the compressed data to produce decompressed data, and providing the decompressed data to the processing unit via the communication bus. In one embodiment, the processing unit issues appropriate instructions (e.g., signals) on the communication bus.

[0062] Similarly, in one embodiment, when the processing unit instructs the codec to write compressed data to memory, the codec, in response, compresses the data provided by the processing unit via the communication bus to produce compressed data and writes the compressed data to memory. Thus, in one embodiment, the processing unit is operable to initiate a (“codec”) bus transaction, which includes the codec compressing the data provided by the processing unit via the communication bus to produce compressed data, and the codec writing the compressed data to memory. In one embodiment, the processing unit issues appropriate instructions (e.g., signals) on the communication bus.

[0063] To facilitate this, in one embodiment, the processing unit may instruct the codec via a communication bus on the encoding parameters and / or attributes that the codec should use when compressing uncompressed data or when decompressing compressed data to produce decompressed data. The processing unit may, for example, in one embodiment, indicate the encoding scheme that should be used.

[0064] Similarly, in one implementation, the processing unit may instruct the codec via a communication bus on parameters and / or attributes of the uncompressed data to be compressed by the codec, or parameters and / or attributes of the decompressed data to be generated by the codec. The indicated parameters and / or attributes can be any suitable parameters or attributes, such as data representation parameters and / or attributes, such as RGB / RGBA / YUV, number of components, number of bits (per component), floating-point / unsigned / signed integers, etc.

[0065] In one implementation, these indications are in the form of one or more signals, which the processing unit may issue on a communication bus (e.g., a control or address channel of the communication bus) along with other control data, and in one implementation, these signals are defined in a bus protocol.

[0066] Therefore, in one embodiment, the processing unit is operable to initiate a bus transaction via a communication bus, the bus transaction including a codec: receiving information from the processing unit via the communication bus indicating parameters and / or attributes to be used when compressing or decompressing data; and compressing or decompressing the data according to the indicated parameters and / or attributes. This information may, for example, be in the form of a compression descriptor. In one embodiment, in response to receiving this information, the codec (its encoder and decoder circuitry) is configured to compress or decompress the data according to the parameters and / or attributes indicated by the information.

[0067] Therefore, one embodiment of the technology described herein includes a data processing system, the data processing system comprising: Processing unit; Codecs including encoder and decoder circuits; and A communication bus through which bus transactions for accessing memory can be performed; The processing unit is operable to initiate bus transactions via the communication bus, the bus transactions including: Through the communication bus, the processing unit sends signals instructing the codec to access the memory, as well as information indicating the parameters and / or attributes the codec will use when compressing or decompressing data; and In response to receiving the signal via the communication bus, the codec configures the encoder and decoder circuits to compress or decompress data according to parameters and / or attributes indicated by the information.

[0068] One embodiment of the technology described herein includes a method for operating a data processing system, the data processing system comprising: Processing unit; Codecs including encoder and decoder circuits; and A communication bus through which bus transactions for accessing memory can be performed; The method includes: The processing unit initiates a bus transaction via the communication bus, the bus transaction including: Through the communication bus, the processing unit sends signals instructing the codec to access the memory, as well as information indicating the parameters and / or attributes the codec will use when compressing or decompressing data; and In response to receiving the signal via the communication bus, the codec configures the encoder and decoder circuits to compress or decompress data according to parameters and / or attributes indicated by the information.

[0069] These implementations may include, as appropriate, any one or all of the optional features described herein. For example, a bus transaction may include a codec: decompressing data and returning the decompressed data to the processing unit; or compressing data and writing the compressed data to memory.

[0070] The "codec" bus transaction request issued by the processing unit on the communication bus may include any other suitable information. In one embodiment, the processing unit may issue an indication of the memory address that the codec should access and / or information that can determine the memory address that the codec should access, and in response to receiving the memory address indication via the communication bus, the codec accesses the memory address (and, for example, reads compressed data from or writes compressed data thereto) based on the memory address indication. In one embodiment, such a memory address indication is in the form of a signal that the processing unit may issue on the communication bus (e.g., the control or address channel of the communication bus), and the codec may receive the signal via the communication bus, and the signal is in one embodiment defined by the bus protocol.

[0071] The memory address indication signal issued by the processing unit can directly indicate to the codec the memory address in the memory that the codec should access. For example, the memory address indication signal may include an indication of an actual memory address to be accessed.

[0072] In one implementation, the memory address indication signal includes information that a codec can use to determine a memory address to be accessed in the memory.

[0073] For example, where the data array is divided into multiple blocks and the compressed data of each block is stored in a corresponding memory location in memory, the corresponding memory location can be determined based on the location within the array represented by the corresponding block (e.g., as described in US 2013 / 0036290 and / or US 2013 / 0198485). The memory address indication signal can include an indication of the location within the data array from which the codec can determine a corresponding memory address to be accessed, for example, in the form of an indication of a “base” address of a block set and an indication of an index of a block within that block set.

[0074] For example, indirectly indicating a memory address in this manner reduces the amount of information required to indicate a memory address to be accessed by transmitting it between the processing unit and the codec via the communication bus, compared to explicitly indicating both the "base" memory address and the "block" memory address. For instance, and in one embodiment, the block index may be indicated by one or more least significant bits of the address information transmitted via the communication bus.

[0075] The memory address indication signal issued by the processing unit on the communication bus may include all the information needed by the codec to determine the memory address in the memory from which the codec should access to read compressed data (or write compressed data).

[0076] For example, in the case where the memory address indication signal indicates a base address and an index, there may be an implicit relationship between the index and the memory address offset relative to the base address, such that each index "hints" at a specific memory address offset relative to the base address, and that the (codec) can determine the memory address to be accessed (only) from the information in the memory address indication signal (and the knowledge of the "implicit" relationship). For example, and in one embodiment, this could be a case where adjacent memory space regions ("blocks") are divided into fixed-size sub-regions, where each sub-region is associated with a corresponding index.

[0077] In one implementation, compressed data may be written to memory along with information that the codec can (later) use to determine the (e.g., first) memory address where the compressed data has been written. In this case, the memory address indication signal issued by the processing unit on the communication bus may include less information than all the information the codec needs in order to determine the memory address in the memory from which the codec should access to read the compressed data.

[0078] Therefore, in one implementation, when compressed data is written to memory, the codec writes associated memory address information to memory, which can be used to determine the memory address where the compressed data is stored; and when compressed data is read from memory, the associated memory address information is read from memory, and the read memory address information is used to determine the memory address from which the compressed data is read.

[0079] The memory address information can be provided in any suitable and desired form. In one embodiment, compressed data is stored in memory in association with a header (where the compressed data is “text” data associated with (and for) its respective header), and the memory address information of the compressed data is stored in the header associated with the compressed data.

[0080] A set of neighboring memory addresses can be assigned to a header, which is adjacent to, for example, a set of neighboring memory addresses assigned to the associated text data, and is located before or after it.

[0081] In one implementation, the text data of multiple blocks are stored together, and the corresponding headers of these blocks are stored together. Therefore, in one implementation, with all header data stored in a single memory area and all text data stored in a single text data area, there will be multiple corresponding sets of associated headers and text data. In one implementation, for each (in one implementation, a fixed-size) "block," there is a corresponding separate "header" and "text" memory area. Other arrangements are possible.

[0082] In the case of using a header, in one embodiment, a memory address indication signal issued by the processing unit on the communication bus indicates the memory address (e.g., a first memory address) of the header associated with the compressed data to be accessed (wherein, the codec then, for example and in one embodiment, reads the header and uses the memory address information in the header to access the compressed data itself). Therefore, the codec can read header information from the memory address indicated by the memory address indication signal issued by the processing unit, or write header information to that memory address.

[0083] The header information may include any suitable information that can be used to determine the memory address where the compressed data is stored, such as the memory address of the associated text data. The header data may, for example, include the size of the associated text data in one embodiment.

[0084] In one embodiment, the header information includes memory address offset information indicating a memory address offset relative to the memory address of the header, which can be applied to the memory address of the header to determine the memory address in memory accessible to the codec for reading compressed data. Therefore, in one embodiment, the codec: in response to receiving a memory address indication signal indicating the memory address (and in one embodiment, an index) of the header associated with the compressed data to be read, determines the memory address offset from the memory address offset information in the header, which indicates a memory address offset relative to the memory address of the header; and determines the memory address of the compressed data to be read from the memory address of the header and the determined memory address offset (and in one embodiment, an index).

[0085] Correspondingly, in one embodiment, in response to receiving a memory address indication signal indicating the memory address of a header associated with the compressed data to be written, the codec writes memory address offset information indicating the memory address offset between the compressed data and the memory address of the header into the header.

[0086] It is believed that the concept of addressing compressed data using an offset relative to the memory address of the header associated with the compressed data could be novel and inventive in itself.

[0087] Therefore, another embodiment of the technology described herein includes a data processing system comprising: Memory, used to store compressed data; and The processing circuit is configured as follows: When reading compressed data associated with the header from memory, the memory address of the compressed data is determined based on the memory address of the header and memory address offset information within the header, where the memory address offset information indicates the memory address offset relative to the header memory address of the compressed data; and When compressed data associated with the header is written to memory, memory address offset information is written to the header, which indicates the memory address offset relative to the header memory address of the compressed data.

[0088] Another embodiment of the technology described herein includes a method for operating a data processing system, the data processing system including a memory for storing compressed data; the method includes: When reading compressed data associated with the header from memory, the memory address of the compressed data is determined based on the memory address of the header and memory address offset information within the header, where the memory address offset information indicates the memory address offset relative to the header memory address of the compressed data; and When compressed data associated with the header is written to memory, memory address offset information is written to the header, which indicates the memory address offset relative to the header memory address of the compressed data.

[0089] These implementations may include any one or more, or all, of the optional features described herein, as appropriate. For example, the processing unit may indicate a memory address, and the codec may determine (and access) the memory address. In one implementation, during a bus transaction triggered by the processing unit, the codec may write or read the memory address offset information in the header. It should be understood that the memory address signaling arrangement used should correspond to the specific arrangement used for compressed data in memory.

[0090] In one implementation, as already described, adjacent memory space regions (“blocks”) are divided into fixed-size sub-regions, each sub-region being associated with a corresponding index. In this case, one (e.g., the first or last) sub-region may be reserved for header data, and each of the other sub-regions may be reserved for a corresponding block of compressed (text) data. Alternatively, all sub-regions may be reserved for corresponding blocks of compressed data, for example, in the absence of a header.

[0091] In this scenario, in one implementation, there is an implicit relationship between the index and the memory address offset relative to the base (e.g., first) address of the "block". Therefore, in one implementation, the memory address indication signal indicates the base address of the "block" and the index indicating one of the sub-regions within that "block". In this scenario, the codec may be able to determine the (e.g., first) memory address of the sub-region from the base (e.g., first) address of the block and the sub-region index within that block (and based on the "implicit" relationship between the index and the sub-region memory address offset) (and based on header information (if present)).

[0092] As described above, in one embodiment, in addition to (or instead) being able to initiate a (“codec”) bus transaction that includes the codec reading the compressed data itself, the processing unit is able to operate to initiate a (“codec”) bus transaction that includes the codec: reading metadata associated with the compressed data from memory; and in one embodiment, providing the read metadata to the processing unit.

[0093] Therefore, one embodiment of the technology described herein includes a data processing system, the data processing system comprising: Processing unit; Codec; and A communication bus through which bus transactions for accessing memory can be performed; The processing unit is operable to initiate bus transactions via the communication bus, the bus transactions including the codec reading metadata associated with compressed data from the memory without reading the compressed data, and returning the read metadata to the processing unit; and The codec is operable to read metadata associated with compressed data from the memory without reading the compressed data in response to the processing unit initiating such a bus transaction via the communication bus, and to return the read metadata to the processing unit.

[0094] One embodiment of the technology described herein includes a method for operating a data processing system, the data processing system comprising: Processing unit; Codec; and A communication bus through which bus transactions for accessing memory can be performed; The processing unit is operable to initiate bus transactions via the communication bus, the bus transactions including the codec reading metadata associated with compressed data from the memory without reading the compressed data, and returning the read metadata to the processing unit; and The codec is operable to read metadata associated with compressed data from the memory without reading the compressed data in response to the processing unit initiating such a bus transaction via the communication bus, and to return the read metadata to the processing unit. The method includes: Through the communication bus, the processing unit initiates a bus transaction, wherein the codec reads metadata associated with the compressed data from the memory without reading the compressed data itself, and returns the read metadata to the processing unit; and In response to the processing unit initiating the bus transaction via the communication bus, the codec reads metadata associated with the compressed data from the memory without reading the compressed data, and returns the read metadata to the processing unit.

[0095] These implementation schemes may include any one or more, or all, of the optional features described herein, as appropriate.

[0096] In these implementations, metadata is data representing one or more attributes of associated compressed data. For example, metadata may represent an associated uncompressed data value (which has been compressed to produce the associated compressed data) and is derived from that associated uncompressed data value in one implementation. Thus, in one implementation, metadata can provide information about data that has been compressed without extracting and decompressing the data.

[0097] In one implementation, the arrangement enables the processing unit to initiate (“codec”) bus transactions, whereby the codec reads (and returns) only the metadata associated with the compressed data via the communication bus, without reading (or returning) the compressed data itself.

[0098] To facilitate these arrangements, the processing unit should be able, and in one embodiment, via a communication bus, instruct the codec that it should (only) access metadata. In one embodiment, via the communication bus, the codec can instruct the codec whether it should access compressed data or metadata associated with compressed data. This can be implemented in any suitable and desirable manner.

[0099] In one implementation, the processing unit is operable to issue a “compressed data” signal on the communication bus indicating that compressed data should be accessed, and to issue a different “compressed data” signal on the communication bus indicating that (only) metadata associated with the compressed data should be accessed (and the codec is configured to respond accordingly).

[0100] Metadata can be stored in memory in any suitable and desired manner. In cases where compressed data is stored in memory as body data associated with a header (e.g., as discussed above), in one embodiment, metadata is stored in the header of the compressed data in question.

[0101] Therefore, in one embodiment, the processing unit is capable of operating to initiate a (“codec”) bus transaction, which includes the codec reading a header (in which metadata is read), in one embodiment not reading the associated body data (or other header data, if present), and in one embodiment providing the header (in which metadata is read) (in one embodiment, no body data (or other header data)) to the processing unit via a communication bus.

[0102] In one implementation, if the codec cannot read such metadata in response to a request to read metadata from the processing unit, for example because it does not exist in memory, the codec returns an indication to the processor that it cannot read the metadata.

[0103] Once the metadata has been returned to the processing unit via the communication bus, the processing unit can use the metadata in any appropriate and desired manner.

[0104] In one implementation, the processing unit uses metadata associated with the compressed data to determine whether the compressed data should be decompressed. Therefore, in one implementation, when the metadata associated with the compressed data indicates that the compressed data should be decompressed, the compressed data is decompressed (only) by the codec.

[0105] For example, and in one implementation, metadata is used for image compositing purposes. In this case, a display controller that synthesizes an image for display by combining image data from different layers (e.g., stored in different compressed buffers in memory) can use the metadata provided by the codec to determine whether it is necessary to read and decompress compressed data for a particular layer to generate the final synthesized image.

[0106] For example, if the metadata indicates that image elements are transparent, there is no need to determine the actual color values ​​of these image elements, since they will not affect the final composite image. Similarly, it may not be necessary to read and decompress the image data of the layers behind opaque image elements. Likewise, if the metadata indicates that image elements are all the same color and specifies that color, the specified color can be used without decompressing the associated compressed data.

[0107] Therefore, in one implementation, the metadata indicates whether all elements of a compressed set of image elements are (fully) transparent and / or (fully) opaque and / or the same color, and in another implementation, whether they are the same color. Then, in one implementation, when it is appropriate to do so (as indicated by the metadata), the compressed image data is decompressed (only) by the codec.

[0108] Therefore, in one embodiment, in response to a request from the processing unit, the codec (only) returns metadata to the processing unit via the communication bus, and then, in another embodiment, the processing unit uses the returned metadata to determine whether the compressed data associated with the metadata should be decompressed. When it is determined that the compressed data should be decompressed, in one embodiment, the processing unit issues a further request to the codec via the communication bus to read and decompress the compressed data, and in response, the codec reads and decompresses the compressed data and returns the decompressed data to the processing unit via the communication bus. When it is determined that the compressed data should not be decompressed, in one embodiment, the processing unit does not issue such a request, and therefore, the codec does not read or decompress the compressed data.

[0109] Although the above describes the codec reading metadata, the processing unit may also, or alternatively, initiate bus transactions involving the codec writing metadata associated with compressed data.

[0110] Therefore, in one embodiment, the processing unit is operable to initiate a bus transaction (“codec”) via a communication bus, which includes the codec writing metadata associated with compressed data to memory.

[0111] Similarly, although the above describes metadata that indicates whether compressed data should be decompressed and is used to determine whether compressed data should be decompressed, metadata can indicate any other suitable data attributes and be used for any other suitable purpose.

[0112] For example, and in one implementation, metadata is used for error detection purposes. Errors may occur, for example, due to errors during compression or decompression, due to corruption or overwriting of stored compressed data, or due to errors in data transmitted via a communication bus (interconnector).

[0113] In this context, in one implementation, the metadata includes a "signature" that represents the associated compressed data and, in one implementation, indicates the corresponding (e.g., uncompressed or decompressed) data values ​​derived from or based on those data values. Such a "signature" may include, for example, and in one implementation, any suitable set of derived information that can be considered to represent those data values, such as checksums, CRCs, or hash values ​​derived from those data values. Suitable signatures would include: standard CRCs, such as CRC32; or other forms of signatures, such as MD5, SHA1, etc.

[0114] In one implementation, metadata including a signature (e.g., a checksum) is generated based on the uncompressed data value. The uncompressed data is then compressed, and the signature and compressed data are stored in memory in association with each other. Then, when the compressed data is decompressed, the signature (e.g., the checksum) is used for error detection purposes. In this case, in one implementation, the signature (e.g., the checksum) is regenerated from the decompressed data and compared with the signature (e.g., the checksum) stored in memory and generated from the uncompressed data. In one implementation, this comparison process is used to determine whether an error has occurred (or not).

[0115] Signatures (e.g., checksums) may also be generated from compressed data (and comparisons may be performed based on such signatures). For example, in the case of lossy compression schemes, signatures generated from compressed data may catch some types of errors.

[0116] The signature comparison process can be used to determine whether an error has occurred in any suitable and expected manner. For example, when the signatures match perfectly, it can be determined that no error has occurred, and when the signatures do not match perfectly, it can be determined that an error has occurred. Alternatively, when the signatures are sufficiently similar, it can be determined that no error has occurred, and when the signatures are not sufficiently similar, it can be determined that an error has occurred. In the case of lossy encoding schemes that generate signatures from uncompressed / decompressed data values, the latter approach may be appropriate, for example.

[0117] Therefore, in one implementation, the codec reads compressed data and metadata (e.g., signature) associated with the compressed data (which has already been generated from the associated uncompressed data) from memory, decompresses the compressed data to produce decompressed data, then (re)generates metadata (e.g., signature) from the decompressed data, compares the metadata associated with the compressed data (which has already been generated from the uncompressed data) with the metadata generated from the decompressed data, and uses this comparison process to detect errors.

[0118] These implementations can be carried out in any suitable and desired manner. For example, a processing unit can be configured to generate metadata (e.g., a signature) from uncompressed and / or decompressed data. Alternatively or concurrently, a codec can be configured to generate metadata (e.g., a signature) from uncompressed and / or decompressed data.

[0119] Therefore, in one embodiment, the processing unit includes metadata generation circuitry, and additionally or alternatively, the codec includes metadata generation circuitry. In one embodiment, this arrangement enables the metadata generation circuitry to generate metadata (e.g., signatures) from (uncompressed) data already generated by the processing unit and / or from (decompressed) data already decompressed by the codec.

[0120] Similarly, the comparison process of metadata (such as signatures) can be performed by the processing unit and / or by the codec.

[0121] In cases where the metadata (signature) generation and / or comparison processes are performed by the codec, in one implementation, the codec is triggered to do so by a suitable bus transaction request issued by the processing unit on the communication bus.

[0122] Furthermore, when the codec generates metadata (e.g., a signature) and / or provides metadata to the processing unit, the metadata can be transferred to the processing unit via a communication bus (interconnector) during a bus transaction triggered by the processing unit.

[0123] Therefore, in one embodiment, the processing unit is operable to initiate a bus transaction (“codec”) via a communication bus, the bus transaction including the codec providing the processing unit with metadata (e.g., a signature) (already generated by the codec and / or read from memory) via the communication bus, and in one embodiment, the processing unit uses the provided metadata (signature) to perform a comparison process (e.g., for error detection purposes).

[0124] Similarly, when the processing unit generates metadata (e.g., a signature), the metadata generated by the processing unit can be transmitted to the codec via a communication bus (interconnect) during a bus transaction triggered by the processing unit. In this case, the codec can compare the metadata (signature) provided by the processing unit and / or write the metadata (signature) provided by the processing unit into memory.

[0125] Therefore, in one embodiment, the processing unit is operable to initiate a bus transaction (“codec”) via a communication bus, the bus transaction including: the processing unit providing metadata (e.g., a signature) already generated by the processing unit to the codec via the communication bus; and in one embodiment, the codec writing the provided metadata to memory and / or using the provided metadata to perform a comparison process (e.g., for error detection purposes).

[0126] In one such implementation, metadata (e.g., signatures) is both generated and compared by the codec. This arrangement enables error detection in terms of data storage in memory and the compression and decompression processes. However, in another implementation, metadata (e.g., signatures) is both generated and compared by the processing unit. This arrangement also enables error detection in terms of data storage in memory and the compression and decompression processes, as well as in the data transfer to and from the processing unit via the communication bus.

[0127] Therefore, one embodiment of the technology described herein includes a data processing system, the data processing system comprising: Processing unit; Codec; and A communication bus through which bus transactions for accessing memory can be performed; The processing unit is operable to initiate a bus transaction via the communication bus, the bus transaction comprising: providing a signature representing associated compressed data to the codec via the communication bus; and the codec receiving the signature representing the associated compressed data from the processing unit via the communication bus; and The codec is operable to receive a signature representing associated compressed data from the processing unit via the communication bus in response to the processing unit initiating such a bus transaction through the communication bus.

[0128] One embodiment of the technology described herein includes a method for operating a data processing system, the data processing system comprising: Processing unit; Codec; and A communication bus through which bus transactions for accessing memory can be performed; The processing unit is operable to initiate a bus transaction via the communication bus, the bus transaction comprising: providing a signature representing associated compressed data to the codec via the communication bus; and the codec receiving the signature representing the associated compressed data from the processing unit via the communication bus; and The codec is operable to receive a signature representing associated compressed data from the processing unit via the communication bus in response to the processing unit initiating such a bus transaction through the communication bus. The method includes: The processing unit initiates a bus transaction via the communication bus, wherein, via the communication bus, the processing unit provides a signature representing associated compressed data to the codec, and via the communication bus, the codec receives the signature representing associated compressed data from the processing unit; and In response to the processing unit initiating the bus transaction via the communication bus, the codec receives a signature representing the associated compressed data from the processing unit via the communication bus.

[0129] These implementations may include any one or more, or all, of the optional features described herein. For example, in one implementation, the signature and / or associated compressed data is written to and / or read from memory by a codec.

[0130] The implementation scheme of the technology described herein includes a data processing system, which includes: Processing unit; Codec; and A communication bus through which bus transactions for accessing memory can be performed; The processing unit is operable to initiate a bus transaction via the communication bus, the bus transaction including: the codec providing a signature representing associated compressed data to the processing unit via the communication bus; and The codec is operable to provide a signature representing the associated compressed data to the processing unit in response to the processing unit initiating such a bus transaction via the communication bus.

[0131] One embodiment of the technology described herein includes a method for operating a data processing system, the data processing system comprising: Processing unit; Codec; and A communication bus through which bus transactions for accessing memory can be performed; The processing unit is operable to initiate a bus transaction via the communication bus, the bus transaction including: the codec providing a signature representing associated compressed data to the processing unit via the communication bus; and The codec is operable to provide a signature representing the associated compressed data to the processing unit in response to the processing unit initiating such a bus transaction via the communication bus. The method includes: The processing unit initiates a bus transaction via the communication bus, wherein the codec provides a signature representing the associated compressed data to the processing unit via the communication bus; and In response to the processing unit initiating the bus transaction via the communication bus, the codec provides the processing unit with a signature representing the associated compressed data via the communication bus.

[0132] These implementations may include any one or more, or all, of the optional features described herein. For example, in one implementation, the signature and / or associated compressed data is written to and / or read from memory by a codec.

[0133] In these implementations, the same signature (e.g., checksum) generation process can (always) be used, or the signature generation process can vary. For example, different seeds can be used by different processing units, or whenever data is written to a compressed buffer. In one such implementation, each of the many processing units is associated with a corresponding unique metadata generation process (e.g., a unique seed). This enables error detection where data in one processing unit is accidentally overwritten by a different processing unit.

[0134] In this case, information indicating the metadata generation process (e.g., a seed) used to generate metadata can be written into memory along with the metadata so that it can be subsequently used to regenerate metadata for comparison purposes.

[0135] To facilitate this, information indicating the metadata generation process (e.g., a seed) can be transmitted to the codec via a communication bus (interconnector) during a bus transaction triggered by the processing unit.

[0136] Therefore, in one embodiment, the processing unit is operable to initiate a bus transaction (“codec”) via a communication bus, the bus transaction including: via the communication bus, the processing unit providing information instructing the metadata generation process to the codec; and in one embodiment, the codec writing the information to memory, and / or using the information when generating metadata (e.g., a signature).

[0137] In one implementation, the processing unit is operable to initiate a bus transaction (“codec”) via a communication bus, the bus transaction including the codec: reading information from memory indicating the metadata generation process; and providing the information to the processing unit via the communication bus, and / or using the information when generating metadata (e.g., a signature).

[0138] In one implementation, the processing unit is operable to initiate a bus transaction via a communication bus, the bus transaction including: receiving information indicating the metadata generation process from the processing unit via the communication bus, or providing information indicating the metadata generation process to the processing unit.

[0139] In one embodiment, the data processing system includes a host processor (and optionally a display). In one embodiment, the host processor is operable to execute an application that requires data processing by the processing unit, wherein the processing unit operates in a manner described herein when the application executing on the host processor requires it to process data.

[0140] The techniques described herein can be implemented in any suitable system, such as a microprocessor-based system capable of proper operation. In some implementations, the techniques described herein are implemented in computer- and / or microprocessor-based systems.

[0141] The various functions of the technology described herein can be performed in any desired and suitable manner. For example, the functions of the technology described herein can be implemented in hardware or software as needed. Thus, for example, the various functional elements, stages, units, and "devices" of the technology described herein may include one or more suitable processors, one or more controllers, functional units, circuit systems, circuits, processing logic, microprocessor arrangements, etc., capable of operating to perform various functions, such as appropriate dedicated hardware elements (processing circuits) and / or programmable hardware elements (processing circuits) that can be programmed to operate in a desired manner.

[0142] It should also be noted that the various functions of the technology described herein can be copied and / or executed in parallel on a given processor. Similarly, various processing stages can share processing circuitry / circuits, etc., if needed.

[0143] Furthermore, any one or more processing stages or units of the technology described herein may be embodied as processing stage or unit circuits, for example, in the form of one or more fixed-function units (hardware) (processing circuits), and / or in the form of programmable processing circuits that can be programmed to perform desired operations. Similarly, any one or more of the processing stages or units and processing stage or unit circuits of the technology described herein may be provided as independent circuit elements to other processing stages or units or processing stage or unit circuits, and / or any one or more or all of the processing stages or units and processing stage or unit circuits may be formed at least partially by shared processing circuitry.

[0144] Those skilled in the art should also understand that all embodiments of the technology described herein may include any one or more or all of the optional features described herein, as appropriate.

[0145] The methods described herein can be implemented at least in part using software, such as computer programs. Therefore, further embodiments of the techniques described herein include: computer software, particularly adapted to perform the methods described herein when installed on a data processor; computer program elements including computer software code portions for performing the methods described herein when the program elements are run on a data processor; and a computer program including code adapted to perform all steps of one or more methods described herein when the program is run on a data processing system. The data processing system may be a microprocessor, a programmable FPGA (Field-Programmable Gate Array), etc.

[0146] The techniques described herein also extend to computer software carriers that, when used to operate a graphics processor, renderer, or other system including a data processor, cause said processor, renderer, or system to perform the steps of the methods described herein in conjunction with said data processor. Such computer software carriers can be physical storage media, such as ROM chips, CD-ROMs, RAM, flash memory, or disks, or they can be signals, such as electronic signals transmitted through wires, optical signals, or radio signals, such as signals to satellites.

[0147] It should also be understood that not all steps of the methods described herein need to be performed by computer software; therefore, other embodiments of the techniques described herein include computer software and such software installed on a computer software carrier for performing at least one step of the methods described herein.

[0148] Therefore, the techniques described herein may suitably be embodied as a computer program product used with a computer system. Such embodiments may include a series of computer-readable instructions fixed on a tangible, non-transitory medium, such as a computer-readable medium, for example, a disk, CD-ROM, ROM, RAM, flash memory, or hard disk. It may also include a series of computer-readable instructions that can be invisibly transmitted to the computer system via a modem or other interface device, through a tangible medium (including but not limited to optical or analog communication lines), or using wireless technologies (including but not limited to microwave, infrared, or other transmission technologies). This series of computer-readable instructions embodies all or part of the functions previously described herein.

[0149] Those skilled in the art will understand that such computer-readable instructions can be written in a variety of programming languages ​​to be used with many computer architectures or operating systems. Furthermore, such instructions can be stored using any current or future memory technology (including, but not limited to, semiconductor, magnetic, or optical technologies), or transmitted using any current or future communication technology (including, but not limited to, optical, infrared, or microwave technologies). It is conceivable that such computer program products can be distributed as removable media with accompanying printed or electronic documentation (e.g., shrink-wrapping software), pre-loaded with a computer system on, for example, a system ROM or a fixed disk, or distributed via a network (e.g., the Internet or the World Wide Web) from a server or electronic bulletin board.

[0150] Several implementations of the technology described herein will now be described.

[0151] Figure 1 A data processing system according to one implementation scheme is shown.

[0152] Figure 1 The exemplary data processing system shown includes a host processor, which includes a central processing unit (CPU) 1, a graphics processing unit (GPU) 10, a video processing unit (VPU) 2, a display controller 3, and a compression codec 20. Figure 1 As shown, these processing units can communicate via bus 5 and can access the off-chip memory system (memory) 6 via bus 5 and memory controller 4. Other processing units may be provided.

[0153] When using this system, CPU 1 and / or VPU 2 and / or GPU 10 generate frames (images) to be displayed, and display controller 3 provides the frames to display on monitor 7. To do this, CPU 1 and / or VPU 2 and / or GPU 10 can read data from memory 6 via interconnect 5, process the data, and return the data to memory 6 via interconnect 5. Then, display controller 3 can read the data from memory 6 via interconnect 5 for display on monitor 7.

[0154] For example, an application 8, such as a game, running on the host processor (CPU) 1 may need to display frames rendered by the graphics processing unit (GPU) on the display 7. In this case, the application 8 will send appropriate commands and data to the driver 9 for the GPU 10, which runs on the CPU 1. The driver 9 will then generate appropriate commands and data to cause the GPU 10 to render appropriate frames for display and store these frames in the appropriate frame buffer in the main memory 6. The display controller 3 will then read these frames into the buffer for the display, retrieve them from the buffer, and display them on the display panel of the display 7.

[0155] As part of this process, the graphics processor 10 reads data from the memory 6, such as textures, geometry, etc. to be rendered, processes the data, and then sends the data back to the memory 6 (e.g., in the form of processed textures and / or frames to be displayed). The display controller 3 then reads the data from the memory 6 for display on the display 7, for example, as discussed above.

[0156] Therefore, data will need to be transferred between memory 6 and the processing units of the data processing system (e.g., CPU 1, VPU 2, GPU 10, display controller 3). To facilitate this and to reduce the amount of data that needs to be transferred to and from memory during processing operations, the data can be stored in memory 6 in a compressed form.

[0157] Since the processing units (CPU 1, VPU 2, GPU 10, display controller 3) typically need to operate on data in uncompressed form, this means that data stored in compressed form in memory 6 may need to be decompressed before being processed by the processing units. Correspondingly, data generated by the processing units (e.g., CPU 1, VPU 2, GPU 10) may need to be compressed before being stored in memory 6.

[0158] To facilitate such compression and decompression of data transferred between memory 6 and the processing unit, such as Figure 1As shown, the data processing system includes a compression codec 20 that performs the required compression and decompression operations. In this embodiment, the codec 20 is connected to bus 5 via a bus interface. In other embodiments, the codec may be integrated into bus 5.

[0159] Figure 2 The illustration schematically shows elements of a graphics processing system relevant to the operation of this embodiment and specifically related to the transfer of data in compressed form between the memory system 6 and the processing unit. Those skilled in the art will understand that there may be... Figure 2 Other components of the system not shown in the diagram.

[0160] like Figure 2 As shown, logically, codec 20 is located between each processing unit (e.g., CPU 1, VPU 2, GPU 10, display controller 3) and memory 6. Codec 20 is then operable to decompress data received from memory system 6 for use by the processing units before providing the data in compressed form, and conversely, to compress data received from processing units 1, 2, 3, and 10 and to be written to memory system 6 before writing the data in compressed form to memory 6.

[0161] like Figure 2 As shown, the codec 20 effectively presents the uncompressed view 21 of the compressed data in the memory 6 to the processing units 1, 2, 3, 10, which act as bus masters, so that the processing units 1, 2, 3, 10 can access the uncompressed view of the compressed data via bus transactions.

[0162] As discussed above, using bus transactions in this manner to communicate with and control the codecs can provide a particularly flexible arrangement for compression and decompression in data processing systems.

[0163] For example, and as Figure 1 and Figure 2 As shown, multiple different processing units 1, 2, 3, 10 can use bus transactions to control the same single compression codec 20, and similarly, a single processing unit can use bus transactions to control multiple different codecs. Furthermore, this flexibility can be achieved with relatively minor modifications to existing bus protocols such as AXI. Thus, for example, a processing unit can use the same bus interface it uses for other (e.g.) "direct" bus transactions to control the codec. Additionally, compressed data can be accessed in a "random access" manner.

[0164] Now, various embodiments of the techniques described herein will be described in the context of compressed image data. However, it should be understood that other embodiments involve other types of compressed data.

[0165] Figures 3A to 3C The layout of image data stored in compressed form in memory 6 is shown according to various embodiments. These embodiments involve "memory page compression". It should be understood that other memory layouts are possible.

[0166] like Figures 3A to 3C As shown, in this embodiment, compressed image data is stored in one or more compressed frame buffers 300 in memory 6, wherein each compressed frame buffer 300 includes one or more memory pages 30 of one or more compressed data blocks 33. Figure 3B As shown, the compressed frame buffer 300 may include a set of memory pages 30 arranged in scan line order, wherein compressed data blocks 33 are arranged in scan line order within each memory page 30. Alternatively, as Figure 3C As shown, compressed data blocks 33 can be arranged sequentially according to the scan line order. Other arrangements are possible.

[0167] like Figure 3A As shown, in this embodiment, each memory page 30 is a set of adjacent memory addresses (“block”) including a header 31 and text data 32, the text data including compressed data blocks 33. The text data 32 may include unused (e.g., padding) regions 34. Figure 3A As shown, each compressed data block 33 in memory page 30 is associated with a unique index, which in this example ranges from 0 to 14.

[0168] Each compressed data block 33 can represent a set of image data sub-blocks. In this example, each compressed data block represents 16 image data sub-blocks, where each sub-block represents 64 bytes of uncompressed image data (e.g., corresponding to the burst size used by the data processing system). Therefore, each compressed data block 33 represents 1kB of uncompressed image data. Thus, in contrast to a typical 4kB memory page size, each memory page represents 16kB. Using a larger page size can help reduce address traffic on the bus. Other arrangements will be possible.

[0169] Figures 4A to 4B and Figures 5A to 5B Bus transactions according to various embodiments of the technology described herein are illustrated, wherein processing units 1, 2, 3, 10 can access an uncompressed view of compressed image data stored in a compressed frame buffer 300 in memory 6.

[0170] Figure 4A The diagram illustrates a compressed data read transaction according to one implementation scheme, and Figure 4B It is the corresponding sequence diagram.

[0171] like Figure 4A and Figure 4BAs shown, when processing units 1, 2, 3, and 10 need data stored in memory 6 that is within compressed data block 33, the processing unit issues a read transaction request 400 via its bus interface on the read address channel of bus 5. This includes the processing unit issuing a "COMPRESSED" signal, which indicates that the request involves compressed data in memory 6 and should trigger a bus transaction involving codec 20.

[0172] like Figure 4A As shown, the read transaction request 400 also includes indications 41 and 42 of the memory address of the required compressed data block and a compression descriptor 43. The memory address information includes indication 41 of the location of the header data 31 of the compressed data block and indication 42 of the location of the block 33 within the body data 32 associated with the header.

[0173] Compression descriptor 43 is a signal vector that identifies the compression mechanism (codec) by which the required data block is compressed, and identifies the data format and data type (e.g., RGB, RGBA, YUV, number of components, number of bits per component, whether the data value is an unsigned / signed integer, floating point, etc.) that should be returned to the processing unit.

[0174] like Figure 4B As shown, codec 20 identifies and intercepts request 400, reads the header information 31 of the required compressed data block 401 from memory 6 using header memory address information 41, and then reads the appropriate compressed data block 33 402 using text memory address information 42. Then, according to the compression descriptor information 43, codec decompresses the read compressed data block 403, provides the decompressed data to processing units 1, 2, 3, 10, and signals processing units 1, 2, 3, 10 404 that the read transaction on the read data channel of bus 5 is complete.

[0175] Figure 5A The diagram illustrates a compressed data write transaction according to one implementation scheme, and Figure 5B It is the corresponding sequence diagram.

[0176] like Figure 5A and Figure 5B As shown, when processing units 1, 2, 3, and 10 need to store (uncompressed) data in memory 6 within compressed data block 33, the processing units issue a write transaction request 500 on bus 5 via their bus interface. This includes the processing units issuing a "COMPRESSED" signal on the write address channel of bus 5, indicating that the request involves compressed data in memory 6 and should trigger a bus transaction involving codec 20.

[0177] like Figure 5A As shown, the write transaction request 500 also includes (uncompressed) data 54 that the processing unit needs to store in compressed form in memory 6, indications 51 and 52 of the memory addresses where the compressed data block should be stored in memory 6, and a compression descriptor 53. The memory address information includes an indication 51 of the memory location of the header data 31 for the compressed data block, and an indication 52 of the memory location of the block 33 within the body data 32 associated with the header.

[0178] In this case, compression descriptor 53 is a signal vector that identifies the compression mechanism (codec) that should be used to compress the data, and identifies the data format and data type that provides the uncompressed data (e.g., RGB, RGBA, YUV, number of components, number of bits per component, whether the data value is an unsigned / signed integer, floating point, etc.).

[0179] like Figure 5B As shown, codec 20 identifies and intercepts request 500, compresses uncompressed data 54 501 according to compression descriptor information 53, and writes the compressed data block along with appropriate header information 31 to memory 6 502 based on memory address information 51, 52. After the memory write is completed 503, codec 20 sends a signal to processing units 1, 2, 3, 10 to notify that the write transaction on the write response channel of bus 5 504 is complete.

[0180] Figure 6A and Figure 6B The layout of a data processing system according to various embodiments of the technology described herein is shown. For example... Figure 6A and Figure 6B As can be seen, the memory system may include memory 6 in the form of dynamic random access memory (DRAM) and an associated cache system 60. The memory controller 4 may include: a translation buffer unit (TBU) 4A, which translates virtual memory addresses and physical memory addresses; and a translation control unit (TCU) 4B, which controls memory translation operations. Other memory system arrangements are possible.

[0181] Logically, codec 20 is positioned between processing units 1, 2, 3, and 10 and memory 6, allowing codec 20 to "intercept" bus transaction communication between the processing units and memory 6. Figure 6A In the illustrated embodiment, logically, codec 20 is located between processing units 1, 2, 3, 10 and memory controllers 4A, 4B. In this configuration, codec 20 is operable to access memory 6 via memory controller 4, and therefore can address memory 6 using virtual memory addresses. Figure 6BIn the illustrated implementation, logically, codec 20 is located between memory controllers 4A and 4B and memory 6. In this case, codec 20 can use physical memory addresses to address memory 6.

[0182] Figure 7 The codec unit 20 according to one embodiment is shown in more detail. For example... Figure 7 As shown, the codec unit 20 includes a bus interface module (BIU) 71, an encoder module, and a decoder module 73. The bus interface module 71 receives bus transactions via bus 5 and determines how the codec unit 20 should respond to the received bus transactions.

[0183] In the case of a compressed data read transaction, bus interface module 71 transmits the compressed data to be decompressed to decoder module 73, and decoder module 73 decompresses the data and returns the decompressed data to bus interface module 71. Then, bus interface module 71 forwards the decompressed data to processing units 1, 2, 3, and 10. Bus interface module 71 can initiate a bus transaction to read the compressed data to be decompressed from memory 6.

[0184] In the case of a compressed data write transaction, the bus interface module 71 transmits the data to be compressed to the encoder module 72, and the encoder module 72 compresses the data and returns the compressed data to the bus interface module 71. Then, the bus interface module 71 forwards the compressed data to the memory 6. The bus interface module 71 can initiate a bus transaction to write the compressed data to the memory 6.

[0185] If a bus transaction is not indicated to be related to compressed data, the bus interface module 71 forwards the bus transaction appropriately without activating the encoder or decoder modules 72, 73.

[0186] like Figure 4A and Figure 4B and Figure 5A and Figure 5B As shown in the illustrated implementation, the memory address of the compressed memory block is not explicitly indicated. Instead, the memory address information is in the following form: the memory address of the memory page headers 41 and 51; and the indices 42 and 52 of the compressed data block within that memory page. Therefore, the codec 20 determines the memory address of the compressed memory block using the memory page header memory address and the block index. Specifically, the codec 20 determines the memory address offset using the block indexes 42 and 52 and applies the determined offset to the memory page header memory addresses 41 and 51 to determine the address of the compressed memory block. As discussed above, this reduces the amount of information required to indicate the memory address.

[0187] In this implementation, a fixed relationship exists between the block index and the memory address offset. Specifically, as follows: Figure 3A As shown, in this embodiment, each memory page 30 has a fixed "block" size and is divided into adjacent memory sub-regions of the same size. A sub-region is reserved for each compressed memory block 33 and for header data. (In this embodiment, each memory page is 16kB in size, and each sub-region is 1kB in size, but other arrangements are possible.) This means that the memory address offset is "implicit" for each block index, and therefore, the memory address offset can be determined by the index and the predefined (fixed) relationship between the block index and the memory address offset.

[0188] However, in other implementations, the amount of memory reserved for compressed data blocks can vary, for example, depending on the data, compression scheme, etc. In this case, there may not be a fixed relationship between the block index and the memory address offset. In this case, information indicating the relationship between the block index and the memory address offset can be included in the header 31 in the form of an offset field. In this case, the codec 20 can read the offset field information from the header to determine the address of the compressed memory block to be read. Similarly, when writing a compressed memory block to memory 6, the codec 20 can write the offset field information to the header. In this case, the offset data in the header can indicate the memory address offset relative to the memory address in the header.

[0189] In other implementations, compressed data may be stored in memory without a header. In this case, the memory address may be indicated directly, for example, or it may be determined based on the memory base address of a memory page and the index of a memory sub-region within that page. Other arrangements are possible.

[0190] Although the foregoing generally describes a processing unit that triggers a bus transaction in which codec 20 reads or writes compressed data stored as body data associated with a header, in various embodiments of the technology described herein, the processing unit may trigger a bus transaction in which codec 20 reads only header data 31 from memory 6 without reading the associated body data 32. Specifically, the processing unit may issue a request on bus 5 that triggers codec 20 to read only header information from memory 6 and provide the header information to the processing unit via communication bus 5. In the case that the data storage does not contain a header, such a header read request may return an indication that the header does not exist.

[0191] In one implementation, multiple headers can be read and cached within a single transaction. This reduces latency in scenarios where several adjacent data blocks are expected to be accessed consecutively.

[0192] Such header read requests may cause codec 20 to return all header data or only a specific portion of the header data. For example, in various embodiments of the technology described herein, in addition to (or instead of) including memory offset information, header 31 includes metadata indicating one or more attributes of the associated text data 32. In this case, the processing unit may issue a READ_META request, which will trigger codec 20 to return only the metadata in header 31 to the processing unit via communication bus 5 (but not, for example, any other header data or associated compressed data). In this case, bus interface module 71 may initiate a bus transaction to read metadata from memory 6.

[0193] Metadata can, for example, indicate that the image elements in compressed data block 33 are all the same color and that color. Sometimes this might be the case where a set of image elements is the same color in certain types of images, such as the background in a text page or menu page. In this case, for example when compositing a frame for display on monitor 7, display controller 3 can use metadata to determine the color used for the compressed data block without decompressing it. This can correspondingly reduce the processing workload required to decompress image data. Similarly, when metadata indicates that a compressed data block involves completely transparent or completely opaque image data, the decompression of that block can be omitted. Furthermore, metadata can provide a direct indication of whether the compressed data associated with the metadata should be decompressed. For example, metadata can indicate that all image elements in a set of image elements are not (completely) transparent, not (completely) opaque, and not the same color.

[0194] In various embodiments of the technology described herein, header 31 further (or alternatively) includes one or more checksums for error detection purposes (e.g., for autonomous vehicle applications). In this case, checksums can be generated from uncompressed data values, and these uncompressed data values ​​can be compressed by codec 20 to produce compressed data blocks. The checksums can then be stored in header 31, and the compressed data blocks can be stored in the associated text data 32. Then, when the compressed data blocks are decompressed by codec 20 to produce decompressed data values, the checksums can be regenerated from the decompressed data values. The checksum generated from the decompressed data values ​​can then be compared with the checksum generated from the uncompressed data values, and this comparison process can be used to determine whether an error has occurred.

[0195] In one such implementation, codec 20 generates, stores, and compares checksums. This enables error detection in relation to the data storage in memory 6 and the compression and decompression processes performed by codec 20.

[0196] However, in another such implementation, the checksum is generated and compared by the processing unit. In this case, the checksum can be transmitted between the codec 20 and the processing unit via bus 5 during a bus transaction triggered by the processing unit. This enables error detection in terms of data storage in memory 6, compression and decompression processes performed by the codec 20, and data transmission to and from the processing unit via communication bus 5.

[0197] Furthermore, each processing unit 1, 2, 3, 10 can use a unique seed for the checksum generation process. This enables error detection if data from one processing unit is accidentally overwritten by a different processing unit. In this case, the seed can also be stored in header 31 and read from the header when appropriate. Additionally, the seed of a processing unit can be transmitted between the codec 20 and the processing unit via bus 5 during a bus transaction triggered by the processing unit.

[0198] Although the above describes generating and comparing checksums, other forms of representative data, such as hash values, can be used.

[0199] As should be understood from the foregoing, the techniques described herein provide an improved arrangement for compression and decompression operations in data processing systems, at least in their embodiments. In various embodiments of the techniques described herein, this is achieved, at least by the processing unit initiating bus transactions to control the compression codec unit.

[0200] The specific embodiments described above are presented for illustrative and descriptive purposes only. They are not intended to be exhaustive or to limit the technology described herein to the precise forms disclosed. Many modifications and variations are possible in accordance with the teachings above. The described embodiments were chosen to best explain the principles of the technology described herein and its practical application, thereby enabling others skilled in the art to best utilize the technology described herein in various embodiments and with various modifications suitable for the particular intended use. The scope of the invention is intended to be defined by the appended claims.

Claims

1. A data processing system, the data processing system comprising: Processing unit; A codec that is operable to compress and decompress data; and A communication bus through which bus transactions for accessing memory can be performed; The processing unit is operable to initiate a bus transaction via the communication bus, including the codec accessing the memory, by issuing a bus transaction request on the communication bus, the bus transaction request including a signal indicating that the codec should access the memory; and The codec is operable to respond to receiving a bus transaction request via the communication bus, determine whether to access the memory based on whether the bus transaction request includes a signal instructing the codec to access the memory, and access the memory via the communication bus when it is determined that the memory should be accessed.

2. The data processing system of claim 1, wherein the processing unit is operable to issue the signal on the control channel or address channel of the communication bus instructing the codec to access the memory.

3. The data processing system according to claim 1 or 2, wherein compressed data is stored in one or more memory space regions in the memory, wherein each memory space region is divided into one or more memory space sub-regions; The processing unit is operable to send signals via the communication bus, the signals indicating a memory address of one of the memory space regions and an index indicating a sub-region of the memory space region; and The codec is operable to, in response to receiving the signal indicating a memory address and an index, determine the memory address of the memory space sub-region indicated by the index based on the memory address indicated by the signal and the index, and access the determined memory address.

4. The data processing system according to claim 1 or 2, wherein the processing unit is operable to transmit a signal via the communication bus indicating a memory address of a header associated with compressed data; and the codec is operable to: In response to receiving a memory address indication signal indicating a memory address of a header associated with compressed data to be read, the memory address of the compressed data is determined based on the indicated memory address of the header and memory address offset information in the header, the memory address offset information indicating a memory address offset relative to the memory address of the header of the compressed data; and In response to receiving a memory address indication signal indicating the memory address of a header associated with the compressed data to be written, memory address offset information indicating the memory address offset relative to the memory address of the header of the compressed data is written into the header.

5. The data processing system according to claim 1 or 2, wherein the processing unit is operable to initiate a bus transaction via the communication bus, the bus transaction comprising the codec compressing data provided by the processing unit to generate compressed data; and / or the codec decompressing the compressed data to generate decompressed data and providing the decompressed data to the processing unit.

6. The data processing system according to claim 1 or 2, wherein the processing unit is a central processing unit (CPU), a graphics processing unit (GPU), a video processor, a sound processor, an image signal processor (ISP), a digital signal processor (DSP), a neural network processor, or a display controller.

7. The data processing system according to claim 1 or 2, wherein the processing unit is operable to initiate a bus transaction via the communication bus, the bus transaction including the codec: Receive information from the processing unit via the communication bus indicating parameters and / or attributes to be used when compressing or decompressing data; and Data is compressed or decompressed based on the parameters and / or attributes indicated by the information.

8. The data processing system according to claim 1 or 2, wherein the codec includes encoder and decoder circuitry configured to compress and decompress data, and the processing unit is operable to initiate bus transactions via the communication bus, the bus transactions including: Through the communication bus, the processing unit sends a signal instructing the codec to access the memory, as well as information indicating the parameters and / or attributes to be used when compressing or decompressing data; as well as The codec is operable to configure the encoder and decoder circuitry in response to receiving the signal via the communication bus to compress or decompress data according to parameters and / or attributes indicated by the information.

9. The data processing system of claim 1 or 2, wherein the processing unit is operable to initiate a bus transaction via the communication bus, the bus transaction comprising the codec reading metadata associated with compressed data from the memory and returning the read metadata to the processing unit.

10. The data processing system of claim 1 or 2, wherein the processing unit is operable to initiate a bus transaction via the communication bus, the bus transaction comprising the codec receiving, via the communication bus, a signature representing associated compressed data from the processing unit, or providing a signature representing associated compressed data to the processing unit.

11. The data processing system according to claim 1 or 2, wherein the codec comprises: A bus transaction initiation circuit, configured to initiate a bus transaction via the communication bus to access the memory; and The codec is operable to access the memory by initiating a bus transaction for accessing the memory via the communication bus through the bus transaction initiation circuit of the codec.

12. A codec capable of operating to compress and decompress data, the codec comprising: A bus transaction initiation circuit, configured to initiate a bus transaction via a communication bus to access memory; and A processing circuit is configured to, in response to receiving a bus transaction request via the communication bus, determine whether to access the memory based on whether the bus transaction request includes a signal indicating that the codec should access the memory, and when it is determined that the memory should be accessed, cause the bus transaction initiation circuit to initiate a bus transaction via the communication bus to access the memory.

13. A method for operating a data processing system, the data processing system comprising: Processing unit; A codec that is operable to compress and decompress data; and A communication bus through which bus transactions for accessing memory can be performed; The processing unit is operable to initiate a bus transaction via the communication bus, including the codec accessing the memory, by issuing a bus transaction request on the communication bus, the bus transaction request including a signal indicating that the codec should access the memory; and The codec is operable to respond to receiving a bus transaction request via the communication bus, determine whether to access the memory based on whether the bus transaction request includes a signal instructing the codec to access the memory, and access the memory via the communication bus when it is determined that the memory should be accessed. The method includes: The processing unit initiates a bus transaction for the codec to access the memory via the communication bus by issuing a bus transaction request on the communication bus, the bus transaction request including a signal indicating that the codec should access the memory; as well as In response to receiving the bus transaction request via the communication bus, the codec determines whether to access the memory based on whether the bus transaction request includes a signal instructing the codec to access the memory, and when it is determined that the memory should be accessed, accesses the memory via the communication bus.

14. The method according to claim 13, wherein the method comprises: The processing unit sends a signal on the control channel or address channel of the communication bus instructing the codec to access the memory.

15. The method of claim 13 or 14, wherein the compressed data is stored in one or more memory space regions in the memory, wherein each memory space region is divided into one or more memory space sub-regions; The processing unit initiates the bus transaction by issuing a signal via the communication bus, the signal indicating a memory address of a memory space region and an index indicating a sub-region of the memory space region; and The codec accesses the memory by responding to receiving a signal indicating a memory address and an index, the codec determining a memory address of a sub-region of memory space indicated by the index based on the memory address indicated by the signal and the index, and accessing the determined memory address.

16. The method of claim 13 or 14, wherein initiating the bus transaction by the processing unit includes, via the communication bus, the processing unit issuing a signal indicating a memory address of a header associated with compressed data; and the method includes the codec: In response to receiving a memory address indication signal indicating a memory address of a header associated with compressed data to be read, the memory address of the compressed data is determined based on the indicated memory address of the header and memory address offset information in the header, the memory address offset information indicating a memory address offset relative to the memory address of the header of the compressed data; and / or In response to receiving a memory address indication signal indicating the memory address of a header associated with the compressed data to be written, memory address offset information indicating the memory address offset relative to the memory address of the header of the compressed data is written into the header.

17. The method of claim 13 or 14, wherein initiating the bus transaction by the processing unit comprises the processing unit initiating a bus transaction in which the codec compresses data provided by the processing unit to produce compressed data; and the method comprises: In response to the processing unit initiating the bus transaction, the codec: The data provided by the processing unit is compressed to produce compressed data; or The processing unit initiating the bus transaction includes the processing unit initiating a bus transaction in which the codec decompresses compressed data to generate decompressed data and provides the decompressed data to the processing unit; and the method includes: In response to the processing unit initiating the bus transaction, the codec: Decompress the compressed data to produce decompressed data; as well as The decompressed data is provided to the processing unit.

18. The method of claim 17, wherein the codec receives, via the communication bus, information from the processing unit indicating parameters and / or attributes to be used when compressing data, and compresses the data according to the parameters and / or attributes indicated by the information; or The method includes, via the communication bus, the codec receiving from the processing unit information indicating parameters and / or attributes to be used when decompressing data, and decompressing the compressed data according to the parameters and / or attributes indicated by the information.

19. The method according to claim 13 or 14, wherein the processing unit is a central processing unit (CPU), a graphics processing unit (GPU), a video processor, a sound processor, an image signal processor (ISP), a digital signal processor (DSP), a neural network processor, or a display controller.

20. The method of claim 13 or 14, wherein the codec includes encoder and decoder circuitry configured to compress and decompress data, and the method comprises: Through the communication bus, the processing unit sends a signal instructing the codec to access the memory, as well as information indicating the parameters and / or attributes to be used when compressing or decompressing data; and In response to receiving the signal via the communication bus, the codec configures the encoder and decoder circuits to compress or decompress data according to parameters and / or attributes indicated by the information.

21. The method of claim 13 or 14, wherein the processing unit initiating the bus transaction includes the processing unit initiating a bus transaction in which the codec reads metadata associated with compressed data from the memory and returns the read metadata to the processing unit. And the method includes: In response to the processing unit initiating the bus transaction, the codec: Read the metadata associated with the compressed data from the memory; as well as The read metadata is returned to the processing unit.

22. The method of claim 13 or 14, wherein the processing unit initiating the bus transaction comprises the processing unit initiating a bus transaction in which the codec receives a signature representing associated compressed data from the processing unit via the communication bus, or provides a signature representing associated compressed data to the processing unit; and the method comprises: In response to the processing unit initiating the bus transaction, the codec: The processor receives a signature representing associated compressed data from the processing unit via the communication bus, or provides a signature representing associated compressed data to the processing unit.

23. The method of claim 13 or 14, wherein the codec includes a bus transaction initiation circuit configured to initiate a bus transaction via the communication bus to access the memory; and The codec accesses the memory via the communication bus, wherein the codec's bus transaction initiation circuitry initiates a bus transaction to access the memory.

24. A method of operating a codec, the codec being operable to compress and decompress data, wherein, The codec includes a bus transaction initiation circuit configured to initiate a bus transaction via a communication bus to access memory; the method includes: In response to receiving a bus transaction request via the communication bus, the system determines whether to access the memory based on whether the bus transaction request includes a signal indicating that the codec should access the memory, and when it determines that the memory should be accessed, causes the bus transaction initiation circuit to initiate a bus transaction via the communication bus to access the memory.

25. A computer program product comprising computer software code, said computer software code performing the method according to claim 13 or 14 when executed on a data processing apparatus.

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