Partition identifier space selection

Abstract

A processing circuit (310) processes instructions in one of at least three domains, each of the at least three domains being associated with a corresponding physical address space, and issues a memory access request to a memory system, the memory access request including a partition identifier (selected based on programmable partition identifier selection information associated with a current software execution environment from which the memory access request is issued) and a multi-bit partition identifier space indicator indicating a selected partition identifier space (selected from at least three partition identifier spaces based on a current domain of the processing circuit). The selected partition identifier space and the partition identifier (332, 334) together represent information for selecting parameters at a memory system component for controlling allocation of resources for processing the memory access request or for managing contention for the resources or for selecting whether to update performance monitoring data in response to the memory access request.

Description

[0001] This technology relates to the field of data processing.

[0002] Two or more software execution environments (such as applications or virtual machines) can run on the same data processing system through access to a shared memory system. For some systems, a significant issue is that the performance of one software execution environment cannot be maintained due to another software execution environment consuming excessive resources in the shared memory system. This problem can be referred to as the "noisy neighbor" problem and can be particularly pronounced in, for example, enterprise networks or server systems.

[0003] At least some examples provide an apparatus comprising:

[0004] The processing circuitry is used to process instructions in one of at least three domains and to issue a memory access request to the memory system specifying a target address indicating the location of the target memory system, each of the at least three domains being associated with a corresponding physical address space.

[0005] A partition identifier selection circuit, configured to select a partition identifier based on programmable partition identifier selection information associated with the current software execution environment that caused the memory access request to be issued; and

[0006] A partition identifier space selection circuit is used to select a partition identifier space from at least three partition identifier spaces based on the current domain of the processing circuit; wherein:

[0007] The selected partition identifier space and the partition identifier together represent information used to select one or more sets of memory system resource control parameters at a memory system component of the memory system, or to select at a memory system component whether to update performance monitoring data in response to a memory access request. The set of one or more memory system resource control parameters is used to control the allocation of resources for processing memory access requests or to manage contention for said resources; and

[0008] The processing circuitry is configured to issue a memory access request to the memory system, wherein the memory access request specifies a partition identifier and a partition identifier space indicator, the partition identifier space indicator including multiple bits indicating a selected partition identifier space selected by the partition identifier space selection circuitry.

[0009] At least some examples provide a memory system component that includes:

[0010] A memory access request receiving circuit is configured to receive a memory access request specifying a target address indicating a target memory system location in the memory system, including a partition identifier space indicator comprising multiple bits indicating a selected partition identifier space chosen from at least three partition identifier spaces, and a partition identifier associated with the current software execution environment that caused the memory access request to be issued; and

[0011] At least one of the following:

[0012] A resource control circuit is configured to select one or more memory system resource control parameters based on a partition identifier space indicator and a partition identifier, and to control the allocation of resources for processing memory access requests or manage contention for said resources based on the selected set of memory system resource control parameters; and / or

[0013] The performance monitoring and control circuit controls whether to update performance monitoring data in response to memory access requests based on the partition identifier space indicator and the partition identifier.

[0014] At least some examples provide a method that includes:

[0015] Process instructions in one of at least three domains, each of which is associated with a corresponding physical address space;

[0016] Select a partition identifier based on programmable partition identifier selection information associated with the current software execution environment that caused the memory access request to be issued;

[0017] Based on the current domain of the processing circuit, a selected partition identifier space is chosen from at least three partition identifier spaces; and

[0018] A memory access request is issued to the memory system, specifying the target address indicating the location of the target memory system, a partition identifier, and a partition identifier space indicator including multiple bits indicating the selected partition identifier space; and

[0019] At least one of the following:

[0020] Based on the partition identifier space indicator and the partition identifier, select one or more sets of memory system resource control parameters, and control the allocation of resources used to process memory access requests or manage contention for said resources based on the selected set of memory system resource control parameters; and / or

[0021] The partition identifier space indicator and partition identifier control whether to update performance monitoring data in response to memory access requests.

[0022] Further aspects, features, and advantages of this technology will become apparent from the following description, which is taken in conjunction with the accompanying drawings.

[0023] Figure 1 An example of a data processing system including a memory system is illustrated schematically;

[0024] Figure 2 An example of partition control of memory system resources is illustrated based on the partition ID assigned to the software execution environment associated with the memory transaction and the partition ID space indicator.

[0025] Figure 3 An example of a device having processing circuitry, partition ID selection circuitry, and partition ID space selection circuitry is schematically shown.

[0026] Figure 4 Multiple domains in which the processing circuitry can operate are shown;

[0027] Figure 5 This schematically illustrates multiple physical address spaces as aliases in the system physical address space that identify locations within the memory system;

[0028] Figure 6 An example is shown of partitioning the effective hardware physical address space so that different architecture physical address spaces have access to the corresponding portions of the system physical address space;

[0029] Figure 7 This is a flowchart illustrating a method for controlling the issuance of memory access requests;

[0030] Figure 8 This is a flowchart illustrating the selection of a physical address space for a given memory access request;

[0031] Figure 9 This is a flowchart illustrating a physical address space filter check based on information specified in the granular protection table entry corresponding to the accessed physical address;

[0032] Figure 10 An example of a control register is shown for controlling the selection of the partition ID and partition ID space used for memory access requests;

[0033] Figure 11 An example of a discovery register is shown, which provides discovery information indicating the features performed in the processing system;

[0034] Figure 12 Showing more details Figure 10 Some of the control registers shown are among the control registers;

[0035] Figure 13A and Figure 13B The partition ID selection for data access and command retrieval access is shown separately;

[0036] Figure 14 This is a flowchart illustrating the selection of partition ID space;

[0037] Figure 15 It shows in more detail Figure 14 A flowchart of the steps for selecting whether to use the primary partition ID space or the alternative partition ID space;

[0038] Figure 16 This shows a portion of the memory system components;

[0039] Figure 17 This is a flowchart illustrating the processing of memory access requests at the memory system component; and

[0040] Figure 18 An example of a processing system is shown, including bridging circuitry located at the boundary between regions of the device that support different numbers of partition ID spaces. Detailed Implementation

[0041] An apparatus may include processing circuitry for processing instructions and for issuing memory access requests to a memory system specifying a target address indicating the location of the target memory system. Partition ID selection circuitry may be provided to select a partition identifier (ID) based on programmable partition ID selection information associated with the current software execution environment that caused the memory access request to be issued. The selected partition ID may be used by a memory system component of the memory system to select a set of one or more memory system resource control parameters or at the memory system component to select whether to update performance monitoring data in response to the access request. These one or more memory system resource control parameters control the allocation of resources for processing the memory access request or manage contention for resources. Therefore, a partition ID can represent a label for the memory access request that can be used to distinguish different software issuing the memory access request, allowing resources in the memory system to be partitioned among software execution environments to prevent one software execution environment from consuming more than its fair share of resources, thereby resolving the noisy neighbor problem described above, and / or performance monitoring can be performed at the memory system component on different software segments or subsets associated with different partition IDs, enabling the collection of more accurate information about the performance perceived by different software. Either way, this can help resolve the noisy neighbor problem.

[0042] The processing circuitry can process instructions from at least one of three domains, each associated with a corresponding physical address space. Physical addresses can be used in data processing systems to refer to locations within the memory system, but the processing system may support the use of virtual memory, where address translation circuitry can be used to translate the virtual address specified by an instruction executed on the processing circuitry into a corresponding physical address linked to the location to be accessed and the memory system. The mapping between virtual and physical addresses can be defined in one or more page table structures. Page table entries within the page table structure can also define access permission information that controls whether a given software procedure executing on the processing circuitry is allowed to access a specific virtual address.

[0043] In some processing systems, address translation circuitry maps all virtual addresses to a single physical address space, which the memory system uses to identify locations in memory to be accessed. In such systems, page table structures, which provide the virtual-to-physical address translation mapping, control over whether a particular software process can access a specific address is provided. However, such page table structures are typically defined by the operating system and / or hypervisor. If the operating system or hypervisor is compromised, this can introduce security vulnerabilities, allowing attackers to access sensitive information.

[0044] Therefore, for systems that require certain processes to be executed securely in isolation from other processes, such systems can support operations in multiple domains and multiple different physical address spaces. For at least some components of the memory system, even if physical addresses in corresponding physical address spaces actually correspond to the same location in memory, memory access requests whose virtual addresses are translated into physical addresses in different physical address spaces are treated as completely separate addresses accessing memory. By isolating accesses from different operational domains of the processing circuitry into corresponding different physical address spaces as perceived by some memory system components, this provides stronger security guarantees independent of page table permission information set by the operating system or hypervisor.

[0045] Some systems that support different physical address spaces in this way may support only two domains, each associated with a corresponding physical address space, to allow secure software running in a secure domain to be isolated from less secure software running in a less secure domain. However, there is a growing need to provide secure computing environments for software providers, which limits the need to trust other software providers associated with other software executing on the same hardware platform. For example, there may be many uses in areas such as mobile payments and banking, the implementation of anti-fraud or anti-piracy mechanisms, security enhancements for secure virtual machine hosting in cloud systems, and confidential computing, where one party providing software code may be unwilling to trust another party providing software code to execute on the same physical platform. This situation may even increasingly occur between two or more parties, each wanting a secure computing environment isolated from the less secure environment associated with normal application-level code, but distrusting each other, and therefore able to support three or more different domains each associated with a corresponding physical address space. In some examples, four or more domains may exist, and thus processing circuitry can support selection between at least four different physical address spaces.

[0046] In the example discussed below, a partition ID space selection circuit is provided to select a partition ID space from at least three partition ID spaces based on the current domain of the processing circuit. As discussed above, the selected partition ID space, together with the partition ID of the memory access request, is used as information for selecting a set of memory system resource control parameters or selecting whether to update performance data in response to the memory access request, thereby enabling performance partitioning and performance monitoring of memory resources. When the processing circuit issues a memory access request to the memory system, the memory access request simultaneously specifies a partition ID and a partition ID space indicator, which includes multiple bits indicating the selected partition ID space chosen by the partition ID space selection circuit.

[0047] By supporting at least three partition ID spaces selectable based on the current domain of the processing circuitry, it means that the same partition ID can be used in different domains, but requests to specify a partition ID can be differentiated based on different sets of memory system resource control parameters or for performance monitoring purposes of memory system components. An alternative would be to support fewer partition ID spaces than the number of domains and physical address spaces supported by the processing circuitry. This would be an efficient design choice, but it may have a drawback: if software in two or more different domains must share the same partition ID space, this could require the software managing the allocation of partition IDs in different domains to coordinate with each other to ensure that partition IDs used in different domains do not become aliases, thus affecting the performance guarantees sought by the software in a given domain through the use of partition IDs. Requiring coordinated development of software across different domains can increase software development costs.

[0048] In the example below, by supporting at least three partition ID spaces corresponding to at least three domains supported by the processing circuitry, and by selecting among the at least three partition ID spaces based on the current domain, and by using a partition ID space indicator that includes two or more bits to distinguish the three or more partition ID spaces within a memory access request, this reduces the need for coordination between software in different domains to avoid inappropriate aliases for partition IDs. This simplifies software development by maintaining a non-coordinating partition ID manager. Software in each domain can freely choose any partition ID when making a selection without worrying about whether software in another domain might be using a conflicting partition ID.

[0049] In summary, the examples discussed below provide a processing circuit that processes instructions in one of at least three domains and issues a memory access request to a memory system. Each of the at least three domains is associated with a corresponding physical address space. The memory access request includes a partition ID (selected based on programmable partition ID selection information associated with the current software execution environment that caused the memory access request to be issued) and a multi-bit partition ID space indicator indicating the selected partition ID space (selected from at least three partition ID spaces based on the current domain of the processing circuit). The selected partition ID space and the partition ID together represent information for selecting parameters at the memory system component for controlling the allocation of resources used to process the memory access request or managing contention for said resources, or information for selecting at the memory system component whether to update performance monitoring data in response to the memory access request.

[0050] The current domain of the processing circuitry may not be the only information used to select the chosen partition ID space for a given memory access request. In some examples, the chosen partition ID space can be selected based on both the current domain of the processing circuitry and programmable control information. For example, control states in one or more registers can be used to select the chosen partition ID space. The programmable control information can be programmed in software to influence which partition ID space is selected for a given memory access request. While it may be useful to have a corresponding partition ID space for each domain in the hardware, not all software may need to use different partition ID spaces for each domain, and in some cases, such as when performing traditional software designed for a system with fewer partition ID spaces, or when performing software provided by a single provider that includes sub-compartments operating in different domains, it may be desirable for software in different domains to operate using a common partition ID space, allowing software in different domains to trust a common software component to manage the allocation of partition IDs for these sub-compartments. In such cases, it may be desirable to simplify the management of partition IDs by using a coordinated partition ID manager software component. Therefore, providing support for changing which partition ID space is selected for a given domain based on programmable control information can be useful for supporting different software usage models.

[0051] Programmable control information can be defined in different ways, and in some implementations, any of the supported partition ID spaces can be selected as the chosen partition ID space to be used for a given domain. Therefore, in some systems, it may be desirable to support the free selection of which partition ID space is used for a given access, and thus, the programmable control information may include partition ID space selection information that indicates that any of the supported partition ID spaces can be selected.

[0052] However, in other examples, the available options may be more restricted, making it impossible to select all available partition ID spaces supported by the hardware for at least some domains, thus making the choice of partition ID spaces more limited in at least some domains. Restricting the available options can be useful for a variety of reasons, such as to avoid selecting a less secure state of a partition ID space associated with a more secure state, and / or to reduce hardware complexity and the amount of control states required, thereby reducing the processor's circuit area and power cost.

[0053] In some examples, the partition ID space selection circuitry can select, based on programmable control information, whether the selected partition ID space should be the primary partition ID space associated with the current domain or an alternative partition ID space associated with the current domain. For at least one of at least three domains, the alternative partition ID space can be a primary partition ID space associated with a different domain. Therefore, using this method, each domain can have its own primary partition ID space, but there can also be programmable support for selecting the same alternative partition ID space as the primary partition ID space associated with different domains for use within a domain, allowing the same partition ID space to be used for two domains to be programmed. The definition of which particular partition ID space is the alternative partition ID space for a given domain can vary depending on the specific architectural implementation. Typically, supporting both primary and alternative partition ID spaces for each domain may be sufficient to support the intended software usage model and may be a less complex option to implement compared to supporting a wider selection of partition ID spaces.

[0054] For this domain, the primary partition ID space used for a given domain can be fixed, regardless of the programmable control information. For some domains, the alternative partition ID spaces can also be fixed, so that programmable control information that selects only whether to use the primary or alternative partition ID spaces cannot change which partition ID space is the alternative partition ID space used for this domain.

[0055] However, in some examples, for at least one domain, the alternative partition ID space associated with that domain can be a partition ID space that is variably selected based on programmable control information. This can allow a wider selection of partition ID spaces to be chosen as alternative partition ID spaces, which may be useful for some domains, such as root domains that may supervise other domains (e.g., root domains may be used to execute code for switching processing circuitry between other domains), and for these domains, supporting a wider selection of alternative partition ID spaces may be useful.

[0056] The processing circuitry can support processing instructions from one of multiple different permission levels, and for at least one permission level, at least a portion of the programmable control information can be programmed at a higher permission level than the at least one permission level. This portion of the programmable control information controls the selection of a selected partition ID space for memory access requests issued at the at least one permission level. Therefore, higher-privilege software can set programmable control information that constrains the selection of a partition ID space for lower-privilege software.

[0057] In some scenarios, it may be useful for lower-privilege software to understand which partition ID space to select for that privilege level based on programmable control information and higher-privilege levels. Therefore, in some implementations, for at least a subset of privilege levels, processing circuitry may enable at least one instruction executed at the privilege level of that subset to access mandatory space indication information, which indicates the selection of a partition ID space for the current privilege level based on programmable control information programmable at higher-privilege levels. For example, software at a given privilege level (e.g., operating system privilege level) may be allowed to assign partition IDs without changing the partition ID space selected for a request made at that given privilege level or at a lower-privilege level. However, this may be useful for software to determine whether a partition ID space is for the current domain or an alternative partition ID space, as this could affect how the software assigns partition IDs (e.g., whether coordination with another software execution environment is needed).

[0058] In some examples, where the processing circuitry supports processing instructions at two or more different privilege levels, the programmable control information may include: hierarchical control enable information programmable at a first privilege level, and space selection control information programmable at a second privilege level with privileges lower than the first privilege level; wherein when the hierarchical control information has a first value, the partition ID selection circuitry is configured to select a selected partition ID space for a memory access request issued at the second privilege level or a third privilege level with privileges lower than the second privilege level, based on the space selection control information programmable at the second privilege level; and when the hierarchical control information has a second value, the partition ID selection circuitry is configured to select a selected partition ID space for a memory access request issued at the second privilege level or the third privilege level, independently of the space selection control information programmable at the second privilege level.

[0059] Using this method, software operating at the first privilege level (with the highest privilege among the first, second, and third privilege levels) can control whether software operating at the second privilege level is allowed to use programmable control information to influence the selection of a chosen partition ID space for memory access requests issued at the second or third privilege level. This hierarchical control scheme can be useful for supporting different software usage models, where some software at the first privilege level may want to delegate the responsibility of controlling which partition ID space to be selected to code operating at the second privilege level, while other software at the first privilege level may prefer to set the control state for controlling the selection of the partition ID space itself, without allowing code operating at the second privilege level to influence the selection of the partition ID space for memory access requests issued at the second or third privilege level.

[0060] The partition ID and partition ID space together represent information used to select memory system resource control parameters or control whether performance monitoring data is updated. This may affect the performance level implemented for a specific memory access request or the performance view collected using performance monitoring, but the functional outcome of processing the memory access request may be independent of the partition ID and the selected partition ID space. Therefore, accessing which specific memory system location corresponding to the target address does not depend on the partition ID and the selected partition ID space. Similarly, whether a memory access request is allowed or denied does not depend on the partition ID and the selected partition ID space.

[0061] The apparatus may have physical address space selection circuitry for selecting a chosen physical address space for a memory access request based on the current domain, and processing circuitry may issue a memory access request specifying a physical address space indicator that indicates the selected physical address space. For example, the physical address space selection circuitry may be part of a memory management unit for performing address translation, or it may be part of a physical address space filter for performing checks to determine whether code operating in the current domain is allowed to access a physical address within the selected physical address space.

[0062] Physical address space selection circuitry can select a chosen physical address space based on the current domain and physical address space selection information specified in address translation entries that provide address translation information for memory access requests. Therefore, for memory access from a given domain as the current domain, the memory access request can specify the physical address space associated with a threshold different from the current domain as the selected physical address space based on the information specified in the address translation entry. For example, this could be useful for allowing software in different domains to share access to shared variables in memory. There may be constraints on which domains are allowed to access each physical address space, and certain combinations of the current domain and physical address space may not be permitted to maintain security (e.g., when processing circuitry is located in a non-secure domain, the selected physical address space might not be prohibited as a secure physical address space associated with a secure domain).

[0063] The physical address space indicator can be separate from the partition ID space indicator. Selecting a partition ID space based on the current domain may be unrelated to the physical address space selection information, which is specified in the address translation entry corresponding to the target address of the memory access request. Therefore, even if the physical address space selection information indicates that the selected physical address space should be an address space other than the physical address space associated with the current domain, the selected partition ID space can still be the partition ID space of that current domain, or, if programmable control information is supported, the programmable control information can also allow the selection of a partition ID space different from the physical address space. This provides flexible support for different software usage models.

[0064] Therefore, the physical address space indicator can specify the physical address space of a given domain, and the partition ID space indicator can specify either a partition ID space associated with a domain whose address space is the same as the domain indicated by the physical address space indicator, or a partition ID space associated with a domain whose physical address space is different from the domain indicated by the physical address space indicator. Thus, although both the selection of the physical address space and the selection of the partition ID space may depend on the current domain, they can still be selected independently (e.g., the selected partition ID space can be changed based on programmable control information as discussed above).

[0065] The apparatus may include a Physical Alias ​​Point (PoPA) memory system component configured to dealias multiple alias physical addresses corresponding to the same memory system resource from different physical address spaces to map any one of the multiple alias physical addresses to a dealiased physical address to be provided to at least one downstream memory system component; and at least one upstream PoPA memory system component provided upstream of the PoPA memory system component, wherein the at least one upstream PoPA memory system component is configured to treat alias physical addresses from different physical address spaces as alias physical addresses corresponding to different memory system resources.

[0066] Therefore, a memory system may include a Physical Alias ​​Point (PoPA), which is a point that maps aliased physical addresses from different physical address spaces corresponding to the same memory system resource to a single physical address that uniquely identifies that memory system resource. The memory system may include at least one pre-PoPA memory system component provided upstream of the PoPA that treats the aliased physical addresses as corresponding to different memory system resources.

[0067] For example, at least one pre-PoPA memory system component may include a cache or translation lookup buffer that caches data, program code, or address translation information for aliased physical addresses in separate entries, such that if requests to access the same memory system resource from different physical address spaces result in the allocation of separate cache or TLB entries. For example, at least one pre-PoPA memory system component may be a data cache, an instruction cache, or a unified Level 2, Level 3, or system cache.

[0068] Furthermore, pre-PoPA memory system components may include consistency control circuitry, such as consistency interconnects, snooping filters, or other mechanisms for maintaining consistency between cached information at various master devices. Consistency control circuitry can assign individual consistency states to individual alias physical addresses in different physical address spaces. Therefore, to maintain consistency, alias physical addresses are treated as separate addresses, even if they actually correspond to the same underlying memory system resource. Although, superficially, tracking consistency separately for alias physical addresses may seem to cause a consistency penalty, this is not actually a problem because if processes operating in different domains do intend to share access to a particular memory system resource, these processes can use a common physical address (e.g., a less secure physical address space) to access that resource. Another example of a pre-PoPA memory system component could be a memory protection engine, which is provided to protect data stored in off-chip memory from confidentiality loss and / or tampering. For example, such a memory protection engine can use different encryption keys to individually encrypt data associated with a specific memory system resource based on which physical address space the resource is accessed from, effectively treating alias physical addresses as corresponding to different memory system resources (e.g., an encryption scheme that makes encryption address-dependent can be used, and the physical address space ID can be considered as part of the address used for this purpose).

[0069] Regardless of the form of the pre-PoPA memory system components, it is useful for such PoPA memory system components to treat alias physical addresses as corresponding to different memory system resources, because this provides a hardware-enforced separation between accesses issued to different physical address spaces, so that information associated with one domain cannot leak to another domain through features such as cache timing side channels or side channels involving consistency changes triggered by consistency control circuitry.

[0070] In some implementations, different digital physical address values ​​for different physical address spaces can be used to represent alias physical addresses in different physical address spaces. This approach may require a mapping table to determine at the PoPA which of the different physical address values ​​corresponds to the same memory system resource. However, the overhead of maintaining such a mapping table may be considered unnecessary, and therefore, in some implementations, it may be simpler if the alias physical address includes the physical address represented by the same digital physical address value in each different physical address space. If this approach is adopted, at the physical alias point, it is sufficient to simply discard the physical address space ID that identifies which physical address space is being accessed using memory access, and then provide the remaining physical address bits downstream as the de-alias physical address.

[0071] Therefore, in addition to the pre-PoPA memory system component, the memory system may also include a PoPA memory system component configured to de-alias the plurality of aliased physical addresses to obtain de-aliased physical addresses to be provided to at least one downstream memory system component. The PoPA memory system component may be a device that accesses a mapping table to find the de-aliased address corresponding to the aliased address in a specific address space, as described above. However, the PoPA component may also simply be the location in the memory system where the physical address label associated with a given memory access is discarded, such that the physical address provided downstream uniquely identifies the corresponding memory system resource, regardless of which physical address space it is provided from. Alternatively, in some cases, the PoPA memory system component may still provide physical address space labels to at least one downstream memory system component (e.g., to implement additional filter checks at the downstream system component), but the PoPA may mark a point within the memory system beyond which the downstream memory system component no longer treats the aliased physical address as a different memory system resource, but instead considers each of the aliased physical addresses to map to the same memory system resource. For example, if a downstream memory controller or hardware memory storage device of PoPA receives a physical address tag and physical address for a given memory access request, then if that physical address corresponds to the same physical address as a previously seen transaction, then any danger checks or performance improvements performed on transactions accessing the same physical address (such as merging accesses to the same address) can be applied, even if the transactions specify different physical address space tags. In contrast, for upstream memory system components of PoPA, if transactions accessing the same physical address specify the same physical address in different physical address spaces, then such danger checks or performance improvement steps performed on these transactions may not be invoked.

[0072] In some examples, the apparatus described above may not include the memory system component itself, which may be an external memory system component.

[0073] However, in other examples, the memory system component may be part of the device itself, and the memory system component may include at least one of the following: a resource control parameter selection circuit for selecting a set of one or more memory system resource control parameters based on a partition ID space indicator and a partition ID; and / or a performance monitoring control circuit for controlling whether to update performance monitoring data in response to a memory access request based on a partition ID space indicator and a partition ID.

[0074] When resource control parameter selection circuitry is provided within the memory system components, memory system resource control parameters can be mapped to a portion of the physical address space, allowing these resource control parameters to be updated software executed on the processing circuitry. Since multiple physical address spaces are supported, there are multiple options to select which physical address space should be used to access the memory system control parameters for a given partition ID space. In one example, where each of at least three partition ID spaces is associated with a corresponding domain among at least three domains, a given set of memory system resource control parameters corresponding to a given partition ID space can be accessed in response to an issued memory access request specifying a target address in the physical address space corresponding to the domain associated with the given partition ID space. By defining the memory system resource control parameters for partition ID spaces associated with the same given domain within the physical address space associated with the given domain, the management of memory system resource control parameters is simplified, and security can be maintained.

[0075] For the reasons discussed above, providing support for selection among at least three partition ID spaces on the processing side may be useful. However, in practice, the processing element, including the processing circuitry, partition ID selection circuitry, and partition ID space selection circuitry described above, can be integrated into a data processing system (e.g., a system-on-a-chip) with which the processing element can communicate. Upgrading all memory system components in the system to equally support three or more different partition ID spaces could require significant development work, and therefore some legacy components may support fewer partition ID spaces. Therefore, providing bridging circuitry at the boundary between a first region and a second region of the device, the first region including one or more components supporting at least three partition ID spaces, and the second region including one or more components supporting fewer partition ID spaces than the components in the first region, wherein the bridging circuitry is configured to remap partition ID space indicators for memory access requests passed between the first and second regions. The mapping used by the bridging circuitry can be a fixed mapping or a programmable mapping that can vary based on programmable partition ID space mapping information. In some cases, the bridging circuitry can also remap the physical address space indicator specified by a given memory access request. In this case, the bridging circuitry is located a point upstream of the PoPA in the system (if the bridging circuitry is downstream of the PoPA, the physical address space indicator may have been discarded, and therefore remapping may not be necessary). Typically, by providing the bridging circuitry described above, this offers greater flexibility in combining different types of memory system components, enabling the support of multiple partition ID spaces at the processing element, even if not all memory system components equally support three or more partition ID spaces.

[0076] As mentioned above, in some implementations, the memory system component can be considered an external component to the processing element, which includes processing circuitry, and therefore can be considered a standalone product. Thus, in some examples, the memory system component may include memory access request receiving circuitry (e.g., from the processing element or other element of the system-on-chip) that receives memory access requests, wherein the memory access request specifies a target address as discussed above and a partition ID space indicator, wherein the partition ID space includes two or more bits to select a selected partition ID space from at least three partition ID spaces. The memory access request also specifies a partition ID associated with the current software execution environment that caused the memory access request to be issued, which is defined within the selected partition ID space. The memory component system includes resource control circuitry and / or performance monitoring control circuitry as discussed above to use the partition ID space indicator and the partition ID to select memory system resource control parameters, or to control whether performance monitoring data is updated, or both.

[0077] Memory resource and performance monitoring partition

[0078] Figure 1 An example of a data processing system 2 comprising N processing clusters 4 (N being 1 or more) is schematically shown, wherein each processing cluster includes one or more processing units 6, such as CPUs (Central Processing Units) or GPUs (Graphics Processing Units). Each processing unit 6 may have at least one cache, such as a Level 1 data cache 8, a Level 1 instruction cache 10, and a shared Level 2 cache 12. It should be understood that this is only one example of a possible cache hierarchy, and other cache arrangements may be used. The processing units 6 within the same cluster are coupled by a cluster interconnect 14. This cluster interconnect may have a cluster cache 16 for caching data accessible by any processing unit.

[0079] The System-on-Chip (SoC) interconnect 18 is coupled to the N clusters and any other master devices 22 (such as a display controller or a direct memory access (DMA) controller). The SoC interconnect may have a system cache 20 for caching data accessible by any host connected to it. The SoC interconnect 18 controls the consistency between the respective caches 8, 10, 12, 16, and 20 according to any known consistency protocol. The SoC interconnect is also coupled to one or more memory controllers 24, each controlling access to a corresponding memory 25 (such as DRAM or SRAM). The SoC interconnect 18 may also route transactions to other slave devices, such as cryptographic units for providing encryption / decryption functionality.

[0080] Therefore, the data processing system 2 includes a memory system for storing data and providing access to the data in response to transactions initiated by the processing unit 6 and other master devices 22. Caches 8, 10, 12, 16, and 20, interconnects 14 and 18, the memory controller 24, and the memory device 25 can each be considered as components of this memory system. Other examples of memory system components may include a memory management unit or translation buffer (within the processing unit 6 itself or further down within the system interconnect 18 or another part of the memory system) for translating memory addresses for accessing memory, and thus may also be considered part of the memory system. Typically, memory system components may include any components of the data processing system used to service memory transactions to access memory data or to control the processing of those memory transactions.

[0081] The memory system may have various resources for processing memory transactions. For example, caches 8, 10, 12, 16, and 20 may have storage capacity available for caching the data required by a given software execution environment executed on one of the processors 6, to provide faster access to data or instructions than if they had to be retrieved from main memory 25. Similarly, the MMU / TLB may have capacity available for cache address translation data. Furthermore, interconnects 14 and 18, the memory controller 24, and the memory device 25 may each have a certain amount of bandwidth available for processing memory transactions.

[0082] When multiple software execution environments (QEs) running on processing element 6 share access to the memory system, it may be desirable to prevent one QE from using more resources than its fair share, thereby preventing other QEs from experiencing a performance penalty. This can be particularly important for data center (server) applications, where there is a need to improve data center server utilization by increasing the number of independent software processes interacting with a given amount of memory capacity to reduce the increase in capital expenditure. However, tail latency targets for web applications still need to be met, and it is undesirable if a process running on the server monopolizes memory system resources to a degree that is detrimental to other processes. Similarly, for networking applications, it is increasingly common to combine multiple functions that were previously on separate SoCs onto a single SoC. This again leads to the desire to limit the performance interactions between QEs, and to monitor how these QEs need to allow those independent processes access to shared memory while limiting performance interactions.

[0083] Figure 2This illustration schematically demonstrates an example of control over the allocation of memory system resources based on the software execution environment that issues the corresponding memory transaction. In this context, the software execution environment can be any process or part of a process executed by a processing unit within a data processing system. For example, a software execution environment can include an application, a guest operating system or virtual machine, a host operating system or hypervisor, a security monitor program for managing different security states of the system, or a sub-part of any of these types of processes (e.g., a single virtual machine can have different parts that are considered separate software execution environments). Figure 2 As shown, a specific partition ID 30 can be assigned to each software execution environment, and this partition ID, along with the memory transactions associated with that software execution environment, is transmitted to the memory system component.

[0084] The memory access request sent to the memory component specifies the address, the partition ID (PartID) determined for the corresponding software execution environment, and the partition ID space indicator (MPAM_SP) indicating the selected partition ID space.

[0085] Within a memory system component, resource allocation or contention resolution operations can be controlled based on one set of multiple sets of memory system component parameters, selected based on partition IDs and partition ID space indicators. For example, ... Figure 2 As shown, each software execution environment can be assigned an allocation threshold, which represents the maximum amount of cache capacity that can be allocated for the data / instructions associated with that software execution environment. The relevant allocation threshold for servicing a given transaction is selected based on the partition ID and partition ID space indicator associated with the transaction. For example, in... Figure 2 In this context, a transaction associated with partition ID 0 and partition ID space indicator 0 can allocate up to 50% of the cache's storage capacity, leaving at least 50% of the cache available for other purposes. On the other hand, the same partition ID 0 in different partition ID spaces (e.g., MPAM_SP = 1 instead of 0) can correspond to different sets of resource control parameters (e.g., in this example, a limit of 40% of the cache capacity is defined).

[0086] Similarly, in a memory system component (such as memory controller 24) with a limited amount of bandwidth available for servicing memory transactions, minimum and / or maximum bandwidth thresholds can be specified for the corresponding combinations of partition IDs and partition ID space indicators. If, within a given time period, a memory transaction specifying that partition ID and partition ID space ID uses less bandwidth than the minimum bandwidth, the memory transaction associated with that given partition ID and partition ID space ID can be prioritized, while if the maximum bandwidth has been used or exceeded for a transaction specifying the same partition ID and partition ID space indicator, a lower priority can be applied to the memory transaction.

[0087] It should be understood that these are merely two examples of ways to partition memory system resources based on the software execution environment that issues the corresponding transaction. Typically, by allowing different processes to "see" different partitions of the resources provided by the memory system, this allows for limiting performance interactions between processes to help address the problems discussed above.

[0088] Similarly, partition IDs and partition ID space indicators associated with memory transactions can be used for partition performance monitoring within a memory system. This allows for tracking separate sets of performance monitoring data for each partition ID, enabling the identification of information specific to a given software execution environment (or group of software execution environments). This makes it easier to identify sources of potential performance interactions than when performance monitoring data is recorded for all software execution environments as a whole. This can also aid in diagnosing potential performance interaction effects and in identifying possible solutions.

[0089] The following discusses the architecture for setting control partition IDs, selecting a partition ID space, tagging memory transactions based on a set of partition IDs for the corresponding software execution environment, routing partition IDs through the memory system, and providing partition-based control at memory system components within the memory system. This architecture is scalable to a wide range of partition ID usage. The use of partition IDs is designed to override them without altering the existing architectural semantics of the memory system, and therefore any required addressing, consistency, and ordering of memory transactions imposed by the specific memory protocols used by the memory system will not be affected by resource / performance monitoring partitioning. When using partition IDs and partition ID spaces to control resource allocation, while this may affect the performance achieved when servicing memory transactions for a given software execution environment, it does not affect the results of architecturally efficient computations. That is, partition IDs and partition ID spaces do not change the effect or outcome of a memory transaction (e.g., what data is accessed), but only affect the timing or performance achieved for that memory transaction.

[0090] Processing elements support physical address space selection and memory resource partitioning and / or performance monitoring.

[0091] Figure 3 Showing more details Figure 1 Some components within a given processing element 6 of the system 2 shown, for example, the processing element may be Figure 1 The CPU shown is one of the CPUs in CPU 6. The processing element includes processing circuitry 310 capable of executing instructions according to an instruction set architecture. Processing circuitry 310 includes instruction fetch circuitry 300 for fetching instructions from an instruction cache or from memory, instruction decoder 302 for decoding the fetched instructions, and one or more execution units 304 for performing processing operations in response to instructions decoded by instruction decoder 302. Register 312 is provided for storing operands of instructions executed by processing circuitry 310, and result control data of the executed instructions is used to configure how processing circuitry 310 performs processing.

[0092] As discussed further below, the processing circuitry can support the execution of instructions in multiple operating domains (safe states), and register 312 can include control states for identifying which operating domain is the current domain. Figure 3 In the example shown, the register includes a control register that provides a current domain indication 314, indicating which operational domain is the current domain. However, this is not required, and other architectures may determine the current domain based on two or more control status entries that can be stored in different registers or different portions of the same register, rather than providing a single domain indication to identify the current domain. For example, which domain is the current domain can be determined as a Boolean function of control bits accessible from different system registers.

[0093] Furthermore, the processing circuitry can support the execution of instructions at multiple exception levels (privilege levels), which can be associated with different privilege levels. This allows instructions executed at higher privilege levels to have greater privileges than those executed at lower privilege levels (e.g., the ability to perform operations not permitted for code at lower privilege levels, or to access data in registers or memory that is inaccessible to code at lower privilege levels). Register 312 can specify a current exception level (privilege level) indicator 315, indicating which exception level the processing circuitry 310 is currently operating on. In this application, the terms "exception level" and "privilege level" are interchangeable.

[0094] Processing circuitry 310 can issue memory access requests that specify a virtual address (VA) and a domain ID (or "security state") identifying the current domain. Address translation circuitry 316 (e.g., a memory management unit (MMU)) translates the virtual address into a physical address (PA) through one or more stages of address translation based on page table data defined in page table structure 317 stored in the memory system. Translation lookup buffer (TLB) 318 acts as a lookup cache to cache some information from the page table information, thus enabling faster access than if the page table information had to be retrieved from memory every time an address translation was needed. In this example, in addition to generating the physical address, address translation circuitry 316 also selects one of several physical address spaces associated with the physical address and outputs a Physical Address Space (PAS) ID identifying the selected physical address space. The selection of the PAS will be discussed in more detail below.

[0095] PAS filter 320 acts as a requester-side filter circuit to check whether access to the physical address identified by the PAS ID is permitted based on the translated physical address and PAS ID. This lookup is based on granular protection information stored in the granular protection table structure 321 stored within the memory system. Similar to the caching of page table data in TLB 318, the granular protection information can be cached in the granular protection information cache 322. Although the granular protection information cache 322 is in... Figure 1 In the example shown, it is a separate structure from TLB 18, but in other examples, these types of lookup caches can be combined into a single lookup cache structure such that a single lookup of an entry in the combined structure provides both page table information and granular protection information. The granular protection information defines information that restricts access to the physical address space of a given physical address, and based on this lookup, PAS filter 320 determines whether to allow the memory access request to continue being issued to one or more caches 8, 10, 12, 16, 20 and / or interconnect 18. If the specified PAS of the memory access request is not allowed to access the specified physical address, PAS filter 320 can signal a fault and, for example, prevent the request from being passed to the memory system to mitigate its impact.

[0096] Although Figure 3 An example is shown where the address translation circuit 316 performs the selection of a PAS for a given request. However, in other examples, the address translation circuit 316 may output information for determining which PAS to select, along with the PA, to the PAS filter 320, and the PAS filter 320 may select the PAS and check whether access to the PA is permitted within the selected PAS.

[0097] The provision of the PAS filter 320 helps support systems that can operate in multiple operational domains, each associated with its own isolated physical address space. This means that, for at least a portion of the memory system (e.g., for some cache or coherence implementation such as a snooping filter), even if addresses within these address spaces actually refer to the same physical location in the memory system, the individual physical address spaces are viewed as completely separate sets of addresses that identify individual memory system locations. This can be useful for security purposes.

[0098] To support the partitioning and performance monitoring of memory system resources discussed above, processing element 6 also includes a partition ID selection circuit 332 for selecting the partition ID used to specify memory access requests sent to caches, interconnects, or other memory system components, and a partition ID space selection circuit 334 for selecting the partition ID space in which the partition IDs are defined. Both partition ID selection circuit 332 and partition ID space selection circuit 334 can be selected based on control information such as the current domain 314, the current exception level 315, and information specified in one or more memory partitioning and monitoring (MPAM) control registers 330. These will be discussed in more detail below.

[0099] Therefore, a memory access request sent to a cache, interconnect, or other memory system component specifies the physical address obtained by the MMU 316 in address translation, the selected physical address space (PAS) selected by the physical address space selection circuitry (e.g., the MMU 316 or PAS filter 320) based on information in the current domain 314 and page table 317, the partition ID space indicator (MPAM_SP) identifying the selected partition ID space, and one or more partition IDs (PARTID, PMG) that can be used in conjunction with the selected partition ID space to control the selection of resource control parameters or performance monitoring at the memory system component.

[0100] Support for domains associated with the corresponding physical address space

[0101] Figure 4 Examples of different operating states and domains in which the processing circuit 310 can operate are shown, as well as examples of the types of software that can be executed in different exception levels and domains (of course, it should be understood that the specific software installed on the system is selected by the parties managing the system and is therefore not a fundamental feature of the hardware architecture).

[0102] The processing circuitry 310 can operate at multiple different exception levels 80 (in this example, four exception levels labeled EL0, EL1, EL2, and EL3), where EL3 refers to the exception level with the highest privilege level, and EL0 refers to the exception level with the lowest privilege level. It should be understood that other architectures may choose the reverse numbering so that the exception level with the highest number can be considered to have the lowest privilege. In this example, the lowest privilege exception level EL0 is used for application-level code, the next highest privilege exception level EL1 is used for operating system-level code, the next highest privilege exception level EL2 is used for hypervisor-level code managing the switching between multiple virtualized operating systems, and the highest privilege exception level EL3 is used for monitoring code managing the switching between corresponding domains and the allocation of physical addresses to the physical address space, as described later.

[0103] When an exception occurs while the processing software is at a specific exception level, for some types of exceptions, an exception of a higher (higher privilege) exception level is generated, where the specific exception level to generate the exception is selected based on the attributes of the specific exception that occurred. However, in some cases, it is possible for other types of exceptions to be generated at the same exception level as the exception level associated with the code that was processed when the exception occurred. When an exception occurs, information characterizing the state of the processor at the time the exception occurred can be saved, including, for example, the current exception level 315 at the time the exception occurred. Therefore, once an exception handler has been processed to handle the exception, processing can return to the previous processing, and the saved information can be used to identify the exception level to which the processing should return.

[0104] In addition to different exception levels, the processing circuitry supports multiple operating domains, including a root domain 82, a secure (S) domain 84, a less secure domain 86, and a domain 88. For ease of reference, the less secure domain will be described hereinafter as an “unsecure” (NS) domain, but it should be understood that this is not intended to imply any particular level of security (or lack thereof). Rather, “unsecure” simply indicates that the unsecure domain is intended for code that is not as secure as code operating in a secure domain. The root domain 82 is selected when the processing circuitry 310 is at the highest exception level EL3. When the processing circuitry is at one of the other exception levels EL0 through EL2, the current domain is selected based on the current domain indicator 314, which indicates which of the other domains 84, 86, and 88 is active. For each of the other domains 84, 86, and 88, the processing circuitry can be at any exception level of EL0, EL1, or EL2.

[0105] At boot time, multiple fragments of boot code (e.g., BL1, BL2, OEM boot) may be executed, for example, within a higher privilege exception level EL3 or EL2. Boot code BL1 and BL2 may be associated with, for example, a root domain, and the OEM boot code may operate within a security domain. However, once the system is booted, during runtime, processing circuitry 310 can be considered to operate at one time within one of domains 82, 84, 86, and 88. Each of domains 82 through 88 is associated with its own associated physical address space (PAS), which achieves the isolation of data from different domains within at least a portion of the memory system. This will be described in more detail below.

[0106] Non-security domain 86 can be used for regular application-level processing and for operating system and hypervisor activities to manage such applications. Thus, within non-security domain 86, there can be application code 30 operating at EL0, operating system (OS) code 32 operating at EL1, and hypervisor code 34 operating at EL2.

[0107] Security domain 84 enables the isolation of certain on-chip security, media, or system services into a separate physical address space from the physical address space used for non-secure processing. Non-secure domain code cannot access resources associated with security domain 84, while secure domain code can access both secure and non-secure resources; in this sense, secure and non-secure domains are not equivalent. An example of a system supporting this partitioning of security domain 84 and non-secure domain 86 is based on Arm... ® TrustZone provided by Limited ® The system architecture includes a trusted application 36 at EL0, a trusted operating system 38 at EL1, and optionally a secure partition manager 40 at EL2. If secure partitioning is supported, the secure partition manager uses stage 2 page tables to support isolation between different trusted operating systems 38 running in the secure domain 84, in a manner similar to how the hypervisor 34 manages isolation between virtual machines or guest operating systems 32 running in the non-secure domain 86.

[0108] Extending this system to support security domain 84 has become common in recent years because it enables a single hardware processor to support isolated secure processing, thus avoiding the need to execute that processing on a separate hardware processor. However, with the increasing prevalence of security domains, many real-world systems with such security domains now support relatively complex hybrid service environments offered by a wide variety of different software vendors within the security domain. For example, code operating in security domain 84 may include different pieces of software provided by, among other things: silicon wafer providers that manufacture integrated circuits; original equipment manufacturers (OEMs) that assemble the integrated circuits provided by the silicon wafer providers into electronic devices such as mobile phones; operating system vendors (OSVs) that provide the operating system 32 for such devices; and / or cloud platform providers that manage cloud servers that support services for multiple different clients via the cloud.

[0109] However, there is a growing desire to provide secure computing environments for parties providing user-level code (which may typically be expected to execute as application 30 within a non-secure domain 86), environments that can be trusted not to leak information to other parties operating the code on the same physical platform. It may be desirable for such secure computing environments to be dynamically allocated at runtime and to be certified and provable, allowing users to verify adequate security guarantees on the physical platform before trusting the device to process potentially sensitive code or data. Users of such software may not want to trust a party providing a rich operating system 32 or hypervisor 34 that may typically operate in a non-secure domain 86 (or even if these providers are trusted, users may want to protect themselves from attackers who could compromise the operating system 32 or hypervisor 34). Furthermore, while a secure domain 84 can be used for such user-provided applications requiring secure processing, this can actually create problems for both users providing code that requires a secure computing environment and providers of existing code operating within a secure domain 84. For providers of existing code operating within security domain 84, adding arbitrary user-supplied code within the security domain would increase the attack surface of their code, which is likely undesirable. Therefore, it is strongly recommended that users not be allowed to add code to security domain 84. On the other hand, users providing code that requires a secure computing environment may be reluctant to trust that all providers of different fragments of code operating within security domain 84 have access to their data or code. If authentication or certification of code operating within a specific domain is required as a prerequisite for user-supplied code to perform its processing, it may be difficult to audit and authenticate all different fragments of code operating within security domain 84 provided by different software providers. This could limit opportunities for third parties to provide more secure services.

[0110] Therefore, as Figure 4As shown, an additional domain 88 (referred to as a domain domain) is provided, which can be used by code introduced by such users to provide a secure computing environment orthogonal to any secure computing environment associated with components operating in secure domain 84. Within a domain domain, the software executed may include multiple domains, each of which may be isolated from other domains by a Domain Management Module (RMM) 46 operating at exception level EL2. RMM 46 may control the isolation between corresponding domains 42, 44 executing domain domain 88, for example, by defining access permissions and address mappings in a page table structure, in a manner similar to how hypervisor 34 manages the isolation between different components operating in non-secure domain 86. In this example, the domains include an application-level domain 42 executing at EL0 and a packaged application / operating system domain 44 executing across exception levels EL0 and EL1. It should be understood that it is not necessary to support both EL0 and EL0 / EL1 type domains simultaneously, and multiple domains of the same type may be created by RMM 46.

[0111] Similar to security domain 84, domain 88 has its own physical address space allocated to it. However, while domain 88 and security domain 84 can each access the non-secure PAS associated with non-secure domain 86, they cannot access each other's physical address spaces. In this sense, the domain is orthogonal to security domain 84. This means that the code executing in domain 88 and security domain 84 is independent of each other. The code in the domain only trusts the switching code between the hardware RMM 46 and the management domain operating in root domain 82, which makes proof and authentication more feasible. Proof enables a given piece of software to request verification that the code installed on the device matches certain expected characteristics. This can be achieved by checking whether the hash of the program code installed on the device matches an expected value signed by a trusted party using a cryptographic protocol. For example, proof can be made by checking whether the hash of the software matches an expected value signed by a trusted party, such as a silicon chip provider that manufactures integrated circuits including processing system 2 or an architecture provider that designs processor architectures that support domain-based memory access control. This allows the user-provided code 42, 44 to verify whether the integrity of the domain-based architecture can be trusted before performing any security or sensitive functions.

[0112] Thus, it can be seen that the code associated with domains 42 and 44 (which was previously executed in non-secure domain 86, as shown by the dashed lines indicating gaps in the non-secure domain where these processes were previously executed) can now be moved to the domain domain, where they can have stronger security guarantees because their data and code will not be accessed by other code operating in non-secure domain 86. However, the fact that domain domain 88 and secure domain 84 are orthogonal and therefore cannot see each other's physical address spaces means that the provider of the code in the domain domain does not need to trust the provider of the code in the secure domain, and vice versa. The code in the domain domain can simply trust the trusted firmware that provides the monitoring code 29 for root domain 82 and the RMM 46 provided by the silicon provider or the provider of the instruction set architecture supported by the processor (which may already be inherently needed to be trusted when the code executes on its device), so that a secure computing environment can be provided to users without further trust relationships with other operating system vendors, OEMs, or cloud hosts.

[0113] This can be used in a range of applications and use cases, including, for example, mobile wallets and payment applications, game anti-cheating and anti-piracy mechanisms, operating system platform security enhancements, secure virtual machine hosting, confidential computing, and gateway processing for networked or IoT devices. It should be understood that users can find many other applications with useful support for this domain.

[0114] To support security assurances provided to the domain, the processing system may support a proof reporting function, in which firmware images and configurations (e.g., monitoring code images and configurations or RMM code images and configurations) are measured at boot time or runtime, and domain content and configurations are measured at runtime, so that the domain owner can trace back the relevant proof reports to known implementations and certifications, thereby making a trust decision on whether to operate on the system.

[0115] like Figure 4As shown, a separate root domain 82 is provided for managing domain switching, and this root domain has its own isolated root physical address space. Even for systems with only non-secure domains 86 and secure domains 84 but no domain 88, the creation of the root domain and the isolation of its resources from the secure domains allows for a more robust implementation, but it can also be used in implementations that do not support domain 88. Root domain 82 can be implemented using monitoring software 29 provided (or certified) by the silicon provider or architect, and can be used to provide secure boot functionality, trusted boot measurement, on-chip system configuration, debug control, and management of firmware updates for firmware components provided by other parties (such as OEMs). Root domain code can be developed, certified, and deployed by the silicon provider or architect without relying on the final device. In contrast, secure domain 84 can be managed by the OEM to implement certain platform and security services. The management of non-secure domain 86 can be controlled by operating system 32 to provide operating system services, while domain 88 allows for the development of new forms of trusted execution environments that can be dedicated to user or third-party applications while being isolated from the existing security software environment in secure domain 84.

[0116] Figure 5 The concept of aliases on physical memory provided to the hardware by the corresponding physical address space is illustrated. As previously described, each of the domains 82, 84, 86, and 88 has its own corresponding physical address space 61.

[0117] At the point when the address translation circuit 316 generates the physical address, the physical address has a value within a certain range 62 supported by the system, and this value is the same regardless of which physical address space is selected. However, in addition to generating the physical address, the address translation circuit 316 can also select a specific physical address space (PAS) based on the current domain 14 and / or information in the page table entries used to derive the physical address. Alternatively, instead of the address translation circuit 316 performing the selection of the PAS, the address translation circuit (e.g., MMU) can output the physical address and information derived from the page table entries (PTE) for selecting the PAS, which the PAS filter 320 can then use to select the PAS.

[0118] The selection of PAS for a given memory access request can be restricted according to the rules defined in the table below, based on the current domain that the processing circuit 310 is operating on when issuing the memory access request:

[0119]

[0120] For those domains where multiple physical address spaces are available, information from page table entries used to provide access to physical addresses is used to select among the available PAS options.

[0121] Thus, at the point in time when the PAS filter 320 outputs the memory access request to the system architecture (assuming it passes any filtering checks), the memory access request is associated with the physical address (PA) and the selected physical address space (PAS).

[0122] From the perspective of memory system components (such as caches, interconnects, snooping filters, etc.) operating prior to the Physical Alias ​​Point (PoPA) 60, the corresponding physical address space 61 is viewed as a completely separate address range corresponding to different system locations within memory. This means that, from the perspective of the pre-PoPA memory system components, the address range identified by the memory access request is actually four times the size of the range 62 that can be output in address translation, because the PASID is actually treated as an additional address bit next to the physical address itself, so that the same physical address PAx can be mapped to multiple alias physical addresses 63 in different physical address spaces 61 depending on which PAS is selected. These alias physical addresses 63 all actually correspond to the same memory system location implemented in the physical hardware, but the pre-PoPA memory system components treat the alias address 63 as a separate address. Thus, if any pre-PoPA cache or snooping filter exists to allocate entries for such addresses, the alias address 63 will be mapped to a different entry with separate cache hit / miss decisions and separate consistency management. This reduces the likelihood or effectiveness of an attacker using a cache or consistency side channel as a mechanism to probe operations in other domains.

[0123] The system may include more than one PoPA 60 (e.g., different PoPAs may be implemented on different paths, through which memory access requests can be routed to different subsets of the receiving memory system components). At each PoPA 60, the aliased physical address is shrunk into a single de-aliased address 65 in the system physical address space 64. The de-aliased address 65 is provided downstream of any subsequent PoPA component such that the system physical address space 64, which actually identifies the memory system location, is once again the same size as the range of physical addresses that can be output in the address translation performed on the requester side. For example, at PoPA 60, a PAS ID may be stripped from these addresses, and for downstream components, these addresses may simply be identified using physical address values ​​without specifying a PAS. Alternatively, for some cases of completer-side filtering of expected memory access requests, the PAS ID may still be provided downstream of PoPA 60, but may not be interpreted as part of the address, so that the same physical address appearing in different physical address spaces 60 will be interpreted downstream of PoPA as involving the same memory system location, but the supplied PAS identifier may still be used to perform any completer-side security checks.

[0124] Figure 6 This illustrates how the granularity protection table 321 can be used to divide the system physical address space 64 into blocks of access allocations within a specific architecture physical address space 61. The granularity protection table (GPT) 321 defines which portions of the system physical address space 65 are allowed to be accessed from each architecture physical address space 61. For example, the GPT 321 may include multiple entries, each corresponding to a physical address granularity of a certain size (e.g., 4K pages or different granularity sizes), and may be defined as the PAS allocated for that granularity, which may be selected from non-secure domains, secure domains, domains, and root domains. By design, if a particular granularity or group of granules is allocated to a PAS associated with one of these domains, it can only be accessed within the PAS associated with that domain and cannot be accessed within PASs of other domains. However, it should be noted that while the granularity allocated to a secure PAS (for example) cannot be accessed from within the root PAS, the root domain 82 can access this physical address granularity by specifying PAS selection information in its page table 317 to ensure that virtual addresses associated with pages in that region of physically addressed memory are translated into physical addresses in the secure PAS (rather than the root PAS). Thus, cross-domain data sharing can be controlled at the point in time when a PAS is selected for a given memory access request (to the extent permitted by the accessibility / inaccessibility rules defined in the previously described tables).

[0125] However, in some implementations, in addition to allowing access to the physical address granularity within the allocated PAS as defined by GPT 321, GPT may also use other GPT attributes to mark certain regions of the address space as shared with another address space (e.g., an address space associated with a domain of lower or orthogonal privileges (which typically does not allow it to select an allocated PAS for access requests to that domain)). This facilitates temporary sharing of data without requiring changes to the allocated PAS for a given granularity. For example, in Figure 6 In the GPT, region 70 of the domain PAS is defined as being allocated to the domain domain and therefore is normally inaccessible from the non-secure domain 86 because the non-secure domain 86 cannot select the domain PAS for its access requests. Since the non-secure domain 86 cannot access the domain PAS, non-secure code typically cannot see the data in region 70. However, if a domain temporarily wishes to share some data in its allocated region of memory with the non-secure domain, it can request the monitoring code 29 operating in the root domain 82 to update GPT 321 to indicate that region 70 will be shared with the non-secure domain 86, and this allows region 70 to also be accessed from the non-secure domain 86. Figure 6The left-hand side shows the non-secure PAS access, without needing to change which domain is the domain allocated to region 70. If a domain has designated a region of its address space to be shared with a non-secure domain, then although a memory access request originating from the non-secure domain targeting that region may initially specify a non-secure PAS, PAS filter 20 can remap the PAS ID of the request to instead specify a domain PAS, so that downstream memory system components treat the request as if it always originated from the domain domain. This sharing can improve performance because the operations used to allocate different domains to specific memory regions can be more performance-intensive, involving a greater degree of cache / TLB invalidation and / or data zeroing in memory or data copying between memory regions (which can be undesirable if the sharing is expected to be only temporary).

[0126] Issue a memory access request

[0127] Figure 7 This is a flowchart illustrating the steps performed when a memory access request is issued from processing element 6. At step 100, processing circuitry 310 processes instructions in one of at least three domains, each associated with a corresponding physical address space. At step 101, processing circuitry determines whether a memory access request should be issued. The memory access request may be a data access request triggered by the execution of a load / store instruction, or an instruction fetch access request caused by an instruction fetch stage 300 issuing a fetch request to fetch instructions from memory or an instruction cache (or by a prefetcher issuing a prefetch request to prefetch instructions into the instruction cache before they are actually needed by the instruction fetch stage 300). If there is no memory access request to issue at present, processing continues at step 100.

[0128] When a memory access request is issued, at step 102, the MMU 316 translates the virtual address specified for the memory access into a physical address, and the physical address selection circuit (e.g., the MMU 316 or the PAS filter 320) selects the output PAS based on the current domain 314 and the information specified in the page table entry corresponding to the virtual address of the memory access in the page table 317.

[0129] Figure 8 Showing more details Figure 7 Step 102. In Figure 8At step 130, processing circuit 310 issues a memory access request specifying a given virtual address (VA) as the target VA. At step 132, address translation circuit 316 searches its TLB 318 for any page table entries (or cached information derived from such page table entries (PTEs)). If any required page table information is unavailable, address translation circuit 316 initiates a page table roaming to memory to obtain the required PTE (potentially requiring a series of memory accesses to progressively traverse the corresponding levels of the page table structure, and / or potentially requiring multiple stages of address translation to obtain a mapping from VA to intermediate address (IPA) and then from IPA to PA). It should be noted that any memory access request issued by address translation circuit 16 during the page table roaming operation may itself undergo address translation and PAS filtering; therefore, the request received at step 130 may be a memory access request issued to request a page table entry from memory. Once the relevant page table information has been identified, the virtual address is translated into a physical address (possibly via IPA in two stages). At step 134, the address translation circuit 316 or the PAS filter 320 determines which domain is the current domain (if the current exception level 315 is EL3, then the current domain is the root domain, and if the current exception level 315 is EL2, EL1, or EL0, then the current domain is one of the non-secure domain, secure domain, and neighborhood domain as indicated by the current domain indicator 314).

[0130] If the current domain is a non-secure domain, then at step 136, the output PAS selected for the memory access request is a non-secure PAS.

[0131] If the current domain is a secure domain, then at step 138, an output PAS is selected based on PAS selection information that provides the physical address included in the PTE, wherein the output PAS will be selected as a secure PAS or a non-secure PAS.

[0132] If the current domain is a domain domain, then at step 140, an output PAS is selected based on the PAS selection information included in the PTE, which derives the physical address from the PAS selection information. In this case, the output PAS is selected as either a domain PAS or a non-secure PAS.

[0133] If the current domain is determined to be the root domain at step 134, then at step 142, an output PAS is selected based on the PAS selection information derived from the physical address in PTE 114. In this case, the output PAS is selected as any physical address space associated with the root domain, the domain, the secure domain, and the non-secure domain.

[0134] Although Figure 8The description describes selecting the PAS based on information defined in the PTE of page table 317. However, another approach could be to provide a separate data structure independent of page table 317 that specifies the PAS for each VA. In practice, however, there may be some space in the PTE available for specifying PAS selection information, and by combining the PAS selection information with the page table information, the need to look up a second structure besides TLB 318 or page table 317 is avoided, which helps save power and reduce circuit area.

[0135] Return to Figure 7 Once the output PAS is available, at step 103, the PAS filter 320 initiates a PAS filter check based on the physical address (PA) and the output PAS selected at step 102. Step 103... Figure 9 This is shown in more detail below. Figure 9 At step 160, PAS filter 320 receives a memory access request for the specified PA and the output PAS, and at step 162, PAS filter 320 obtains the granularity protection table entry corresponding to the physical address of the memory access from granularity protection table entry 321 (if the PA is hit in GPT cache 322, the GPT entry can be obtained from GPT cache 322; otherwise, it can be obtained by performing an access to GPT 321 in memory). At step 164, PAS filter 320 determines whether the obtained granularity protection table entry GPT[PA] corresponding to the target PA indicates whether access to the granularity of the address space corresponding to the target PA within the output PA selected in step 102 is permitted. If so, memory access is permitted to continue at step 166. If the GPT entry corresponding to a specific physical address indicates that access within the output PAS selected at step 102 is not permitted at the granularity corresponding to the physical address, then at step 168, the memory access request is blocked and prevented from being issued to the cache, interconnect, or other memory system components. Alternatively, in systems where speculative issuance of memory access requests is permitted before the checks performed by the PAS filter are completed, the PAS filter may take action to cancel the effect of the memory access request. For example, the PAS filter may issue a control signal ensuring that any state changes in memory caused by the memory access request are reversed, or ensuring that any state returned from memory in response to the memory access request is not used to update registers or otherwise make the memory accessible to software.

[0136] The format of the information included in the GPT entry for specifying whether access to a given granularity within a given output PAS is permitted can vary depending on the implementation. Some implementations may support allowing only one specific PAS for a given PA in a GPT entry, and in this case, it can be simply checked whether the output PA matches the permitted PAS specified in the GPT entry accessed at step 162. Other examples may support multiple permitted output PAS for the same physical address, and in this case, the check may be whether the output PAS is any of the permitted PAS among one or more permitted PAS specified by the PA's GPT entry.

[0137] Return to Figure 7 Simultaneously, in response to the issuance of memory access request 101, at step 104, partition ID selection circuitry 332 selects a partition ID (e.g., PARTID and / or PMG, as discussed in more detail later) based on programmable partition ID selection information associated with the current execution environment. For example, partition ID selection information can be obtained from MPAM control register 330. Each software execution environment can be associated with a specific set of MPAM states stored in MPAM control register 330, which can be part of the context information of that software execution environment, saved / restored when context switching occurs between execution environments. Therefore, when switching from one software execution environment to another, the context associated with the upcoming software execution environment can be written to the register, including updating MPAM control register 330 to specify the MPAM state associated with the upcoming software execution environment. The selection of the partition ID can also be based on the current exception level 315 and / or the type of access being performed (e.g., whether the access is an instruction fetch access or a data access). This is described below. Figure 13A and Figure 13B The selection of partition IDs is shown in more detail below.

[0138] Furthermore, at step 105, the partition ID space selection circuit 334 selects a partition ID space based on the current domain 340 (and optionally also based on programmable control information that can be specified in the MPAM control register 330, and / or based on the current exception level 350). Further details are described below. Figure 14 and Figure 15 The selection of the partition ID space is shown in more detail. Although Figure 7 Steps 104 and 105 are shown to be executed in parallel with steps 102 and 103, but in other examples, they may be performed sequentially. Furthermore, although step 105 is shown to be executed sequentially after step 104, in other examples, step 105 may occur before step 104, or steps 104 and 105 may occur in parallel.

[0139] At step 106, a memory access request is issued to the memory system (e.g., to a cache, interconnect, or other memory system component). This memory access request specifies the physical address obtained by the MMU 316 at step 102, a PAS indicator indicating the output PAS selected at step 102, a partition ID space indicator (MPAM_SP) indicating the selected partition ID space selected at step 105, and one or more selected partition IDs selected at step 104. The partition ID space indicator MPAM_SP is a multi-bit value that can indicate one of at least three distinct partition ID spaces corresponding to a corresponding domain in which processing circuitry can execute. In, for example... Figure 4 In the example shown that supports four different domains (non-secure, secure, domain, and root), MPAM_SP can distinguish four different partition ID spaces, each corresponding to one of these domains. For example, MPAM_SP can have a two-bit encoding as follows (of course, other encodings are also possible):

[0140] • Insecure partition ID space: 0b01;

[0141] • Security partition ID space: 0b00;

[0142] • Domain partition ID space 0b11;

[0143] • Root partition ID space 0b10.

[0144] Selection of partition ID and partition ID space

[0145] Figure 10 It shows Figure 3 An example of MPAM control register 330 is shown. MPAM control register 330 includes multiple partition ID registers MPAMi_ELj 340, 342, 344, 346, where i indicates the exception level at which the register provides the partition ID, and j indicates the exception level with the least privilege to update the information in the register. Thus, MPAM0_EL1 340 provides the partition ID used at exception level EL0 and can be updated by code operating at exception level EL1 or higher.

[0146] MPAM control register 330 also includes discovery register MPAMIDR_EL1 348, which discovery register in Figure 11 This is illustrated in more detail and is used to provide information about the hardware capabilities of the processor implementation, enabling software to discover which features are implemented in the hardware. For example... Figure 11As shown, the discovery register 348 may include maximum partition ID values ​​370 and 372, indicating the maximum allowed values ​​for the Resource Control Partition ID (PARTID) and Performance Monitoring Group (PMG) fields of the partition ID registers 340, 342, 344, and 346. This allows for different hardware implementations to support different bit widths in these IDs, and software can read the maximum value fields 370 and 372 of the discovery register to discover the maximum partition ID value supported by the hardware.

[0147] Discovery register 348 also includes a function to indicate whether the hardware implementation supports the above. Figure 4 The SP4 field 374 is shown for the four partition ID spaces: non-secure, secure, domain, and root. Not all hardware implementations support four partition ID spaces, and therefore the support field 374 for the four spaces can be useful for software to identify whether it can use additional partition ID spaces. In implementations with partition ID space selection circuitry 334 that supports four partition ID spaces, the SP4 field 374 can be set to 1. The SP4 field 374 can be located in a bit of the discovery register 348, which would be set to 0 in conventional devices that do not support four partition ID spaces.

[0148] Furthermore, the discovery register includes an alternative partition ID space support indication field 376, indicating whether the hardware implementation supports providing alternative partition ID spaces, as discussed further below. In implementations that do not support providing alternative partition ID spaces, each field is restricted to using the primary partition ID space field 376, which will be set to 0 (again, field 376 can be a bit in the discovery register, which in legacy devices would be set to 0). In implementations that support providing alternative partition ID spaces, the HAS_ALTSP field 376 is set to 1.

[0149] Figure 12 ID registers 340, 342, 344, and 346 are shown in more detail. These registers include information for selecting the partition ID to be attached to a memory access request when sent to the memory system, and for selecting the partition ID space to be indicated for the memory access request. The state in partition ID registers 340, 342, 344, and 346 can be considered as part of the context information associated with a given software execution environment executing on the processing circuitry. When a context switch occurs, registers 340, 342, 344, and 346 are updated with the context information associated with the upcoming software execution environment.

[0150] Each partition ID register 340 to 346 includes multiple partition ID fields 350, 352, 354, and 356, used to provide partition IDs for software execution at the corresponding exception level. In this example, there are at least four fields, including the data (resource partition) partition ID (PARTID_D) field 350, the instruction (resource partition) partition ID (PARTID_I) field 352, the data performance monitoring group ID (PMG_D) field 354, and the instruction performance monitoring group ID (PMG_I) field 356.

[0151] Fields 350 and 354 are used for data memory access, and fields 352 and 356 are used for instruction fetch memory access.

[0152] Fields 350 and 352 provide resource partition IDs for data access and instruction fetching, respectively. Memory system components can use the partition ID selected based on the value in one of the resource partition ID fields 350 and 352 to control the allocation of resources such as cache capacity or memory bus bandwidth, or to manage contention between different requests (e.g., by selecting request priorities based on the partition ID).

[0153] Performance monitoring group fields 354 and 356 provide information for controlling whether performance monitoring data is updated based on the performance monitoring group ID. In some examples, the performance monitoring group ID in fields 354 and 356 can be treated as a separate ID, distinct from the resource control partition ID fields 350 and 352. However, in other examples, performance monitoring group IDs 354 and 356 can be additional bits that can be used in conjunction with resource control partition IDs 350 and 352, such that in this case, the performance monitoring group ID value used by the memory system component to control performance monitoring can be a concatenation of the selected partition ID and the selected performance monitoring group ID, rather than treating the values ​​in fields 354 and 356 as separate IDs. For example, PMG fields 354 and 356 can be treated as a prefix or suffix to a corresponding field in the PARTID field. Regardless of whether PMG fields 354 and 356 are interpreted independently of or read in combination with PARTID values, defining performance monitoring group IDs 354 and 356 allows for the differentiation of different subsets of requests sharing the same resource partition partition ID for performance monitoring purposes.

[0154] It should be understood that providing separate partition IDs for resource partitions (using fields 350 and 352) and performance monitoring and control (using fields 354 and 356) is not necessary. In other examples, the same ID may be used for both purposes, or some implementations may only support one of the partitions for resource allocation and the partitions for performance monitoring and control, and therefore may not provide both types of fields.

[0155] Furthermore, supporting separate instruction and data partition IDs is not necessary, and other examples can provide a common ID for both purposes. However, allowing separate partition IDs to be defined for data and instruction accesses within the same software execution environment can be useful, enabling different resource control parameters to be used for the corresponding instruction and data accesses. An alternative approach is to treat the single partition ID associated with the software execution environment as a whole, but append additional 0 or 1 bits depending on whether the access is for instruction or data, allowing the memory system component to select different control parameters for instruction and data accesses respectively. However, for a given number of control parameter sets selected based on the partition ID, this approach would imply a 50 / 50 split of the partition ID space between data and instruction. In implementation, it may often be desirable to have more data partitions than instruction partitions, as it is relatively common for multiple software execution environments to use the same code but execute with different data inputs, and therefore, it can be particularly useful to be able to share a single instruction partition ID across multiple software execution environments while allowing each of these environments to use a different data partition. In this case, appending 0 or 1 bits to indicate instruction or data access would require defining multiple sets of the same configuration information at the memory system component for each individual instance of that common code. In contrast, by providing separate instruction and data partition fields in partition ID registers 340 to 346, where the instruction and data partition IDs are selected from a common ID space, the same partition ID can be reused across different software execution environments, and the partition ID space can be divided between data and instructions as needed, without constraining this division to be halved. Even though more than twice the partition ID fields in each partition ID register 340 to 346 might require some additional storage capacity, this approach also saves resources at the memory system component because by sharing a single partition across instruction accesses across multiple execution environments, fewer sets of control parameters (and therefore less storage) are needed at the memory system component.

[0156] Figure 13A A method for controlling the selection of partition IDs assigned for memory access requests is shown. Figure 13AThe method shown can be used for data access memory transactions. At step 110, processing circuitry 310 issues a data access (load / store) memory access request, for example, in response to a load / store instruction executed by execution unit 304. At step 112, partition ID selection circuitry 332 reads one of the partition ID registers 340, 342, 344, and 346 selected based on the processor's current operating state. For example, partition ID selection circuitry 332 can select one of the partition ID registers 340, 342, 344, and 346 corresponding to the current exception level 315 (register 340 is selected if the current exception level is EL0, register 342 if the current exception level is EL1, register 344 if the current exception level is EL2, and register 346 if the current exception level is EL3). In some implementations, further control state information can be defined within the control register, which can alter which partition ID register is selected for a specific exception level, departing from the default use of registers 340 to 346 associated with the current exception level. For example, a parameter can be set to force the use of the partition ID in register MPAM1_EL1 342 when the current exception level is EL0. This can be useful if the operating system wants applications it manages to use the same partition ID as the operating system itself as defined in MPAM1_EL1 342, thus avoiding the need for the operating system to set a partition ID value for MPAM0_EL1 340. Therefore, in some systems, in addition to the current exception level, certain control states may also influence the selection of the MPAM register, but this is not necessary.

[0157] At step 118, since the current memory access request is a data access request, the PMG_D field 354 and the PARTID_D field 350 are read from one of the registers 340, 342, 344, and 346 selected at step 112. At step 120, the partition ID selection circuit 332 determines whether virtualization of the partition ID is implemented and enabled for reading the partition ID from the selected register in the current operating state. For processes executing in EL2 and EL3, virtualization is not required. For software execution environments in EL0 or EL1, if virtualization is hardware-supported, whether virtualization is currently enabled may depend on information specified in the control register (e.g., controlled by the hypervisor executing in EL2). When partition ID virtualization is both implemented in hardware and currently enabled for the current exception level, at step 122, the partition ID selection circuit 332 performs a virtual-to-physical partition ID mapping to map the virtual partition ID value read at step 118 to the corresponding physical partition ID value based on the mapping information set for the current execution environment. For example, the hypervisor can maintain a partition ID remapping table that can be used to implement partition ID remapping. This can be useful for allowing different guest operating systems that may have defined conflicting partition ID values ​​to coexist conflict-free on the same system, so that conflicting virtual partition ID values ​​can be remapped to different physical partition ID values, and access requests from the respective operating systems can be differentiated at the memory system component to perform individual resource allocation control or performance monitoring. The mapping table can be implemented in different ways; for example, a set of partition ID remapping registers can be provided to specify physical partition ID values ​​corresponding to different values ​​of virtual partition IDs read from registers 340, 342, 344, and 346, or alternatively, a remapping structure stored in memory can be used to provide the mapping table. If virtualization is implemented and enabled at step 122, and the partition ID is remapped to a physical partition ID, the remapped partition ID is output at step 150 for transmission along with the memory access request to the cache, interconnect, or other memory system component (once the request has undergone any necessary address translation and PAS filtering). If virtual-to-physical partition ID mapping is not implemented on the hardware device or is not currently enabled, step 122 is omitted, and at step 150, the partition IDs read from the selected registers 340 to 346 are simply output in their original form without remapping.

[0158] Figure 13B A method for obtaining the partition ID of the memory access transaction selected for an instruction is shown. Figure 13BAt step 111, processing circuit 310 issues an instruction fetch memory access request to request the fetch of an instruction for a given address. When the instruction is actually needed for execution, the fetch circuit 300 can issue the instruction fetch request, or some specific embodiments may have a prefetch circuit to prefetch the instruction into the instruction cache before the actual time when the instruction needs to be prefetched for execution, and thus the prefetch circuit can also generate the instruction fetch memory access request. In response to issuing the instruction fetch memory access request, Figure 13B Steps 112 to 150 and Figure 13A The steps for data access requests are the same, except... Figure 13A Step 118 in the process was Figure 13B Step 116 is replaced, where PMG_I and PARTID_I fields 356 and 352 are read from the selected partition ID register instead of PMG_D fields 354 and PARTID_D fields 350. Steps 120, 122, and 150 are the same, except that they use the instruction partition ID values ​​from fields 356 and 352 instead of the data partition ID values ​​from fields 354 and 350.

[0159] Return to Figure 12 Some partition ID registers in the partition ID registers also include control status information for controlling the selection of a partition ID space for a given memory access request. Each domain in the domain supported by the processing circuitry has a corresponding primary partition ID space associated with that domain. The control status in registers 344 and 346 can be used to select whether to use the primary partition ID space or an alternative partition ID space. This control status information includes:

[0160] • In MPAM3_EL3 346:

[0161] • Root Alternate Space Selection Information (RT_ALTSP_NS) 360, which is used by EL3 codes to select whether the alternative partition ID space for the root domain is a secure partition ID space or an insecure partition ID space.

[0162] • EL3 partition ID space selection information (ALTSP_EL3 362) is used to select whether to use the primary partition ID space or the alternative partition ID space to respond to memory accesses issued by EL3.

[0163] • EL3 control hierarchical forced space selection information (ALTSP_HFC) 364 provides space selection control information that can be programmed by EL3 to control whether to use the primary partition ID space or the alternative partition ID space for access from EL2, EL1 and EL0 when hierarchical control is disabled using ALTSP_HEN 366.

[0164] • Hierarchical control enable information (ALTSP_HEN) 366: Enables or disables hierarchical control. When hierarchical control is enabled, instructions executed in EL2 are allowed to influence the selection between the primary partition ID space and the alternative partition ID space for access from EL2, EL1, or EL0. When hierarchical control is disabled, instructions executed in EL2 cannot influence the selection between the primary partition ID space and the alternative partition ID space for access from EL2, EL1, or EL0, and the selection between the primary partition ID space and the alternative partition ID space for access from EL2, EL1, or EL0 depends on ALSTP_HFC 364 set in register MPAM3_EL3 346 by instructions executed in EL3.

[0165] • In MPAM2_EL2 344:

[0166] • EL2 Hierarchical Forced Space Indicator (ALTSP_FRCD), which indicates whether the code operating with EL3 is forced to select the alternative partition ID space for the code operating with EL2;

[0167] • EL2 partition ID space selection information (ALTSP_EL2) 372, which is set by the code operating with EL2, controls whether the code operating with EL2 should use the primary partition ID space or the alternative primary partition ID space when hierarchical control has been enabled using MPAM3_EL3.ALTSP_HEN 366.

[0168] • The hierarchical forced space selection information (ALTSP_HFC) 374 controlled by EL2 is a programmable partition ID space selection information set at EL2. When hierarchical control is enabled by MPAM3_EL3.ALTSP_HEN 366, the hierarchical forced space selection information controlled by EL2 specifies whether the code operating with EL0 or EL1 should use the primary partition ID space or the alternative primary partition ID space.

[0169] • In MPAM1_EL1 342:

[0170] • EL1 Hierarchical Forced Space Indication Information (ALTSP_FRCD) 380, which indicates to the code operating in EL1 whether the alternative partition ID space has been forced to be selected on the code operating in EL1 by the code operating in EL3 or EL2.

[0171] The options supported by these partition ID selection controls are summarized below:

[0172] When the Alternate Partition ID Space Feature (ALTSP) is supported by the hardware (e.g., indicated by field 376 in the Discover register), the Alternate Partition ID Space is supported for every secure state (domain) except for the non-secure one (using the non-secure partition ID space for this purpose, regardless of whether the control in registers 344 and 346 indicates that a primary / alternate space is selected). Similarly, a non-secure secure state can still be considered to have an Alternate Partition ID Space, but its Alternate Partition ID Space is the same as the primary partition ID space. Therefore, the primary and Alternate Partition ID Spaces supported for each domain in the domain are as follows:

[0173]

[0174] The selection of the alternative space for the root is performed in MPAM3_EL3 346 within the RT_ALTSP_NS field 360. 0b1 in this field selects the non-secure partition ID space as the alternative partition ID space for the root secure state. 0b0 selects the secure partition ID space as the alternative partition ID space for the root secure state.

[0175] When executed in EL3, the processing element is in root-safe state. The selection of the primary partition ID space or the alternative partition ID space for a memory system generated in root-safe state is controlled by bits in MPAM3_EL3 346:

[0176] •RT_ALTSP_NS 360 sets whether the alternative partition ID space in the root secure state is the insecure partition ID space or the secure partition ID space.

[0177] •ALTSP_EL3 362 sets whether memory system requests generated from EL3 use the primary partition ID space or the alternate partition ID space.

[0178] These two bits together provide three combinations for accessing the partition ID space from EL3 in root state:

[0179]

[0180] When executed as EL2, EL1, or EL0, the security state can be secure, non-secure, or domain-secure. Root software running in EL3 can allow EL2 to control its own partition ID space as well as the partition ID spaces used by EL1 and EL0, or the root software can force the selection of a primary or secondary space for EL2, EL1, and EL0.

[0181] If EL3 has the alternative space control enabled in MPAM2_EL2 344 (i.e., hierarchical control is indicated to be enabled by MPAM3_EL3.ALTSP_HEN 366), EL2 can select, via MPAM2_EL2.ALTSP_EL2 370, whether the partition ID generated by EL2 uses the primary partition ID space or the alternative partition ID space. When EL3 has the alternative space control enabled in MPAM2_EL2 344, EL2 can also select whether EL1 and EL0 use the primary partition ID space or the alternative partition ID space. EL3 forces selection for all lower ELs by clearing MPAM3_EL3.ALTSP_HEN 366 and setting MPAM3_EL3.ALTSP_HFC 364 to force the alternative partition ID space, or by clearing ALTSP_HFC 364 to force the primary partition ID space on all lower ELs.

[0182] The combined settings for EL2, EL1, and EL0 are shown in the table below:

[0183]

[0184] In each of MPAM2_EL2 344 and MPAM1_EL1 342, the fields ALTSP_FRCD 370 and 380 indicate that the partition ID space has been forcibly prepared on the partition ID in MPAM2_EL2 and the partition ID in MPAM1_EL1 and MPAM0_EL1, respectively. Because EL1 and EL0 are always the same, and EL1 controls the partition ID in MPAM0_EL1, it is not necessary to indicate this separately in MPAM0_EL1 340.

[0185] Figure 14This is a flowchart illustrating the selection of a partition ID space via partition ID space circuit 334. At step 170, partition ID space selection circuit 334 determines whether the programmable control information in registers 344, 346 specifies whether to use the primary partition ID space or an alternative partition ID space. When the primary partition ID space is to be used, at step 172, the selected partition ID space indicated by the partition ID space indicator MPAM_SP for the issued memory access request is the primary partition ID space associated with the current domain. If an alternative partition ID space is to be used, at step 176, the selected partition ID space indicated by MPAM_SP is an alternative partition ID space associated with the current domain. When the current domain is a domain, secure, or insecure domain, this alternative partition ID space can be fixed as an insecure partition ID space, and according to the root alternative space selection information MPAM_EL3.RT_ALTSP_NS 360 set by EL3-operated code within MPAM3_EL3 346, this alternative partition ID space can be programmed as a secure or insecure partition ID space for the root domain.

[0186] Figure 15 This shows the usage in more detail. Figure 14 Step 170 establishes the criteria for selecting between the primary partition ID space and the alternative partition ID space. At step 180, the partition ID space selection circuit 334 determines whether the current permission level is EL3, and if so, at step 182, EL3 space selection information (MPAM3_EL3.ALTSP_EL3 362) set by the code operating in EL3 is used to select between the primary partition ID space and the alternative partition ID space.

[0187] If the current permission level is EL2, EL1, or EL0, then at step 184, the partition ID space selection circuit 334 determines whether hierarchical control for partition ID space selection is enabled by EL3. For example, circuit 334 determines whether the hierarchical enable value MPAM3_EL3.ALTSP_HEN 366 has a first value or a second value. If ALTSP_HEN 366 has a first value (e.g., 1), hierarchical control is enabled, and if ALTSP_HEN 366 has a second value (e.g., 0), hierarchical control is disabled.

[0188] If hierarchical control is disabled by the code operating with EL3, the code operating with EL3 will determine whether the primary / alternate partition ID space should be used by the code operating with EL2, EL1, or EL0. Therefore, at step 186, the hierarchical forced space selection information MPAM3_EL3.ALTSP_HFC 364 set by the code operating with EL3 is used to select between the primary and alternative partition ID spaces for use with EL2, EL1, or EL0. Thus, in this case, the code operating with EL2 has no effect on whether the code operating with EL2 or the code operating with EL1 or EL0 should use the primary or alternative partition ID space.

[0189] If hierarchical control for partition ID space selection is enabled by EL3 (ALTSP_HEN 366 has a first value), then at step 188, the partition ID space selection circuit 334 determines whether the current permission level is EL2 or one of EL1 and EL0. If the current permission level is EL2, then at step 190, the EL2 space selection information MPAM2_EL2.ALTSP_EL2 372, set in register 344 by code operating in EL2, is used to select between the primary partition ID space and the alternative partition ID space. On the other hand, if the current permission level is EL1 or EL0, then at step 192, the hierarchical forced selection information MPAM2_EL2.ALTSP_HFC 374, set in register 344 by code operating in EL2, is used to select between the primary partition ID space and the alternative partition ID space.

[0190] It should be understood that although the flowchart described above shows the steps occurring in a specific order or sequence, other implementations may reorder the steps or perform some of the steps in parallel.

[0191] In summary, by using programmable control information within registers, partition IDs can be defined within one of the four partition ID spaces corresponding to the respective operating domains discussed above. Software has the flexibility to decide whether it actually needs to use all four supported partition ID spaces, or whether some software might prefer to use alternative partition ID spaces, allowing for the sharing of a common partition ID space among software operating in different security states. If software can share a common partition ID space, this reduces the number of sets of resource control parameters defined for each combination of currently used partition IDs and partition ID spaces in the memory system components, thus reducing software management overhead.

[0192] Partition ID and partition ID space memory system components use

[0193] Figure 16An example of circuitry within a memory system component is shown, which may be, for example, caches 8, 10, 12, 16, 20, control circuitry within interconnects 14, 18, or memory controller 24. A memory access request is received by the memory system component, which, as discussed above, specifies the physical address (PA) to be accessed, a partition ID space indicator MPAM_SP, and one or more partition IDs, such as a resource control partition ID (PARTID) and a performance monitoring group ID (PMG). If the memory system component is a pre-PoPA component upstream of a physical alias point (PoPA) 60, the memory access request also specifies a physical address space PAS ID that identifies the physical address space to be accessed. If the memory system component is downstream of PoPA 60, the PAS ID may not be provided with the request because the request has already passed through the PoPA, where the aliased physical address in a different physical address space is de-aliased (e.g., by stripping the PAS ID).

[0194] The memory system component includes a resource control parameter selection circuit 400, which selects one or more memory system resource control parameters from a resource control setting structure 402 based on a combination of a partition ID space indicator MPAM_SP and a resource control partition ID value (PARTID) supplied with the request. The resource control setting structure 402 includes multiple entries 404, each corresponding to a different combination of MPAM_SP and PARTID values. Therefore, the same partition ID value PARTID appearing in different partition ID spaces can correspond to different sets of resource control parameters 404. Resource control setting structure 402 may be a set of registers implemented in hardware within the memory system component. This set of registers can be updated by processing circuitry 310 issuing a memory access request specifying the address of one of these registers mapped to as its target address. (In some cases, to maximize the number of addresses exposed to the memory map, a single register may act as an interface with the memory-mapped address to be written when updating resource control settings, and part of the information of the target interface register specified by the memory access request may be an entry ID indicating which resource control setting entry 404 to update, so that each resource control setting register provided in hardware does not need to have a separate memory-mapped address.) Alternatively, resource control setting structure 402 may be a structure maintained in memory at a set of addresses reserved for the structure by software, and in this case, the hardware of the memory system component may only have a register identifying the base address of the data structure within the memory address space. Optionally, the memory system component may include a resource control setting cache for caching resource control setting entries 404 from the memory-based structure.

[0195] Typically, regardless of whether resource control settings 402 are implemented using registers of hardware system components or data structures in memory, software executing on processing element 6 can access resource control parameters 404 corresponding to a given partition ID space by issuing memory access requests. These memory access requests specify the physical address space corresponding to the domain associated with the given partition ID space in the PAS ID. Therefore, resource control settings defining partition IDs in the non-secure, secure, domain, and root partition ID spaces can be accessed using memory access requests specifying physical addresses within the non-secure, secure, domain, and root physical address spaces, respectively.

[0196] Based on a selected set of resource control parameters 404, the resource usage control circuit 406 controls the service of memory access requests based on the selected resource control parameters. The way resource control parameters are used to influence the service of requests can vary depending on the type of memory system component and the characteristics implemented; however, typically these parameters may affect the allocation of performance resources used to process requests, or manage contention for such resources between different requests. However, the resource control settings do not affect the functional outcome of processing requests, such as determining whether a request should be allowed or denied, or selecting which specific memory system location to access in response to a request.

[0197] For example, if the memory system component is a cache, resource control setting 404 can be used to control the allocation of cache storage capacity for data or instructions associated with a requested physical address PA. For instance, resource control setting 404 can define the maximum cache capacity allowed to be allocated for data instructions associated with a specified partition ID and partition ID space, where the cache capacity limit, for example, defines a maximum fraction of the cache capacity allowed for combinations of partition IDs and partition ID space indicators. Another option is for the resource control setting to specify which individual portions of the cache (e.g., which paths of the set-associative cache) are allowed to be allocated for data or instructions associated with corresponding partition IDs and partition ID spaces. Using portion-based control, a software process can be restricted to using a relatively small subset of cache paths, while another software execution environment can be allowed to use a larger number of paths, making it more likely that the other software execution environment will see higher performance when accessing memory. Either way, by providing some resource control settings that can limit the amount of cache capacity used by a given software execution environment, this can reduce noisy neighbor problems by preventing one software execution environment from exhausting most of the cache capacity.

[0198] Another example of resource usage control could be interconnect or memory controllers controlling bandwidth allocation on the bus based on resource control settings 404, which are selected based on specified partition IDs and partition ID spaces for the current request. For example, minimum and / or maximum bandwidth can be defined in the resource control settings, which can be used to control how many time slots on the bus are available for requests associated with a specific software execution environment, such as those indicated by the partition ID and partition ID space specified in the memory access request. For instance, if the bandwidth recently used by a given process falls below the minimum bandwidth indicated in the corresponding set of resource control settings selected for the combination of partition IDs and partition ID spaces, requests for that combination of partition IDs and partition ID spaces can be prioritized in future bus arbitration. If the bandwidth used by a given process exceeds the defined maximum bandwidth, memory access requests for corresponding combinations of partition IDs and partition ID spaces can be de-prioritized in future bus arbitration decisions, for example, by preventing the allocation of more bus time slots before bandwidth utilization falls below the maximum value.

[0199] Another option is that memory system components, such as memory controllers or interconnects, can prioritize given memory access requests based on resource control settings, allowing requests to one software execution environment to be processed before requests to another, where priority is used to manage resource contention between requests. Therefore, there are various ways in which resource control settings can influence the performance achieved when servicing requests to access memory.

[0200] like Figure 16As shown, the memory system component may also include performance monitor selection and filtering circuitry 410, which controls the updating of performance monitor counter 412 in response to a memory access request process of the memory system component, wherein the criteria for updating performance monitor 412 are defined in filter parameters 414. Similar to resource control settings 402, filter parameters 414 may be defined within registers of the memory system component or within a memory-based architecture (which may optionally be cached). Performance monitor 412 may also be accessed as a memory-mapped register or in memory. Partition ID space indicator and performance monitor group ID PMG (and optionally, resource control partition ID value (PARTID), and in embodiments where PMG is considered a prefix / suffix concatenated with PARTID) may be used to select which performance monitor 412 is updated and / or whether the performance monitor is updated based on the selection of a set of filter parameters 414 corresponding to a combination of MPAM_SP, PMG, and optionally PARTID. Therefore, different performance monitors 412 can be defined for different combinations of partition IDs and partition ID space indicators, and different sets of filter parameters can also be defined for such combinations. This allows the performance of a software execution environment to be tracked independently compared to another software execution environment, and software executing in different security domains can have different sets of performance monitors or different sets of filter parameters associated with them to define different criteria for performance monitoring. For example, performance monitor 412 can be a set of counters that increments in response to memory access requests meeting specific criteria, and filter parameters can define criteria such as defining the memory address range to update the performance monitor, defining the type of memory access to be tracked (e.g., load or store), or defining the type of events to be counted by performance monitor 412, such as cache misses, total requests, wait time for processing requests, etc.

[0201] Although Figure 16 An example of a memory system component is shown that has both resource control setting selection circuitry 400 and performance monitoring selection and filtering circuitry 410; however, not all memory system components have both, and some system components may have only one of them. Furthermore, a memory system may include components that do not support resource partitioning at all, and these components have neither resource control setting selection circuitry 400 nor performance monitoring selection and filtering circuitry 410. However, such a memory system component that does not support any partitioning can coexist in the same memory system with other memory system components that support partitioning.

[0202] Figure 17This is a flowchart illustrating the processing of memory access requests at a memory system component. At step 200, the memory system component receives a memory access request specifying a physical address (PA), a partition ID (PARTID and / or PMG), a partition ID space indicator (MPAM_SP), and optionally a PAS indicator, for example, if the memory system component is upstream of PoPA 60. At step 202, if the memory system component supports resource partitioning, the method proceeds to step 204, where resource control setting selection circuitry 400 selects one or more sets of resource control parameters 404 based on the resource control partition ID (PARTID) and partition ID space indicator (MPAM_SP). At step 206, resource usage control circuitry 406 controls resource allocation or contention management for memory access requests based on the selected set of resource control parameters 204. If the memory system component does not support resource partitioning, steps 204 and 206 are omitted.

[0203] If, at step 208, the memory system component supports performance monitoring partitions, then at step 210, the performance monitor selection and filtering circuitry 210 selects whether to update the performance monitoring data 412 based on the partition ID (at least the performance monitoring group ID (PMG), but optionally also the resource control partition ID (PARTID) in some embodiments) and the partition ID space indicator MPAM_SP. For example, a set of filter parameters 414 corresponding to the combination of the partition ID and the partition ID space indicator is selected, and it is determined whether the memory access request conforms to these filter parameters; if so, the performance monitor 414 corresponding to the combination of the partition ID and the partition ID space indicator is updated. If the memory system component does not support performance monitoring partitions, step 210 is omitted.

[0204] Regardless of whether the memory system component supports resource partitioning and / or performance monitoring partitioning, the memory access request is serviced at step 212. If the memory system component is a pre-PoPA located upstream of PoPA 60, alias physical addresses in different physical address spaces will be treated as referring to different memory system resources. For example, if the memory system component is a cache, cache capacity lookup can be performed, for example, by including a PAS indicator as part of an index value for selecting a set of caches and / or as part of a tag value for determining whether the cache location being looked up corresponds to a specified address. In practice, the PAS indicator can be treated as some additional address bits during cache lookup. If the memory system component is a pre-PoPA memory controller, interconnect, or other component that outputs requests on the bus, the PAS indicator may be provided along with the PA to define the PA and act as additional address bits.

[0205] At step 214, if any memory access request needs to be sent to downstream memory system components (such as a cache line fill request in the event of a cache miss, a request sent on the bus by the interconnect, or a request issued by the memory controller to a memory storage unit), then the partition ID and partition ID space indicator are included as tags attached to the request sent downstream, allowing the downstream memory system component to also implement resource partitioning or performance monitoring partitioning. Furthermore, PA and PAS indicators can also be provided downstream, unless the memory system component is a PoPA memory system component, which can strip the PAS to alias physical addresses from a different physical address space; in this case, the PAS indicator can be omitted from the request sent downstream.

[0206] Bridging between regions that support different numbers of partition ID spaces.

[0207] When constructing data processing systems such as systems-on-a-chip (SoCs), while it may be useful for some components to support three or more partition ID spaces and three or more security domains as in the examples discussed above, other memory system components may exist that can support fewer domains and partition ID spaces. For compatibility with legacy devices, it is expected that such devices, which support fewer partition ID spaces and security domains, can coexist with the processing elements and memory system components discussed above. Therefore, as... Figure 18As shown, the data processing system may include a first region 450 and a second region 452 of the device. The first region includes one or more components supporting at least three partition ID spaces and at least three security domains as discussed above, and the second region includes one or more components supporting fewer partition ID spaces and security domains than the components in the first region. A bridging circuit 460 may be provided to remap physical address space IDs and partition ID space indicators for memory access requests passed between the first and second regions. For example, at the boundary between regions 450 and 452, the four values ​​of a physical address space indicator (PAS ID) may be mapped to selected values ​​from a set of two physical address spaces supported within region 452. Similarly, a 4:2 remapping may be performed on the partition ID space indicator (MPAM_SP). For a request originating from the second region 452 to the first region 450, a corresponding 2:4 domain / partition ID space remapping may be performed. In some cases, bridging circuitry 460 may include remapping circuitry combined with other functions. For example, a system memory management unit (SMMU) 462 that performs address translation on behalf of devices within the second region 452 may also perform remapping at the bridge between regions 450, 452. Alternatively, dedicated bridging circuitry 464, 466, separate from any other functions such as address translation, may be provided at the interface between regions. Separate bridging components may be provided for 4:2 remapping of requests passed from the first region 450 to the second region 452 and 2:4 remapping of requests passed from the second region 452 to the first region 450.

[0208] Under various design objectives, a range of bridging techniques can be used to support legacy region 452. For two PAS and two PARTID space devices 454 making requests to four PAS / PARTID regions 450, the system MMU 462 can perform mapping under the control of software-defined page tables. Alternatively, for a relatively inexpensive but inflexible solution, device 454 can be connected to static translations from non-secure PAS to non-secure PAS and from secure PAS to secure PAS, as well as corresponding translations from non-secure partition ID space to non-secure partition ID space and from secure partition ID space to secure partition ID space. Such legacy devices can encode the non-secure / secure partition ID spaces with a single bit indicator, such that 0b1 indicates non-secure and 0b0 indicates secure. Encoding the aforementioned MPAM_SP using 0b00, 0b01, 0b10, and 0b11, representing secure, non-secure, root, and domain partition ID spaces respectively, may be useful, as this allows static mapping to be implemented simply by appending a more efficient bit 0 to the indication of non-secure / secure requests received from device 454 in region 452. However, static mapping can also be used for other encodings of MPAM_SP.

[0209] When PE 6 and other components within the four PAS and four PARTID space areas 450 request devices in area 452, several options exist:

[0210] 1. Inflexible static mapping turns root PAS and security PAS into security PAS requests for legacy devices, and realm PAS and non-security PAS requests into non-security requests for legacy components. Similarly, it maps the root / security partition ID space to the security partition ID space, and the realm / non-security PAS requests to the non-security partition ID space. Encoding MPAM_SP using 0b00, 0b01, 0b10, and 0b11, representing security, non-security, root, and realm partition IDs, also simplifies the circuitry used to perform this static mapping, as it means the most significant bit of MPAM_SP can simply be discarded to provide single-bit indicators for non-security (0b1) and security (0b0), as can be used by such a legacy device 454.

[0211] 2. A simple programmable space mapper located outside conventional component 454 or conventional region 452. The space mapper controls whether the root partition ID space is mapped to the secure partition ID space or the insecure partition ID space, and whether the domain partition ID space is mapped to the secure partition ID space or the insecure partition ID space.

[0212] a) The mapper can also select whether the root PAS is mapped to a secure PAS or a non-secure PAS, and whether the domain PAS is mapped to a secure PAS or a non-secure PAS. Alternatively, the root PAS can always be mapped to a secure PAS, and the domain PAS can always be mapped to a non-secure PAS. In this case, the programmable aspects of the mapper will affect the partition ID mapping but will not affect the PAS mapping.

[0213] b) The mapper can also indicate via flags (e.g., NO_MON) whether requests from the root partition ID space should not be monitored, and whether requests from the domain partition ID space should not be monitored (this may require a minor redesign of legacy component 454 to implement disabling monitoring when the flag indicates that monitoring should be disabled, but this may be less than the redevelopment work required to support all four partition ID spaces).

[0214] 3. One of the mapper combinations from 2 can be implemented within conventional component 454, thus requiring a greater change in component design compared to that required in 2b.

[0215] In this application, the phrase "configured as..." is used to mean that the elements of the device have a configuration capable of performing the defined operation. In this context, "configuration" means the arrangement or manner of interconnection of hardware or software. For example, the device may have dedicated hardware that provides the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured as" does not mean that the elements of the device need to be changed in any way to provide the defined operation.

[0216] While exemplary embodiments of the invention have been described in detail herein with reference to the accompanying drawings, it should be understood that the invention is not limited to those precise embodiments, and various changes and modifications can be made therein by those skilled in the art without departing from the scope of the invention as defined by the appended claims.

Claims

1. A data processing apparatus, the apparatus comprising: The processing circuit is configured to process instructions in one of at least three domains and issue a memory access request to the memory system specifying a target address indicating the location of the target memory system, each of the at least three domains being associated with a corresponding physical address space. A partition identifier selection circuit is used to select a partition identifier based on programmable partition identifier selection information associated with the current software execution environment that causes the memory access request to be issued. and A partition identifier space selection circuit, wherein the partition identifier space selection circuit is used to select a partition identifier space from at least three partition identifier spaces based on the current domain of the processing circuit; wherein: The selected partition identifier space and the partition identifier together represent information for selecting a set of one or more memory system resource control parameters at the memory system component of the memory system or for selecting at the memory system component whether to update performance monitoring data in response to the memory access request. The set of one or more memory system resource control parameters is used to control the allocation of resources for processing the memory access request or to manage competition for the resources. and The processing circuitry is configured to issue the memory access request to the memory system, wherein the memory access request specifies the partition identifier and the partition identifier space indicator, the partition identifier space indicator including a plurality of bits indicating the selected partition identifier space selected by the partition identifier space selection circuitry.

2. The apparatus of claim 1, wherein the partition identifier space selection circuit is configured to select the selected partition identifier space based on the current domain of the processing circuit and based on programmable control information.

3. The apparatus of claim 2, wherein the partition identifier space selection circuit is configured to select, based on the programmable control information, whether the selected partition identifier space should be a primary partition identifier space associated with the current domain or a candidate partition identifier space associated with the current domain, wherein for at least one of the at least three domains, the candidate partition identifier space is the primary partition identifier space associated with a different domain.

4. The apparatus of claim 3, wherein the primary partition identifier space associated with a given domain is a fixed partition identifier space defined for the given domain independently of the programmable control information.

5. The apparatus of claim 3, wherein for at least one domain, the alternative partition identifier space associated with the domain is a partition identifier space that is variably selected according to the programmable control information.

6. The apparatus according to any one of claims 2 to 5, wherein the processing circuitry is configured to process instructions at one of a plurality of permission levels, and For at least one permission level, at least a portion of the programmable control information is programmable at a higher permission level than the at least one permission level, and the at least a portion of the programmable control information controls the selection of the selected partition identifier space for memory access requests issued at the at least one permission level.

7. The apparatus of claim 6, wherein for at least one subset of the at least one permission level, the processing circuitry is configured such that at least one instruction executed at the permission level of the subset can access forced space indication information, the forced space indication information indicating the selected partition identifier space based on programmable control information programmable at the higher permission level.

8. The apparatus according to any one of claims 2 to 5, wherein the processing circuitry is configured to process instructions at one of a plurality of permission levels, and the programmable control information includes: Hierarchical control activation information, which can be programmed at the first permission level; and Space selection control information, wherein the space selection control information can be programmed at a second permission level with permissions lower than the first permission level; wherein: When the hierarchical control information has a first value, the partition identifier selection circuit is configured to select the selected partition identifier space for a memory access request issued at the second permission level or a third permission level with a permission lower than the second permission level, based on the space selection control information programmable at the second permission level; and When the hierarchical control information has a second value, the partition identifier selection circuit is configured to select the selected partition identifier space for a memory access request issued at the second or third permission level, independently of the space selection control information that can be programmed at the second permission level.

9. The apparatus according to any one of claims 1 to 5, wherein the functional result of processing the memory access request is independent of the partition identifier and the selected partition identifier space.

10. The apparatus according to any one of claims 1 to 5, the apparatus comprising a physical address space selection circuit, the physical address space selection circuit being configured to select a selected physical address space for the memory access request based on the current domain, and the processing circuit being configured to issue the memory access request specifying a physical address space indicator indicating the selected physical address space.

11. The apparatus of claim 10, wherein the physical address space selection circuit is configured to select the selected physical address space based on the current domain and based on physical address space selection information, the physical address space selection information being specified in an address translation entry that provides address translation information corresponding to the target address of the memory access request.

12. The apparatus of claim 11, wherein the partition identifier space selection circuit is configured to select the selected partition identifier space based on the current domain and independently of the physical address space selection information, the physical address space selection information being specified in the address translation entry corresponding to the target address.

13. The apparatus of claim 10, wherein the apparatus comprises: A Physical Alias ​​Point (PoPA) memory system component is configured to dealias multiple alias physical addresses corresponding to the same memory system resource from different physical address spaces, so as to map any one of the multiple alias physical addresses to a dealiased physical address to be provided to at least one downstream memory system component. and At least one pre-PoPA memory system component is provided upstream of the PoPA memory system component, wherein the at least one pre-PoPA memory system component is configured to treat the aliased physical address from a different physical address space as the aliased physical address corresponding to a different memory system resource.

14. The apparatus according to any one of claims 1 to 5, the apparatus comprising a memory system component, the memory system component comprising at least one of: Resource control parameter selection circuit, the resource control parameter selection circuit being used to select one or more sets of memory system resource control parameters based on the partition identifier space indicator and the partition identifier; and / or A performance monitoring and control circuit is used to control whether to update the performance monitoring data in response to the memory access request, based on the partition identifier space indicator and the partition identifier.

15. The apparatus of claim 14, wherein each of the at least three partition identifier spaces is associated with a corresponding field of the at least three fields; and In response to an issued memory access request, a given set of memory system resource control parameters corresponding to a given partition identifier space can be accessed, the memory access request specifying a target address in the physical address space corresponding to the domain associated with the given partition identifier space.

16. The apparatus of any one of claims 1 to 5, the apparatus comprising a bridging circuit located at a boundary between a first region of the apparatus and a second region of the apparatus, the first region including one or more components supporting the at least three partition identifier spaces, the second region including one or more components supporting fewer partition identifier spaces than the one or more components in the first region, wherein the bridging circuit is configured to remap the partition identifier space indicator for memory access requests passed between the first region and the second region.

17. The apparatus of claim 16, wherein the bridging circuit is configured to remap the partition identifier space indicator according to one of the following: Fixed mapping; and Programmable mapping.

18. The apparatus of claim 16, wherein the bridging circuitry is further configured to remap a physical address space indicator that indicates a selected physical address space associated with the memory access request transmitted between the first region and the second region.

19. A memory system component, the memory system component comprising: A memory access request receiving circuit is configured to receive a memory access request specifying a target address indicating a target memory system location in the memory system, including a partition identifier space indicator with multiple bits indicating a selected partition identifier space selected from at least three partition identifier spaces, and a partition identifier associated with the current software execution environment that caused the memory access request to be issued. and At least one of the following: A resource control circuit, the resource control circuit being configured to select one or more sets of memory system resource control parameters based on the partition identifier space indicator and the partition identifier, and to control the allocation of resources for processing the memory access request or manage contention for the resources based on the selected set of memory system resource control parameters. and / or A performance monitoring and control circuit is used to control whether to update performance monitoring data in response to a memory access request, based on the partition identifier space indicator and the partition identifier.

20. A data processing method, the method comprising: Process instructions in one of at least three domains, each of the at least three domains being associated with a corresponding physical address space; The partition identifier is selected based on programmable partition identifier selection information associated with the current software execution environment that caused the memory access request to be issued. Select a partition identifier space from at least three partition identifier spaces based on the current domain; as well as The memory access request is sent to the memory system, the memory access request specifying a target address indicating the location of the target memory system, the partition identifier, and a partition identifier space indicator including multiple bits indicating the selected partition identifier space; as well as At least one of the following: Based on the partition identifier space indicator and the partition identifier, select one or more sets of memory system resource control parameters, and control the allocation of resources for processing the memory access request or manage contention for the resources based on the selected set of memory system resource control parameters. And / or The partition identifier space indicator and the partition identifier control whether to update performance monitoring data in response to the memory access request.

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