Solid-state imaging device, driving method of solid-state imaging device and electronic device

Abstract

A solid-state imaging device, a driving method for the solid-state imaging device, and an electronic device are provided, which can read out small signals in low illumination with low noise while maintaining sensitivity and saturation charge number, and can achieve pixel miniaturization. The pixel circuit (200) includes: a readout pixel (210) that performs photoelectric conversion by a photodiode (PD11) and can read out a signal corresponding to the illumination conditions of the incident light, and includes an overflow path to a floating diffusion layer (FD11); a comparator (220) that compares a voltage signal (Sfout) read from the readout pixel (210) with a reference signal (Vref) and outputs a comparison result signal (Vout) corresponding to the comparison result; and a selection counter circuit (230) that includes a selection circuit and a counter circuit, wherein the selection circuit can select either an external clock or the comparator output (Vout), and the counter circuit counts the output from the selection circuit.

Description

Technical Field

[0001] This invention relates to a solid-state imaging device, a driving method for the solid-state imaging device, and an electronic device. Background Technology

[0002] CMOS (Complementary Metal Oxide Semiconductor) image sensors have been put into practical use as solid-state imaging devices (image sensors) that use photoelectric conversion elements that detect light and generate charge.

[0003] CMOS image sensors have been widely used as part of various electronic devices such as digital cameras, camcorders, surveillance cameras, medical endoscopes, personal computers (PCs), and mobile phones.

[0004] CMOS image sensors include FD amplifiers with photodiodes (photoelectric conversion elements) and floating diffusion layers (FD) in each pixel. The mainstream readout type of this CMOS image sensor is column-to-column output, that is, a row in the pixel array is selected and read out in the column output direction.

[0005] Furthermore, various schemes have actually been proposed for the pixel signal readout (output) circuit of the parallel output CMOS image sensor.

[0006] One of its most advanced circuits is an analog-to-digital converter (ADC) in each column that extracts pixel signals as digital signals (see, for example, Patent Documents 1 and 2).

[0007] In this CMOS image sensor equipped with a column-to-parallel ADC (column AD CMOS image sensor), the comparator compares the so-called RAMP wave and the pixel signal (voltage signal), and performs AD conversion by digital CDS through a downstream counter.

[0008] However, while this type of CMOS image sensor can transmit signals at high speed, it has the drawback of not being able to perform global shutter readout.

[0009] In contrast, a digital pixel sensor has been proposed, in which each pixel is configured with an ADC (and consequently a memory section) including a comparator, which enables a global shutter to be executed at the same timing for all pixels in the pixel array to start and end exposure at the same time (see, for example, Patent Documents 3 and 4).

[0010] In a CM OS image sensor that incorporates the aforementioned conventional digital pixel sensor, a global shutter function can be achieved. Furthermore, by configuring an ADC (Automatic DC-DC converter) including a comparator in each pixel, a wide dynamic range can be achieved through a specified readout mode.

[0011] In addition, as a method to expand the dynamic range, for example, there is a method that reads out two signals with different storage times from the same pixel of an image sensor and combines the two signals to expand the dynamic range, or a method that combines a signal with a small dynamic range from a high-sensitivity pixel with a signal with an expanded dynamic range from a low-sensitivity pixel to expand the dynamic range.

[0012] Patent document 5 proposes a unit pixel structure for infrared imaging, which has two input segments covering both low and high light levels, and an internal automatic input selection circuit for extending dynamic range.

[0013] Furthermore, as an achievable digital installation, Patent Document 5 describes a technique for applying a pulse frequency modulation (PFM) ADC to a unit pixel.

[0014] Furthermore, Patent Document 6 describes a pixel circuit for a digital readout system with PFM function and extended counter that achieves excellent quantum noise performance.

[0015] Here, we will combine Figure 1 and Figure 2 The basic structure and functions of PFM are explained.

[0016] Figure 1 This is a diagram illustrating a first configuration example of a pixel circuit in a digital readout system with PFM functionality.

[0017] Figure 2 This is a diagram illustrating a second configuration example of a pixel circuit in a digital readout system with PFM functionality.

[0018] Figure 1 The pixel circuit 1 is composed of a photodiode PD1, a reset transistor RST-Tr, a comparator 2, and a counter 3.

[0019] In pixel circuit 1, comparator 2 compares the voltage of the charge storage node ND1 of photodiode PD1 with the reference voltage Vref1 (=VSA1) which is equivalent to the saturation voltage VSA1 of photodiode PD1.

[0020] As a result of the comparison, if the node voltage ND1 reaches the saturation voltage VSA1, the output of comparator 2 is fed back to the gate of the reset transistor RST-Tr as the feedback reset signal FRST, thereby turning on the reset transistor RST-Tr.

[0021] That is, the stored charge of photodiode PD1 is reset by a feedback reset action. Furthermore, counter 3 counts the number of resets of photodiode PD1.

[0022] Figure 2 The pixel circuit 1A has a transmission transistor TG-Tr connected between the charge storage node ND1 of the photodiode PD1 and the floating diffusion layer FD1, which serves as the output node. The conduction state of the transmission transistor TG-Tr is controlled by the control signal TG.

[0023] Furthermore, in pixel circuit 1A, a logic circuit 4 is configured in the feedback path of the feedback reset signal FRST. Considering the delay of logic circuit 4, delay circuits 5-1 and 5-2 are configured on the output side of comparator 2 and the input side of logic circuit 4.

[0024] In pixel circuit 1A, the transmission transistor TG-Tr is controlled to be in the on state during exposure and to be in the off state during the reset phase of floating diffusion layer FD1.

[0025] Existing technical documents

[0026] Patent documents

[0027] Patent Document 1: Japanese Patent Application Publication No. 2005-278135

[0028] Patent Document 2: Japanese Patent Application Publication No. 2005-295346

[0029] Patent Document 3: US 7164114 B2 FIG,4

[0030] Patent Document 4: US 2010 / 0181464 A1

[0031] Patent Document 5: US 9324745 B2

[0032] Patent Document 6: US 9197834 B2 Summary of the Invention

[0033] The technical problem to be solved by the present invention

[0034] However, the above Figure 1 and Figure 2 The pixel circuits 1 and 1A have the following disadvantages.

[0035] exist Figure 1In the pixel circuit 1, since there is no transmission transistor TG-Tr, the dark current of photodiode PD1 becomes a major problem. In the above operation, it is difficult to read out the small signal of photodiode PD1 under low illumination.

[0036] Although Figure 2 The pixel circuit 1A has a transmission transistor TG-Tr, but the dark current of the photodiode PD1 at the silicon interface under the transmission transistor TG-Tr remains a significant problem. Furthermore, in the aforementioned operation, it is difficult to read out small signals from the photodiode PD1 under low illumination.

[0037] Furthermore, in the pixel circuit 1A, since it has logic circuits (NAND, NOR) 4 that control the transmission transistor TG-Tr, it is difficult to achieve miniaturization of the pixel size.

[0038] The present invention provides a solid-state imaging device, a driving method for the solid-state imaging device, and an electronic device, which can read out small signals under low illumination with low noise while maintaining sensitivity and saturation charge number, and can achieve miniaturization of pixel size.

[0039] Technical solutions for solving technical problems

[0040] The solid-state imaging device of the first aspect of the present invention comprises: a readout pixel that performs photoelectric conversion and is capable of reading out a signal corresponding to the illuminance condition of incident light; a comparator that compares a voltage signal read from the readout pixel with a reference signal and outputs a comparison result signal corresponding to the comparison result; and a selection counter circuit comprising a selection circuit and a counter circuit, the selection circuit being capable of selecting either an external clock or a comparator output, and the counter circuit counting the output from the selection circuit. The readout pixel includes: a photoelectric conversion element that stores a charge corresponding to the amount of incident light during exposure; a transmission element that is held in a non-conductive state during exposure and held in a conductive state during transmission to transmit the charge stored in the photoelectric conversion element; and a floating diffusion layer that holds the charge transmitted by the transmission element to... The device reads out the charge as a voltage signal; it has at least one reset element capable of performing a reset process to discharge the stored charge of the floating diffusion layer; and an overflow path capable of allowing the charge overflowing from the photoelectric conversion element to overflow towards the floating diffusion layer region. Under high illumination conditions, if the voltage signal corresponding to the stored charge of the floating diffusion layer reaches the reference voltage, the readout pixel, the comparator, the selection circuit, and the counter circuit perform a self-reset of the floating diffusion layer through a feedback reset action of the comparison result signal of the comparator, and operate in a pulse frequency modulation (PFM) mode based on the reset frequency of the floating diffusion layer according to the comparison result signal, counting by the selection counter circuit. Under low illumination conditions, it performs a dual-sampling readout mode operation using the stored charge and overflow charge of the photoelectric conversion element.

[0041] The second aspect of this invention is a driving method for a solid-state imaging device, the solid-state imaging device comprising: a readout pixel that performs photoelectric conversion and is capable of reading out a signal corresponding to the illuminance conditions of incident light; a comparator that compares a voltage signal read from the readout pixel with a reference signal and outputs a comparison result signal corresponding to the comparison result; and a selection counter circuit comprising a selection circuit and a counter circuit, the selection circuit being capable of selecting either an external clock or a comparator output, the counter circuit counting the output from the selection circuit, the readout pixel comprising: a photoelectric conversion element that stores a charge corresponding to the amount of incident light during exposure; a transmission element that is held in a non-conductive state during exposure and held in a conductive state during transmission to transmit the charge stored in the photoelectric conversion element; and a floating diffusion layer. It maintains the charge transmitted by the transmission element to read the charge as a voltage signal; at least one reset element capable of performing a reset process to discharge the stored charge of the floating diffusion layer; and an overflow path capable of allowing the charge overflowing from the photoelectric conversion element to overflow towards the floating diffusion layer region, wherein, under high illumination conditions, if the voltage signal corresponding to the maintained charge of the floating diffusion layer reaches the reference voltage, the floating diffusion layer is self-reset by the feedback reset action of the comparison result signal of the comparator, and the floating diffusion layer is operated in pulse frequency modulation (PFM) mode operation based on the reset frequency of the floating diffusion layer according to the comparison result signal, and under low illumination conditions, a dual sampling readout mode operation using the stored charge and overflow charge of the photoelectric conversion element is performed.

[0042] The electronic device of the third aspect of the present invention comprises: a solid-state imaging device; and an optical system for imaging an image of a subject in the solid-state imaging device, the solid-state imaging device comprising: a readout pixel that performs photoelectric conversion and is capable of reading out a signal corresponding to the illuminance conditions of incident light; a comparator that compares a voltage signal read from the readout pixel with a reference signal and outputs a comparison result signal corresponding to the comparison result; and a selection counter circuit comprising a selection circuit and a counter circuit, the selection circuit being capable of selecting either an external clock or a comparator output, the counter circuit counting the output from the selection circuit, the readout pixel comprising: a photoelectric conversion element that stores a charge corresponding to the amount of incident light during exposure; a transmission element that is held in a non-conductive state during exposure and held in a conductive state during transmission to transmit the charge stored in the photoelectric conversion element; and a floating diffusion layer. The system maintains the charge transmitted by the transmission element to read out the charge as a voltage signal; at least one reset element capable of performing a reset process to discharge the stored charge of the floating diffusion layer; and an overflow path capable of allowing the charge overflowing from the photoelectric conversion element to overflow towards the floating diffusion layer region. Under high illumination conditions, if the voltage signal corresponding to the stored charge of the floating diffusion layer reaches the reference voltage, the readout pixel, the comparator, the selection circuit, and the counter circuit perform a self-reset of the floating diffusion layer through a feedback reset action of the comparison result signal of the comparator, and operate in a pulse frequency modulation (PFM) mode based on the reset frequency of the floating diffusion layer according to the comparison result signal, counting by the selection counter circuit. Under low illumination conditions, a dual-sampling readout mode operation using the stored charge and overflow charge of the photoelectric conversion element is performed.

[0043] Beneficial effects

[0044] According to the present invention, it is possible to read out small signals under low illumination with low noise while maintaining sensitivity and saturation charge number, and it is possible to achieve miniaturization of pixel size. Attached Figure Description

[0045] Figure 1 This is a diagram illustrating a first configuration example of a pixel circuit in a digital readout system with PFM functionality.

[0046] Figure 2 This is a diagram illustrating a second configuration example of a pixel circuit in a digital readout system with PFM functionality.

[0047] Figure 3 This is a block diagram illustrating an example of the configuration of a solid-state imaging device according to the first embodiment of the present invention.

[0048] Figure 4This is a block diagram illustrating a basic configuration example of the pixel circuit of the solid-state imaging device according to the first embodiment of the present invention.

[0049] Figure 5 This is a circuit diagram illustrating an example of the configuration of a readout pixel in the pixel circuit of the first embodiment of the present invention.

[0050] Figure 6 This is a circuit diagram illustrating an example of the configuration of a comparator according to the first embodiment of the present invention.

[0051] Figure 7 This is a simplified cross-sectional view showing an example of the configuration of the readout pixel according to the first embodiment of the present invention.

[0052] Figure 8 This is a timing diagram illustrating an example of the readout sequence of the pixel circuit in PFM mode and dual-sample readout mode under high illumination conditions for the solid-state imaging device according to the first embodiment of the present invention.

[0053] Figure 9 This is a diagram illustrating the sequence of operations and potential shifts of the pixel circuit in PFM mode and dual-sampling readout mode under high illumination conditions for the solid-state imaging device according to the first embodiment of the present invention.

[0054] Figure 10 This is a timing diagram illustrating an example of the readout sequence of the pixel circuit in PFM mode and dual-sample readout mode under low-light conditions for a solid-state imaging device according to the first embodiment of the present invention.

[0055] Figure 11 This is a diagram illustrating the sequence of operations and potential shifts of the pixel circuit in low-light conditions of the PFM mode and dual-sampling readout mode of the solid-state imaging device according to the first embodiment of the present invention.

[0056] Figure 12 This is a graph showing the linearity of the composite signal of each readout signal in the dual-sampling readout mode of the solid-state imaging device according to the first embodiment of the present invention.

[0057] Figure 13 This is a circuit diagram illustrating an example of the configuration of a readout pixel in the pixel circuit of the second embodiment of the present invention.

[0058] Figure 14 This is a simplified cross-sectional view showing an example of the configuration of a charge storage and transport system having a shutter gate transistor, which is a major part of the pixel circuit of the second embodiment of the present invention.

[0059] Figure 15This is a timing diagram illustrating an example of the readout sequence of the pixel circuit in PFM mode and dual-sample readout mode under high illumination conditions for a solid-state imaging device according to a second embodiment of the present invention.

[0060] Figure 16 This is a timing diagram illustrating an example of the readout sequence of the pixel circuit in PFM mode and dual-sample readout mode under low-light conditions for a solid-state imaging device according to a second embodiment of the present invention.

[0061] Figure 17 This is a circuit diagram illustrating an example of the configuration of a pixel circuit according to the third embodiment of the present invention.

[0062] Figure 18 This is a circuit diagram illustrating an example of the pixel circuit configuration of the solid-state imaging device according to the fourth embodiment of the present invention.

[0063] Figure 19 This is a circuit diagram illustrating an example of the pixel circuit configuration of the solid-state imaging device according to the fifth embodiment of the present invention.

[0064] Figure 20 This is a diagram illustrating an example of an application device for a solid-state imaging apparatus according to an embodiment of the present invention.

[0065] Figure 21 It is a schematic representation Figure 20 The timing diagram of the operating principle of the application device.

[0066] Figure 22 This is a diagram illustrating an example of the configuration of an electronic device to which an embodiment of the present invention is applied. Detailed Implementation

[0067] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0068] (First Implementation)

[0069] Figure 3 This is a block diagram illustrating an example of the configuration of a solid-state imaging device according to the first embodiment of the present invention.

[0070] Figure 4 This is a block diagram illustrating a basic configuration example of the pixel circuit of the solid-state imaging device according to the first embodiment of the present invention.

[0071] In this embodiment, the solid-state imaging device 10 is, for example, a CMOS image sensor.

[0072] like Figure 3As shown, the solid-state imaging device 10 has a pixel unit 20 as the imaging unit, a vertical scanning circuit (row scanning circuit) 30, a readout circuit (column readout circuit) 40, a horizontal scanning circuit (column scanning circuit) 50, and a timing control circuit 60 as its main components.

[0073] Among these components, for example, the pixel signal readout unit 70 is composed of the vertical scanning circuit 30, the readout circuit 40, the horizontal scanning circuit 50, and the timing control circuit 60.

[0074] In this first embodiment, the solid-state imaging device 10, as described below, includes a pixel circuit 200 arranged in rows and columns in the pixel section 20, comprising: a readout pixel 210 that performs photoelectric conversion via a photodiode PD11 as a photoelectric conversion element, capable of reading out a signal corresponding to the illuminance condition of the incident light, and including an overflow path to a floating diffusion layer FD (Floating Diffusion) 11; a comparator 220 that compares the voltage signal (SFout) read from the readout pixel 210 with a reference signal Vref, and outputs a comparison result signal Vout corresponding to the comparison result; a selection counter circuit 230 that receives the comparison result signal Vout from the comparator 220, selects a counting clock for the counter, and performs a counting operation synchronized with the selected clock; and a memory circuit 240 that stores the digitized data of the selection counter circuit 230 corresponding to the comparison result signal Vout from the comparator 220.

[0075] The readout pixel 210, comparator 220, and select counter circuit 230 operate in PFM (pulse frequency modulation) mode under high illumination conditions and in dual sampling readout (e.g., LOFIC) mode using stored charge and overflow charge with photoelectric conversion elements under low illumination conditions.

[0076] In PFM mode operation under high illumination conditions, if the voltage signal corresponding to the holding charge of the floating diffusion layer FD11 reaches the reference voltage of the comparator, the floating diffusion layer FD11 is self-reset by the feedback reset action FRST11 of the comparison result signal Vout of the comparator 220, and the number of resets (frequency) of the floating diffusion layer FD11 is counted by the selector counter circuit 230 according to the comparison result signal Vout of the comparator 220.

[0077] In the solid-state imaging device 10 of the first embodiment of the present invention, as described laterally, the pixel circuit 210 is provided with a structure called a lateral overflow storage capacitor (hereinafter referred to as "LOFIC"). Under low illumination conditions, it performs a dual-sampling readout mode (LOFIC mode) operation using dual gain related to the stored charge and overflow charge of the photodiode PD11, which is a photoelectric conversion element.

[0078] In the pixel circuit 200, the readout pixel 210 and the selection counter circuit 230 can selectively operate in PFM mode or dual-sample readout mode according to the mode selection signal SMS.

[0079] In PFM mode, the readout pixel 210 uses the first comparison result signal Vout11 as the feedback reset signal FRST11 to turn on the reset element, thereby resetting the floating diffusion layer FD11 to the specified potential VAPIX.

[0080] In PFM mode, a constant (fixed) first reference signal (reference voltage) Vref11, which is equivalent to the saturation voltage of the photodiode PD11, which is a photoelectric conversion element, is provided to comparator 220. If the voltage signal corresponding to the holding charge of the floating diffusion layer FD11 reaches the first reference signal level Vref11, the first comparison result signal Vout11 is output to the readout pixel 210 and the selection counter circuit 230.

[0081] In dual-sampling readout mode, a continuously variable ramp-shaped second reference signal Vref12 is provided to comparator 220, and the comparison result of the voltage signal corresponding to the holding charge of the floating diffusion layer FD11 and the second reference signal Vref12 is output to the selection counter circuit 230 as the second comparison result signal Vout12.

[0082] In PFM mode, the selector counter circuit 230 counts the first comparison result signal Vout11 of the comparator 220, and in dual-sampling readout mode, it latches the second comparison result signal Vout12 synchronously with a clock of a specified frequency.

[0083] exist Figure 4 In the example, the selector counter circuit 230 is configured to include a selector 231 and a counter 232.

[0084] The input terminal A of selector 231 is connected to the output line of the comparison result signal Vout of comparator 220, the input terminal B is connected to the supply line of clock pulse CP, and the output terminal C is connected to the input terminal (e.g., clock terminal) of counter 232.

[0085] Selector 231 selectively connects output terminal C and input terminal A or B according to the mode selection signal SMS, and selects the signal input to counter 232.

[0086] Specifically, when the mode selection signal SMS specifies the PFM mode, the selector 231 connects the input terminal A to the output terminal C and provides the comparison result signal Vout11 of the comparator 220 to the counter 232.

[0087] When the mode selection signal MSM specifies the dual sampling readout mode, selector 231 connects input terminal B to output terminal C and provides clock pulse CP of a specified frequency to counter 232.

[0088] In PFM mode, counter 232 counts the first comparison result signal Vout11 of comparator 220, and in dual-sample readout mode, it latches the second comparison result signal Vout12 synchronously with the clock pulse CP.

[0089] Furthermore, in this first embodiment, under high illumination conditions, a PFM mode is specified in the exposure period after the reset of the photodiode PD11, which serves as a photoelectric conversion element, and the floating diffusion layer FD11, and a double sampling readout mode is specified after the PFM mode.

[0090] In PFM mode, during the exposure period PEXP, the following actions are repeatedly performed: the overflow of charge from photodiode PD11 to floating diffusion layer FD11; the feedback reset action of the comparison result signal Vout of comparator 220 to self-reset floating diffusion layer FD11; and the counting action of the number of resets (frequency) of floating diffusion layer FD11 by selection counter circuit 230.

[0091] In this embodiment, the actual charge generated can be counted by counting the number of resets, thus preventing false detection even when unstable light such as pulsed light is incident during exposure.

[0092] Furthermore, in this first embodiment, the readout unit 70 is configured to perform a first conversion gain mode readout and a second conversion gain mode readout during readout. The first conversion gain mode readout reads out pixel signals with a first conversion gain corresponding to the first capacitor, and the second conversion gain mode readout reads out pixel signals with a second conversion gain corresponding to the second capacitor (different from the first capacitor).

[0093] That is, the solid-state imaging device 10 of this first embodiment is provided as a solid-state imaging device with a wide dynamic range. During readout, within a pixel, it outputs a signal by switching a first conversion gain (e.g., high conversion gain: HCG) mode and a second conversion gain (low conversion gain: LCG) mode for the charge (electrons) converted by photoelectric conversion during a single exposure (storage period), and outputs both a bright signal and a dark signal.

[0094] The following will describe in detail, after explaining a specific configuration example of the readout pixel 210 of the solid-state imaging device 10, a structural example of the embedded diode (PPD) section and the overflow path.

[0095] Here, an example of the configuration of the readout pixel 210 with the LOFIC structure will be explained.

[0096] (Specific example of the composition of readout pixel 210)

[0097] Figure 5 This is a circuit diagram illustrating an example of the configuration of a readout pixel in the pixel circuit of the first embodiment of the present invention.

[0098] In the pixel section 20, multiple pixel circuits 200, each having a readout pixel 210 including a photodiode (photoelectric conversion element) and an in-pixel amplifier, are arranged in a two-dimensional matrix (N rows × M columns).

[0099] For example, such as Figure 5 As shown, the readout pixel 210 has a photodiode PD11 as a photoelectric conversion element, a transfer transistor TG11-Tr as a charge transfer gate (transfer element), a reset transistor RST11-Tr as a reset element, a self-reset reset transistor RST12-Tr, an AND gate AD11, a storage transistor SG11-Tr as a storage element, and a storage capacitor CS11 as a storage capacitor element.

[0100] In addition, in this first embodiment, as described later, the source follower transistor SF11-Tr, which is a source follower element, is shared as one of the transistors in the differential transistor pair of comparator 220.

[0101] The photodiode PD11 generates and stores a signal charge (in this case, electrons) corresponding to the amount of incident light.

[0102] The following explanation will cover the case where the signal charge is an electron and each transistor is an n-type transistor. However, the signal charge can also be a hole, and each transistor can also be a p-type transistor.

[0103] In each readout pixel 210, an embedded photodiode (PPD) is used as a photodiode (PD).

[0104] Because of the presence of interface energy levels caused by defects such as dangling bonds on the substrate surface where a photodiode (PD) is formed, a large amount of charge (dark current) may be generated due to heat, which may result in the inability to read out the correct signal.

[0105] In embedded photodiodes (PPDs), dark current interference with the signal can be reduced by embedding the charge storage portion of the photodiode (PD) into the substrate.

[0106] The transmission transistor TG11-Tr is connected between the embedded photodiode (PPD) and the floating diffusion layer FD11, and is controlled by the control signal TG.

[0107] The transfer transistor TG11-Tr is selected to be in the on state during the period when the control signal TG is high (H), and transfers the charge (electrons) that is photoelectrically converted by the photodiode PD11 and stored in the storage node ND10 to the floating diffusion layer FD11.

[0108] exist Figure 5 In the example, the reset transistor RST11-Tr is connected between the power supply potential VAPIX and the storage transistor SG11-Tr connected to the floating diffusion layer FD11, and is controlled by the control signal RST.

[0109] The reset transistor RST11-Tr is selected to be in the on state when the control signal RST is at level H. When the storage transistor SG11-T is in the on state, the floating diffusion layer FD11 is reset to the power supply potential VAAPIX.

[0110] exist Figure 5 In the example, the reset transistor RST12-Tr for self-reset is connected in parallel with the reset transistor RST11-Tr between the power supply potential VAAPIX and the storage transistor SG11-Tr connected to the floating diffusion layer FD11, and is controlled by the output control signal SRST of the AND gate AD11.

[0111] The self-reset transistor RST12-Tr is selected to be in the on state when the control signal SRST is at level H. When the storage transistor SG11-Tr is in the on state, the floating diffusion layer FD11 is reset to the power supply potential VAAPIX.

[0112] In the first embodiment, in PFM mode, during the self-reset operation, the reset transistor RST12-Tr and the storage transistor SG11-Tr are kept in the on state, and the floating diffusion layer FD11 and the storage capacitor CS11 are reset.

[0113] Furthermore, in this first embodiment, by selectively connecting the floating diffusion layer FD11 and the storage capacitor CS11 through the storage transistor SG11-Tr, the capacitance of the floating diffusion layer FD11 can be changed to a first capacitor or a second capacitor, and the conversion gain can be converted to a first conversion gain (high conversion gain: HCG) determined by the first capacitor or a second conversion gain (low conversion gain: LCG) determined by the second capacitor.

[0114] The source of the storage transistor SG11-Tr is connected to the floating diffusion layer FD11, for example.

[0115] The first electrode EL1 of the storage capacitor CS11 is connected to the reference potential VSS (e.g., ground potential GND), and the second electrode EL2 is connected to the drain of the capacitor connection node ND11, which serves as the storage transistor SG11-Tr.

[0116] The storage transistor SG11-Tr is controlled by the control signal SG applied to the gate via the control line.

[0117] The storage transistor SG11-Tr is selected to be in the on state when the control signal SG is at level H, and connects the floating diffusion layer FD11 and the storage capacitor CS11.

[0118] During the first conversion gain (high conversion gain: HCG) signal readout processing in dual-sample readout mode, the storage transistor SG11-Tr is kept in a non-conducting state, so that the charge of the floating diffusion layer FD11 is separated from the charge of the storage capacitor CS11 for readout processing.

[0119] During the second conversion gain (low conversion gain: LCG) signal readout processing in dual-sample readout mode, the storage transistor SG11-Tr is kept in the on state, so that the charge of the floating diffusion layer FD11 is shared (mixed) with the charge of the storage capacitor CS11 for readout processing.

[0120] exist Figure 5 In the example, the storage transistor SG11-Tr is connected between the floating diffusion layer FD11 and the reset transistors RST11-Tr and RST12-Tr, and a storage capacitor CS11 is connected between its connection node ND11 and the reference potential VSS. However, the connection configuration is not limited to this.

[0121] For example, the reset transistor RST11-Tr and the storage transistor SG11-Tr can be directly connected to the floating diffusion layer FD11, respectively.

[0122] One input terminal of AND gate AD11 is connected to the supply line of the reset count signal RCNT, and the other input terminal is connected to the supply line of the comparison result signal Vout of comparator 220. The output terminal of control signal SRST is connected to the gate of reset transistor RST12-Tr for self-reset.

[0123] The reset count signal RCNT is synchronized with the mode selection signal SMS. For example, when the mode selection signal SMS is high during the PFM mode, the reset count signal RCNT is provided at a high level during the same period. When the mode selection signal SMS is low during the dual-sample readout mode, the reset count signal RCNT is provided at a low level during the same period.

[0124] Therefore, AND gate AD11 takes the logical product of the reset count signal RCNT, which is provided at a high level during PFM mode, and the comparison result signal Vout of comparator 220, and outputs the control signal SRST at a high level during the period when the comparison result signal Vout is at a high level.

[0125] As a result, the self-reset transistor RST12-Tr is kept in the on state while the control signal SRST is high.

[0126] In this first embodiment, the source follower transistor SF11-Tr, which is a source follower element, is shared as one of the transistors in the differential transistor pair of comparator 220.

[0127] Here, a specific example of the configuration of comparator 220 will be explained.

[0128] Example of comparator 220 configuration

[0129] The comparator 220 of this first embodiment is configured with a differential transistor pair and an active load circuit. In the differential transistor pair, the signal voltage VSL is provided to the gate of one transistor, and the fixed voltage of the first reference signal Vref11 or the ramp signal RAMP of the second reference signal Vref12 is provided to the gate of the other transistor. The signal voltage VSL is compared with the reference voltage Vref or the ramp signal RAMP. The active load circuit is connected to the drain side of one transistor and the drain side of the other transistor to form a current mirror.

[0130] Figure 6 This is a circuit diagram showing an example of the configuration of the comparator according to the first embodiment.

[0131] Figure 6 The comparator 220 is composed of PMOS transistors PT21 and PT22, NMOS transistors NT21 and NT22, current source I21, and nodes ND21 and ND22.

[0132] The source of PMOS transistor PT21 and the source of PMOS transistor PT22 are connected to each other, and their connection node is connected to the power supply potential VDD.

[0133] The source of NMOS transistor PT21 and the source of NMOS transistor PT22 are connected to each other, and their connection node is connected to the current source I21 connected to the reference potential VSS.

[0134] The drain of PMOS transistor PT21 is connected to the drain of NMOS transistor N21, and the connection point forms node ND21.

[0135] The drain of PMOS transistor PT22 is connected to the drain of NMOS transistor NT22, and the connection point forms node ND22.

[0136] Furthermore, node ND21 is connected to the gates of PMOS transistors PT21 and PT22, and node ND22 is connected to the output node ND221.

[0137] Among these constituent components, NMOS transistors NT21 and NT22, whose sources are connected to each other, form a differential transistor pair 221.

[0138] A transistor 221-1 is formed by NMOS transistor NT21, and another transistor 221-2 is formed by NMOS transistor NT22.

[0139] Furthermore, a voltage signal VSL is provided to the gate of NMOS transistor NT21, which forms a transistor 221-1, and a fixed voltage as a first reference signal Vref11 or a ramp signal RAMP as a second reference signal Vref12 is provided to the gate of NMOS transistor NT22, which forms another transistor 221-2.

[0140] Furthermore, an active load circuit 222, which forms a current mirror by PMOS transistors PT21 and PT22, is provided on the drain side of NMOS transistor NT21, which is a transistor, and on the drain side of NMOS transistor NT22, which is another transistor.

[0141] In the comparator 220 with this configuration, the connection node ND22 between the drain of the NMOS transistor NT22 (which is another transistor) and the drain of the PMOS transistor PT22 (which constitutes the active load circuit 222) is connected to the output node ND221 of the comparison result signal Vout.

[0142] That is, comparator 220 outputs the comparison result signal Vout from the drain side of NMOS transistor NT22, which is another transistor.

[0143] For example, comparator 220 performs a comparison operation between voltage signal VSL and first reference signal Vref11 or second reference signal Vref12. When voltage signal VSL and first reference signal Vref11 or second reference signal Vref12 become equal, the output level of comparison result signal Vout is reversed from an inactive level (e.g., low level) to an active level (high level).

[0144] The source follower transistor SF11-Tr, which is shared with a differential transistor of comparator 220, outputs a readout signal (voltage signal) from the column output. The readout signal from the column output is obtained by converting the charge of the floating diffusion layer FD11 into a voltage signal according to the gain corresponding to the capacitor.

[0145] For example, since the gates of the transmission transistor TG11-Tr, the reset transistors RST11-Tr and RST12-Tr, and the storage transistor SG1-Tr are connected in the row unit, these actions are performed simultaneously and in parallel for each pixel in a row.

[0146] In the pixel section 20, the pixel circuit 200 is configured as N rows × M columns, so there are N control lines and M vertical signal lines.

[0147] exist Figure 3 In this context, each control line is represented as a single row scan control line.

[0148] The vertical scanning circuit 30 drives pixels in the shutter line and readout line through the line scanning control line under the control of the timing control circuit 60.

[0149] Furthermore, the vertical scanning circuit 30 outputs a readout signal and a row selection signal for the row address of the shutter row, which resets the charge stored in the photodiode PD11, based on the address signal.

[0150] The readout circuit 40 can be configured to include multiple column signal processing circuits (not shown) configured to correspond to each column output of the pixel unit 20, and can perform column-parallel processing by the multiple column signal processing circuits.

[0151] The horizontal scanning circuit 50 scans the signal processed by the multiple column signal processing circuits of the readout circuit 40, transmits the signal in the horizontal direction, and outputs the signal to a signal processing circuit (not shown).

[0152] The timing control circuit 60 generates timing signals required for signal processing of the pixel unit 20, vertical scanning circuit 30, readout circuit 40, and horizontal scanning circuit 50.

[0153] The above provides a general overview of the structure and function of each part of the solid-state imaging device 10.

[0154] Next, the structure and function of the readout pixels, etc., in this first embodiment will be described in detail.

[0155] (Specific example of the composition of readout pixel 210)

[0156] Figure 7 This is a simplified cross-sectional view showing an example of the configuration of the readout pixel according to the first embodiment of the present invention.

[0157] Additionally, here, reference numeral 2100 indicates a readout pixel including an embedded photodiode (PPD).

[0158] Figure 7 The readout pixel 2000 has a semiconductor substrate (hereinafter referred to as substrate) 2100, which has a first substrate surface 2110 side (e.g., back side) irradiated by light L and a second substrate surface 2120 side (front side) opposite to the first substrate surface 2110 side.

[0159] The readout pixel 2000 has: a photoelectric conversion section 2200 as a photodiode PD11, which includes a first conductivity type (n-type in this embodiment) semiconductor layer (n-layer) 2210 formed in a manner embedded in a substrate 2100, and has photoelectric conversion function for received light and charge storage function; and a second conductivity type (p-type in this embodiment) semiconductor layer 2300, which is formed on at least a side portion of the n-layer (first conductivity type semiconductor layer) 2210 of the photoelectric conversion section 2200.

[0160] Furthermore, the n-layer (first conductive semiconductor layer) 2210 of the photoelectric conversion unit 2200 is formed with a concentration gradient so that the impurity concentration of n-ions gradually increases from the first substrate surface 2110 side to the second substrate surface 2120 side.

[0161] Furthermore, the readout pixel 2000 includes: a transfer transistor TG11-Tr, which is capable of transferring the charge stored in the photoelectric conversion unit 2200; a floating diffusion layer FD11, which transfers the charge through the transfer transistor TG11-Tr; a storage transistor SG11-Tr, the source of which is connected to the floating diffusion layer FD11; and a storage capacitor CS11, which serves as a storage capacitor element, and stores the charge from the floating diffusion layer FD11 via the drain side of the storage transistor SG11-Tr.

[0162] In the readout pixel 2000, the storage capacitor CS11, which is a storage capacitor element, is formed such that it has a portion that spatially overlaps with the photoelectric conversion unit 2200 in a direction orthogonal to the substrate surface (Z direction of the orthogonal coordinate system in the figure) on the side of the second substrate surface 2120.

[0163] Furthermore, in the photoelectric conversion unit 220, a second conductive semiconductor region (p+ region) 2230 with a higher impurity concentration than the p layer (second conductive semiconductor layer) 2300 on the surface of the second substrate surface 2120 side of the n layer (first conductive semiconductor layer) 2220 is formed.

[0164] Furthermore, the storage capacitor CS11, which is a storage capacitor element, shares the n+ region (first conductivity semiconductor region) 2240 on the surface of the p layer (second conductivity semiconductor layer) 2300 formed on the second substrate surface 2120 side with the first electrode EL1.

[0165] That is, in this first embodiment, the storage capacitor CS11, which is a storage capacitor element, is composed of a first electrode EL1 and a second electrode EL2. The first electrode EL1 is formed by an n+ region (first conductivity type semiconductor region) 2240 formed on the surface of the second substrate surface 2120 of the substrate 2100. The second electrode EL2 is formed on the second substrate surface 2120 in such a way that it is opposite to the first electrode EL1 at a predetermined interval in a direction orthogonal to the substrate surface.

[0166] In this first embodiment, a planarization layer 2250 is formed on the surface of the n-layer (first conductive semiconductor layer) 2210 and the p-layer (second conductive semiconductor layer) 2300 of the photoelectric conversion unit 2200 on the first substrate surface 2110 side.

[0167] In addition, a color filter section CF is formed on the light incident side of the planarization layer 2250, and a microlens MCL is formed on the light incident side of the color filter section in a manner corresponding to the photoelectric conversion section 2200, which is a photodiode PD11, and the p layer (second conductive semiconductor layer) 2300.

[0168] In this first embodiment, the transmission transistor TG11-Tr, the floating diffusion layer FD11, and the storage transistor SG11-Tr are formed on the p layer (first conductivity type semiconductor layer) 2320 in the right region of the second substrate surface 2120 of the substrate 2100.

[0169] The floating diffusion layer FD11 is formed on the surface of the second substrate surface 2120 of the substrate 2100 as an n+ region (first conductive semiconductor region) 2330 with a higher impurity concentration than the n layer (first conductive semiconductor layer) 2210, 2220 of the photoelectric conversion section 2200.

[0170] The capacitance connection node ND11 of the storage transistor SG11-Tr and the storage capacitor CS11 is formed on the surface of the second substrate surface 2120 of the substrate 2100 as an n+ region (first conductive semiconductor region) 2340 with a higher impurity concentration than the n layer (first conductive semiconductor layer) 2210, 2220 of the photoelectric conversion section 2200.

[0171] The n+ region 2340 of node ND11 is connected to the second electrode EL2 of storage capacitor CS1 via wiring layer WR1.

[0172] The transmission transistor TG11-Tr is formed by a gate electrode 2510 disposed on a second substrate surface 2120 of a substrate 2100 between a p+ region (second conductivity semiconductor region) 2230 and an n+ region (first conductivity semiconductor region) 2330 which is a floating diffusion layer FD11.

[0173] The storage transistor SG11-Tr is formed by a gate electrode 2520 disposed on a second substrate surface 2120 of a substrate 2100 between an n+ region (first conductive semiconductor region) 2330, which serves as a floating diffusion layer FD11, and an n+ region (first conductive semiconductor region) 2340, which serves as a capacitor connection node ND11.

[0174] Furthermore, in this first embodiment, an embedded overflow path 2600 is formed, which is connected to the upper side (p+ layer 2230 side) of the n layer 2220 of the photoelectric conversion unit 2200, and can transmit the overflow charge of the photoelectric conversion unit 2200 to the floating diffusion layer FD11 and then to the capacitor connection node ND11 with the storage capacitor CS11.

[0175] The embedded overflow path 2600 is formed in the following manner: the lower layer formed by the channel under the gate electrode 2510 of the transmission transistor TG11-Tr, the lower layer of the n+ region (first conductive semiconductor region) 2330 as the floating diffusion layer FD11, the lower layer of the channel formed region under the gate electrode 2520 of the storage transistor SG11-Tr, and the lower layer portion of the n+ region (first conductive semiconductor region) 2340 as the capacitor connection node ND11 are connected.

[0176] The embedded overflow path 2600 is formed by an n-layer with low impurity concentration of the n-layer 2220 of the photoelectric conversion unit 2200.

[0177] As described above, in the readout pixel 2000 of this first embodiment, an embedded overflow path 2600 is formed, which is connected to the upper side (p+ layer 2230 side) of the n-layer 2220 of the photoelectric conversion unit 2200, and can transfer the overflow charge of the photoelectric conversion unit 2200 to the floating diffusion layer FD11, and further to the capacitor connection node ND11 with the storage capacitor CS11. Therefore, during exposure, by keeping the transmission transistor TG11-Tr always off (non-conducting state), dark current generated at the silicon interface under the transmission transistor TG11-Tr can be suppressed, while charge overflow is allowed.

[0178] Furthermore, in the readout pixel 2000 of this first embodiment, the storage capacitor CS11, which is a storage capacitor element, is configured to include a first electrode EL1 and a second electrode EL2. The first electrode EL1 is formed on the second substrate surface 2120 side of the second substrate surface 2120, such that it has a portion that spatially overlaps with the photoelectric conversion unit 2200 in a direction orthogonal to the substrate surface (Z direction of the orthogonal coordinate system in the figure). The second electrode EL2 is formed on the second substrate surface 2120 opposite to the first electrode EL1 in a direction orthogonal to the substrate surface.

[0179] Therefore, even if the capacitance of the storage capacitor CS11 is set to be large, it can prevent the aperture of the photodiode PD11 from becoming smaller and the sensitivity from decreasing. Moreover, even if the light-receiving area of ​​the photodiode PD11 is set to be large, the area occupied by the storage capacitor CS11 will be smaller, thus preventing the dynamic range from decreasing.

[0180] That is, according to this first embodiment, both high dynamic range and high sensitivity can be achieved simultaneously.

[0181] As described above, in this first embodiment, under high illumination conditions, the PFM mode is specified in the exposure period after the reset of the photodiode PD11, which serves as a photoelectric conversion element, and the floating diffusion layer FD11, and the double sampling readout mode is specified after the PFM mode.

[0182] If a dual-sampling readout mode is specified after the PFM mode, the readout unit 70 keeps the storage transistor SG11-Tr in a non-conducting state, separates the storage capacitor CS11 from the floating diffusion layer FD11, separates the charge of the floating diffusion layer FD11 from the charge of the storage capacitor CS11, and converts the conversion gain to the first conversion gain HCG determined by the first capacitor.

[0183] Then, during the first reset readout period after the reset process, the readout unit 70 reads out the first readout reset signal HCGRST(ADC) converted by the first conversion gain determined by the first capacitance of the floating diffusion layer FD11 from the source follower transistor SF11-Tr, which is the output buffer unit, and performs a first conversion gain reset readout process HCGRRD that performs a specified process on the first readout reset signal HCGRST(ADC).

[0184] Then, during the first readout period following the first transmission period after the first reset readout period, the readout unit 70 reads out the first readout signal HCGSIG(ADC) converted by the first conversion gain determined by the first capacitance of the floating diffusion layer FD11 from the source follower transistor SF11-Tr, which serves as the output buffer, and performs the first conversion gain readout process HCGSRD that performs the prescribed processing on the first readout signal HCGSIG(ADC).

[0185] Then, the readout unit 70 maintains the reset level and the signal level, or performs CDS calculation based on the difference between the reset level and the signal level.

[0186] Next, after the first conversion gain readout process HCGSRD, the readout unit 70 switches the storage transistor SG11-Tr to the on state, connects the storage capacitor CS11 to the floating diffusion layer FD11, so that the charge of the floating diffusion layer FD11 and the charge of the storage capacitor are shared, and converts the conversion gain to the second conversion gain LCG determined by the second capacitor.

[0187] Then, during the second readout period following the second transmission period after the first readout period, the readout unit 70 reads out the second readout signal LCGSIG(ADC) converted by the second conversion gain determined by the second capacitance of the floating diffusion layer FD11 from the source follower transistor SF11-Tr, which serves as the output buffer, and performs the second conversion gain readout process LCGSRD, which performs the prescribed processing on the second readout signal LCGSIG(ADC).

[0188] Then, after resetting the floating diffusion layer FD11 by the reset transistor RST11-Tr, the readout unit 70 reads the second readout reset signal LCGRST(ADC) converted by the second conversion gain LCG determined by the second capacitance of the floating diffusion layer FD11 from the source follower transistor SF11-Tr, which serves as the output buffer, and performs the second conversion gain reset readout process LCGRRD, which performs the prescribed processing on the second readout reset signal LCGRST(ADC).

[0189] Then, the readout unit 70 maintains the reset level and the signal level, or performs DDS operation based on the difference between the reset level and the signal level.

[0190] When the subject is under high illumination, the source follower's reset level is obtained by resetting the floating diffusion layer FD11 after acquiring the source follower signal level. Therefore, it becomes an incomplete differential signal (also known as a DDS (Double Data Sampling) signal or DRS (Delta Reset Sampling) signal) that is independent of reset noise. This kind of reset noise is obvious in a typical CMOS image sensor, but in the readout method of this first embodiment, since the DDS signal is, for example, a signal read out from the high illumination (high brightness) side during the source follower readout operation, it is not used under low illumination. It is buried in the impulse noise of the signal and is difficult to visually identify and is not obvious.

[0191] In addition, the readout unit 70 is capable of performing the first conversion gain reset readout process HCGRRD during exposure of PEXP.

[0192] Furthermore, under extremely low illumination conditions, as a normal readout operation, the readout unit 70 performs, for example, the second conversion gain reset readout process LCG RRD and the second conversion gain readout process LCGSRD.

[0193] Under moderate illumination conditions, the readout unit 70 performs the first conversion gain reset readout process HCGRRD, the first conversion gain readout process HCGSRD, the second conversion gain readout process LCGSRD, and the second conversion gain reset readout process LCGRRD.

[0194] Thus, in this first embodiment, the configuration having a storage transistor SG 11-Tr and a storage capacitor CS11 can change the capacitance of the floating diffusion layer FD1 1 to a first capacitor or a second capacitor, and convert the conversion gain to a first conversion gain determined by the first capacitor (e.g., high conversion gain: HCG) or a second conversion gain determined by the second capacitor (e.g., low conversion gain: LCG).

[0195] Therefore, FWC (Full Well Capacity) decreases at high conversion gain (HCG) and increases at low conversion gain (LCG).

[0196] Here, an example of the readout sequence of the pixel circuit in the solid-state imaging device according to the first embodiment will be described.

[0197] Figure 8 (A) to (H) are timing diagrams illustrating an example of the readout sequence of the pixel circuit in high illumination conditions and the double sampling readout mode of the solid-state imaging device according to the first embodiment of the present invention.

[0198] Figure 9 (A) to (N) are diagrams showing the sequence of operations and potential shifts of the pixel circuit in high-illuminance conditions and the double-sampling readout mode of the solid-state imaging device according to the first embodiment of the present invention.

[0199] Figure 10 (A) to (H) are timing diagrams illustrating an example of the readout sequence of the pixel circuit in PFM mode and dual-sample readout mode under low-light conditions for the solid-state imaging device according to the first embodiment of the present invention.

[0200] Figure 11 (A) to (N) are diagrams showing the sequence of operations and potential shifts of the pixel circuit in low-light conditions of the PFM mode and the dual-sampling readout mode of the solid-state imaging device according to the first embodiment of the present invention.

[0201] Figure 8 (A) and Figure 10 (A) shows the reset count signal RCNT, which is synchronized with the mode selection signal SMS to indicate the PFM mode and the double-sample readout mode. Figure 8 (B) and Figure 10 (B) shows the control signal RST of the reset transistor RST11-Tr. Figure 8 (C) and Figure 10 (C) shows the control signal SG of the storage transistor SG11-Tr. Figure 8 (D) and Figure 10 (D) shows the control signal TG of the transmission transistor TG11-Tr. Figure 8 (E) and Figure 10 (E) shows the potential of the floating diffusion layer FD11. Figure 8 (F) and Figure 10 (F) shows the output voltage SFout of the source follower transistor SF11-Tr and the reference signal Vref(1, 2) of comparator 220. Figure 8 (G) and Figure 8 (G) shows the digitized output voltage Vout of comparator 220. Figure 8 (H) and Figure 10 (H) shows the clock signal CLK used in the double-sample readout mode.

[0202] (Actions under high illumination conditions)

[0203] Under high illumination conditions, before the PFM mode starts, the control signal RST is set to high level, and the reset transistor RST11-Tr is kept in the on state. Then, the control signal TG is set to high level, and the transmission transistor TG11-Tr is kept in the on state. With the floating diffusion layer FD11 and the photodiode PD11 connected, the control signal SG switches from low level to high level, and the storage transistor SG11-Tr switches from non-conducting state to conducting state.

[0204] Therefore, photodiode PD11 and floating diffusion layer FD11 are reset to a fixed potential VAAPIX. That is, a global reset is performed. Figure 9 (A)).

[0205] Subsequently, the control signal TG switches from high level to low level, and the transmission transistor TG11-Tr switches from the on state to the off state.

[0206] The timing of the transmission transistor TG11-Tr switching from the on state to the off state is the start exposure time PEXP. Figure 9 (B)

[0207] During the exposure period, after PEXP begins, the control signal RST switches from high level to low level, and the reset transistor RST11-Tr switches from the on state to the off state. On the other hand, the PFM mode is activated by the reset count signal RCNT, which is synchronized with the mode selection signal SMS.

[0208] In PFM mode operation under high illumination conditions, if the voltage signal corresponding to the holding charge of the floating diffusion layer FD11 reaches the reference signal Vref11, the reset transistor RST12-Tr is held in the on state by the feedback reset action of the comparison result signal Vout of comparator 220 for a specified period, and the floating diffusion layer FD11 is self-reset. Figure 9 (C), (D), (E)). Then, based on the comparison result signal Vout of comparator 220, the counter circuit 230 is selected to count the number of resets (frequency) of the floating diffusion layer FD11.

[0209] In PFM mode operation under high illumination conditions, during the exposure period PEXP, the following actions are repeatedly performed: charge overflow from photodiode PD11 to floating diffusion layer FD11; feedback reset of comparator comparison result signal Vout; self-reset of floating diffusion layer FD11; and counting of the number of resets (frequency) of floating diffusion layer FD11 by selection counter circuit 230. Figure 9 (C), (D), (E)).

[0210] Next, in order to switch from PFM mode to double sampling (LOFIC) readout mode, the reset count signal RCNT, which is synchronized with the mode selection signal SMS, switches from high level to low level.

[0211] At the same time, the control signal SG switches from high level to low level, the storage transistor SG11-Tr is kept in a non-conducting state, and the storage capacitor CS11 is separated from the floating diffusion layer FD11.

[0212] Thus, the charge of the floating diffusion layer FD11 is separated from the charge of the storage capacitor CS11, and the gain of the floating diffusion layer FD11 is converted into a first conversion gain HCG determined by the first capacitor.

[0213] Then, during the first reset readout period after the reset process, the first readout reset signal HCGRST(ADC) converted by the first conversion gain HCG determined by the first capacitance of the floating diffusion layer FD11 is read from the source follower transistor SF11-Tr. Figure 9 The first conversion gain reset readout process HCGRRD is performed on the first readout reset signal HCGRST (ADC) and the first conversion gain reset readout process HCGRRD is performed on the first readout reset signal HCGRST (ADC).

[0214] Next, during the first transmission period following the first reset readout period, the control signal TG is switched high, the transmission transistor TG11-Tr is kept on, and the stored charge of the photodiode PD11 is transferred to the floating diffusion layer FD11. After the first transmission period, the control signal TG is switched low, and the transmission transistor TG11-Tr is switched off.

[0215] Next, during the first readout period following the first transmission period, the first readout signal HCGSIG(ADC) converted by the first conversion gain determined by the first capacitance of the floating diffusion layer FD11 is read out from the source follower transistor SF11-Tr, and the first conversion gain readout process HCGSRD is performed on the first readout signal HCGSIG(ADC) to perform the prescribed processing.

[0216] Then, maintain the reset level HCGRSTADC and the signal level HCGSIGADC, or perform CDS calculation based on the difference between the reset level and the signal level.

[0217] Next, after the first conversion gain readout process HCGSRD, the control signal SG switches from low level to high level, switching the storage transistor SG11-Tr to the on state, and the storage capacitor CS11 is connected to the floating diffusion layer FD11.

[0218] As a result, the charge of the floating diffusion layer FD11 is shared with the charge of the storage capacitor, and the gain of the floating diffusion layer FD11 is switched to the second conversion gain LCG determined by the second capacitor.

[0219] Next, during the second transmission period following the second readout period, the control signal TG is switched high, the transmission transistor TG11-Tr remains on, and the stored charge of photodiode PD11 is transferred to the floating diffusion layer FD11. After the second transmission period, the control signal TG is switched low, and the transmission transistor TG11-Tr is switched off.

[0220] Then, during the second readout period following the second transmission period after the first readout period, the second readout signal LCGSIG(ADC) converted by the second conversion gain LCG determined by the second capacitance of the floating diffusion layer FD11 is read out from the source follower transistor SF11-Tr. Figure 9 The second readout signal (LCGSIG(ADC)) is processed by a second conversion gain readout process (LCGSRD) that performs the specified processing on the second readout signal (LCGSIG(ADC)).

[0221] Next, during the second reset readout period following the second transmission period, the second readout reset signal LCGRST(ADC) converted by the second conversion gain LCG determined by the second capacitance of the floating diffusion layer FD11 is read out from the source follower transistor SF11-Tr, and the second conversion gain reset readout process LCGRRD is performed on the second readout reset signal LCGRST(ADC) with specified processing.

[0222] Then, maintain the reset level LCGRSTADC and the signal level LCGSIGADC, or perform DDS operation based on the difference between the reset level LCGRSTADC and the signal level LCGSIGADC.

[0223] (Actions under low light conditions)

[0224] Under low illumination conditions, in PFM mode, the reference signal Vref11 corresponding to the holding charge of the floating diffuser layer FD11 will not be reached.

[0225] Therefore, during the PFM mode operation under low illumination conditions, the following actions will not be repeated during the exposure period PEXP: the overflow of charge from photodiode PD11 to floating diffusion layer FD11, the self-reset of floating diffusion layer FD11 by the feedback reset action of the comparator's comparison result signal Vout, and the counting action of the number of resets (frequency) of floating diffusion layer FD11 of selection counter circuit 230.

[0226] Furthermore, the operation in the low-light condition double sampling (LOFIC) readout mode is the same as the operation in the high-light condition described above.

[0227] Therefore, its detailed description is omitted here.

[0228] As described above, according to this first embodiment, the pixel circuit 200 includes: a readout pixel 210, which performs photoelectric conversion using a photodiode PD11 as a photoelectric conversion element, and is capable of reading out a signal corresponding to the illuminance condition of the incident light; a comparator 220, which compares the voltage signal SFout read from the readout pixel 210 with a reference signal Vref, and outputs a comparison result signal Vout corresponding to the comparison result; a selection counter circuit 230, which receives the comparison result signal Vout from the comparator 220, selects the counting clock of the counter, and performs a counting operation synchronized with the selected clock; and a memory circuit 240, which stores the digitized data of the selection counter circuit 230 corresponding to the comparison result signal Vout of the comparator 220.

[0229] The pixel circuit 200 has an overflow path 2600 that allows the charge overflowing from the photodiode PD11 to overflow into the floating diffusion layer FD11, and then to overflow into the connection node with the storage capacitor CS11.

[0230] Furthermore, the readout pixel 210, comparator 220, and select counter circuit 230 operate in PFM (pulse frequency modulation) mode under high brightness conditions and in dual sampling readout (e.g., LOFIC) mode using stored charge and overflow charge of photoelectric conversion elements under low brightness conditions.

[0231] Specifically, in the PFM mode operation under high illumination conditions, if the voltage signal corresponding to the holding charge of the floating diffusion layer FD11 reaches the saturation voltage of the photodiode PD11, which is a photoelectric conversion element, the floating diffusion layer FD11 is self-reset by the feedback reset action FRST11 of the comparison result signal Vout of the comparator 220. According to the comparison result signal Vout of the comparator 220, the selection counter circuit 230 counts the number of resets (frequency) of the floating diffusion layer FD11.

[0232] Under low illumination conditions, a dual-sampling readout mode (LOIC mode) operation was performed using dual gain related to the stored charge and overflow charge of the photodiode PD11, which is a photoelectric conversion element.

[0233] Therefore, according to this first embodiment, since at least an overflow path is embedded in the formation region from the photodiode PD11 to the floating diffusion layer FD11, during exposure, the dark current generated at the silicon interface under the transmission transistor TG11-Tr can be suppressed and the charge can overflow by controlling the transmission transistor TG11-Tr to a non-conducting state (off).

[0234] That is, according to this first embodiment, it is possible to read out small signals in a saturated state while maintaining sensitivity and saturation charge number, and it is possible to achieve miniaturization of pixel size.

[0235] Furthermore, according to this first embodiment, the dynamic range can be expanded with a small pixel size through a predetermined readout mode.

[0236] According to this first embodiment, high dynamic range and high frame rate can be substantially achieved.

[0237] Furthermore, according to this first embodiment, such as Figure 12 As shown, it can read out ultra-high dynamic range signals with a linear response from PFM, and can read out high-sensitivity / low-noise signals with HCG. Furthermore, it can prevent inter-pixel connection point signal deviation caused by saturation bias.

[0238] Furthermore, according to this first embodiment, the actual generated charge can be counted by counting the number of times the floating diffusion layer FD11 is reset, thus preventing false detection even when unstable light such as pulsed light is incident during exposure.

[0239] (Second Implementation)

[0240] Figure 13 This is a circuit diagram illustrating an example of the configuration of a readout pixel in the pixel circuit of the second embodiment of the present invention.

[0241] Figure 14 This is a simplified cross-sectional view showing an example of the configuration of a charge storage and transport system having a shutter gate transistor, which is a major part of the pixel circuit of the second embodiment of the present invention.

[0242] Figure 15 (A) to (H) are timing diagrams illustrating an example of the readout sequence of the pixel circuit in PFM mode and dual-sample readout mode under high illumination conditions for the solid-state imaging device according to the second embodiment of the present invention.

[0243] Figure 16 (A) to (I) are timing diagrams illustrating an example of the readout sequence of the pixel circuit in PFM mode and dual-sample readout mode under low-light conditions for the solid-state imaging device according to the second embodiment of the present invention.

[0244] The differences between the pixel circuit 200A of the solid-state imaging device 10A in this second embodiment and the pixel circuit 200 of the solid-state imaging device 10 in the first embodiment are as follows.

[0245] In the pixel circuit 200A of the solid-state imaging device 10A of this second embodiment, an anti-blooming transistor AB11-Tr, which serves as a gate element, is provided between the charge storage region of the photodiode PD11 and the fixed potential (e.g., power supply potential) VAAPIX. The anti-blooming transistor is capable of discharging the charge of the photodiode PD11 to the fixed potential VAAPIX outside the floating diffusion layer FD11 region.

[0246] like Figure 14 (and Figure 7 As shown in the figure, in the solid-state imaging device 10A of this second embodiment, the overflow path 2600 is embedded in the overflow barrier of the transmission transistor TG11-Tr, so it is lower than the overflow barrier of the anti-high light overflow transistor AB11-Tr.

[0247] As a result, the charge of photodiode PD11 overflows only in the direction of the floating diffusion layer FD11.

[0248] (The composition of the left separation layer 2310 in the X direction (column direction))

[0249] exist Figure 14 An n+ layer 2340, which serves as a drain electrode to resist high-light overflow AB11-Tr, is formed on the second substrate surface 2120 side of the p-type separation layer 2310 on the left side of the X direction (column direction).

[0250] Furthermore, above the second substrate surface 2120, a gate electrode 2540 for an anti-high light overflow transistor AB11-Tr is formed across a gate insulating film.

[0251] An overflow path 2600 is formed under the transmission transistor TG11-Tr, from the photodiode PD11 to the floating diffusion layer FD11, and then to the connection node 2340 with the storage capacitor CS11.

[0252] Alternatively, the potential of the overflow path 2600 can also be controlled by the gate, for example.

[0253] In this structure, when the intensity (amount) of the incident light is very high, the charge exceeding the saturation charge of the PD overflows as overflow charge to the floating diffusion layer FD11 through the overflow path 2600 under the transfer transistor TG11-Tr.

[0254] Furthermore, in the solid-state imaging device 10A of this second embodiment, such as Figure 15 (E) and Figure 16 As shown in (E), the stored charge of photodiode PD11 is reset by keeping the anti-high light overflow transistor AB11-Tr in the on state for a specified period.

[0255] Furthermore, during the exposure period, PEXP begins from the moment the control signal AB of the anti-high-brightness overflow transistor AB11-Tr switches from a high level to a low level.

[0256] The other components are the same as those in the first embodiment described above.

[0257] According to this second embodiment, not only can the same effects as those of the first embodiment described above be obtained, but the following effects can also be obtained.

[0258] That is, according to this second embodiment, it is possible to prevent signals (overflowing charges) exceeding the stored charge of the photodiode PD from flowing into adjacent pixels, causing charge mixing (becoming false signals).

[0259] (Third Implementation)

[0260] Figure 17 This is a circuit diagram illustrating an example of the pixel circuit configuration of the solid-state imaging device 10B according to the third embodiment of the present invention.

[0261] The difference between the pixel circuit 200B of the solid-state imaging device 10B in this third embodiment and the pixel circuit 200A of the solid-state imaging device 10A in the second embodiment lies in the configuration of the comparator 220B.

[0262] In the pixel circuit 200B of the solid-state imaging device 10B of this third embodiment, the comparator 220B provides a voltage signal VSL output from the output node of the source side of the source follower transistor SF11-Tr of the readout pixel 210B to the inverting input terminal (-) which is the first input terminal, and provides a reference signal (reference voltage) Vref (11, 12) to the non-inverting input terminal (+) which is the second input terminal. The voltage signal VSL and the reference signal Vref are compared, and the digitized comparison result signal SCMP is output as an AD conversion processing (comparison processing).

[0263] The comparator 220B is configured such that a coupling capacitor CC1 is connected to the inverting input terminal (-) which is the first input terminal. By coupling the output node of the source follower transistor SF11-Tr of the output buffer of the readout pixel 210B on the first substrate 2110 side to the input AC of the comparator 220B on the second substrate 2120 side, it can achieve low noise and high SNR in low illumination.

[0264] Furthermore, comparator 220B is configured such that an automatic zeroing switch SW-AZ, which serves as a reset switch, is connected between the output terminal and the inverting input terminal (-), which serves as the first input terminal, thereby removing the offset of comparator 220B.

[0265] For example, in comparator 220B, the analog signal (potential VSL) read from the source follower transistor SF11-Tr, which is the output buffer of the readout pixel 210B, is compared with the reference signal Vref12 in comparator 220B, for example, with the ramp signal RAMP, which is a slope waveform with a linear change of a certain slope.

[0266] At this time, for example, a counter (not shown) configured in each column, similar to comparator 220B, operates to convert the voltage signal VSL into a digital signal by changing the ramp signal RAMP with a ramp waveform and the counter value in a one-to-one correspondence.

[0267] Basically, in the AD conversion section, the change of the reference signal Vref (e.g., the ramp signal RAMP) is a change in voltage that is converted into a change in time, and then converted into a digital value by counting the time within a certain period (clock).

[0268] Then, when the analog signal VSL and the ramp signal RAMP (reference signal Vref) intersect, the output of comparator 220B is inverted, stopping the input clock of the counter, or the stop input clock is input to the counter. At this time, the value (data) of the counter is stored in the memory section 230, thereby completing the AD conversion.

[0269] As described above, according to this third embodiment, the offset of comparator 220B can be removed, and low noise can be achieved, enabling high SNR in low illumination.

[0270] (Fourth Implementation)

[0271] Figure 18 This is a circuit diagram illustrating an example of the pixel circuit configuration of the solid-state imaging device 10C according to the fourth embodiment of the present invention.

[0272] The difference between the pixel circuit 200C of the solid-state imaging device 10C in this fourth embodiment and the pixel circuit 200 of the solid-state imaging device 10 in the first embodiment is that a specific configuration example of the selection counter circuit 230C is shown.

[0273] In the pixel circuit 200C of the solid-state imaging device 10C of this fourth embodiment, the selection counter circuit 230C has an up / down (U / D) counter 233 and a selector 234 that selects the clock terminal of the up / down counter 231 based on the comparison result signal output by the comparator 220 as the main components.

[0274] The first input terminal A of selector 234 is connected to the reference potential VSS, and the second input terminal B is connected to the supply line of the clock signal SCLK. The clock signal SCLK is set to a fixed potential in PFM mode and to a clock pulse of a specified frequency in dual sampling readout mode. The output terminal C is connected to the clock terminal CK of the up and down counter 233.

[0275] If the output of comparator 220 is flipped (reversed) in PFM mode, selector 234 will switch the connection to output terminal C from the first input terminal A to the second input terminal B.

[0276] If the output of comparator 220 flips in double-sample readout mode, selector 234 will switch the connection to output terminal C from the second input terminal B to the first input terminal A.

[0277] As shown in this fourth embodiment, when using up and down counters, there is no need for memory for the reset signals HCGRST and LCGRST.

[0278] That is, as a memory circuit 240, it is sufficient to have a total of three memories: a memory 241 for PFM, a memory 242 for HCG readout signal HCGSIG, and a memory 243 for LCG readout signal LCGSIG.

[0279] Therefore, according to this fourth embodiment, not only can the same effects as the first to third embodiments described above be obtained, but the memory can also be miniaturized.

[0280] (Fifth Implementation)

[0281] Figure 19 This is a circuit diagram illustrating an example of the pixel circuit configuration of the solid-state imaging device 10D according to the fifth embodiment of the present invention.

[0282] The difference between the pixel circuit 200D of the solid-state camera device 10D in this fifth embodiment and the pixel circuit 200 of the solid-state camera device 10 in the first embodiment lies in the configuration of the selection counter circuit 230D.

[0283] In the pixel circuit 200D of the solid-state imaging device 10D of this fifth embodiment, the selection counter circuit 230D has a counter 235 and a latch 236 as main constituent elements.

[0284] When the selector counter circuit 230D is in PFM mode, the counter 235 counts the first comparison result signal Vout11 of the comparator 220.

[0285] In dual-sampling readout mode, the selector counter circuit 223D latches the second comparison result signal Vout12 synchronously with a clock of a specified frequency.

[0286] According to this fifth embodiment, the same effects as those of the first to third embodiments described above can be obtained.

[0287] (Examples of applications of solid-state imaging devices)

[0288] Figure 20 This is a diagram illustrating an example of an application device for a solid-state imaging apparatus according to an embodiment of the present invention.

[0289] Figure 21 It is a schematic representation Figure 20 The timing diagram of the operating principle of the application device.

[0290] Figure 20 The application device 300 is configured to include an image sensor 310, a light emitter 320, and a control unit 333 of the solid-state imaging device 10 (10A-10D) of the first to fifth embodiments described above.

[0291] The application device 300 is configured to: utilize the pixel circuit included in the image sensor 310 to repeatedly perform the following actions during the exposure period PEXP in PFM mode: the overflow action of charge from photodiode PD11 to floating diffusion layer FD11, the feedback reset action of the comparator's comparison result signal Vout to self-reset floating diffusion layer FD11, and the counting action of the selection counter circuit 230 to count the number of resets (frequency) of floating diffusion layer FD11, to detect whether there is an object (event) OBJ within a specified range.

[0292] As a specific example, under ultra-high illumination conditions, a detection light DL is projected from the emitter 310 onto a designated area RGN.

[0293] If there is no object OBJ in the specified area RGN under this state, the number of times (frequency) of resetting the floating diffusion layer FD11 is repeatedly counted at a specified period.

[0294] If the object OBJ enters the designated area RGN, the detection light DL is reflected by the object OBJ and received by the pixel unit 20, which includes the pixel circuit 200. As a result, the intensity of the received light changes compared to the case without the object OBJ, and the time it takes for the potential of the floating diffusion layer FD11 to decay to the reference signal Vout11 becomes longer.

[0295] That is, if object (event) OBJ is detected, the pulse frequency (number of times) corresponding to the output of comparator 220 changes. Therefore, the presence or absence of this change determines whether an event has been detected in the control unit 330.

[0296] (Examples of applications in electronic devices)

[0297] Furthermore, the solid-state imaging devices 10, 10A, 10B, 10C, and 10D described above can be used as imaging devices in digital cameras or camcorders, portable terminals, or electronic devices such as surveillance cameras and medical endoscope cameras.

[0298] Figure 22 This is a diagram illustrating an example of the configuration of an electronic device equipped with a camera system using a solid-state imaging device according to an embodiment of the present invention.

[0299] like Figure 22 As shown, the electronic device 400 has a CMOS image sensor 410 for solid-state imaging devices 10, 10A, 10B, 10C, and 10D to which this embodiment can be applied.

[0300] In addition, the electronic device 400 has an optical system (lens, etc.) 420 that guides incident light to the pixel area of ​​the CMOS image sensor 410 (to image the subject).

[0301] Electronic device 400 has a signal processing circuit (PRC) 430 for processing the output signal of CMOS image sensor 410.

[0302] The signal processing circuit 430 performs prescribed signal processing on the output signal of the CMOS image sensor 410.

[0303] The image signal processed by the signal processing circuit 430 can take various forms. For example, it can be displayed as an animation on a monitor composed of an LCD screen, or it can be output to a printer, or it can be directly recorded on a recording medium such as a memory card.

[0304] As described above, the CMOS image sensor 410 can provide a high-performance, compact, and low-cost camera system by incorporating the aforementioned solid-state imaging devices 10, 10A, 10B, 10C, and 10D.

[0305] Furthermore, it enables the use of electronic devices such as surveillance cameras and medical endoscope cameras in applications where there are limitations in camera setup requirements, such as installation size, number of connectable cables, cable length, and installation height.

[0306] Explanation of reference numerals in the attached figures

[0307] 10, 10A, 10B, 10C, 10D: Solid-state imaging devices

[0308] 20: Pixel section

[0309] 200: Pixel circuit

[0310] PD11: Photodiode

[0311] FD11: Floating diffusion layer

[0312] TG11-Tr: Transfer Transistor

[0313] RST11-Tr, RST12-Tr: Reset transistors

[0314] SF11-Tr: Source Follower Transistor

[0315] SG11-Tr: Storage transistor

[0316] CS11: Storage Capacitor

[0317] AB11-Tr: Anti-high-light-escape transistor

[0318] 220, 220B, 220D: Comparators

[0319] 230, 230C, 230D: Selector Counter Circuit

[0320] 231: Selector

[0321] 232: Counter

[0322] 233: Up / Down Counter

[0323] 234: Selector

[0324] 235: Counter

[0325] 236: Latch

[0326] 300: Application device (event detection device)

[0327] 310: Image Sensor

[0328] 320: Light emitter

[0329] 330: Control Department

[0330] 400: Electronic Equipment

[0331] 410: CMOS image sensor

[0332] 420: Optical System

[0333] 430: Signal Processing Circuit (PRC)

Claims

1. A solid-state imaging device, characterized in that, have: The readout pixel performs photoelectric conversion and can read out a signal corresponding to the illuminance conditions of the incident light; A comparator compares a voltage signal read from the readout pixel with a reference signal and outputs a comparison result signal corresponding to the comparison result; and A selector-counter circuit includes a selector circuit and a counter circuit. The selector circuit can select either an external clock or a comparator output, and the counter circuit counts the output from the selector circuit. The readout pixels include: A photoelectric conversion element that stores a charge corresponding to the amount of incident light during exposure; A transmission element, which is held in a non-conductive state during the exposure period and held in a conductive state during the transmission period to transfer the charge stored in the photoelectric conversion element; A floating diffusion layer is provided to retain the charge transmitted by the transmission element so that the charge can be read out as a voltage signal. At least one reset element is capable of performing a reset process to discharge the stored charge of the floating diffusion layer; as well as An overflow path that allows the charge overflowing from the photoelectric conversion element to overflow towards the floating diffusion layer region. Under high illumination conditions, if the voltage signal corresponding to the stored charge of the floating diffuser layer reaches the reference signal, the readout pixel, the comparator, the selection circuit, and the counter circuit will perform a self-reset of the floating diffuser layer through the feedback reset action of the comparison result signal of the comparator. Based on the reset number and frequency of the floating diffuser layer according to the comparison result signal, the circuit will perform a pulse frequency modulation (PFM) mode operation counted by the selection counter circuit. Under low illumination conditions, the circuit will perform a dual sampling readout mode operation using the stored charge and overflow charge of the photoelectric conversion element.

2. The solid-state imaging device according to claim 1, characterized in that, The readout pixel and the selection counter circuit can selectively operate in PFM mode or double-sample readout mode according to the mode selection signal. In the PFM mode, a constant first reference signal is provided to the comparator. If the voltage signal corresponding to the holding charge of the floating diffusion layer reaches the first reference signal level, the comparator outputs a first comparison result signal to the readout pixel and the selection counter circuit. In the dual-sampling readout mode, a continuously variable ramp-shaped second reference signal is provided to the comparator. The comparator outputs the comparison result between the voltage signal corresponding to the holding charge of the floating diffusion layer and the second reference signal as a second comparison result signal to the selection counter circuit. In the PFM mode, the selection counter circuit counts the first comparison result signal of the comparator; in the dual-sample readout mode, it latches the second comparison result signal synchronously with a clock of a predetermined frequency. In the PFM mode, the readout pixel uses the first comparison result signal as a feedback reset signal to turn on the reset element and reset the floating diffusion layer.

3. The solid-state imaging device according to claim 1 or 2, characterized in that, Under high illumination conditions, the PFM mode is specified during exposure after the photoelectric conversion element and the floating diffusion layer have been reset. Following the PFM mode, the dual-sample readout mode is specified.

4. The solid-state imaging device according to any one of claims 1 to 3, characterized in that, In the PFM mode, during the exposure period, the following actions are repeatedly performed: the overflow of charge from the photoelectric conversion element to the floating diffusion layer; the feedback reset action of the comparison result signal of the comparator to the self-reset action of the floating diffusion layer; and the counting action of the selection counter circuit to the reset frequency of the floating diffusion layer.

5. The solid-state imaging device according to claim 4, characterized in that, If an event occurs, the reset pulse frequency changes.

6. The solid-state imaging device according to claim 4 or 5, characterized in that, The readout pixel also includes: Storage element, which is connected to the floating diffusion layer; and A storage capacitor element, which stores the charge of the floating diffusion layer via the storage element. The storage element is disposed between the floating diffusion layer and the reset element.

7. The solid-state imaging device according to claim 6, characterized in that, In PFM mode, during the self-reset operation, the reset element and the storage element are kept in the on state, and the floating diffusion layer and the storage capacitor element are reset.

8. The solid-state imaging device according to claim 6 or 7, characterized in that, include: As a source follower element of the output buffer, it converts the charge of the floating diffusion layer into a voltage signal corresponding to the charge amount, and outputs the converted voltage signal. By selectively connecting the floating diffusion layer and the storage capacitor element through the storage element, the capacitance of the floating diffusion layer can be changed to a first capacitor or a second capacitor, and the conversion gain can be converted to a first conversion gain determined by the first capacitor or a second conversion gain determined by the second capacitor.

9. The solid-state imaging device according to claim 8, characterized in that, have: A pixel section, which is arranged with the readout pixels; and The readout unit reads pixel signals from the readout pixels of the pixel unit. If the readout unit specifies the dual-sampling readout mode after the PFM mode, it keeps the storage element in a non-conductive state, separates the storage capacitor element from the floating diffusion layer, separates the charge of the floating diffusion layer from the charge of the storage capacitor element, and converts the gain of the floating diffusion layer to a first conversion gain determined by the first capacitor. The system is capable of performing a first conversion gain reset readout process during a first reset readout period following the reset process. This first conversion gain reset readout process reads out a first readout reset signal converted by a first conversion gain determined by the first capacitance of the floating diffusion layer from the source follower element, which serves as the output buffer, and performs prescribed processing on this first readout signal. Furthermore, the system is capable of performing a first conversion gain readout process during a first readout period following a first transmission period after the first reset readout period. This first conversion gain readout process reads out a first readout signal converted by a first conversion gain determined by the first capacitance of the floating diffusion layer from the source follower element, which serves as the output buffer, and performs prescribed processing on this first readout signal. After the first conversion gain readout process, the storage element is switched to the on state, the storage capacitor element is connected to the floating diffusion layer, so that the charge of the floating diffusion layer and the charge of the storage capacitor element are shared, and the gain of the floating diffusion layer is converted into a second conversion gain determined by the second capacitor. The second conversion gain readout process can be performed during the second readout period after the second transmission period following the first readout period. The second conversion gain readout process reads out the second readout signal converted by the second conversion gain determined by the second capacitor of the floating diffusion layer from the source follower element, which is the output buffer, and performs a prescribed processing on the second readout signal. The second conversion gain reset readout process can be performed after the floating diffusion layer is reset by the reset element. The second conversion gain reset readout process reads out the second readout reset signal converted by the second conversion gain determined by the second capacitor of the floating diffusion layer, which is the output node, from the source follower element, which is the output buffer, and performs a prescribed processing on the second readout reset signal.

10. The solid-state imaging device according to claim 9, characterized in that, The readout unit performs the first conversion gain reset readout process during the exposure period.

11. The solid-state imaging device according to claim 9 or 10, characterized in that, The readout unit performs the second conversion gain reset readout process and the second conversion gain readout process under ultra-low illumination conditions.

12. The solid-state imaging device according to claim 9 or 10, characterized in that, Under moderate illumination conditions, the readout unit performs the first conversion gain reset readout process, the first conversion gain readout process, the second conversion gain readout process, and the second conversion gain reset readout process.

13. The solid-state imaging device according to any one of claims 8 to 12, characterized in that, The source follower element is formed by a source follower transistor whose gate is connected to the floating diffusion layer and whose drain is connected to a specified potential. One input terminal of the comparator is connected to the source of the source follower transistor via a coupling capacitor, and the other input terminal is connected to the input line of the reference signal. An automatic zeroing switch is connected between one of the input terminals and the other output terminal.

14. The solid-state imaging device according to claim 2, characterized in that, The selection counter circuit includes: Counters; and A selector that selects the signal input to the counter based on a mode selection signal. When the mode selection signal specifies the PFM mode, the selector provides the comparator's comparison result signal to the counter; when the mode selection signal specifies the double-sample readout mode, it provides a clock pulse of a specified frequency to the counter. The counter counts the comparison result signal of the comparator in PFM mode, and latches the second comparison result signal synchronously with the clock pulse in dual-sample readout mode.

15. The solid-state imaging device according to any one of claims 1 to 13, characterized in that, The selection counter circuit includes: Up and down counters; and The selector selects the signal input to the clock terminal of the up and down counters based on the comparison result signal output by the comparator. The first input terminal of the selector is connected to a reference potential, the second input terminal is set to a fixed potential in the PFM mode, and is connected to a supply line of a signal set as a clock pulse of a specified frequency in the dual-sample readout mode. The output terminal is connected to the clock terminal of the up and down counter. In the PFM mode, if the output of the comparator flips, the connection with the output terminal is switched from the first input terminal to the second input terminal. In the dual-sample readout mode, if the output of the comparator flips, the connection with the output terminal is switched from the second input terminal to the first input terminal.

16. The solid-state imaging device according to claim 2, characterized in that, The selection counter circuit includes: Counters; and latch, In the PFM mode, the counter counts the first comparison result signal of the comparator. In the dual-sample readout mode, the latch latches the second comparison result signal synchronously with a clock of a specified frequency.

17. The solid-state imaging device according to any one of claims 1 to 16, characterized in that, include: A gate element that can transfer the stored charge of the photoelectric conversion element to the outside of the floating diffusion layer region.

18. A driving method for a solid-state imaging device, characterized in that, The solid-state imaging device has: The readout pixel performs photoelectric conversion and can read out a signal corresponding to the illuminance conditions of the incident light; A comparator compares a voltage signal read from the readout pixel with a reference signal and outputs a comparison result signal corresponding to the comparison result; and A selector-counter circuit includes a selector circuit and a counter circuit. The selector circuit can select either an external clock or a comparator output, and the counter circuit counts the output from the selector circuit. The readout pixels include: A photoelectric conversion element that stores a charge corresponding to the amount of incident light during exposure; A transmission element, which is held in a non-conductive state during the exposure period and held in a conductive state during the transmission period to transfer the charge stored in the photoelectric conversion element; A floating diffusion layer is provided to retain the charge transmitted by the transmission element so that the charge can be read out as a voltage signal. At least one reset element is capable of performing a reset process to discharge the stored charge of the floating diffusion layer; as well as An overflow path that allows the charge overflowing from the photoelectric conversion element to overflow towards the floating diffusion layer region. Specifically, under high illumination conditions, if the voltage signal corresponding to the holding charge of the floating diffusion layer reaches the reference signal, the floating diffusion layer is self-reset via the feedback reset action of the comparison result signal of the comparator, and the floating diffusion layer is subjected to PFM mode operation with pulse frequency modulation based on the reset frequency of the floating diffusion layer according to the comparison result signal and counted by the selection counter circuit. Under low illumination conditions, a dual-sampling readout mode operation is performed using the stored charge and overflow charge of the photoelectric conversion element.

19. An electronic device, characterized in that, have: Solid-state imaging devices; and The optical system, in the solid-state imaging device, images the subject. The solid-state imaging device has: The readout pixel performs photoelectric conversion and can read out a signal corresponding to the illuminance conditions of the incident light; A comparator compares a voltage signal read from the readout pixel with a reference signal and outputs a comparison result signal corresponding to the comparison result; and A selector-counter circuit includes a selector circuit and a counter circuit. The selector circuit can select either an external clock or a comparator output, and the counter circuit counts the output from the selector circuit. The readout pixels include: A photoelectric conversion element that stores a charge corresponding to the amount of incident light during exposure; A transmission element, which is held in a non-conductive state during the exposure period and held in a conductive state during the transmission period to transfer the charge stored in the photoelectric conversion element; A floating diffusion layer is provided to retain the charge transmitted by the transmission element so that the charge can be read out as a voltage signal. At least one reset element is capable of performing a reset process to discharge the stored charge of the floating diffusion layer; as well as An overflow path that allows the charge overflowing from the photoelectric conversion element to overflow towards the floating diffusion layer region. Under high illumination conditions, if the voltage signal corresponding to the holding charge of the floating diffuser layer reaches the reference signal, the readout pixel, the comparator, the selection circuit, and the counter circuit will self-reset the floating diffuser layer through the feedback reset action of the comparison result signal of the comparator, and perform PFM mode operation based on the reset frequency of the floating diffuser layer using the pulse frequency modulation counted by the selection counter circuit according to the comparison result signal. Under low illumination conditions, a dual-sampling readout mode operation is performed using the stored charge and overflow charge of the photoelectric conversion element.

Images