A current detection circuit of an intelligent high-side power switch

Abstract

The application relates to the technical field of basic electronic circuits, and discloses a current detection circuit of an intelligent high-side power switch, which is based on a SenseFET current detection circuit and comprises a gain amplification circuit (100) for improving the gain of an amplifier, a DC compensation circuit (200) for eliminating DC errors, and a negative voltage overcharge protection circuit (300) for realizing synchronous turn-off of a detection tube and a power tube. out The gain amplification circuit comprises a nested operational amplifier on a current mirror circuit; the DC compensation circuit comprises a cascade current mirror added between an input voltage and an output voltage V The negative voltage overcharge protection circuit comprises a switch tube arranged between a load and an operational amplifier. The application realizes accurate and safe detection of the current of the high-side power switch.

Description

Technical Field

[0001] This application relates to the field of basic electronic circuit technology, and in particular to a current detection circuit for an intelligent high-side power switch. Background Technology

[0002] Power electronics technology has made significant contributions to the efficient conversion and control of electrical energy and energy conservation. Reducing energy loss is a crucial research direction in the field of power transmission and conversion. Smart Power Integrated Circuits (SPICs) integrate control logic, protection circuits, and power devices, offering advantages such as low cost, high efficiency, and high reliability. Integrating protection circuits within the device greatly improves the reliability of SPICs. Overcurrent protection for power devices is a critical component of SPICs, and current sensing of power devices is essential.

[0003] There are several common methods for current sensing of power devices:

[0004] 1. Connecting a resistor in series in the output circuit can accurately detect the current, but it results in a large power loss in current detection due to the large output current generated.

[0005] 2. Series resistor Rds: Although this method can be integrated internally, the series resistor will cause a large detection error as the operating conditions and external environmental conditions change.

[0006] 3. Adding mutual inductance coils to the output circuit reduces power loss compared to series resistance, but the cost is very high.

[0007] 4. SenseFET (Sense Field Effect Transistor) current detection: Although this method can be fully integrated, has low power consumption, and relatively accurate current detection, the detection accuracy still needs improvement. In addition, at the moment the power transistor is turned off, under the influence of the load inductance, a potential opposite to the original direction is generated across the load, resulting in a large negative voltage at the power transistor source terminal. The substrate diode of the PMOS transistor is forward-biased, and a large current flows through it, which can easily cause the internal components of the operational amplifier to break down and burn out, posing a safety hazard. Summary of the Invention

[0008] To achieve accurate and safe detection of the internal current of power devices, this application provides a current detection circuit for an intelligent high-side power switch, based on a SenseFET current detection circuit, including interconnected components.

[0009] Gain amplifier circuit (100) used to increase amplifier gain;

[0010] DC compensation circuit (200) for eliminating DC error;

[0011] A negative voltage overcharge protection circuit (300) is used to achieve synchronous turn-off of the detection tube and the power tube, and to ensure that the source voltages of the detection tube and the power tube are matched.

[0012] Furthermore, the gain amplifier circuit (100) includes an operational amplifier nested on a current mirror circuit; the DC compensation circuit (200) includes components from the input voltage (VL) to the output voltage (V). out A cascaded current mirror is added between the load and the gain amplifier circuit (100); the negative voltage overcharge protection circuit (300) includes a switching transistor placed between the load and the gain amplifier circuit (100).

[0013] Furthermore, the gain amplifier circuit (100) includes a first current mirror circuit and a second current mirror circuit arranged opposite to each other. The first current mirror circuit is nested with a first operational amplifier (AH), and the second current mirror circuit is nested with a second operational amplifier (AL). The first operational amplifier (AH) and the second operational amplifier (AL) are arranged opposite to each other to improve the loop gain, closed-loop gain, and gain-bandwidth product.

[0014] Furthermore, the first current mirror circuit also includes a first low-voltage current mirror (M1), a second low-voltage current mirror (M2), and a first high-voltage MOSFET (M4). The gate of the first low-voltage current mirror (M1) is connected to the first input terminal of the first operational amplifier (AH); the drain of the second low-voltage current mirror (M2) is connected to the second input terminal of the first operational amplifier (AH); the gate of the first high-voltage MOSFET (M4) is connected to the output terminal of the first operational amplifier (AH); the second current mirror circuit also includes a second high-voltage MOSFET (M5), a third high-voltage MOSFET (M6), a third low-voltage current mirror (M7), a first operational amplifier (AH), a second operational amplifier (AL); the source and drain of the fourth low-voltage current mirror (M8) are connected to the first input terminal of the second operational amplifier (AL); the drain of the third low-voltage current mirror (M7) is connected to the second input terminal of the second operational amplifier (AL); the gate of the third high-voltage MOSFET (M6) is connected to the output terminal of the second operational amplifier (AL); used to improve loop gain, closed-loop gain, and gain-bandwidth product.

[0015] Furthermore, the gain of the first operational amplifier (AH) is equal to that of the second operational amplifier (AL).

[0016] Furthermore, the DC compensation circuit (200) includes a first cascaded current mirror (M11) and a second cascaded current mirror (M12), the output voltage VL is connected to the source of the first cascaded current mirror (M11), the drain of the first cascaded current mirror (M11) is connected to the source of the second cascaded current mirror (M12), and the source of the second cascaded current mirror (M12) is connected to the output voltage (V). out This is used to provide equal compensation current at the source of the second cascaded current mirror (M12) and at the source of the second low-voltage current mirror (M2).

[0017] Furthermore, the negative voltage overcharge protection circuit (300) includes a first switch (M13) and a second switch (M14) disposed between the load and the operational amplifier. The gate of the first switch (M13) is connected to the gate of the power transistor, and the source of the first switch (M13) is connected to the source of the power transistor; this is used to realize the synchronous turn-off of the detection transistor and the power transistor. The gate of the second switch (M14) is connected to the gate of the detection transistor, and the source of the second switch (M14) is connected to the source of the detection transistor. The drain of the first switch (M13) and the drain of the second switch (M14) are connected to a gain amplifier circuit (100) to ensure that the source voltages of the detection transistor and the power transistor are matched.

[0018] Furthermore, the first switch (M13) and the second switch (M14) are arranged vertically symmetrically about the connection line between the detection tube and the power tube to ensure that the source voltages of the detection tube and the power tube are consistent.

[0019] Furthermore, the gate of the first cascaded current mirror (M11) is connected to the first input terminal of the first operational amplifier (AH); the gate of the second cascaded current mirror (M12) is connected to the output terminal of the first operational amplifier (AH).

[0020] Furthermore, the negative voltage overcharge protection circuit includes the detection tube and the power tube connected in parallel, the drain of the detection tube being connected to the drain of the power tube, and the gate of the detection tube being connected to the gate of the power tube.

[0021] Beneficial effects:

[0022] This application modifies the traditional SenseFET current detection circuit by introducing a gain amplifier circuit (100) and nesting operational amplifiers to improve loop gain, closed-loop gain, and gain-bandwidth product gain, thereby improving the accuracy of current detection. By introducing a DC compensation circuit (200), equal compensation current is provided at the source of the added second cascaded current mirror (M12) and the source of the second low-voltage current mirror (M2) to eliminate DC error. By introducing a negative voltage overcharge protection circuit (300), a first switching transistor (M13) is added to the negative voltage overcharge protection circuit (300) to achieve synchronous turn-off of the detection transistor and the power transistor. By adding a second switching transistor (M14) to the negative voltage overcharge protection circuit (300), the source voltage of the detection transistor and the power transistor is matched, thereby protecting the internal transistors of the operational amplifier from breakdown at the moment of turn-off, and comprehensively improving the performance of the current detection circuit. This application achieves accurate and safe detection of the current of the high-side power switch by introducing a gain amplifier circuit (100), a DC compensation circuit (200), and a negative voltage overcharge protection circuit (300). Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is the schematic diagram of the SenseFET current sensing circuit.

[0025] Figure 2 To match the schematic diagram of the current source technology;

[0026] Figure 3 This is a schematic diagram of a matching current source technology used in high-voltage current detection.

[0027] Figure 4 This is a schematic diagram of the equivalent circuit for detecting small signals under high voltage current.

[0028] Figure 5 Flowchart for small signal analysis of high voltage current detection;

[0029] Figure 6 This is a schematic diagram of the novel high-gain, high-precision current detection circuit proposed in this application. Detailed Implementation

[0030] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.

[0031] Example

[0032] This application presents a current sensing method based on a SenseFET current sensing circuit. The idea of ​​using a SenseFET current sensing circuit to detect current originates from a current mirror. Compared to other methods, SenseFET current sensing technology has many advantages, such as full integration, low power consumption, and relatively high accuracy, making it a commonly used method in SPIC (Spatial Component Detection and Control).

[0033] Combined with appendix Figure 1 The sense FET and the main FET are connected in parallel. Typically, the width of the sense FET is much smaller than the gate width of the main FET. The smaller the ratio of the width of the sense FET to the gate width of the main FET, the lower the power consumption. However, the accuracy of current detection will also decrease. Therefore, a suitable value must be found between power consumption and accuracy. Usually, K = W / L(Sense / Main) > 1500 is chosen.

[0034] To achieve high-precision detection, a conventional high-gain operational amplifier is used, ensuring that the source-drain voltage and gate-source voltage of the sense FET are the same as those of the main FET. Both the sense FET and the main FET operate in the linear region during normal operation, and the on-resistance R of the MOSFET is... on It is inversely proportional to its width-to-length ratio W / L:

[0035]

[0036] It can be known that:

[0037] R MS / R ML =K

[0038] Furthermore, due to the MOSFET's on-state current:

[0039]

[0040] We can obtain:

[0041] I MS =I ML / K

[0042] Since I1, I2 < L ,I out Under normal circumstances, it can be considered as: I out I MS Then the output detection voltage is:

[0043] V out =I out ×R​out

[0044] The corresponding load current at this time is:

[0045]

[0046] By measuring the output voltage value V in real time out To monitor the load current of the power transistor (MainFET) in real time.

[0047] To further improve detection accuracy, combined with the attached... Figure 2 By introducing matching current source technology, current mirrors (M3, M4, M5) absorb constant current from PMOS transistors (M1, M2) of the same size and make their source potentials equal.

[0048] To further improve detection accuracy, combined with the attached... Figure 3 The matching current source technology for high voltage current detection is introduced. The low voltage current mirrors (M1, M2, M7, M8) are protected by high voltage MOSFETs (M3, M4, M5, M6), and the feedback MOSFET MR is a high voltage resistant MOSFET.

[0049] For ease of analysis and calculation, in conjunction with the appendix Figure 4 The equivalent resistances of M1 and M3 connected in series with diodes, the equivalent resistances of M2 and M4, and the equivalent resistances of current mirrors M5, M7, M6, and M8 are simplified as follows:

[0050]

[0051] Combined with appendix Figure 5 In the small-signal equivalent circuit,

[0052] node v out :

[0053]

[0054]

[0055] node v R :

[0056] r out =r 2,4 Pr 6,8

[0057]

[0058] node v L :

[0059] v L =-i in ×(R main P(r1,3 +r 5,7 )) (1)

[0060] node v s :

[0061] i sense =i2+i out (2)

[0062] v s =-i sense ×R sense (3)

[0063] v L ≈v1→i2=g m2 ×(v s -v L (4)

[0064] Substituting (1), (2), and (3) into (4) yields:

[0065]

[0066] Based on the above small-signal analysis process, the loop gain of this circuit is:

[0067]

[0068] The closed-loop gain of the entire circuit is:

[0069]

[0070] Therefore, we can conclude that:

[0071]

[0072] v R There exists a principal pole at: f0 = 1 / 2πr out C MR ,

[0073] The gain-bandwidth product is:

[0074]

[0075] Combined with appendix Figure 6 To further reduce the error of the detected current and improve the safety of current detection, Example 1 provides a current detection circuit for an intelligent high-side power switch, based on the SenseFET current detection circuit, including: a gain amplifier circuit (100), a DC compensation circuit (200), and a negative voltage overcharge protection circuit (300).

[0076] To further reduce the error of the detected current, it is necessary to increase the amplifier gain. Based on the traditional matching current source technology for high-voltage current detection, a gain amplifier circuit (100) is introduced. The gain amplifier circuit (100) includes: a power supply (VDD), a first low-voltage current mirror (M1), a second low-voltage current mirror (M2), a third low-voltage current mirror (M7), a fourth low-voltage current mirror (M8), a fifth current mirror (M9), a sixth current mirror (M10), a first high-voltage MOSFET (M4), a second high-voltage MOSFET (M5), a third high-voltage MOSFET (M6), a first operational amplifier (AH), and a second operational amplifier (AL).

[0077] The drain of the first low-voltage current mirror (M1) is connected to the drain of the second high-voltage MOSFET (M5), the drain of the first low-voltage current mirror (M1) is connected to the gate of the first low-voltage current mirror (M1), the gate of the first low-voltage current mirror (M1) is connected to the gate of the second low-voltage current mirror (M2), and the gate of the first low-voltage current mirror (M1) is connected to the first input terminal of the first operational amplifier (AH).

[0078] The drain of the second low-voltage current mirror (M2) is connected to the source of the first high-voltage MOSFET (M4), and the drain of the second low-voltage current mirror (M2) is connected to the second input terminal of the first operational amplifier (AH);

[0079] The gate of the first high-voltage MOSFET (M4) is connected to the output terminal of the first operational amplifier (AH), and the drain of the first high-voltage MOSFET (M4) is connected to the drain of the third high-voltage MOSFET (M6).

[0080] The source of the third high-voltage MOSFET (M6) is connected to the first input terminal of the second operational amplifier (AL), and the source of the third high-voltage MOSFET (M6) is connected to the drain of the fourth low-voltage current mirror (M8); the gate of the third high-voltage MOSFET (M6) is connected to the output terminal of the second operational amplifier (AL).

[0081] The source and drain of the fourth low-voltage current mirror (M8) are connected to the first input terminal of the second operational amplifier (AL); the source of the fourth low-voltage current mirror (M8) is grounded; the gate of the fourth low-voltage current mirror (M8) is connected to the gate of the sixth current mirror (M10).

[0082] The source of the third low-voltage current mirror (M7) is grounded, and the drain of the third low-voltage current mirror (M7) is connected to the second input terminal of the second operational amplifier (AL); the drain of the third low-voltage current mirror (M7) is connected to the source of the second high-voltage MOSFET (M5);

[0083] The gate of the second high-voltage MOSFET (M5) is connected to the gate of the fifth current mirror (M9);

[0084] The drain of said fifth current mirror (M9) is connected to said power supply (VDD); the drain of said fifth current mirror (M9) is connected to the gate of said fifth current mirror (M9); the source of said fifth current mirror (M9) is connected to the drain of said sixth current mirror (M10);

[0085] The drain of said sixth current mirror (M10) is connected to the gate of said sixth current mirror (M10); the source of said sixth current mirror (M10) is grounded.

[0086] Let the gains of the nested operational amplifiers be equal, AH = AL = A. Compared with the traditional structure, the output resistance r< out out is increased by A times, that is, r< out out = A(r< 2，4 o1 || r< 6，8 o2), and the corresponding loop gain, closed-loop gain and gain bandwidth product are all increased by A times.

[0087] In order to eliminate DC errors, a DC compensation circuit (200) is introduced,

[0088] Said DC compensation circuit (200) comprises a first cascaded current mirror (M11), a second cascaded current mirror (M12), a feedback MOS transistor (MR), an output resistance (R< out out), and an output voltage (V< out out);

[0089] The gate of said first cascaded current mirror (M11) is connected to the gate of said first low-voltage current mirror (M1), and the drain of said first cascaded current mirror (M11) is connected to the source of said second cascaded current mirror (M12);

[0090] The gate of said second cascaded current mirror (M12) is connected to the output end of said first operational amplifier (AH); the drain of said second cascaded current mirror (M12) is connected to said output voltage (V< out out);

[0091] The gate of said feedback MOS transistor (MR) is connected to the drain of said first high-voltage MOS transistor (M4); the gate of said feedback MOS transistor (MR) is connected to the drain of said third high-voltage MOS transistor (M6); the source of said feedback MOS transistor (MR) is connected to said output resistance (R< out out).

[0092] The bias currents I1 and I2 of the amplifier must be much smaller than the load currents IL and Iout (I1, I2 << IL, Iout). For low-power applications, when the ratio K = Rmain / Rsense is relatively high, it will result in a small Iout current output. At this time, the DC error caused by the bias current I2 relative to Iout cannot be ignored. By

[0093]

[0094] By V L To output node V out Add an additional cascaded current mirror: the first cascaded current mirror (M11) and the second cascaded current mirror (M12), and provide a compensation current I3 = I2 to eliminate DC error.

[0095] At the moment the power transistor is turned off, under the influence of the load inductance, a potential opposite to the original direction is generated across the load terminals, resulting in a large negative voltage at the power transistor source terminal. The substrate diodes of PMOS transistors M1 and M11 are forward-biased, and a large current flows through them, which can easily cause the internal transistors of the operational amplifier to burn out and break down.

[0096] To achieve synchronous shutdown of the detection tube and the power tube, a negative voltage over-protection circuit is introduced.

[0097] The negative voltage overcharge protection circuit (300) includes a dynamic bias voltage (VBB), a gate bias control signal (Vgate), a sense FET, a power FET, a first switch (M13), a second switch (M14), and a mutual inductance resistor (RL).

[0098] The gate of the SenseFET is connected to the gate bias control signal (Vgate), the drain of the SenseFET is connected to the dynamic bias voltage (VBB), and the source of the SenseFET is connected to the source of the second switch (M14).

[0099] The gate of the power transistor (MainFET) is connected to the gate bias control signal (Vgate), the gate of the power transistor (MainFET) is connected to the gate of the first switching transistor (M13), the gate of the power transistor (MainFET) is connected to the gate of the second switching transistor (M14), the drain of the power transistor (MainFET) is connected to the dynamic bias voltage (VBB), and the source of the sense transistor (SenseFET) is connected to the source of the first switching transistor (M13); the source of the sense transistor (SenseFET) is grounded through a mutual inductance resistor (RL).

[0100] The drain of the first switching transistor (M13) is connected to the source of the first low-voltage current mirror (M1);

[0101] The drain of the second switching transistor (M14) is connected to the source of the second low-voltage current mirror (M2);

[0102] By adding a first switching transistor (M13), the detection transistor and the power transistor are turned off synchronously, cutting off the connection between the load and the operational amplifier, avoiding damage to the operational amplifier caused by negative voltage overshoot, and improving the robustness of the current detection circuit. At the same time, a second switching transistor (M14) is added symmetrically to maintain operational amplifier circuit matching and ensure the consistency of the source voltage of the detection transistor and the power transistor.

[0103] Using the high-power switch current detection circuit provided in this application, when the power supply voltage is 24V, the measurable current range is between 20mA and 17A within a 3% detection error, the loop gain is 133dB, and the gain-bandwidth product is 2.6MHz.

[0104] This application, based on the SenseFET current detection circuit, improves the accuracy of current detection by introducing a gain amplifier circuit (100) and nesting an operational amplifier to enhance the loop gain, closed-loop gain, and gain-bandwidth product gain. It also eliminates DC errors by introducing a DC compensation circuit (200) to provide equal compensation current to the source of the added second cascaded current mirror (M12) and the source of the second low-voltage current mirror (M2). Furthermore, it introduces a negative voltage overcharge protection circuit (300) and adds a first switching transistor (M13) to achieve synchronous turn-off of the SenseFET and the MainFET. Finally, it adds a second switching transistor (M14) to the negative voltage overcharge protection circuit (300) to ensure source voltage matching between the SenseFET and the MainFET, thereby protecting the internal power transistor from breakdown during turn-off and comprehensively improving the performance of the current detection circuit. This application achieves accurate and safe detection of the current of high-side power switches by introducing a gain amplifier circuit (100), a DC compensation circuit (200), and a negative voltage overcharge protection circuit (300). Applying this circuit to high-gain bandwidth products enables accurate and safe current detection in power management applications.

[0105] The above descriptions are merely embodiments of this application. Commonly known structures and characteristics of the solutions are not described in detail here. Those skilled in the art are aware of all common technical knowledge in the field prior to the application date or priority date, are aware of all existing technologies in that field, and have the ability to apply conventional experimental methods prior to that date. Those skilled in the art can, based on the guidance provided in this application, improve and implement this solution in combination with their own capabilities. Some typical known structures or methods should not be obstacles for those skilled in the art to implement this application. It should be noted that those skilled in the art can make several modifications and improvements without departing from the structure of this application. These should also be considered within the scope of protection of this application, and will not affect the effectiveness of the implementation of this application or the practicality of the patent. The scope of protection claimed in this application should be determined by the content of its claims, and the specific embodiments described in the specification can be used to interpret the content of the claims.

Claims

1. A current detection circuit for an intelligent high-side power switch, based on a SenseFET current detection circuit, characterized in that, Including interconnected, Gain amplifier circuit (100) used to increase amplifier gain. DC compensation circuit (200) for eliminating DC error; A negative voltage overcharge protection circuit (300) is used to realize the synchronous turn-off of the detection tube and the power tube, and to ensure the source voltage matching of the detection tube and the power tube. The gain amplifier circuit (100) includes a first current mirror circuit and a second current mirror circuit arranged opposite to each other. The first current mirror circuit is nested with a first operational amplifier (AH), and the second current mirror circuit is nested with a second operational amplifier (AL). The first operational amplifier (AH) and the second operational amplifier (AL) are arranged opposite to each other to improve the loop gain, closed-loop gain, and gain-bandwidth product. The first current mirror circuit further includes a first low-voltage current mirror (M1), a second low-voltage current mirror (M2), and a first high-voltage MOSFET (M4). The gate of the first low-voltage current mirror (M1) is connected to the first input terminal of the first operational amplifier (AH); the drain of the second low-voltage current mirror (M2) is connected to the second input terminal of the first operational amplifier (AH); and the gate of the first high-voltage MOSFET (M4) is connected to the output terminal of the first operational amplifier (AH). The second current mirror circuit further includes a second high-voltage MOSFET (M5), a third high-voltage MOSFET (M6), a third low-voltage current mirror (M7), a fourth low-voltage current mirror (M8), a first operational amplifier (AH), and a second operational amplifier (AL). The source and drain of the fourth low-voltage current mirror (M8) are connected to the first input terminal of the second operational amplifier (AL); the drain of the third low-voltage current mirror (M7) is connected to the second input terminal of the second operational amplifier (AL); and the gate of the third high-voltage MOSFET (M6) is connected to the output terminal of the second operational amplifier (AL). This circuit is used to improve loop gain, closed-loop gain, and gain-bandwidth product.

2. The current detection circuit of an intelligent high-side power switch as described in claim 1, characterized in that: The gain amplifier circuit (100) includes an operational amplifier nested on a current mirror circuit; the DC compensation circuit (200) includes a voltage range from input voltage (VL) to output voltage (V). out A cascaded current mirror is added between the load and the gain amplifier circuit (100); the negative voltage overcharge protection circuit (300) includes a switching transistor placed between the load and the gain amplifier circuit (100).

3. The current detection circuit of an intelligent high-side power switch as described in claim 1, characterized in that: The gain of the first operational amplifier (AH) is equal to that of the second operational amplifier (AL).

4. The current detection circuit of an intelligent high-side power switch as described in claim 2, characterized in that: The DC compensation circuit (200) includes a first cascaded current mirror (M11) and a second cascaded current mirror (M12). The input voltage (VL) is connected to the source of the first cascaded current mirror (M11), the drain of the first cascaded current mirror (M11) is connected to the source of the second cascaded current mirror (M12), and the source of the second cascaded current mirror (M12) is connected to the output voltage (V). out ), used to provide equal compensation current at the source of the second cascaded current mirror (M12) and at the source of the second low-voltage current mirror (M2).

5. The current detection circuit of an intelligent high-side power switch as described in claim 1, characterized in that: The negative voltage overcharge protection circuit (300) includes a first switch (M13) and a second switch (M14) disposed between the load and the operational amplifier. The gate of the first switch (M13) is connected to the gate of the power transistor, and the source of the first switch (M13) is connected to the source of the power transistor. This is used to realize the synchronous turn-off of the detection transistor and the power transistor. The gate of the second switch (M14) is connected to the gate of the detection transistor, and the source of the second switch (M14) is connected to the source of the detection transistor. The drain of the first switch (M13) and the drain of the second switch (M14) are connected to a gain amplifier circuit (100) to ensure that the source voltages of the detection transistor and the power transistor are matched.

6. The current detection circuit of an intelligent high-side power switch as described in claim 5, characterized in that: The first switch (M13) and the second switch (M14) are arranged vertically symmetrically about the line connecting the detection tube and the power tube to ensure that the source voltage of the detection tube and the power tube are consistent.

7. The current detection circuit of an intelligent high-side power switch as described in claim 4, characterized in that: The gate of the first cascaded current mirror (M11) is connected to the first input terminal of the first operational amplifier (AH); the gate of the second cascaded current mirror (M12) is connected to the output terminal of the first operational amplifier (AH).

8. The current detection circuit of an intelligent high-side power switch as described in claim 1, characterized in that: The negative voltage overcharge protection circuit includes the detection tube and the power tube connected in parallel, the drain of the detection tube being connected to the drain of the power tube, and the gate of the detection tube being connected to the gate of the power tube.

Images