A low power adaptive zero current detection circuit for switching power supply

Abstract

The application discloses a low-power adaptive zero-current detection circuit for a switching power supply and belongs to the field of integrated circuits. The low-power adaptive zero-current detection circuit comprises a main comparator and a decision circuit. The main comparator is a low-power static comparator, and only works normally when a synchronous rectifier of the switching power supply is turned on, and sleeps when the synchronous rectifier is turned off. The decision circuit is used for realizing adaptive control of a misadjustment voltage of the main comparator, and the power consumption is proportional to a switching frequency of the switching power supply, so that the problem of comparison accuracy and transmission delay of the low-power static main comparator can be solved. The low-power adaptive zero-current detection circuit has simple structure and small area cost, can accurately turn off the synchronous rectifier when the inductor current is zero, reduces the problem of ringing of a switching node and stress of a device, and improves the overall working efficiency of the switching power supply.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits. Specifically, this invention relates to a low-power adaptive zero-current detection circuit for switching power supplies. Background Technology

[0002] Switching power supplies typically employ different control methods depending on the load current to achieve efficient operation across the entire load range: for larger load currents, the switching power supply operates in continuous conduction mode using pulse width modulation (PWM) control; for smaller load currents, the switching power supply operates in discontinuous conduction mode (DCM) using pulse frequency modulation (PFM) control.

[0003] Operating efficiency is a crucial indicator of a switching power supply's quality, and the Zero-Crossing Detector (ZCD) significantly impacts its efficiency in DCM mode. As a vital component of synchronous rectifier switching power supplies, the ZCD compares the voltage across the synchronous rectifier diode and outputs an enable signal to shut it off when the inductor current crosses zero. This prevents unnecessary power loss caused by the inductor current flowing backward through the synchronous rectifier diode under light loads.

[0004] Semiconductor device mismatch, process variations, power supply voltage, and operating temperature can introduce random input offset voltages at the input of the zero-current detection circuit. Simultaneously, the comparator itself has an inherent propagation delay. Due to the limitations of offset voltage and propagation delay, the timing from when the zero-current detection circuit detects a reverse inductor current to when it outputs an enable signal to turn off the synchronous rectifier is uncertain. Turning off the synchronous rectifier too early or too late will reduce the efficiency of the switching power supply system: if the synchronous rectifier is turned off too early when the inductor current is positive, the parasitic body diode of the synchronous rectifier will conduct, resulting in significant diode conduction losses; if the synchronous rectifier is turned off too late after the inductor current reverses, unnecessary rectifier conduction losses will occur. Furthermore, due to the parasitic effects of bond wires, turning off the synchronous rectifier too early or too late will cause significant ringing at the switching node, increasing voltage stress on the power transistor and inductor, increasing power transistor losses, and introducing electromagnetic interference problems. Therefore, the zero-current detection circuit needs to accurately shut down the synchronous rectifier when the inductor current is zero in order to reduce device stress and electromagnetic interference, and improve the working efficiency of the switching power supply system.

[0005] For engineers in the integrated circuit design field, circuit complexity and area are among the criteria for evaluating the quality of a circuit module: higher circuit complexity leads to a greater risk of failure and lower reliability; while a larger module area increases the production cost of the integrated circuit. Several existing zero-current detection circuits achieve adaptive adjustment of offset voltage at the expense of power consumption, circuit complexity, and area. For example, the patented application in publication CN109660109A utilizes a D flip-flop, an up / down counter, a digital-to-analog converter (DAC), an offset voltage adjustment module, and additional clock control signals udclk and Hold to dynamically adjust the offset voltage of a zero-crossing comparator. The DAC circuit requires an additional reference voltage, operational amplifier, and resistor array. Furthermore, circuit complexity, area, and power consumption increase with the DAC's resolution and conversion rate. The additional clock control signals udclk and Hold require external circuit modules to generate, further increasing design difficulty and area overhead. For example, the patent proposed in publication number CN111786661A uses a reference voltage Vref, a first comparator module, a logic module, and a compensation module to adjust the offset voltage of the second comparator module. The reference voltage Vref requires an additional bandgap reference circuit to generate. A high-precision, low-temperature-drift bandgap reference circuit requires complex high-order curvature compensation, which increases design cost, area overhead, and power consumption. In addition, the first comparator module and the compensation module require additional bias current to maintain normal operation, which increases the overall power consumption of the zero-current detection circuit.

[0006] Modern mobile smart IoT devices are generally powered by miniature mobile batteries and require minimal battery replacement or charging over extended periods. These applications often necessitate switching power supply systems with low quiescent power consumption and the ability to operate efficiently under microampere-level light load currents. Therefore, the power consumption of zero-current detection circuits used in such switching power supply scenarios is severely limited. However, due to the trade-off between power consumption and speed, the accuracy and speed of the static comparator, the main power-consuming module in the zero-current detection circuit, are significantly constrained. In conclusion, existing zero-current detection circuits cannot achieve accurate detection of the inductor current zero-crossing point while maintaining low power consumption. Summary of the Invention

[0007] To address the shortcomings of existing technologies, this invention provides a low-power adaptive zero-current detection circuit for switching power supplies, which can overcome the deficiencies of existing technologies. The switching power supply is a synchronous rectifier switching power supply, and can further be a buck, boost, or buck-boost synchronous rectifier switching power supply.

[0008] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0009] A low-power adaptive zero-current detection circuit for switching power supplies, the low-power adaptive zero-current detection circuit comprising a main comparator and a decision circuit, wherein:

[0010] The main comparator has two input terminals, one offset voltage control terminal, and one output terminal. Its first input terminal is connected to the positive terminal voltage signal of the synchronous rectifier tube of the switching power supply, and its second input terminal is connected to the negative terminal voltage signal of the synchronous rectifier tube. The offset voltage control terminal is connected to the output terminal of the decision circuit. The main comparator output terminal outputs a zero current detection signal to control the working state of the synchronous rectifier tube.

[0011] The decision circuit has three input terminals and one output terminal. The first input terminal is connected to the positive terminal voltage signal of the synchronous rectifier, the second input terminal is connected to the negative terminal voltage signal of the synchronous rectifier, the third input terminal is connected to the drive signal of the synchronous rectifier, and the output terminal is connected to the offset voltage control terminal of the main comparator to control the offset voltage of the main comparator.

[0012] As a preferred embodiment of the present invention, the main comparator is a low-power static comparator used to detect the zero-crossing point of the inductor current of the switching power supply. When the inductor current crosses zero, the main comparator outputs an enable signal to turn off the synchronous rectifier.

[0013] As a preferred embodiment of the present invention, the main comparator operates normally only when the synchronous rectifier is turned on, and is in a dormant state when the synchronous rectifier is turned off.

[0014] As a preferred embodiment of the present invention, the decision circuit outputs an offset voltage control signal to adaptively adjust the offset voltage of the main comparator after the synchronous rectifier is turned off.

[0015] In a preferred embodiment of the present invention, the switching power supply adopts a buck topology, including a high-side power transistor, a low-side power transistor, an inductor, a capacitor, and a control loop. The high-side power transistor is the power transistor of the switching power supply, with its drain connected to the input voltage signal, its source connected to the drain of the low-side power transistor, and its gate connected to the high-side power transistor drive signal. The low-side power transistor is the synchronous rectifier of the switching power supply, with its source connected to ground and its gate connected to the low-side power transistor drive signal. One end of the inductor is connected to the switching node, i.e., the common terminal of the high-side and low-side power transistors, and the other end is connected to the upper plate of the capacitor, supplying power to the load. The lower plate of the capacitor is grounded. The switching power supply regulates the switching on and off of the power transistor and the synchronous rectifier through the control loop. In the closed state; the non-inverting input of the main comparator is connected to the switching node voltage signal, the inverting input is connected to the ground signal, and the offset voltage control terminal is connected to the output of the decision circuit, outputting a zero-current detection signal; the main comparator is used to detect the switching node voltage signal and the ground signal. When the inductor current crosses zero, the switching node voltage signal will be higher than the ground signal, outputting a high-level zero-current detection signal and turning off the low-side power transistor; when the inductor current is positive, the switching node voltage signal is lower than the ground signal, outputting a low-level zero-current detection signal, which does not affect the normal operation of the switching power supply; the first input of the decision circuit is connected to the switching node voltage signal, the second input is connected to the ground signal, and the third input is connected to the low-side power transistor drive signal, outputting 2 n The bit control signal controls the offset voltage of the main comparator, compensates for the effects of the main comparator's propagation delay, improves the comparison accuracy, and thus enables the low-side power transistor to be accurately turned off when the inductor current crosses zero.

[0016] In a preferred embodiment of the present invention, the decision circuit adaptively controls the offset voltage of the main comparator. When the low-side power transistor is turned off, if the inductor current is negative (i.e., the inductor current flows in the reverse direction through the low-side power transistor to ground), the switching node voltage signal is greater than the ground signal, indicating that the low-side power transistor is turned off too late. The decision circuit will increase the offset voltage of the main comparator, causing the low-side power transistor to turn off earlier in the next switching cycle. When the low-side power transistor is turned off, if the inductor current is positive (i.e., the inductor current flows in the forward direction through the load to ground), the switching node voltage signal is less than the ground signal, indicating that the low-side power transistor is turned off too early. The decision circuit will decrease the offset voltage of the main comparator, causing the low-side power transistor to turn off later in the next switching cycle.

[0017] Compared with the prior art, the present invention has the following beneficial effects:

[0018] The zero-current detection circuit proposed in this invention achieves adaptive adjustment of the main comparator offset voltage under low power consumption, compensates for the main comparator's own delay, improves comparison accuracy, and precisely shuts down the synchronous rectifier when the inductor current is zero, reducing switching node ringing, device stress, and electromagnetic interference problems. Furthermore, the proposed zero-current detection circuit has a simple structure and low overall circuit complexity. Since the control signals are all derived from the power transistor drive signals of the switching power supply, they do not require generation by additional circuit modules, thus reducing area and design costs. Therefore, the low-power adaptive zero-current comparator proposed in this invention can overcome the shortcomings of existing technologies and effectively improve the overall operating efficiency of the switching power supply. Attached Figure Description

[0019] Figure 1 This is a structural diagram of the low-power adaptive zero-current detection circuit proposed in this invention.

[0020] Figure 2 This is a structural diagram of a low-power adaptive zero-current detection circuit applied to a buck synchronous rectifier switching power supply according to an embodiment of the present invention.

[0021] Figure 3 This is a circuit diagram of a low-power main comparator with controllable offset voltage according to an embodiment of the present invention.

[0022] Figure 4 This is a diagram illustrating an embodiment of the low-power decision circuit of the present invention, wherein... Figure 4 (a) in the diagram is a decision circuit structure diagram based on a high-precision clock comparator. Figure 4 (b) in the diagram is a decision circuit structure diagram based on an analog edge detection circuit.

[0023] Figure 5 For the present invention Figure 2 The diagram shows the key signal timings for a low-power adaptive zero-current sensing circuit applied to a buck switching power supply during steady-state operation. Among them, Figure 5 (a) in the diagram represents the case where the inductor current is negative when the synchronous rectifier is turned off too late; Figure 5 (b) in the diagram represents the case where the inductor current is positive when the synchronous rectifier is turned off prematurely. Detailed Implementation

[0024] The present invention will be further described and illustrated below with reference to specific embodiments. The embodiments described are merely examples of the content of this disclosure and do not limit the scope of the invention. The technical features of each embodiment in the present invention can be combined accordingly, provided that there is no mutual conflict.

[0025] The low-power adaptive zero-current detection circuit proposed in this invention can be applied to buck, boost, and buck-boost synchronous rectifier switching power supplies. The synchronous rectifier switching power supply includes a power transistor, a synchronous rectifier transistor, an inductor, a capacitor, and a control loop. The synchronous rectifier switching power supply adjusts the on / off states of the power transistor and the synchronous rectifier transistor through the control loop to periodically extract electrical energy from the input voltage and transfer it to the capacitor through an energy storage inductor, thereby providing the load with the desired stable DC voltage.

[0026] like Figure 1 The diagram shown is a structural diagram of the low-power adaptive zero-current detection circuit proposed in this invention, which includes a main comparator and a decision circuit.

[0027] The main comparator is a low-power static comparator. It has two input terminals (connected to the two ends of the synchronous rectifier, respectively), an offset voltage control terminal (for receiving the output signal from the decision circuit), and an output terminal (for outputting a zero-current detection signal). Specifically, in one embodiment of the invention, the first input terminal of the main comparator is connected to the positive terminal voltage signal of the synchronous rectifier, the second input terminal is connected to the negative terminal voltage signal of the synchronous rectifier, and the offset voltage control terminal is connected to the output terminal of the decision circuit. The main comparator is used to detect the voltage across the synchronous rectifier and outputs an enable signal to turn off the synchronous rectifier when the inductor current crosses zero, thereby improving the operating efficiency of the switching power supply in DCM mode.

[0028] The decision circuit has three input terminals and one output terminal (for outputting an offset voltage control signal). Specifically, in one embodiment of the invention, the first input terminal of the decision circuit is connected to the positive terminal voltage signal of the synchronous rectifier, the second input terminal is connected to the negative terminal voltage signal of the synchronous rectifier, the third input terminal is connected to the synchronous rectifier drive signal, and the output terminal is connected to the offset voltage control terminal of the main comparator. The power consumption of the decision circuit is proportional to the switching frequency of the switching power supply. For a switching power supply operating under microampere-level light load, the decision circuit consumes very low power. Based on the voltage signals across the synchronous rectifier and the synchronous rectifier drive signal, the decision circuit outputs an offset voltage control signal to adaptively adjust the offset voltage of the main comparator, solving the accuracy and delay problems of the low-power static main comparator. This allows the zero-current detection circuit to accurately turn off the synchronous rectifier when the inductor current is zero, while maintaining low power consumption.

[0029] like Figure 1 As shown, in a more preferred embodiment of the present invention, the main comparator can operate normally only when the synchronous rectifier is turned on and enter a sleep state when the synchronous rectifier is turned off, thereby significantly reducing the overall power consumption of the zero-current detection circuit. Furthermore, since the propagation delay of the main comparator can be compensated for by adaptively adjusting the offset voltage through the decision circuit, its bias current can be appropriately reduced to further save power consumption.

[0030] like Figure 2 The diagram shown illustrates a low-power adaptive zero-current detection circuit structure for a buck synchronous rectifier switching power supply according to an embodiment of the present invention. The specific control loop is omitted here. The buck synchronous rectifier switching power supply includes a high-side power transistor MH, a low-side power transistor ML, an inductor L, and a capacitor C. The high-side power transistor MH is the power transistor of the switching power supply, with its drain connected to the input voltage signal VIN, its source connected to the drain of the low-side power transistor ML, and its gate connected to the high-side power transistor drive signal DRV_H. The low-side power transistor ML is the synchronous rectifier transistor of the switching power supply, with its source connected to ground and its gate connected to the low-side power transistor drive signal DRV_L. One end of the inductor L is connected to the switching node (i.e., the common terminal of the high-side power transistor MH and the low-side power transistor ML), and the other end is connected to the upper plate of the capacitor C, supplying power to the load. The other end of the load is grounded. The lower plate of the capacitor C is grounded. Both the high-side power transistor drive signal DRV_H and the low-side power transistor drive signal DRV_L originate from the control loop of the switching power supply. The main comparator operates normally only when the low-side power transistor ML is on. Its non-inverting input (first input) is connected to the switching node voltage signal VSW, its inverting input (second input) is connected to ground, and its offset voltage control terminal is connected to the output of the decision circuit. The main comparator outputs a zero-current detection signal VZCD. The main comparator detects the switching node voltage signal VSW and the ground signal. When the inductor current crosses zero, the switching node voltage signal VSW will be higher than the ground signal, and the zero-current detection signal VZCD will become high, driving the low-side power transistor drive signal DRV_L to become low, thus turning off the low-side power transistor ML and preventing the inductor current from flowing backward through the low-side power transistor ML to the ground signal. When the inductor current is positive, the switching node voltage signal is lower than the ground signal, and the zero-current detection signal VZCD is low, which does not affect the normal operation of the switching power supply. The first input of the decision circuit is connected to the switching node voltage signal VSW, the second input is connected to ground, and the third input is connected to the low-side power transistor drive signal DRV_L. The output of the decision circuit outputs 2. n Bit control signal TR[2] n [1] Used to control the offset voltage of the main comparator to compensate for the propagation delay of the low-power main comparator, improve the comparison accuracy of the main comparator, and thus achieve precise shutdown of the low-side power transistor ML when the inductor current crosses zero.

[0031] like Figure 3As shown, in a specific embodiment of the present invention, the main comparator consists of a bias stage, a first-stage preamplifier, and a second-stage common-source amplifier. The bias stage includes an inverter, a first PMOS switch PS0, a first PMOS current mirror PM0, and a current reference IBIAS (used to provide bias current, which can be implemented by a current mirror or an external current source); the first-stage preamplifier includes a second PMOS switch PS10, a third PMOS switch PS11, a second PMOS current mirror PM10, a third PMOS current mirror PM11, a first NMOS current mirror NM10, a second NMOS current mirror NM11, a first NMOS switch NS10, a second NMOS switch NS11, and a third NMOS switch NS12; the second-stage common-source amplifier includes a fourth PMOS switch PS20, a fourth PMOS current mirror PM20, a buffer (used to improve the driving capability of the zero-current detection circuit), (2) n +1) NMOS common-source transistors NM20~NM22 n (2) n +1) NMOS common-source transistor size control switch NS20~NS22 n The system includes an NMOS pull-down transistor (NMB) and a delay circuit (used to prevent the main comparator from outputting incorrect comparison results when transitioning from sleep mode to normal operation). The bias stage of the main comparator provides bias current to the first-stage preamplifier and the second-stage common-source amplifier. The two amplifier stages compare the switching node voltage signal VSW with the ground signal. The output signal of the second-stage common-source amplifier is buffered to obtain the zero-current detection signal VZCD. When the switching node voltage signal VSW is higher than the ground signal, the zero-current detection signal VZCD will go high, thereby turning off the low-side power transistor ML.

[0032] like Figure 3As shown, in a specific embodiment of the present invention, the specific connection relationship between the internal devices of the main comparator is as follows: the inverter input terminal is connected to the low-side power transistor drive signal DRV_L, used to invert the signal DRV_L and output the inverted signal NDRV_L; the inverter output terminal is connected to the gate of all PMOS switches, the gate of the second NMOS switch NS11, and the input terminal of the delay circuit; the source of all PMOS switches is connected to the power supply signal VDD, and the drain is connected to the source of the corresponding PMOS current mirror; the drain of the first PMOS current mirror PM0 is connected to the current reference IBIAS, the other end of the current reference IBIAS is connected to the ground signal, and connected to the gate of all PMOS current mirrors; the drains of the second PMOS current mirror PM10 and the third PMOS current mirror PM11 are respectively connected to the drains of the first NMOS current mirror NM10 and the second NMOS current mirror NM11, and the drain of the second PMOS current mirror PM10 (i.e., the output of the first stage preamplifier) ​​is connected to (2 n +1) NMOS common-source transistors NM20~NM22 n The gate of the second NMOS current mirror transistor NM11 is shorted to the drain and connected to the gate of the first NMOS current mirror transistor NM10; the source of the first NMOS current mirror transistor NM10 is connected to the drain of the first NMOS switch transistor NS10, the source of the first NMOS switch transistor NS10 is connected to the ground signal, and the gate is connected to the power supply signal VDD; the source of the second NMOS current mirror transistor NM11 is connected to the drains of the second NMOS switch transistor NS11 and the third NMOS switch transistor NS12, the source of the second NMOS switch transistor NS11 is connected to the ground signal, the source of the third NMOS switch transistor NS12 is connected to the switching node voltage signal VSW, and the gate is connected to the low-side power transistor drive signal DRV_L; the drain of the fourth PMOS current mirror transistor PM20 (i.e., the output of the second stage common-source amplifier) ​​is connected to (2 n +1) NMOS common-source transistors NM20~NM22 n The drain of the NMOS common source transistor is connected to the buffer input; all NMOS common source transistors are sized to control switches NS20~NS22. n The source of the first NMOS common-source transistor is connected to ground, and the gate of the first NMOS common-source transistor size control switch NS20 is connected to the power supply signal VDD. The second to (2 n +1) NMOS common-source transistor size control switches NS21~NS22 n The gates are respectively connected to 2 n Offset voltage control signal TR[2] n :1]; The gate of the NMOS pull-down transistor NMB is connected to the output of the delay circuit, the drain is connected to the drain of the fourth PMOS current mirror transistor PM20, and the source is connected to the ground signal.

[0033] like Figure 3 As shown, in a specific embodiment of the present invention, the main comparator operates normally only when the low-side power transistor ML is turned on, and sleeps when the low-side power transistor ML is turned off, thereby achieving low power consumption. When the low-side power transistor ML is turned off, DRV_L is low, and the switches PS0, PS10, PS11, and PS20 are turned off. The main comparator is in a sleep state, and its non-inverting input and inverting input are connected to ground through NMOS switches NS10 and NS11, respectively. The output of the second-stage common-source amplifier is pulled down to ground by the NMOS pull-down transistor NMB, consuming only a very low leakage current and outputting a low-level signal. When the low-side power transistor ML is turned on, DRV_L is high, and the switches PS0, PS10, PS11, and PS20 are turned on, and the main comparator operates normally. For a switching power supply using PFM control and operating in DCM mode, the average power consumption of the main comparator decreases as the load current decreases, thereby improving the system's efficiency under light load.

[0034] like Figure 4 As shown in (a) of the diagram, in a specific embodiment of the present invention, the decision circuit includes a clock-controlled comparator, a delay circuit, an n-bit up / down counter, and an n-bit thermometer decoder. The non-inverting input of the clock-controlled comparator is connected to ground, the inverting input is connected to the switching node voltage signal VSW, the clock control terminal is connected to the low-side power transistor drive signal DRV_L, and the output is connected to the input of the n-bit up / down counter. The input of the delay circuit (used to prevent timing errors) is connected to the low-side power transistor drive signal DRV_L, and the output is connected to the clock control terminal of the n-bit up / down counter. The input of the n-bit up / down counter is connected to the output of the clock-controlled comparator, the clock control terminal is connected to the output of the delay circuit, and the output is connected to the input of the n-bit thermometer decoder. The input of the n-bit thermometer decoder is connected to the output of the n-bit up / down counter and outputs 2... n Bit-decoded signal TR[2] n [1] to the offset voltage control terminal of the main comparator. The clocked comparator is controlled by the low-side power transistor drive signal DRV_L. It compares the switching node voltage VSW and the ground signal only when the low-side power transistor ML is off (i.e., when the falling edge of the DRV_L signal arrives), and outputs the comparison result to the n-bit up / down counter. The n-bit up / down counter increments or decrements by one according to the output result of the clocked comparator after the low-side power transistor ML is off for a certain period of time: if the clocked comparator output signal is high, it increments by one (if all n-bit output signals Q[n:1] are high, it remains high); if the clocked comparator output signal is low, it decrements by one (if all n-bit output signals Q[n:1] are low, it remains low). The n-bit output signal Q[n:1] of the n-bit up / down counter is decoded by the n-bit thermometer decoder to obtain 2. nOffset voltage control signal TR[2] n :1], used to control the present invention Figure 3 2 in the main comparator n Common source transistor size control switches NM21~NM22 n The operating state of the decision circuit adaptively adjusts the width-to-length ratio of the NMOS common-source transistor, thereby controlling the input offset voltage of the main comparator. The average power consumption of the decision circuit increases linearly with the switching frequency of the power supply. For a power supply operating under microampere-level light load conditions, the average power consumption of the decision circuit is extremely low.

[0035] The working principle of the decision circuit is as follows: When the low-side power transistor is turned off, if the inductor current is negative (i.e., the inductor current flows in the reverse direction through the low-side power transistor to the ground signal), the switching node voltage signal is greater than the ground signal, indicating that the low-side power transistor is turned off too late. The clocked comparator will output a low level to decrement the n-bit up / down counter by one, reducing the width-to-length ratio of the common-source transistor in the second stage of the main comparator, thereby increasing the offset voltage of the main comparator and causing the low-side power transistor to turn off earlier in the next switching cycle. When the low-side power transistor is turned off, if the inductor current is positive (i.e., the inductor current flows in the forward direction through the load to the ground signal), the switching node voltage signal is less than the ground signal, indicating that the low-side power transistor is turned off too early. The clocked comparator will output a high level to increment the n-bit up / down counter by one, increasing the width-to-length ratio of the common-source transistor in the second stage of the main comparator, thereby reducing the offset voltage of the main comparator and causing the low-side power transistor to turn off later in the next switching cycle.

[0036] like Figure 4 As shown in (b) of the diagram, in another specific embodiment of the present invention, the decision circuit includes an analog edge detection circuit, a delay circuit, an n-bit up / down counter, and an n-bit thermometer decoder. The input of the analog edge detection circuit is connected to the switching node voltage signal VSW, the clock control terminal is connected to the low-side power transistor drive signal DRV_L, and the output is connected to the input of the n-bit up / down counter. The input of the delay circuit is connected to the low-side power transistor drive signal DRV_L, and the output is connected to the clock control terminal of the n-bit up / down counter. The input of the n-bit up / down counter is connected to the output of the analog edge detection circuit, the clock control terminal is connected to the output of the delay circuit, and the output is connected to the input of the n-bit thermometer decoder. The input of the n-bit thermometer decoder is connected to the output of the n-bit up / down counter and outputs 2... n Bit-decoded signal TR[2] n:1] to the offset voltage control terminal of the main comparator. The analog edge detection circuit only detects the direction of change of the switching node voltage signal VSW when the low-side power transistor ML is off (i.e., when the falling edge of the DRV_L signal arrives). If the switching node voltage signal VSW increases upward (i.e., the rising edge of the switching node voltage signal VSW is detected), a low-level signal is output; if the switching node voltage signal VSW decreases downward (i.e., the falling edge of the switching node voltage signal VSW is detected), a high-level signal is output. The working principle of the n-bit up / down counter and the n-bit thermometer decoder is the same as... Figure 4 The same applies to (a) in the above, so I will not repeat it here.

[0037] like Figure 5 As shown, this is the present invention. Figure 2 The diagram shows the key signal timing of a low-power adaptive zero-current detection circuit applied to a buck switching power supply during steady-state operation. Figure 5 As shown in (a), at the end of the Φ2 phase of the previous switching cycle, the low-side power transistor ML turns off when the inductor current is negative. This indicates that the offset voltage of the main comparator is too small, causing the low-side power transistor ML to turn off too late. In this case, the clocked comparator (or analog edge detection circuit) will output a low-level signal when the low-side power transistor ML turns off, causing the n-bit up / down counter to decrement by one, thereby reducing the width-to-length ratio of the second-stage common-source transistor of the main comparator and increasing the offset voltage of the main comparator. Therefore, at the end of the Φ5 phase of the next switching cycle, the low-side power transistor ML will turn off earlier. Figure 5 As shown in (b), at the end of the Φ2 phase of the previous switching cycle, the low-side power transistor ML turns off when the inductor current is positive, indicating that the offset voltage of the main comparator is too large, causing the low-side power transistor ML to turn off prematurely. In this case, the clocked comparator (or analog edge detection circuit) will output a high-level signal when the low-side power transistor ML turns off, causing the n-bit up-down counter to increment by one, thereby increasing the width-to-length ratio of the second stage common-source transistor of the main comparator and reducing the offset voltage of the main comparator. Therefore, at the end of the Φ5 phase of the next switching cycle, the low-side power transistor ML will turn off later.

[0038] The zero-current detection circuit proposed in this invention adaptively adjusts the offset voltage of the low-power static master comparator through a decision circuit, compensating for the effect of the master comparator's own delay, improving comparison accuracy, and enabling the zero-current detection circuit to accurately shut down the synchronous rectifier when the inductor current is zero, reducing switching node ringing, device stress, and electromagnetic interference problems. The proposed zero-current detection circuit has a simple structure and low overall circuit complexity. Furthermore, the control signals are all derived from the power transistor drive signals of the switching power supply, eliminating the need for additional circuit modules and thus reducing area and design costs. In addition, the master comparator, as the main power-consuming module, only operates normally when the synchronous rectifier is on and sleeps when it is off. The average power consumption of the decision circuit changes proportionally to the switching frequency of the switching power supply; therefore, the proposed zero-current detection circuit effectively saves power. In summary, the low-power adaptive zero-current detection circuit proposed in this invention overcomes the shortcomings of existing technologies, achieving accurate detection of the inductor current zero-crossing point with low power consumption, low circuit complexity, and a small area, effectively improving the overall operating efficiency of the switching power supply.

[0039] The above examples specifically illustrate and describe exemplary implementations of the present invention. These embodiments are merely illustrative of the technical solutions of the present invention, enabling those skilled in the art to understand and apply it. The present invention is not limited to the detailed structures, configuration methods, or implementations described herein. It should be noted that those skilled in the art can readily make various modifications to the above embodiments, or make equivalent substitutions for some or all of the technical features of the present invention, or apply the general principles described herein to other embodiments without creative effort. All modifications, improvements, or equivalent substitutions of the technical features of the present invention should be within the scope of protection of the present invention.

Claims

1. A low-power adaptive zero-current detection circuit for switching power supplies, characterized in that, The low-power adaptive zero-current detection circuit includes a main comparator and a decision circuit, wherein: The main comparator has two input terminals, one offset voltage control terminal, and one output terminal. Its first input terminal is connected to the positive terminal voltage signal of the synchronous rectifier tube of the switching power supply, and its second input terminal is connected to the negative terminal voltage signal of the synchronous rectifier tube. The offset voltage control terminal is connected to the output terminal of the decision circuit. The main comparator output terminal outputs a zero current detection signal to control the working state of the synchronous rectifier tube. The decision circuit has three input terminals and one output terminal. The first input terminal is connected to the positive terminal voltage signal of the synchronous rectifier, the second input terminal is connected to the negative terminal voltage signal of the synchronous rectifier, the third input terminal is connected to the drive signal of the synchronous rectifier, and the output terminal is connected to the offset voltage control terminal of the main comparator to control the offset voltage of the main comparator. The main comparator is a low-power static comparator; the main comparator only works normally when the synchronous rectifier is turned on, and is in a sleep state when the synchronous rectifier is turned off; The switching power supply adopts a step-down topology, including a high-side power transistor, a low-side power transistor, an inductor, a capacitor, and a control loop. The high-side power transistor is the power transistor of the switching power supply; its drain is connected to the input voltage signal, its source is connected to the drain of the low-side power transistor, and its gate is connected to the high-side power transistor drive signal. The low-side power transistor is the synchronous rectifier of the switching power supply; its source is connected to ground, and its gate is connected to the low-side power transistor drive signal. One end of the inductor is connected to the switching node, which is the common terminal of the high-side and low-side power transistors. The other end of the inductor is connected to the upper plate of the capacitor, and the lower plate of the capacitor is grounded. The other end of the inductor is also connected to the load to supply power to the load. The control loop adjusts the on / off state of the power transistor and the synchronous rectifier, periodically... The system extracts electrical energy from the input voltage and transfers it to the capacitor through an inductor to provide a stable DC voltage to the load. Both the high-side power transistor drive signal and the low-side power transistor drive signal originate from the control loop. The non-inverting input of the main comparator is connected to the switching node voltage signal, the inverting input is connected to ground, and the offset voltage control terminal is connected to the output of the decision circuit, outputting a zero-current detection signal. The main comparator detects the switching node voltage signal and the ground signal. When the inductor current crosses zero, the switching node voltage signal is higher than the ground signal, outputting a high-level zero-current detection signal and turning off the low-side power transistor. The first input of the decision circuit is connected to the switching node voltage signal, the second input is connected to ground, and the third input is connected to the low-side power transistor drive signal, outputting a 2... n The bit control signal controls the offset voltage of the main comparator, compensates for the effect of the main comparator's propagation delay, improves the comparison accuracy, and thus enables the low-side power transistor to be accurately turned off when the inductor current crosses zero. The decision circuit adaptively controls the offset voltage of the main comparator. When the low-side power transistor is off, if the inductor current is negative (i.e., the inductor current flows in the reverse direction through the low-side power transistor to ground), the switching node voltage signal is greater than the ground signal, indicating that the low-side power transistor is turning off too late. The decision circuit will increase the offset voltage of the main comparator, causing the low-side power transistor to turn off earlier in the next switching cycle. When the low-side power transistor is off, if the inductor current is positive (i.e., the inductor current flows in the forward direction through the load to ground), the switching node voltage signal is less than the ground signal, indicating that the low-side power transistor is turning off too early. The decision circuit will decrease the offset voltage of the main comparator, causing the low-side power transistor to turn off later in the next switching cycle. The decision circuit includes a clock-controlled comparator, a delay circuit, an n-bit up / down counter, and an n-bit thermometer decoder. The non-inverting input of the clock-controlled comparator is connected to ground, the inverting input is connected to the switching node voltage signal, the clock control terminal is connected to the low-side power transistor drive signal, and the output is connected to the input of the n-bit up / down counter. The input of the delay circuit is connected to the low-side power transistor drive signal, and the output is connected to the clock control terminal of the n-bit up / down counter. The input of the n-bit thermometer decoder is connected to the output of the n-bit up / down counter, and outputs 2... n The bit-decoded signal is sent to the offset voltage control terminal of the main comparator; the clock comparator is used to compare the switching node voltage signal and the ground signal when the low-side power transistor is off. If the switching node voltage signal is greater than the ground signal, a low-level signal is output; if the switching node voltage signal is less than the ground signal, a high-level signal is output.

2. The low-power adaptive zero-current detection circuit for switching power supplies according to claim 1, characterized in that, The main comparator is used to detect the zero-crossing point of the inductor current of the switching power supply. When the inductor current crosses zero, the main comparator outputs an enable signal to turn off the synchronous rectifier.

3. The low-power adaptive zero-current detection circuit for switching power supplies according to claim 1, characterized in that, The decision circuit outputs an offset voltage control signal after the synchronous rectifier is turned off to adaptively adjust the offset voltage of the main comparator.

4. The low-power adaptive zero-current detection circuit for switching power supplies according to claim 1, characterized in that, The main comparator consists of a bias stage, a first-stage preamplifier, and a second-stage common-source amplifier. The bias stage includes an inverter, a first PMOS switch, a first PMOS current mirror, and a current reference. The first-stage preamplifier includes a second PMOS switch, a third PMOS switch, a second PMOS current mirror, a third PMOS current mirror, a first NMOS current mirror, a second NMOS current mirror, a first NMOS switch, a second NMOS switch, and a third NMOS switch. The second-stage common-source amplifier includes a fourth PMOS switch, a fourth PMOS current mirror, a buffer, and (2... n +1) NMOS common-source transistors, (2) n +1) NMOS common-source transistor size control switch, NMOS pull-down transistor and delay circuit; The specific connection relationship between the main comparator devices is as follows: the inverter input is connected to the low-side power transistor drive signal, and the output is connected to the gates of all PMOS switches, the gate of the second NMOS switch, and the input of the delay circuit; the sources of all PMOS switches are connected to the power supply signal VDD, and the drains are connected to the sources of the corresponding PMOS current mirrors; the drain of the first PMOS current mirror is connected to the current reference, the current reference is connected to the ground signal, and connected to the gates of all PMOS current mirrors; the drains of the second and third PMOS current mirrors are connected to the drains of the first and second NMOS current mirrors, respectively, and the drain of the second PMOS current mirror is connected to (2 n +1) The gates of the NMOS common source transistors are connected to each other. The gate and drain of the second NMOS current mirror transistor are shorted and connected to the gate of the first NMOS current mirror transistor. The source of the first NMOS current mirror transistor is connected to the drain of the first NMOS switch transistor. The source of the first NMOS switch transistor is connected to the ground signal, and its gate is connected to the power supply signal VDD. The source of the second NMOS current mirror transistor is connected to the drains of the second and third NMOS switches. The source of the second NMOS switch transistor is connected to the ground signal, and the source of the third NMOS switch transistor is connected to the switching node voltage signal. Its gate is connected to the low-side power transistor drive signal. The drain of the fourth PMOS current mirror transistor is connected to (2 n +1) The drains of the NMOS common-source transistors are connected to the buffer input; the sources of all NMOS common-source transistor size control switches are connected to ground; the gate of the first NMOS common-source transistor size control switch is connected to the power supply signal VDD; the second to (2) n +1) The gates of the NMOS common-source transistor-sized control switches are respectively connected to 2 n The offset voltage control signal; the gate of the NMOS pull-down transistor is connected to the output of the delay circuit, the drain is connected to the drain of the fourth PMOS current mirror transistor, and the source is connected to ground signal; The main comparator operates normally only when the low-side power transistor is on and sleeps when the low-side power transistor is off. When the low-side power transistor is off, all PMOS switches are off, the main comparator is in sleep mode, and its non-inverting input and inverting input are connected to ground through the first NMOS switch and the second NMOS switch, respectively. The output of the second-stage common-source amplifier is pulled down to ground by the NMOS pull-down transistor, outputting a low-level signal. When the low-side power transistor is on, all PMOS switches are on, and the main comparator operates normally.

5. A low-power adaptive zero-current detection circuit for a switching power supply according to claim 1, characterized in that, The decision circuit includes an analog edge detection circuit, a delay circuit, an n-bit up / down counter, and an n-bit thermometer decoder. The input of the analog edge detection circuit is connected to the switching node voltage signal, the clock control terminal is connected to the low-side power transistor drive signal, and the output terminal is connected to the input of the n-bit up / down counter. The input of the delay circuit is connected to the low-side power transistor drive signal, and the output terminal is connected to the clock control terminal of the n-bit up / down counter. The input of the n-bit thermometer decoder is connected to the output of the n-bit up / down counter, and it outputs 2... n The bit-decoded signal is sent to the offset voltage control terminal of the main comparator; the analog edge detection circuit is used to detect the direction of change of the switching node voltage signal when the low-side power transistor is turned off. If the switching node voltage signal increases upward, a low-level signal is output; if the switching node voltage signal decreases downward, a high-level signal is output.

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