Semiconductor device

Abstract

Embodiments relate to a semiconductor device. The semiconductor device of the embodiments includes a first terminal, a second terminal, a third terminal, a first circuit that outputs a signal of a first level when a temperature satisfies a condition, and a second circuit that electrically insulates between the second terminal and the third terminal when the first circuit outputs the signal of the first level by being driven by a voltage supplied through the first terminal. The first circuit includes an element provided between a first wiring and the first terminal, and outputs the signal of the first level regardless of the temperature when the first voltage is supplied to the first wiring.

Description

[0001] Cross-referencing of related applications

[0002] This application claims priority to Japanese Patent Application No. 2022-086200 (filed on May 26, 2022). The entire contents of the basic application are incorporated herein by reference. Technical Field

[0003] The implementation relates to a semiconductor device. Background Technology

[0004] A semiconductor device is known that protects surrounding equipment from excessive temperature rise by stopping the power supply. Such a semiconductor device includes a test circuit for determining whether the power supply has been stopped properly. Summary of the Invention

[0005] The semiconductor device of the embodiment includes: a first terminal; a second terminal; a third terminal; a first circuit that outputs a signal of a first level when a temperature condition is met; and a second circuit that is driven by a voltage supplied via the first terminal, and electrically insulates the second terminal from the third terminal when the first circuit outputs the signal of the first level, the first circuit including an element disposed between a first wiring and the first terminal, and outputting the signal of the first level independently of the temperature when the first wiring is supplied with a first voltage.

[0006] The semiconductor device of the embodiment can suppress the high limitation of the voltage used to control the power supply and can suppress the increase of chip size. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating an example of the structure of a power supply system including the semiconductor device involved in the embodiments.

[0008] Figure 2 This is a circuit diagram illustrating an example of the structure of the power supply circuit involved in the implementation method.

[0009] Figure 3 This is a circuit diagram illustrating an example of the structure of the over-temperature detection circuit and test circuit involved in the implementation method.

[0010] Figure 4 This is a circuit diagram illustrating an example of the structure of the over-temperature detection circuit and the test circuit used to illustrate the test operation in the first example of the implementation method.

[0011] Figure 5This is a circuit diagram illustrating an example of the structure of an over-temperature detection circuit and a test circuit for normal operation in the first operating example of the embodiment.

[0012] Figure 6 This is a diagram illustrating an example of the change in voltage relative to the temperature of the semiconductor device and the signal supplied from the over-temperature detection circuit during normal operation in the first operating example of the embodiment.

[0013] Figure 7 This is a circuit diagram illustrating an example of the structure of the over-temperature detection circuit and the test circuit for normal operation in the second operating example of the embodiment.

[0014] Figure 8 This is a circuit diagram illustrating one example of the structure of the over-temperature detection circuit and test circuit involved in the first modified example.

[0015] Figure 9 This is a circuit diagram illustrating one example of the structure of the over-temperature detection circuit and test circuit involved in the second variation.

[0016] Figure 10 This is a circuit diagram illustrating one example of the structure of the over-temperature detection circuit and test circuit involved in the third variation.

[0017] Figure 11 This is a circuit diagram illustrating one example of the structure of the over-temperature detection circuit and test circuit involved in the fourth variation.

[0018] Figure 12 This is a circuit diagram illustrating one example of the structure of the over-temperature detection circuit and test circuit involved in the fifth variation.

[0019] Figure 13 This is a circuit diagram illustrating one example of the structure of the power supply circuit involved in the sixth variation.

[0020] Figure 14 This is a block diagram illustrating an example of the structure of a power supply system for a semiconductor device, including the seventh variation.

[0021] Figure 15 This is a circuit diagram illustrating an example of the structure of the power supply circuit and filter circuit involved in the seventh variation. Detailed Implementation

[0022] The embodiments will now be described with reference to the figures. Furthermore, in the following description, structural elements having the same function and structure will be given common reference numerals.

[0023] 1. Implementation Method

[0024] The semiconductor device involved in the implementation method is described.

[0025] 1.1 Structure

[0026] 1.1.1 Power Supply System

[0027] Regarding the structure of the power supply system including the semiconductor device involved in the implementation, using Figure 1 Please provide an explanation. Figure 1 This is a block diagram illustrating an example of the structure of a power supply system including the semiconductor device according to the embodiments. The power supply system includes a semiconductor device 1, a power source 2, a drive circuit 3, and a load 4.

[0028] Semiconductor device 1 is, for example, an IC (Integrated Circuit) chip. Semiconductor device 1 outputs voltage VOUT to load 4 based on the voltage VIN supplied from power source 2.

[0029] Semiconductor device 1 includes terminals PGND, PVIN, PVOUT and PVSHARE.

[0030] Terminal PGND is the ground terminal. Terminal PGND is supplied with voltage VSS. Voltage VSS is the ground voltage. Voltage VSS is, for example, 0V.

[0031] Terminal PVIN is connected to power source 2. Voltage VIN is supplied to terminal PVIN from power source 2. Voltage VIN is higher than voltage VSS.

[0032] Terminal PVSHARE is connected to drive circuit 3. Drive circuit 3 is used to drive external circuitry of semiconductor device 1 and is a tester used to determine whether the power supply has been properly stopped when the temperature of semiconductor device 1 rises excessively. Voltage VSHARE is supplied to terminal PVSHARE from drive circuit 3. Voltage VSHARE is the voltage used to drive semiconductor device 1 and the voltage used to determine whether the power supply has been properly stopped.

[0033] Terminal PVOUT is connected to load 4. Voltage VOUT is supplied to load 4 from terminal PVOUT.

[0034] 1.1.2 Semiconductor Devices

[0035] Regarding the structure of the semiconductor device 1 involved in the implementation method, the following will use... Figure 1 Please provide an explanation.

[0036] The semiconductor device 1 includes a power supply circuit 101, an over-temperature detection circuit 102, and a test circuit 103.

[0037] Power supply circuit 101 is connected to over-temperature detection circuit 102 and terminals PVIN, PVSHARE, PVOUT, and PGND. The over-temperature detection circuit 102 supplies a signal OVT to power supply circuit 101. Power supply circuit 101 is supplied with voltage VSHARE via terminal PVSHARE. Power supply circuit 101 is enabled when voltage VSHARE is at a "H" (High) level. An "H" level voltage VSHARE is, for example, voltage V1 or higher. When enabled, power supply circuit 101 supplies voltage VOUT based on voltage VIN, based on the signal OVT from over-temperature detection circuit 102. Conversely, power supply circuit 101 is disabled when voltage VSHARE is at a "L" (Low) level. An "L" level voltage VSHARE is, for example, less than voltage V1. When disabled, power supply circuit 101 stops supplying voltage VOUT based on voltage VIN, regardless of the signal OVT from over-temperature detection circuit 102.

[0038] The over-temperature detection circuit 102 detects whether the temperature of the semiconductor device 1 is above a threshold temperature T1. The threshold temperature T1 is, for example, around 200°C. Based on this detection result, the over-temperature detection circuit 102 supplies a signal OVT to the power supply circuit 101. More specifically, for example, if the over-temperature detection circuit 102 detects that the temperature of the semiconductor device 1 is above the threshold temperature T1, it supplies the signal OVT to the power supply circuit 101 to stop the supply of voltage VOUT based on voltage VIN. Conversely, for example, if the over-temperature detection circuit 102 detects that the temperature of the semiconductor device 1 is below the threshold temperature T1, it supplies the signal OVT to the power supply circuit 101 to supply voltage VOUT based on voltage VIN.

[0039] Test circuit 103 is connected to terminal PVSHARE. Test circuit 103 controls over-temperature detection circuit 102 based on voltage VSHARE to determine whether over-temperature detection circuit 102 is operating normally. Hereinafter, the action of determining whether over-temperature detection circuit 102 is operating normally will be referred to as test action. Details of the test action will be described later.

[0040] 1.1.2.1 Structure of the power supply circuit

[0041] Regarding an example of the structure of the power supply circuit 101 involved in the implementation method, using Figure 2 Please provide an explanation. Figure 2 This is a circuit diagram illustrating an example of the structure of the power supply circuit involved in the embodiment. The power supply circuit 101 in the embodiment is an LDO (Low Dropout) regulator.

[0042] The power supply circuit 101 includes a switching element Q1, resistors R1 and R2, an error amplifier AMP1, a constant voltage source VS1, and a control circuit CNT. The switching element Q1 is a P-type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor).

[0043] The first terminal of switching element Q1 is connected to terminal PVIN. The gate of switching element Q1 is connected to error amplifier AMP1. The second terminal of switching element Q1 is connected to terminal PVOUT.

[0044] The first end of resistor R1 is connected to terminal PVOUT. The second end of resistor R1 is connected to node N1.

[0045] The first end of resistor R2 is connected to node N1. The second end of resistor R2 is connected to terminal PGND.

[0046] With this structure of resistors R1 and R2, the voltage VN1 at node N1 becomes a voltage divider of the voltage VOUT based on the ratio of the resistance values ​​of resistors R1 and R2.

[0047] The first terminal of the constant voltage source VS1 is connected to the error amplifier AMP1. A voltage V2 is supplied to the error amplifier AMP1 from the first terminal of the constant voltage source VS1. The second terminal of the constant voltage source VS1 is connected to the terminal PGND.

[0048] The control circuit CNT has a first terminal, a second terminal, and a third terminal. The first terminal is connected to the terminal PVSHARE. The second terminal is connected to the error amplifier AMP1. The third terminal is connected to the terminal PGND. A signal ST based on the voltage VSHARE is supplied to the error amplifier AMP1 from the second terminal of the control circuit CNT. More specifically, when the voltage VSHARE is at a "H" level, the control circuit CNT supplies the "H" level signal ST to the error amplifier AMP1, enabling the power supply circuit 101. Conversely, when the voltage VSHARE is at a "L" level, the control circuit CNT supplies the "L" level signal ST to the error amplifier AMP1, disabling the power supply circuit 101.

[0049] Error amplifier AMP1 has a non-inverting input terminal (+), an inverting input terminal (-), an output terminal, a first control terminal, and a second control terminal. The non-inverting input terminal (+) is connected to node N1. The inverting input terminal (-) is connected to the first terminal of constant voltage source VS1. The output terminal is connected to the gate of switching element Q1. The first control terminal is connected to over-temperature detection circuit 102. The second control terminal is connected to the second terminal of control circuit CNT. Error amplifier AMP1 sets switching element Q1 to the on or off state based on the signal OVT from over-temperature detection circuit 102 and the signal ST from control circuit CNT.

[0050] More specifically, during the period when voltage VSHARE and signal ST are at the "H" level (when power supply circuit 101 is enabled), and signal OVT is at the "L" level, error amplifier AMP1 turns on switching element Q1, supplying a voltage VOUT that is higher than voltage VSS based on voltage VIN. During the period when power supply circuit 101 is enabled, and signal OVT is at the "H" level, error amplifier AMP1 turns off switching element Q1. Conversely, during the period when voltage VSHARE and signal ST are at the "L" level (when power supply circuit 101 is disabled), error amplifier AMP1 turns off switching element Q1 regardless of signal OVT.

[0051] With the structure described above, the power supply circuit 101 supplies voltage VOUT to the load 4 based on voltage VSHARE and signal OVT.

[0052] 1.1.2.2 Structure of the over-temperature detection circuit and test circuit

[0053] Regarding the structure of the over-temperature detection circuit 102 and the test circuit 103 involved in the implementation method, using Figure 3 Please provide an explanation. Figure 3 This is a circuit diagram illustrating an example of the structure of the over-temperature detection circuit and test circuit involved in the implementation method.

[0054] Explain the structure of the over-temperature detection circuit 102.

[0055] The over-temperature detection circuit 102 includes a constant current source I1, a diode D1, an operational amplifier AMP2, a resistor R3, and a constant voltage source VS2. Diode D1 is a PN junction diode.

[0056] A constant current source I1 supplies current to node N2. The constant current source I1 is driven, for example, by a voltage VIN. The current supplied by the constant current source I1 remains almost unchanged with respect to the temperature changes of the semiconductor device 1.

[0057] The anode of diode D1 is connected to node N2. The cathode of diode D1 is grounded. Diode D1, for example, has a negative temperature characteristic where the forward voltage decreases as the temperature increases.

[0058] The first terminal of the constant voltage source VS2 is connected to resistor R3. A voltage V3 is supplied from the first terminal of the constant voltage source VS2 to resistor R3. The second terminal of the constant voltage source VS2 is grounded. Voltage V3 is a voltage that remains almost unchanged relative to temperature changes in semiconductor device 1. Voltage V3 is higher than voltage VSS.

[0059] The first terminal of resistor R3 is connected to the first terminal of constant voltage source VS2. The second terminal of resistor R3 is connected to node N3. The resistance value of resistor R3 remains almost unchanged with temperature changes.

[0060] Operational amplifier AMP2 has a non-inverting input terminal (+), an inverting input terminal (-), and an output terminal. The non-inverting input terminal (+) is connected to node N3. The inverting input terminal (-) is connected to node N2. The output terminal is connected to the first control terminal of error amplifier AMP1 in power supply circuit 101. A signal OVT is supplied from the output terminal. Operational amplifier AMP2 compares the magnitudes of the voltage VN2 at node N2 (the voltage at the inverting input terminal (-)) and the voltage VN3 at node N3 (the voltage at the non-inverting input terminal (-)). When voltage VN3 is higher than voltage VN2, a "H" level signal OVT is supplied from the output terminal of operational amplifier AMP2. When voltage VN3 is lower than voltage VN2, a "L" level signal OVT is supplied from the output terminal of operational amplifier AMP2.

[0061] With the above structure, the over-temperature detection circuit 102 supplies the signal OVT based on the comparison result of voltages VN2 and VN3 to the power supply circuit 101.

[0062] Furthermore, the over-temperature detection circuit 102 is configured, as described below, such that when the over-temperature detection circuit 102 and the test circuit 103 are electrically insulated, the voltage VN2 and the voltage V3 are equal when the temperature of the semiconductor device 1 is the threshold temperature T1.

[0063] Explain the structure of test circuit 103.

[0064] The test circuit 103 includes switching elements Q2 and Q3, resistor R4, constant voltage sources VS3 and VS4, operational amplifier AMP3, and element E1. Switching elements Q2 and Q3 are, for example, N-type MOSFETs.

[0065] Component E1 is connected to terminal PVSHARE and node N4. Node N4 is, for example, wiring within test circuit 103. Component E1 may have a conductive state that electrically connects terminal PVSHARE and node N4, and an insulating state that electrically insulates terminal PVSHARE from node N4.

[0066] More specifically, element E1 is, for example, a wiring pattern of a conductor disposed on a semiconductor chip. This conductor, for example, comprises polysilicon. Element E1 in a conductive state forms a conductive path electrically connecting terminal PVSHARE and node N4. Element E1 is configured to be melted by irradiation with a laser. Thus, the conductive path between terminal PVSHARE and node N4 is physically severed. That is, the wiring pattern of element E1 in a conductive state is melted by laser irradiation, thereby irreversibly changing it into element E1 in an insulating state.

[0067] Furthermore, in some embodiments, element E1 irreversibly changes from a conductive state to an insulating state, for example. However, it is not limited to this. Element E1 can also reversibly change between a conductive state and an insulating state.

[0068] The first terminal of the constant voltage source VS3 is connected to the resistor R4. A voltage V4 is supplied from the first terminal of the constant voltage source VS3 to the resistor R4. The second terminal of the constant voltage source VS3 is grounded.

[0069] The first terminal of resistor R4 is connected to the first terminal of constant voltage source VS3. The second terminal of resistor R4 is connected to node N4. The resistance value of resistor R4 is set so that the voltage VN4 at node N4 is equal to the voltage VSHARE when component E1 is conducting.

[0070] The first terminal of the constant voltage source VS4 is connected to the operational amplifier AMP3. Voltage V5 is supplied to the operational amplifier AMP3 from the first terminal of the constant voltage source VS4. The second terminal of the constant voltage source VS4 is grounded. Voltage V5 is a higher voltage than voltage V4.

[0071] Operational amplifier AMP3 has a non-inverting input terminal (+), an inverting input terminal (-), and an output terminal. The inverting input terminal (-) is connected to the first terminal of a constant voltage source VS4. The non-inverting input terminal (+) is connected to node N4. The output terminal is connected to switching elements Q2 and Q3. Operational amplifier AMP3 compares the voltage V5 supplied from the constant voltage source VS4 (the voltage at the inverting input terminal (-)) with the voltage VN4 at node N4 (the voltage at the non-inverting input terminal (-)). When voltage VN4 is higher than voltage V5, a "H" level signal is supplied from the output terminal of operational amplifier AMP3. When voltage VN4 is lower than voltage V5, a "L" level signal is supplied from the output terminal of operational amplifier AMP3.

[0072] The first terminal of switching element Q2 is connected to node N2. The gate of switching element Q2 is connected to the output terminal of operational amplifier AMP3. The second terminal of switching element Q2 is grounded.

[0073] For the first terminal of switching element Q3, voltage VIN is supplied, for example, via terminal PVIN. The gate of switching element Q3 is connected to the output terminal of operational amplifier AMP3. The second terminal of switching element Q3 is connected to node N3.

[0074] With the structure described above, the test circuit 103 sets the switching elements Q2 and Q3 to either the on or off state based on the comparison result between the voltage VN4 at the non-inverting input terminal (+) and the voltage V5 at the inverting input terminal (-) of the operational amplifier AMP3. When switching element Q2 is on, voltage VN2 becomes voltage VSS. When switching element Q3 is on, voltage VN3 becomes voltage VIN. When switching elements Q2 and Q3 are off, the over-temperature detection circuit 102 and the test circuit 103 are electrically isolated. Therefore, voltage VN2 depends on the constant current source I1 and diode D1. Furthermore, voltage VN3 depends on the constant voltage source VS2 and resistor R3.

[0075] 1.2 Actions

[0076] The operation of the semiconductor device 1 according to the embodiments will be explained. The operation of the semiconductor device 1 according to the embodiments includes the test operation and the operation of the semiconductor device 1 after the test operation. In the following description, the operation of the semiconductor device 1 after the test operation will be referred to simply as the normal operation.

[0077] Hereinafter, a first operating example of a semiconductor device 1 using a component E1 in an insulating state during normal operation and a second operating example of a semiconductor device 1 using a component E1 in a conductive state during normal operation will be described.

[0078] Furthermore, in the first and second operation examples, the test operation is performed using a semiconductor device 1 that includes an element E1 in a conductive state.

[0079] 1.2.1 Example of the first action

[0080] Explain the first action example.

[0081] In the first operational example, after the test operation is performed and before normal operation, the state of element E1 changes from a conductive state to an insulating state. Then, normal operation is performed using the semiconductor device 1, which includes element E1 in the insulating state.

[0082] 1.2.1.1 Test Actions

[0083] Regarding test actions, use Figure 4 Please provide an explanation. Figure 4 This is a circuit diagram illustrating an example of the structure of an over-temperature detection circuit and a test circuit used to illustrate the test operation involved in the implementation method.

[0084] For example, the test is performed in an environment where the temperature of semiconductor device 1 is equal to room temperature. In this embodiment, the room temperature is below the threshold temperature T1. For example, the room temperature in this embodiment is approximately 25°C.

[0085] During the test, the test circuit 103 supplies voltages to voltages VN2 and VN3, causing the over-temperature detection circuit 102 to simulate that the temperature of the semiconductor device 1 is above the threshold temperature T1. If the over-temperature detection circuit 102 simulates that the temperature of the semiconductor device 1 is above the threshold temperature T1, it is determined that the over-temperature detection circuit 102 is operating normally. If the over-temperature detection circuit 102 detects that the temperature of the semiconductor device 1 is below the threshold temperature T1, it is determined that the over-temperature detection circuit 102 has malfunctioned.

[0086] During the test, component E1 is in a conductive state. Figure 4 In this diagram, a circle ("○") is added to element E1, which is in a conductive state. This connects node N4 to terminal PVSHARE.

[0087] During the test, voltage VIN is supplied to terminal PVIN.

[0088] The voltage VSHARE is supplied to the terminal PVSHARE. During the test operation, the voltage VSHARE is a "H" level voltage that is higher than voltages V1 and V5.

[0089] In test circuit 103, since component E1 is conductive, voltage VN4 becomes equal to voltage VSHARE. Consequently, the voltage VN4 at the non-inverting input terminal (+) of operational amplifier AMP3 becomes higher than the voltage V5 at the inverting input terminal (-) of operational amplifier AMP3. Therefore, through the operation of operational amplifier AMP3, switching components Q2 and Q3 become conductive. Figure 4 In this configuration, switching elements Q2 and Q3, which are in the ON state, are marked with an "○". Therefore, node N2 (the inverting input terminal (-) of operational amplifier AMP2) is grounded via switching element Q2. Additionally, for node N3 (the non-inverting input terminal (+) of operational amplifier AMP2), voltage VIN is supplied via switching element Q3.

[0090] Based on the above, when the over-temperature detection circuit 102 is operating normally, a "H" level signal OVT is supplied from the output terminal of the operational amplifier AMP2 to the first control terminal of the error amplifier AMP1. That is, the over-temperature detection circuit 102 simulates and detects that the temperature of the semiconductor device 1 is above the threshold temperature T1.

[0091] The power supply circuit 101 is enabled based on a voltage VSHARE of "H" level supplied via terminal PVSHARE. During the period when the power supply circuit 101 is enabled, the error amplifier AMP1 outputs a voltage, for example, equal to voltage VIN, from its output terminal based on a signal OVT of "H" level. This causes the switching element Q1 to become off. Consequently, voltage VOUT becomes equal to voltage VSS.

[0092] On the other hand, if the over-temperature detection circuit 102 malfunctions, there may be a situation where an "L" level signal OVT is supplied from the output terminal of the operational amplifier AMP2 to the first control terminal of the error amplifier AMP1. In this case, the over-temperature detection circuit 102 cannot simulate detecting that the temperature of the semiconductor device 1 is above the threshold temperature T1.

[0093] In the enabled power supply circuit 101, the error amplifier AMP1 sets the switching element Q1 to the on state based on the "L" level signal OVT supplied from the faulty over-temperature detection circuit 102. Consequently, a voltage VOUT, higher than the voltage VSS, is supplied from the second terminal of the switching element Q1 based on the voltage VIN.

[0094] Based on the above, during the test, if the voltage VOUT and voltage VSS are equal, the over-temperature detection circuit 102 is determined to be operating normally. Conversely, during the test, if the voltage VOUT is, for example, higher than the voltage VSS, the over-temperature detection circuit 102 is determined to be malfunctioning.

[0095] The test is now complete after completing the above steps.

[0096] 1.2.1.2 Common Actions

[0097] Regarding normal actions, use Figure 5 and Figure 6 Please provide an explanation. Figure 5 This is a circuit diagram illustrating an example of the structure of an over-temperature detection circuit and a test circuit for normal operation in the first operating example of the embodiment. Figure 6 This is a graph illustrating an example of the changes in voltages VN2 and VN3 relative to the temperature of semiconductor device 1 and the signal OVT supplied from over-temperature detection circuit 102 during normal operation in the first operating example of the embodiment.

[0098] In the case of a semiconductor device that is determined to be operating normally during testing, as described above, before normal operation, the state of element E1 is changed from a conductive state to an insulating state. More specifically, element E1 is melted by irradiating it with a laser on the semiconductor chip. Furthermore, in Figure 5 In the diagram, an "×" mark is added to component E1 which is in an insulating state.

[0099] When component E1 is blown, voltage VN4 in test circuit 103 becomes equal to voltage V4. Therefore, operational amplifier AMP3 sets switching elements Q2 and Q3 to the off state regardless of voltage VSHARE. Figure 5 In the diagram, an "×" mark is added to the switching elements Q2 and Q3 that are in the off state.

[0100] With switching element Q2 in the off state, the voltage VN2 in the over-temperature detection circuit 102 is determined based on diode D1 and constant current source I1. Therefore, as... Figure 6 As shown, voltage VN2 decreases as the temperature of semiconductor device 1 increases, due to the negative temperature characteristic of diode D1. Furthermore, when switching element Q3 is in the off state, voltage VN3 becomes equal to voltage V3.

[0101] First, let’s explain the operation of the power supply circuit 101 when it is set to the enabled state.

[0102] When the power supply circuit 101 is enabled, the PVSHARE terminal is supplied with a voltage of "H" level.

[0103] like Figure 6As shown, when the temperature of semiconductor device 1 is below the threshold temperature T1, voltage VN2 is higher than voltage VN3. Therefore, signal OVT is at the "L" level. In the power supply circuit 101 in the enabled state, when signal OVT is at the "L" level, error amplifier AMP1 supplies voltage to the gate of switching element Q1, such that the voltage VN1 at the non-inverting input terminal (+) of error amplifier AMP1 is equal to V2 at the inverting input terminal (-) of error amplifier AMP1. That is, error amplifier AMP1 supplies voltage to the gate of switching element Q1, such that voltage VOUT is equal to the target voltage VTARG. More specifically, the voltage supplied from the output terminal of error amplifier AMP1 increases as the voltage obtained by subtracting voltage V2 from voltage VN1 increases. As a result, as the voltage obtained by subtracting voltage V2 from voltage VN1 increases, the on-resistance of switching element Q1 increases. Therefore, the error amplifier AMP1 is configured to output a higher voltage from its output terminal when the voltage VOUT is higher than the target voltage VTARG, compared to the output voltage when VOUT is equal to the target voltage VTARG. Conversely, the error amplifier AMP1 is configured to output a lower voltage from its output terminal when the voltage VOUT is lower than the target voltage VTARG, compared to the output voltage when VOUT is equal to the target voltage VTARG. By supplying a voltage to the gate of the switching element Q1 as described above, the error amplifier AMP1 supplies a voltage VOUT equal to the target voltage VTARG to the load 4.

[0104] Furthermore, when the temperature of semiconductor device 1 is above the threshold temperature T1, voltage VN2 is below voltage VN3. Therefore, signal OVT is at level "H". In the power supply circuit 101 in the enabled state, when signal OVT is at level "H", error amplifier AMP1 sets switching element Q1 to the off state in the same way as the test operation. Therefore, the supply of voltage VOUT based on voltage VIN is stopped. That is, voltage VOUT becomes equal to voltage VSS.

[0105] Next, the operation of the power supply circuit 101 when it is set to a disabled state will be explained.

[0106] When the power supply circuit 101 is disabled, the PVSHARE terminal is supplied with an "L" level voltage. In the disabled power supply circuit 101, the error amplifier AMP1, independent of the signal OVT, sets the switching element Q1 to the off state, just as it would during a test operation. Therefore, the supply of voltage VOUT based on voltage VIN is stopped, independent of the temperature of the semiconductor device 1.

[0107] Perform the usual actions as described above.

[0108] 1.2.2 Example of the second action

[0109] Next, regarding the operation of semiconductor device 1 in the second action example, using... Figure 7 Please provide an explanation. Figure 7 This is a circuit diagram illustrating an example of the structure of the over-temperature detection circuit and the test circuit for the normal operation of the second operating example in the embodiment. The test operation in the second operating example is the same as the test operation in the first operating example, so its description is omitted. Hereinafter, regarding the normal operation in the second operating example, the differences from the normal operation in the first operating example will be mainly explained. Furthermore, in the second operating example, the voltage V5 is higher than the voltage V1.

[0110] The normal operation in the second example is performed using a semiconductor device including element E1 in a conductive state, as described above. That is, after the test operation is performed but before the normal operation is performed, element E1 does not melt.

[0111] A voltage VSHARE is applied to terminal PVSHARE. In the normal operation of the second operating example, voltage VSHARE is above voltage V1 and less than voltage V5. Therefore, in test circuit 103, voltage VN4 is less than voltage V5. Consequently, through the operation of operational amplifier AMP3, as... Figure 7 As shown, switching elements Q2 and Q3 are always in the off state.

[0112] The operation of the power supply circuit 101 and the over-temperature detection circuit 102 in the normal operation of the second operation example is substantially the same as that of the power supply circuit 101 and the over-temperature detection circuit 102 in the normal operation of the first operation example, so their description is omitted.

[0113] Through the usual operation described above, semiconductor device 1 can also supply voltage VOUT to load 4 based on the temperature of semiconductor device 1.

[0114] 1.3 Effects of the Implementation Method

[0115] According to the semiconductor device 1 of the embodiment, it is possible to suppress the limitation of the voltage used to control the power supply and to suppress the increase in chip size.

[0116] The semiconductor device 1 of this embodiment includes terminals PVSHARE, PVIN, and PVOUT, a power supply circuit 101, an over-temperature detection circuit 102, and a test circuit 103. The power supply circuit 101 is driven based on a voltage VSHARE supplied via the terminal PVSHARE. The over-temperature detection circuit 102 determines whether the temperature of the semiconductor device 1 has risen excessively. In the test circuit 103, an element E1 is provided between the terminal PVSHARE and node N4. The element E1 is a wiring pattern of a conductor that can have both conductive and insulating states. The test circuit 103 is configured such that if the temperature of the semiconductor device 1 rises excessively when the voltage VN4 at node N4 is above voltage V5, the over-temperature detection circuit 102 will make a simulated determination. When the over-temperature detection circuit 102 determines that the temperature of the semiconductor device 1 has risen excessively, the power supply circuit 101 electrically insulates the terminals PVIN and PVOUT.

[0117] In the semiconductor device 1 of the embodiment, the power supply circuit 101 and the test circuit 103 share a common terminal PVSHARE. This suppresses the increase in the chip size of the semiconductor device 1. Furthermore, in the first operating example of the embodiment, after the test operation is performed, the component E1 is melted by laser irradiation. This electrically insulates the terminal PVSHARE from the node N4. Therefore, in normal operation, the structure of the test circuit 103 can suppress the limitation of the voltage VSHARE height. Accordingly, the semiconductor device 1 according to the embodiment can suppress the limitation of the voltage VSHARE height supplied in normal operation and can suppress the increase in chip size.

[0118] To elaborate further, when the terminals supplied with voltage for normal operation differ from the terminals supplied with voltage for testing, the number of pads on the semiconductor chip increases. This results in an increase in the area of ​​the semiconductor chip. To suppress the increase in the number of pads on the semiconductor chip, it is desirable to share both the terminals supplied with voltage for normal operation and the terminals supplied with voltage for testing.

[0119] However, when both the terminal supplied with voltage for normal operation and the terminal supplied with voltage for test operation are shared, there is a limitation on the voltage level supplied to the terminal during normal operation. More specifically, without a structure capable of electrically isolating the test circuit from the aforementioned terminals, the voltage for performing normal operation is also supplied to the test circuit. Therefore, in order to suppress the execution of test operation during normal operation, the range of voltage supplied to the aforementioned terminals during test operation and the range of voltage supplied to the aforementioned terminals during normal operation are set to not overlap with each other.

[0120] According to an embodiment, the test circuit 103 includes an element E1 between the terminal PVSHARE and the node N4. In a first operational example of the embodiment, after the test operation and before the normal operation, the element E1 melts, thereby electrically isolating the test circuit 103 from the over-temperature detection circuit 102. Therefore, even if the terminals supplied with the voltage for performing the normal operation and the terminals supplied with the voltage for performing the test operation are shared, the execution of the test operation during normal operation can be suppressed. Thus, the height of the voltage VSHARE during normal operation can be limited, and the increase in chip size can be suppressed.

[0121] Furthermore, according to the semiconductor device 1 of the embodiment, even if element E1 does not electrically insulate the terminal PVSHARE from the node N4 as in the second operation example of the embodiment, it can still perform normal operation.

[0122] 2. Variations

[0123] Next, the semiconductor device involved in the modified example will be described. Hereinafter, descriptions of structures and operations equivalent to those in the embodiment will be omitted, and descriptions of structures and operations different from those in the embodiment will be mainly provided.

[0124] 2.1 First Variation Example

[0125] In the above embodiment, an example of element E1 being melted by irradiation with a laser is shown, but it is not limited to this. Element E1 may also be configured to melt based on the current flowing through element E1. Hereinafter, the structure and operation of the semiconductor device 1 according to the first modified example will be mainly described in terms of the differences from the embodiment.

[0126] Regarding the structure of the semiconductor device 1 involved in the first modified example, using Figure 8 Please provide an explanation. Figure 8 This is a circuit diagram illustrating one example of the structure of the over-temperature detection circuit and test circuit involved in the first modified example.

[0127] The test circuit 103 of the first variation includes switching elements Q2, Q3, Q4, Q5, and Q6, resistor R4, constant voltage sources VS3 and VS4, operational amplifier AMP3, and element E1. Switching elements Q4, Q5, and Q6 are, for example, N-type MOSFETs. The structures of switching elements Q2 and Q3, resistor R4, constant voltage sources VS3 and VS4, and operational amplifier AMP3 are identical to those in the embodiment.

[0128] The first terminal of switching element Q4 is connected to terminal PVSHARE. The second terminal of switching element Q4 is connected to node N5. The gate of switching element Q4 is supplied with a signal S. Signal S is a signal of "H" level or "L" level. The turn-on voltage of switching element Q4 is a voltage higher than the "L" level signal S and lower than the "H" level signal S.

[0129] The first terminal of switching element Q5 is connected to terminal PVIN. The second terminal of switching element Q5 is connected to node N5. The gate of switching element Q5 is supplied with signal / S. Signal / S is the inverted signal of signal S. The turn-on voltage of switching element Q5 is, for example, the same as the turn-on voltage of switching element Q4.

[0130] The first terminal of switching element Q6 is grounded. The second terminal of switching element Q6 is connected to node N4. The gate of switching element Q6 is supplied with a signal / S. The turn-on voltage of switching element Q6 is, for example, the same as the turn-on voltage of switching element Q4 and the turn-on voltage of switching element Q5.

[0131] Component E1 is connected to nodes N4 and N5. Component E1 may have a conductive state that electrically connects nodes N4 and N5, and an insulating state that electrically isolates nodes N4 and N5. The wiring pattern of component E1 is configured to fuse based on the current flowing through the wiring pattern. More specifically, component E1 is configured, for example, to fuse when the current flowing through component E1 exceeds a first current value during a predetermined first period. Here, the first current value is, for example, set to be greater than the current flowing through the wiring pattern during the test operation. With such a structure, component E1 is configured to irreversibly change from a conductive state to an insulating state by physically cutting the wiring pattern between nodes N4 and N5.

[0132] The structure of the power supply circuit 101 and the over-temperature detection circuit 102 in the first modification is the same as that in the embodiment.

[0133] Explain the operation of the semiconductor device 1 involved in the first modified example.

[0134] In the test operation of the first operation example of the first modification, signal S is set to the "H" level. Therefore, switching element Q4 becomes the on state. Additionally, signal / S is set to the "L" level. Therefore, switching elements Q5 and Q6 become the off state. The test operation of the first operation example of the first modification is substantially the same as the test operation of the first operation example of the embodiment, except for the operation of switching elements Q4, Q5, and Q6.

[0135] In the first operation example of the first modification, between the test operation and the normal operation, signal S is set to the "L" level. As a result, switching element Q4 becomes the off state. Additionally, signal / S is set to the "H" level. As a result, switching elements Q5 and Q6 become the on state. Furthermore, in element E1, a current exceeding a first current value flows through terminal PVIN during the first period. As a result, element E1 melts.

[0136] Furthermore, element E1 may melt within a semiconductor chip in which the semiconductor device 1 is not sealed by an insulator, but is not limited thereto. Element E1 may also melt within a package in which the semiconductor device 1 is sealed by an insulator.

[0137] In the normal operation of the first operating example of the first modification, signal S is set to the "H" level. Additionally, signal / S is set to the "L" level. The normal operation of the first operating example of the first modification is substantially the same as the normal operation of the first operating example of the embodiment, except for the operation of switching elements Q4, Q5, and Q6.

[0138] The test action of the second action example of the first variation is the same as the test action of the first action example of the first variation.

[0139] In the normal operation of the second operating example of the first modification, the supplied signals S and / S are the same as those supplied in the normal operation of the first operating example of the first modification. The normal operation of the second operating example of the first modification is substantially the same as the normal operation of the second operating example of the embodiment, except for the operation of switching elements Q4, Q5, and Q6.

[0140] In the first variation, it also achieves the same effect as the implementation method.

[0141] Furthermore, in the first variation described above, an example is shown where element E1 is blown by current flowing through element E1 via terminal PVIN between the test operation and normal operation of the first operation example of the first variation. However, this is not a limitation. Element E1 may also be configured to be blown by current flowing through element E1 via terminal PVSHARE. In this case, the gate of switching element Q6 is supplied with signal S, for example.

[0142] 2.2 Second Variation

[0143] In the above embodiment, the test circuit 103 is shown to include switching elements Q2 and Q3, but it is not limited thereto. The test circuit 103 may also include only one of the switching elements Q2 and Q3. Hereinafter, regarding the structure and operation of the semiconductor device according to the second modification, the differences between the structure and operation of the semiconductor device according to the embodiment will be mainly explained.

[0144] Regarding the structure of the semiconductor device 1 involved in the second modification, using Figure 9 Please provide an explanation. Figure 9 This is a circuit diagram illustrating one example of the structure of the over-temperature detection circuit and test circuit involved in the second variation.

[0145] Figure 9 The test circuit 103 shown includes a switching element Q3, a resistor R4, constant voltage sources VS3 and VS4, an operational amplifier AMP3, and a component E1. That is, the test circuit 103 only includes switching element Q3 from the switching elements Q2 and Q3 in the embodiment. The structures of the switching element Q3, resistor R4, constant voltage sources VS3 and VS4, operational amplifier AMP3, and component E1 are identical to the structures of the switching element Q3, resistor R4, constant voltage sources VS3 and VS4, operational amplifier AMP3, and component E1 in the test circuit 103 of the embodiment.

[0146] The structure of the power supply circuit 101 and the over-temperature detection circuit 102 in the second modification is the same as that in the embodiment.

[0147] In addition, Figure 9 The example shown illustrates a test circuit 103 including a switching element Q3, but it is not limited to this. In a second variation, the test circuit 103 may also include only the switching element Q2 from Q2 and Q3. In this case, the test circuit 103 includes the switching element Q2, resistor R4, constant voltage sources VS3 and VS4, operational amplifier AMP3, and element E1. The structure of the switching element Q2, resistor R4, constant voltage sources VS3 and VS4, operational amplifier AMP3, and element E1 is identical to the structure of the switching element Q2, resistor R4, constant voltage sources VS3 and VS4, operational amplifier AMP3, and element E1 in the test circuit 103 of the embodiment.

[0148] The operation of semiconductor device 1 in the second variation is substantially the same as that of semiconductor device 1 in the embodiment, therefore this description is omitted.

[0149] The second variation also achieves the same effect as the implementation method.

[0150] 2.3 Third variation example

[0151] In the above embodiments, the first modification, and the second modification, a fused wiring pattern was shown as element E1, but the invention is not limited to this. A switching element may also be used as element E1. Hereinafter, regarding the structure and operation of the semiconductor device according to the third modification, the differences from the structure and operation of the semiconductor device 1 according to the embodiments will be mainly explained.

[0152] Regarding the structure of the semiconductor device 1 involved in the third variation, using Figure 10 Please provide an explanation. Figure 10 This is a circuit diagram illustrating one example of the structure of the over-temperature detection circuit and test circuit involved in the third variation.

[0153] The test circuit 103 in the third variation includes switching elements Q2, Q3, and Q7, resistors R4 and R5, constant voltage sources VS3 and VS4, operational amplifier AMP3, and anti-fuse element E2. Switching element Q7 is, for example, a P-type MOSFET. The structures of switching elements Q2 and Q3, resistors R4, constant voltage sources VS3 and VS4, and operational amplifier AMP3 are identical to those of the switching elements Q2 and Q3, resistors R4, constant voltage sources VS3 and VS4, and operational amplifier AMP3 in the test circuit 103 of the embodiment.

[0154] Antifuse element E2 includes, for example, a first terminal connected to terminal PVIN and a second terminal connected to node N6. Antifuse element E2 changes from an insulating state, where the first and second terminals are electrically insulated, to a conductive state, where the first and second terminals are electrically connected. More specifically, the insulating antifuse element E2 includes an insulating film that electrically insulates the first and second terminals. Antifuse element E2 is configured such that an increase in voltage between the first and second terminals causes the insulating film to break, thereby irreversibly changing from an insulating state to a conductive state. The insulating film is broken, for example, when a voltage above a predetermined height is supplied to the first terminal of antifuse element E2. This voltage is higher than the voltage VIN during normal operation.

[0155] The first terminal of resistor R5 is connected to node N6. The second terminal of resistor R5 is grounded.

[0156] The first terminal of switching element Q7 is connected to PVSHARE. The gate of switching element Q7 is connected to node N6. The second terminal of switching element Q7 is connected to node N4. The conducting state of switching element Q7 is a conductive state in which terminal PVSHARE and node N4 are electrically connected. The cutting state of switching element Q7 is an insulating state in which terminal PVSHARE and node N4 are electrically insulated. That is, switching element Q7 is a device whose state can reversibly change between a conductive state and an insulating state. The on-state voltage of switching element Q7 is, for example, a voltage lower than the voltage VIN during normal operation.

[0157] With the structure described above, when the insulating film of the antifuse element E2 is intact, a voltage VSS is supplied to the gate of the switching element Q7. Thus, the switching element Q7 is in the on state. Conversely, when the insulating film of the antifuse element E2 is damaged, a voltage VIN is supplied to the gate of the switching element Q7 via the antifuse element E2. Thus, when the gate of the switching element Q7 is supplied with the normally operating voltage VIN, the switching element Q7 is in the off state.

[0158] The structure of the power supply circuit 101 and the over-temperature detection circuit 102 in the third variation is the same as that in the embodiment.

[0159] Explain the operation of the semiconductor device 1 involved in the third variation.

[0160] In the test operation of the first operating example of the third modification, the voltage VIN is set to the height at which the insulating film of the antifuse element E2 is not damaged. Therefore, the switching element Q7 is set to the on state. The test operation of the first operating example of the third modification is substantially the same as the test operation of the first operating example of the embodiment, except that the switching element Q7 is in the on state.

[0161] In the first operating example of the third variation, between the test operation and the normal operation, the insulating film of the antifuse element E2 is broken by the supply of voltage VIN via the terminal PVIN. As a result, voltage VIN is supplied to the gate of the switching element Q7 via the antifuse element E2.

[0162] Furthermore, the insulating film of the antifuse element E2 may be damaged, for example, in a semiconductor chip in which the semiconductor device 1 is not sealed by an insulator, but is not limited thereto. The insulating film of the antifuse element E2 may also be damaged in a package in which the semiconductor device 1 is sealed by an insulator.

[0163] In the normal operation of the first operating example of the third variation, the switching element Q7 is turned off by supplying a voltage VIN to the gate of the switching element Q7. The normal operation is substantially the same as the normal operation of the first operating example of the embodiment, except that the switching element Q7 is in the off state.

[0164] The test action of the second action example of the third variation is the same as the test action of the first action example of the third variation.

[0165] The normal operation of the second operation example of the third variation is substantially the same as that of the second operation example of the embodiment, except that the switching element Q7 is in the on state.

[0166] The third variation achieves the same effect as the implementation method, the first variation, and the second variation.

[0167] 2.4 Fourth Variation Example

[0168] In the third modification, the switching element Q7 is shown to be set to the on or off state by an insulating film-breaking type fuse element, but it is not limited to this. The state of the switching element Q7 can also be configured to be set to the on or off state by a non-volatile memory. Hereinafter, regarding the structure and operation of the semiconductor device according to the fourth modification, the differences from the structure and operation of the semiconductor device 1 according to the third modification will be mainly explained.

[0169] Regarding the structure of the semiconductor device 1 involved in the fourth variation, using Figure 11 Please provide an explanation. Figure 11 This is a circuit diagram illustrating one example of the structure of the over-temperature detection circuit and test circuit involved in the fourth variation.

[0170] The test circuit 103 of the fourth modification includes switching elements Q2, Q3, and Q7, resistor R4, constant voltage sources VS3 and VS4, operational amplifier AMP3, and storage circuit M. The structures of the switching elements Q2, Q3, and Q7, resistor R4, constant voltage sources VS3 and VS4, and operational amplifier AMP3 in the fourth modification are identical to those in the test circuit 103 of the third modification.

[0171] In the fourth variation, the storage circuit M has a first storage cell. The first storage cell is, for example, an EEPROM. TM Elements included in electrically erasable programmable read-only memory, OTP (One-Time Programmable) memory, and flash memory. The first memory cell stores "0" data (in... Figure 11 In the text, "0" is used to represent the number of digits, and "1" is used to represent the number of digits. Figure 11 In the diagram, "1" represents the value. The storage circuit M is configured, for example, to rewrite the data in the first storage cell via internal or external circuitry of the semiconductor device 1. The storage circuit M is configured to supply a voltage Von to the gate of the switching element Q7 when the first storage cell stores "0" data. Figure 11 In this context, "0" is represented by "Von". Voltage Von is the voltage below the turn-on voltage of switching element Q7. Furthermore, the storage circuit M is configured to supply a voltage Voff to the gate of switching element Q7 when the first storage element stores "1" data. Figure 11(In this context, it is represented by "1": Voff). The voltage Voff is a voltage higher than the turn-on voltage of the switching element Q7.

[0172] Explain the operation of the semiconductor device 1 involved in the fourth variation.

[0173] In the test operation of the first operation example of the fourth variation, the first storage element stores "0" data. Therefore, a voltage Von is supplied to the gate of the switching element Q7. Thus, the switching element Q7 is set to the on state. The test operation of the first operation example of the fourth variation is substantially the same as the test operation of the first operation example of the third variation.

[0174] In the first operating example of the fourth variation, after the test operation and before the normal operation, the data in the first storage element is overwritten from "0" to "1". As a result, a voltage Voff is supplied to the gate of the switching element Q7. Consequently, during normal operation, the switching element Q7 is in the off state.

[0175] The normal operation of the first action example of the fourth variation is the same as that of the first action example of the third variation, except that the first storage element stores the second data.

[0176] The test action of the second action example of the fourth variation is the same as the test action of the first action example of the fourth variation.

[0177] The normal operation of the second action example of the fourth variation is the same as the test operation of the second action example of the third variation, except that the first storage element stores "0" data.

[0178] The fourth variation achieves the same effect as the implementation method and the first to third variations.

[0179] 2.5 Fifth Variation

[0180] In the above-described embodiments and the first to fourth modifications, it is shown that the power supply circuit 101 is enabled based on a voltage VSHARE at an "H" level and disabled based on a voltage VSHARE at an "L" level, but this is not a limitation. The power supply circuit 101 may also be enabled based on a voltage VSHARE at an "L" level and disabled based on a voltage VSHARE at an "H" level. Hereinafter, regarding the structure and operation of the semiconductor device according to the fifth modification, the differences from the structure and operation of the semiconductor device according to the embodiments will be mainly explained.

[0181] 2.5.1 Structure

[0182] The power supply circuit 101 involved in the fifth modification includes a switching element Q1, resistors R1 and R2, an error amplifier AMP1, a constant voltage source VS1, and a control circuit CNT. The structure of the switching element Q1, resistors R1 and R2, error amplifier AMP1, and constant voltage source VS1 is the same as that of the switching element Q1, resistors R1 and R2, error amplifier AMP1, and constant voltage source VS1 involved in the embodiment.

[0183] In the fifth variation, during the period when the voltage VSHARE is at the "L" level (when the voltage VSHARE is less than the voltage V1), the control circuit CNT supplies the error amplifier AMP1 with the "H" level signal ST, thus enabling the power supply circuit 101. Conversely, during the period when the voltage VSHARE is at the "H" level, the control circuit CNT supplies the error amplifier AMP1 with the "L" level signal ST, thus disabling the power supply circuit 101.

[0184] Regarding the structure of the over-temperature detection circuit 102 and the test circuit 103 involved in the fifth modification, using Figure 12 Please provide an explanation. Figure 12 This is a circuit diagram illustrating one example of the structure of the over-temperature detection circuit and test circuit involved in the fifth variation.

[0185] The test circuit 103 includes switching elements Q2 and Q3, resistor R4, constant voltage sources VS3 and VS4, operational amplifier AMP3, and element E1. The structures of switching elements Q2 and Q3, resistor R4, constant voltage sources VS3 and VS4, and element E1 are the same as those in the embodiment.

[0186] In the fifth variation, the inverting input terminal (-) of operational amplifier AMP3 is connected to node N4. The non-inverting input terminal (+) of operational amplifier AMP3 is connected to the first terminal of constant voltage source VS4.

[0187] Furthermore, in the fifth variation, the voltage V4 supplied from the constant voltage source VS3 is higher than the voltage V5 supplied from the constant voltage source VS4.

[0188] The structure of the over-temperature detection circuit 102 in the fifth variation is the same as that of the over-temperature detection circuit 102 in the embodiment.

[0189] 2.5.2 Actions

[0190] Regarding the first and second action examples of the fifth variation, the differences from the first and second action examples of the implementation method will be explained in detail.

[0191] 2.5.2.1 Example of the first action

[0192] Regarding the test action and normal action of the first action example in the fifth variation, the differences between the test action and normal action of the first action example in the implementation are explained.

[0193] During the test, voltage VSHARE is lower than voltages V1 and V5. Therefore, in the test circuit 103, through the operation of operational amplifier AMP3, switching elements Q2 and Q3 become conductive.

[0194] In addition, the power supply circuit 101 is set to the enabled state based on the voltage VSHARE at the "L" level.

[0195] The other actions in the test actions of the first action example of the fifth variation are substantially the same as the test actions of the first action example of the implementation, so their description is omitted.

[0196] In normal operation, when the power supply circuit 101 is enabled, the terminal PVSHARE is supplied with an "L" level voltage VSHARE.

[0197] In addition, when the power supply circuit 101 is disabled, the terminal PVSHARE is supplied with a voltage VSHARE at the "H" level.

[0198] The other actions in the normal operation of the first action example of the fifth variation are substantially the same as the actions in the normal operation of the first action example of the embodiment, so their description is omitted.

[0199] 2.5.2.2 Example of the second action

[0200] Regarding the test operation and normal operation of the second operating example in the fifth variation, the differences between the test operation and normal operation and those of the second operating example in the embodiment will be explained. Furthermore, in the second operating example, voltage V1 is a higher voltage than voltage V5.

[0201] The test action in the second action example of the fifth variation is the same as the test action in the first action example of the fifth variation, so its description is omitted.

[0202] In normal operation, the element E1 is in a conductive state, just as in the normal operation of the second operation example of the embodiment.

[0203] The voltage VSHARE supplied to terminal PVSHARE is higher than voltage V5 but lower than voltage V1. Therefore, the voltage VN4 at the non-inverting input terminal (+) of operational amplifier AMP3 is higher than the voltage V5 at the inverting input terminal (-) of operational amplifier AMP3. Consequently, through the operation of operational amplifier AMP3, switching elements Q2 and Q3 are turned off.

[0204] The other actions in the normal operation of the second action example of the fifth variation are substantially the same as the actions in the normal operation of the second action example of the embodiment, so their description is omitted.

[0205] The fifth variation also achieves the same effect as the implementation method and the first to fourth variations.

[0206] 2.6 Sixth Variation

[0207] In the above-described embodiments and the first to fifth modifications, the power supply circuit 101 is shown as an LDO regulator, but it is not limited to this. The power supply circuit 101 can also be a load switch. Hereinafter, regarding the structure and operation of the semiconductor device involved in the sixth modification, the differences from the structure and operation of the semiconductor device involved in the embodiments will be mainly explained.

[0208] Regarding the structure of the power supply circuit 101, the following is used... Figure 13 Please provide an explanation. Figure 13 This is a circuit diagram illustrating one example of the structure of the power supply circuit involved in the sixth variation.

[0209] The power supply circuit 101 includes a switching element Q1, a driver DRV, and a control circuit CNT. As described above, the power supply circuit 101 is a load switch.

[0210] The gate of the switching element Q1 is connected to the driver DRV.

[0211] The second terminal of the control circuit CNT is connected to the driver DRV. A signal ST based on the voltage VSHARE is supplied to the driver DRV from the second terminal.

[0212] The driver DRV has a first control terminal, a second control terminal, and an output terminal. The first control terminal is connected to the over-temperature detection circuit 102. The second control terminal is connected to the second terminal of the control circuit CNT. The output terminal is connected to the gate of the switching element Q1. The driver DRV sets the switching element Q1 to the on or off state based on the signal OVT from the over-temperature detection circuit 102 and the signal ST from the control circuit CNT.

[0213] More specifically, during the period when voltage VSHARE and signal ST are at the "H" level (when power supply circuit 101 is enabled), and signal OVT is at the "L" level, driver DRV turns on switching element Q1, supplying a voltage VOUT that is higher than voltage VSS based on voltage VIN. During the period when power supply circuit 101 is enabled, and signal OVT is at the "H" level, driver DRV turns off switching element Q1. Conversely, during the period when voltage VSHARE and signal ST are at the "L" level (when power supply circuit 101 is disabled), driver DRV turns off switching element Q1 independently of signal OVT.

[0214] With the structure described above, the power supply circuit 101 supplies voltage VOUT to the load 4 based on voltage VSHARE and signal OVT.

[0215] The operation of the semiconductor device 1 in the sixth variation is substantially the same as the operation of the semiconductor device in the embodiment, therefore its description is omitted.

[0216] The sixth variation also achieves the same effect as the implementation method and the first to fifth variations.

[0217] 2.7 Seventh Variation

[0218] In the above-described embodiments and the first to sixth modifications, the power supply circuit 101 is shown as an LDO regulator and a load switch, but it is not limited to this. The power supply circuit 101 may also be a structure included in a DC-DC converter. Hereinafter, regarding the structure and operation of the semiconductor device according to the seventh modification, the differences from the structure and operation of the semiconductor device according to the embodiments will be mainly explained.

[0219] 2.7.1 Power Supply System

[0220] Regarding the structure of the power supply system including the semiconductor device involved in the implementation, using Figure 14 Please provide an explanation. Figure 14 This is a block diagram illustrating an example of the structure of a power supply system including the semiconductor device involved in the seventh modification. The power supply system includes a semiconductor device 1, a power source 2, a drive circuit 3, a load 4, and a filter circuit 5.

[0221] Semiconductor device 1 includes terminals PGND, PVIN, PVSHARE, PVSW, and PFB.

[0222] Terminal PVSW is connected to filter circuit 5. Voltage VSW is supplied to filter circuit 5 from terminal PVSW. Voltage VSW is used to generate voltage VOUT. Filter circuit 5 smooths the voltage VSW supplied from semiconductor device 1. Filter circuit 5 supplies the smoothed voltage VOUT to load 4.

[0223] Terminal PFB is connected to filter circuit 5. Voltage VOUT is supplied to terminal PFB from filter circuit 5.

[0224] 2.7.2 Semiconductor Devices

[0225] Regarding the structure of the semiconductor device 1 involved in the seventh variation, the following will be used... Figure 14 Please provide an explanation.

[0226] Power supply circuit 101 is connected to over-temperature detection circuit 102 and terminals PVIN, PVSHARE, PVSW, PFB, and PGND. The over-temperature detection circuit 102 supplies a signal OVT to power supply circuit 101. For power supply circuit 101, a voltage VSHARE is supplied via terminal PVSHARE. Power supply circuit 101 is enabled when voltage VSHARE is at a "H" level. An "H" level voltage VSHARE is, for example, voltage V1 or higher. For power supply circuit 101, a voltage VOUT is supplied via terminal PFB. When enabled, power supply circuit 101 supplies a voltage VSW based on voltage VIN to filter circuit 5 based on the signal OVT from over-temperature detection circuit 102 and the voltage VOUT from filter circuit 5. Additionally, power supply circuit 101 is disabled when voltage VSHARE is at a "L" level. The power supply circuit 101, which is in a disabled state, stops supplying voltage VSW based on voltage VIN, regardless of the signal OVT from the over-temperature detection circuit 102 and the voltage VOUT from the filter circuit 5.

[0227] Furthermore, the structures of the over-temperature detection circuit 102 and the test circuit 103 are identical to those of the over-temperature detection circuit 102 and the test circuit 103 described in the embodiment. Hereinafter, the structure of the power supply circuit 101 will be primarily described.

[0228] 2.7.3 Power Supply Circuit

[0229] Regarding the structure of the power supply circuit 101 and the filter circuit 5, the following is used... Figure 15 Please provide an explanation. Figure 15 This is a circuit diagram illustrating one example of the structure of the power supply circuit and filter circuit involved in the seventh modification. In the seventh modification, the power supply circuit 101 and the filter circuit 5 constitute a DC-DC converter.

[0230] The power supply circuit 101 includes switching elements Q1 and Q8, a driver DRV, and a control circuit CNT. The switching element Q8 is an N-type MOSFET.

[0231] The gate of switching element Q1 is connected to the driver DRV. The second terminal of switching element Q1 is connected to the terminal PVSW.

[0232] The first terminal of switching element Q8 is connected to terminal PVSW. The gate of switching element Q8 is connected to driver DRV. The second terminal of switching element Q8 is connected to terminal PGND.

[0233] The second terminal of the control circuit CNT is connected to the driver DRV. A signal ST based on the voltage VSHARE is supplied to the driver DRV from the second terminal.

[0234] The driver DRV has a first control terminal, a second control terminal, a third control terminal, a first output terminal, and a second output terminal. The first control terminal is connected to the over-temperature detection circuit 102. The second control terminal is connected to the second terminal of the control circuit CNT. The third control terminal is connected to the terminal PFB. The first output terminal is connected to the gate of the switching element Q1. The second output terminal is connected to the gate of the switching element Q8. The driver DRV sets the switching elements Q1 and Q8 to the on or off state, respectively, based on the signal OVT from the over-temperature detection circuit 102, the signal ST from the control circuit CNT, and the voltage VOUT.

[0235] More specifically, during the period when the power supply circuit 101 is enabled, with the signal OVT at the "L" level, the driver DRV sets switching element Q1 to the on state and switching element Q8 to the off state during the second period. Therefore, during the second period, the voltage VSW becomes a voltage based on voltage VIN. During the third period, the driver DRV sets switching element Q1 to the off state and switching element Q8 to the on state. Therefore, terminal PVSW is grounded. The driver DRV supplies voltage to the gates of switching elements Q1 and Q8 in a sequential manner, with the second period, third period, and so on. For example, if the voltage VOUT is lower than the target voltage VTARG, the driver DRV increases the ratio of the second period to the third period. For example, if the voltage VOUT is equal to the target voltage VTARG, the driver DRV maintains the ratio of the second period to the third period. For example, if the voltage VOUT is higher than the target voltage VTARG, the driver DRV decreases the ratio of the second period to the third period. This causes a change in the waveform of voltage VSW. When the power supply circuit 101 is enabled, and the signal OVT is at level "H", the driver DRV sets switch element Q1 to the off state and switch element Q8 to the on state. Conversely, when the power supply circuit 101 is disabled, the driver DRV sets switch element Q1 to the off state and switch element Q8 to the on state independently of the signal OVT.

[0236] With the structure described above, the power supply circuit 101 supplies voltage VSW to the filter circuit 5 based on voltages VSHARE and VOUT and signal OVT.

[0237] The filter circuit 5 includes an inductor L and a capacitor C.

[0238] The first terminal of inductor L is connected to terminal PVSW. The second terminal of inductor L is connected to terminal PFB. Terminal PFB is connected to load 4.

[0239] The first terminal of capacitor C is connected to terminal PFB. The second terminal of capacitor C is grounded.

[0240] With the structure described above, the filter circuit 5 smooths the waveform of the voltage VSW supplied from the semiconductor device 1. Thus, the filter circuit 5 uses the voltage VSW to generate a voltage VOUT that is equivalent to the target voltage VTARG.

[0241] The operation of the semiconductor device 1 in the seventh variation is substantially the same as the operation of the semiconductor device in the embodiment, therefore its description is omitted.

[0242] The seventh variation also achieves the same effect as the implementation method and the first to sixth variations.

[0243] 3. Other

[0244] Furthermore, in the above embodiments and modifications, the semiconductor device 1 is shown to include the over-temperature detection circuit 102 and the test circuit 103 as separate circuits, but this is not a limitation. In the semiconductor device 1, for example, the structures of the over-temperature detection circuit 102 and the test circuit 103 may also be included in one circuit.

[0245] Some embodiments of the invention have been described, but these embodiments are presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, as well as within the scope of the invention as described in the claims and their equivalents.

Claims

1. A semiconductor device, characterized in that, have: First terminal; Second terminal; Third terminal; The first circuit outputs a first signal of a first level when the temperature condition is met. as well as The second circuit, driven by the voltage supplied via the first terminal, electrically insulates the second terminal from the third terminal when the first circuit outputs the first signal at the first level. The first circuit includes an element disposed between the first wiring and the first terminal. During the testing of the semiconductor device, the element is in a conductive state that electrically connects the first wiring to the first terminal, and when a first voltage is supplied to the first wiring via the first terminal, the first circuit outputs the first signal of the first level regardless of the temperature. After the test action, the element is physically disconnected, thereby changing to an insulating state that electrically insulates the first wiring from the first terminal.

2. The semiconductor device according to claim 1, characterized in that, When the temperature is above a first temperature, the first circuit outputs the first signal at the first level.

3. The semiconductor device according to claim 1, characterized in that, The element is a conductor that is melted by irradiating the element with a laser.

4. The semiconductor device according to claim 1, characterized in that, The element is a conductor that melts when the current flowing through it reaches a first current value or higher.

5. The semiconductor device according to claim 4, characterized in that, The first circuit also includes: A first transistor, connected to the first terminal and the element; and The second transistor is connected to the node between the first transistor and the element, and to the second terminal. The signal supplied to the gate of the first transistor is the inverse of the signal supplied to the gate of the second transistor.

6. The semiconductor device according to claim 1, characterized in that, The first circuit includes: A first operational amplifier has a non-inverting input terminal connected to the first wiring, an inverting input terminal supplied with a second voltage, and an output terminal; and The load is connected to the non-inverting input terminal. The first circuit is configured to output the first signal at the first level based on the output of the output terminal when the voltage at the non-inverting input terminal is higher than the second voltage.

7. The semiconductor device according to claim 6, characterized in that, The first circuit also includes: First current source; A diode having an anode that is supplied with current from the first current source; as well as The second operational amplifier has an inverting input terminal connected to the anode of the diode, a non-inverting input terminal supplied with a third voltage, and an output terminal that outputs the first signal to the second circuit. When the third voltage is higher than the voltage at the inverting input terminal of the second operational amplifier, the second operational amplifier outputs the first signal at the first level. The first circuit is configured such that, when the voltage at the non-inverting input terminal of the first operational amplifier is higher than the second voltage, the third voltage, based on the output of the output terminal of the first operational amplifier, is higher than the voltage at the inverting input terminal of the second operational amplifier.

8. The semiconductor device according to claim 1, characterized in that, The first circuit includes: A first operational amplifier has a non-inverting input terminal supplied with a second voltage, an inverting input terminal connected to the first wiring, and an output terminal; and The load is connected to the non-inverting input terminal. The first circuit is configured to output the first signal at the first level based on the output of the output terminal when the voltage at the inverting input terminal is lower than the second voltage.

9. The semiconductor device according to claim 8, characterized in that, The first circuit also includes: First current source; A diode having an anode that is supplied with current from the first current source; as well as The second operational amplifier has an inverting input terminal connected to the anode of the diode, a non-inverting input terminal supplied with a third voltage, and an output terminal that outputs the first signal to the second circuit. When the third voltage is higher than the voltage at the inverting input terminal of the second operational amplifier, the second operational amplifier outputs the first signal at the first level. The first circuit is configured such that, when the voltage at the inverting input terminal of the first operational amplifier is lower than the second voltage, the third voltage is higher than the voltage at the inverting input terminal of the second operational amplifier based on the output of the first operational amplifier.

10. The semiconductor device according to claim 1, characterized in that, The second circuit includes a first transistor connected to the second terminal and the third terminal. The second circuit is configured such that, based on the first signal and the voltage of the first terminal, the first transistor becomes either in an on state or an off state.

11. The semiconductor device according to claim 10, characterized in that, The second circuit further includes an error amplifier having a non-inverting input terminal connected to the third terminal, an inverting input terminal supplied with a second voltage, an output terminal connected to the gate of the first transistor, a first input terminal supplied with the first signal, and a second input terminal supplied with a second signal based on the voltage of the first terminal. The error amplifier sets the first transistor to an on or off state based on the first signal and the second signal.

12. The semiconductor device according to claim 10, characterized in that, When the voltage at the first terminal is at the second level and the first signal is at a level different from the first level, the second circuit sets the first transistor to the on state. The second circuit sets the first transistor to the off state when the first signal is at the first level and when the voltage of the first terminal is at a level different from the second level.

13. The semiconductor device according to claim 1, characterized in that, The second circuit also includes: A first transistor is connected to the second terminal and the third terminal; The second transistor is connected to the third terminal; and The driver has a first input terminal to which the first signal is supplied, a second input terminal to which a second signal based on the voltage of the first terminal is supplied, a first output terminal connected to the gate of the first transistor, and a second output terminal connected to the gate of the second transistor. The driver is configured as follows: When the voltage at the first terminal is at the second level and the first signal is at a level different from the first level, a first period in which the first transistor is turned on and the second transistor is turned off is alternately repeated with a second period in which the first transistor is turned off and the second transistor is turned on. When the first signal is at the first level and the voltage of the first terminal is at a level different from the second level, the first transistor is set to the off state and the second transistor is set to the on state.

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