Optical tweezer device and method of manufacturing the same

Abstract

A light tweezer device and a method of manufacturing the same are disclosed. The light tweezer device includes a transparent substrate, a semiconductor layer, a first electrode, an insulating structure, and a reflective layer. The semiconductor layer is on the transparent substrate and includes a first doped region, a second doped region, and a transition region. The transition region is between the first doped region and the second doped region. The first electrode is on the first doped region and electrically connected to the first doped region. The insulating structure is on the transition region. The insulating structure has a first opening overlapping the first electrode in a normal direction of the transparent substrate. The reflective layer is on the insulating structure and has a second opening overlapping the first opening in the normal direction.

Description

Technical Field

[0001] This invention relates to an optical tweezers device and its manufacturing method. Background Technology

[0002] Optical tweezers (OETs) are tools for manipulating tiny particles, such as semiconductor particles, metal particles, metal nanowires, biological cells, or other particles. Generally, optical tweezers can manipulate particles using a highly focused laser beam. Nano- or micro-sized dielectric particles can be manipulated by the forces generated by the laser beam. Optical tweezers operate in a non-mechanical contact manner, and damage to the particles being held can be reduced by selecting an appropriate laser wavelength. Therefore, many biotechnological studies utilize optical tweezers to manipulate single cells. Summary of the Invention

[0003] This invention provides an optical tweezers device that can enhance the photocurrent generated after being irradiated by light.

[0004] This invention provides a method for manufacturing an optical tweezers device, which can save on the production cost of the optical tweezers device.

[0005] At least one embodiment of the present invention provides an optical tweezers device, comprising a transparent substrate, a semiconductor layer, a first electrode, an insulating structure, and a reflective layer. The semiconductor layer is situated on the transparent substrate and includes a first doped region, a second doped region, and a transition region. The transition region is located between the first doped region and the second doped region. The first electrode is situated on the first doped region and electrically connected to it. The insulating structure is situated on the transition region. The insulating structure has a first opening overlapping the first electrode in the normal direction of the transparent substrate. The reflective layer is situated on the insulating structure and has a second opening overlapping the first opening in the normal direction.

[0006] At least one embodiment of the present invention provides a method for manufacturing an optical tweezers device, comprising the following steps: forming a semiconductor material layer on a transparent substrate; performing a doping process on the semiconductor material layer to form a semiconductor layer including a first doped region, a second doped region, and a transition region, wherein the transition region is located between the first doped region and the second doped region; forming an insulating structure on the transition region of the semiconductor layer, wherein the insulating structure has a first opening; forming a conductive layer on the insulating structure and the semiconductor layer, wherein the conductive layer includes a first electrode located on the first doped region and a reflective layer located on the insulating structure. The first opening of the insulating structure overlaps with the first electrode in the normal direction of the transparent substrate, and the reflective layer has a second opening overlapping the first opening in the normal direction. Attached Figure Description

[0007] Figure 1A This is a cross-sectional schematic diagram of an optical tweezers device according to an embodiment of the present invention;

[0008] Figure 1B yes Figure 1A A top view of the optical tweezers device;

[0009] Figure 2 This is a cross-sectional schematic diagram of an optical tweezers device according to an embodiment of the present invention;

[0010] Figures 3A to 9A This is a cross-sectional schematic diagram of a method for manufacturing an optical tweezers device according to an embodiment of the present invention;

[0011] Figures 3B to 9B yes Figures 3A to 9A A top view of the structure;

[0012] Figure 10 This is a cross-sectional schematic diagram of an optical tweezers device according to an embodiment of the present invention;

[0013] Figure 11 This is a cross-sectional schematic diagram of an optical tweezers device according to an embodiment of the present invention;

[0014] Figure 12 This is a cross-sectional schematic diagram of an optical tweezers device according to an embodiment of the present invention;

[0015] Figures 13 to 17 This is a cross-sectional schematic diagram of a method for manufacturing an optical tweezers device according to an embodiment of the present invention.

[0016] Symbol Explanation

[0017] 10, 20, 30, 40, 50: Optical tweezers device

[0018] 100: Transparent substrate

[0019] 110, 110A, 110B, 110C: Semiconductor layers

[0020] 110a: Semiconductor material layer

[0021] 112, 112a, 112A, 112B, 112C: First doped region

[0022] 114, 114B, 114C: Transition Zone

[0023] 116, 116A, 116B, 116C: Second doped region

[0024] 120, 220: Insulation structure

[0025] 120a: Insulation material layer

[0026] 130: Dielectric layer

[0027] 132: First through hole

[0028] 200: Buffer solution

[0029] 222a: First insulating material layer

[0030] 224a: Second insulating material layer

[0031] 222b: Patterned first insulating layer

[0032] 224b: Patterned second insulating layer

[0033] 300: Particles / Induced Polarization Particles

[0034] 400: Opposing electrode

[0035] D1: First Direction

[0036] D2: Second Direction

[0037] E1: First electrode

[0038] E2: Second electrode

[0039] E3: Reflective layer

[0040] LF: Flow direction

[0041] LS: Beam

[0042] ND: Normal direction

[0043] O1: First opening

[0044] O2: Second opening

[0045] PR1: First mask pattern

[0046] PR2: Second mask pattern

[0047] PR3: Third mask pattern

[0048] R1: Zone 1

[0049] R2: Second Zone

[0050] R3: Third District

[0051] Ta, Tb: Thickness

[0052] W1, W2, Wa, Wb: Width Detailed Implementation

[0053] Figure 1A This is a cross-sectional schematic diagram of an optical tweezers device 10 according to an embodiment of the present invention. Figure 1B yes Figure 1A A top view of the optical tweezers device, in which... Figure 1A Corresponding Figure 1B The position of line a-a'. Figure 1B The first electrode E1, the second electrode E2, and the reflective layer E3 are shown, while other components are omitted.

[0054] Please refer to Figure 1A and Figure 1B The optical tweezers device 10 includes a transparent substrate 100, a semiconductor layer 110, a first electrode E1, an insulating structure 120, and a reflective layer E3. In this embodiment, the optical tweezers device 10 further includes a second electrode E2, a dielectric layer 130, a buffer solution 200, a plurality of particles 300, and a counter electrode 400. In some embodiments, the optical tweezers device 10 is a self-locking optical tweezer (SLOT) device.

[0055] The transparent substrate 100 can be made of materials such as glass, quartz, organic polymers, or other suitable materials. Compared to using a silicon wafer as the substrate, using a transparent substrate 100 can save on the production cost of the optical tweezers device 10.

[0056] A semiconductor layer 110 is located on a transparent substrate 100. In some embodiments, the semiconductor layer 110 is made of materials such as polycrystalline silicon, amorphous silicon, monocrystalline silicon, or other suitable materials. The semiconductor layer 110 includes a first doped region 112, a second doped region 116, and a transition region 114, wherein the transition region 114 is located between the first doped region 112 and the second doped region 116.

[0057] Multiple first doped regions 112 are separated from each other. In some embodiments, the first doped regions 112 are arrayed on the transparent substrate 100. For example, the vertical projection of the first doped regions 112 on the transparent substrate 100 is a circle, ellipse, triangle, quadrilateral, pentagon, hexagon or other geometric shape, and the multiple first doped regions 112 are arrayed on the transparent substrate 100 along a first direction D1 and a second direction D2. Figure 1A Two first doped regions 112 in the optical tweezers device 10 are illustrated, but the number of first doped regions 112 can be adjusted according to actual needs. In some embodiments, the width W1 of the first doped region 112 is 2 micrometers to 100 micrometers.

[0058] The transition regions 114 are separated from each other, and each transition region 114 surrounds a corresponding first doped region 112. In some embodiments, the transition regions 114 and the first doped regions 112 are concentric circles, but the invention is not limited thereto. In other embodiments, the first doped region 112 may include a shape other than a circle, and the shape of the transition region 114 varies with the shape of the first doped region 112. In some embodiments, the width W2 of the transition region 114 is 2 micrometers to 20 micrometers.

[0059] The second doped region 116 surrounds a plurality of transition regions 114. In this embodiment, the second doped region 116 is a continuous structure, and the transition regions 114 and the first doped region 112 are distributed in the second doped region 116.

[0060] In some embodiments, one of the first doped region 112 and the second doped region 116 is a P-type semiconductor, and the other of the first doped region 112 and the second doped region 116 is an N-type semiconductor, and the transition region 114 is a pure semiconductor or a lightly doped semiconductor with a purity close to that of a pure semiconductor. Therefore, the semiconductor layer 110 includes a plurality of PIN diodes composed of the first doped region 112, the transition region 114, and the second doped region 116.

[0061] Multiple insulating structures 120 are located on the transition region 114 of the semiconductor layer 110. Each insulating structure 120 is disposed on a corresponding transition region 114, and the multiple insulating structures 120 are separated from each other. In this embodiment, the insulating structure 120 is annular, but the invention is not limited thereto. The shape of the insulating structure 120 depends on the shape of the transition region 114. In some embodiments, the shape of the insulating structure 120 projected vertically onto the transparent substrate 100 is approximately equal to the shape of the transition region 114 projected vertically onto the transparent substrate 100.

[0062] The insulating structure 120 has a first opening O1 that overlaps the first doped region 112 of the semiconductor layer 110 in the normal direction ND of the transparent substrate 100. In this embodiment, the insulating structure 120 surrounds the first opening O1. In other words, the first opening O1 is laterally closed by the insulating structure 120. In other embodiments, the insulating structure 120 does not completely surround the first opening O1. The width of the bottom of the first opening O1 is greater than, equal to, or less than the width W1 of the first doped region 112. When the width of the bottom of the first opening O1 is greater than the width W1 of the first doped region 112, resulting in a portion of the transition region 114 not being covered by the insulating structure 120, there is a risk of leakage current in the semiconductor layer 110. When the width of the bottom of the first opening O1 is less than the width W1 of the first doped region 112, resulting in a portion of the first doped region 112 being covered by the insulating structure 120, the polarization effect on the particle 300 is reduced. Therefore, the width of the bottom of the first opening O1 is preferably equal to the width W1 of the first doped region 112.

[0063] exist Figure 1A In this illustration, the insulating structure 120 is shown as a single layer, but the invention is not limited thereto. The insulating structure 120 may be a single-layer or multi-layer structure. In some embodiments, the material of the insulating structure 120 includes, for example, silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials or combinations thereof.

[0064] In some embodiments, the first electrode E1 is arrayed on the semiconductor layer 110 along a first direction D1 and a second direction D2, but the invention is not limited thereto. In other embodiments, the first electrode E1 is arrayed on the semiconductor layer 110 in other arrangements. The first electrode E1 is located on and electrically connected to the first doped region 112. An insulating structure 120 surrounds the first electrode E1. In this embodiment, the first electrode E1 is formed directly on the first doped region 112. In this embodiment, the first electrode E1 has an island-like structure, and each first electrode E1 overlaps a corresponding first doped region 112. In some embodiments, the sidewalls of the first electrode E1 are substantially aligned with the boundary of the first doped region 112, but the invention is not limited thereto. In other embodiments, the sidewalls of the first electrode E1 are offset from the boundary of the first doped region 112.

[0065] The second electrode E2 is located on and electrically connected to the second doped region 116. In this embodiment, the second electrode E2 is formed directly on the second doped region 116. The second electrode E2 surrounds the insulating structure 120. In this embodiment, the second electrode E2 is a continuous structure and surrounds the island-shaped first electrode E1. In some embodiments, the sidewalls of the second electrode E2 are substantially aligned with the boundary of the second doped region 116, but the invention is not limited thereto. In other embodiments, the sidewalls of the second electrode E2 are offset from the boundary of the second doped region 116.

[0066] A reflective layer E3 is located on the insulating structure 120 and is separated from the first electrode E1 and the second electrode E2. In some embodiments, the reflective layer E3 is annular, but this is not a limitation of the invention. The shape of the reflective layer E3 depends on the shape of the top surface of the insulating structure 120. In some embodiments, the shape of the reflective layer E3 projected vertically onto the transparent substrate 100 is approximately equal to the shape of the insulating structure 120 projected vertically onto the transparent substrate 100. The reflective layer E3 has a second opening O2 that overlaps the first opening O1 in the normal direction ND. In this embodiment, the reflective layer E3 surrounds the second opening O2. In other embodiments, the second opening O2 is laterally closed by the reflective layer E3. In other embodiments, the reflective layer E3 does not completely surround the second opening O2. In some embodiments, the sidewalls of the reflective layer E3 are substantially aligned with the sidewalls of the insulating structure 120, but this is not a limitation of the invention. In other embodiments, the sidewalls of the reflective layer E3 are offset from the sidewalls of the insulating structure 120.

[0067] The first electrode E1, the second electrode E2, and the reflective layer E3 can be a single-layer or multi-layer structure. The materials of the first electrode E1, the second electrode E2, and the reflective layer E3 include metals or other suitable materials with conductive and reflective properties. In some embodiments, the first electrode E1, the second electrode E2, and the reflective layer E3 belong to the same conductive layer. In other words, the first electrode E1, the second electrode E2, and the reflective layer E3 are formed by the same deposition process. In some embodiments, the first electrode E1, the second electrode E2, and the reflective layer E3 comprise the same material. In some embodiments, the thickness of the insulating structure 120 is greater than the thickness of the first electrode E1, the thickness of the second electrode E2, and the thickness of the reflective layer E3.

[0068] A dielectric layer 130 is located above the semiconductor layer 110. In this embodiment, the dielectric layer 130 is formed above the second electrode E2, the reflective layer E3, and the insulating structure 120. The dielectric layer 130 covers the top surface of the second electrode E2 and the top surface of the reflective layer E3. The dielectric layer 130 has a first via 132 that overlaps the first opening O1 and the second opening O2 in the normal direction ND. In some embodiments, the dielectric layer 130 is made of silicon oxide, silicon nitride, silicon oxynitride, organic materials, or other suitable materials.

[0069] The first via 132 exposes at least a portion of the top surface of the first electrode E1. In this embodiment, the dielectric layer 130 has an array of multiple first vias 132, each first via 132 overlapping a corresponding first electrode E1. In some embodiments, the widths of the first vias 132, the widths of the first opening O1, and the second opening O2 are the same, but the invention is not limited thereto. In other embodiments, the width of the first via 132 is smaller than the widths of the first opening O1 and the second opening O2. Additionally, although in Figure 1A In this embodiment, the dielectric layer 130 is not filled into the first opening O1 and the second opening O2, but the present invention is not limited thereto. In other embodiments, the dielectric layer 130 is filled into the first opening O1 and the second opening O2. In some embodiments, the width of the first via 132 is 2 micrometers to 100 micrometers.

[0070] The counter electrode 400 overlaps with a plurality of first electrodes E1. In some embodiments, the counter electrode 400 comprises a light-transmitting material (e.g., indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium gallium zinc oxide, organic conductive material or other suitable material or a stacked layer of the above materials) or an opaque material (e.g., a metal).

[0071] A buffer solution 200 is located between the counter electrode 400 and the first electrode E1. The buffer solution 200 is also located between the counter electrode 400 and the dielectric layer 130. In some embodiments, the buffer solution 200 fills the first through-hole 132 of the dielectric layer 130, and the buffer solution 200 contacts the counter electrode 400, the first electrode E1, and the dielectric layer 130. In some embodiments, the buffer solution 200 is, for example, a physiological buffer solution or other buffer solutions (e.g., an isotonic buffer solution). A plurality of particles 300 are located in the buffer solution 200. The particles 300 can be biological particles, organic particles, or inorganic particles. The particle size of the particles 300 is from 2 micrometers to 100 micrometers.

[0072] In some embodiments, an alternating current is applied at a frequency to the counter electrode 400 and the first electrode E1 to generate an electric field between the counter electrode 400 and the first electrode E1. The induced polarization particles 300 are attracted to the dielectric layer 130 overlapping the first via 132 of the first electrode E1 by the dielectrophoretic force.

[0073] Please refer to Figure 2 Select the desired induced polarization particle 300 and illuminate the position of the semiconductor layer 110 below the selected induced polarization particle 300 with a beam LS. The beam LS enters the optical tweezers device 10 from the side of the transparent substrate 100 opposite to the semiconductor layer 110.

[0074] In some embodiments, a light beam LS illuminates a PIN diode beneath a selected first electrode E1. The diameter of the LS is from 2 micrometers to 120 micrometers. For example, the light beam LS illuminates a first doped region 112 and a transition region 114, causing a photocurrent to be generated in the PIN diode beneath the selected induced polarization particle 300, and reversing the direction of the dielectric force of the selected induced polarization particle 300, causing the selected induced polarization particle 300 to be repelled and leave the first via 132 of the dielectric layer 130. In some embodiments, a buffer solution 200 flows along the flow direction LF, so the induced polarization particle 300 leaving the first via 132 flows downstream with the buffer solution 200. In some embodiments, the induced polarization particle 300 flowing downstream is collected and analyzed, but the invention is not limited thereto. In other embodiments, the induced polarization particle 300 retained on the first via 132 is collected and analyzed.

[0075] In some embodiments, the light beam LS includes laser light, ultraviolet light, visible light, or other suitable light.

[0076] In some embodiments, a light beam LS passing through the transparent substrate 100, the transition region 114, and the insulating structure 120 can be reflected by the reflective layer E3 and return to the semiconductor layer 110. Therefore, the semiconductor layer 110 can generate a large photocurrent. In some embodiments, the ratio of the photocurrent to the dark current generated by the semiconductor layer 110 is greater than or equal to two orders of magnitude.

[0077] The doping morphology of the semiconductor layer 110 affects the direction of the current generated by the PIN diode after illumination. In this embodiment, the first doped region 112 is an N-type semiconductor, the second doped region 116 is a P-type semiconductor, and the surface of the induced polarization particle 300 is negatively charged. In other embodiments, the first doped region 112 is a P-type semiconductor, the second doped region 116 is an N-type semiconductor, and the surface of the induced polarization particle 300 is positively charged.

[0078] Figures 3A to 9A This is a cross-sectional schematic diagram of a method for manufacturing an optical tweezers device according to an embodiment of the present invention. Figures 3B to 9B yes Figures 3A to 9A A top view of the structure. It must be noted here that... Figures 3A to 9B The embodiments follow Figure 1A , Figure 1B and Figure 2 The component reference numerals and partial contents of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here.

[0079] Please refer to Figure 3A and Figure 3B A semiconductor material layer 110a is formed on the transparent substrate 100. In this embodiment, since the semiconductor material layer 110a is located on the transparent substrate 100, it can be formed using a thin-film fabrication process, thereby reducing the production cost of the optical tweezers device. In some embodiments, the method for forming the semiconductor material layer 110a includes, for example, a low-temperature polysilicon (LTPS) fabrication process or other suitable fabrication processes. Furthermore, compared to fabricating the optical tweezers device on a wafer, a large-area optical tweezers device can be more easily obtained using a thin-film fabrication process.

[0080] Please refer to Figures 4A to 5A as well as Figures 4B to 5B A doping process is performed on the semiconductor material layer 110a to form a semiconductor layer 110 including a first doped region 112, a second doped region 116 and a transition region 114, wherein the transition region 114 is located between the first doped region 112 and the second doped region 116.

[0081] Please refer to this first. Figure 4Aand Figure 4B A first mask pattern PR1 is formed on a first region R1 of the semiconductor material layer 110a, and the first mask pattern PR1 exposes a second region R2 and a third region R3 of the semiconductor material layer 110a, wherein the first region R1 surrounds the third region R3 and is located between the second region R2 and the third region R3. In some embodiments, the first mask pattern PR1 is, for example, a patterned photoresist.

[0082] Using the first mask pattern PR1 as a mask, a first doping process is performed on the second region R2 and the third region R3 of the semiconductor material layer 110a to form the semiconductor material layer 110a. The first doping process is, for example, P-type doping or N-type doping. In this embodiment, the first doping process is a P-type doping process. In this embodiment, the first doping process forms a second doped region 116 and a first doped region 112a with the same doping type in the second region R2 and the third region R3.

[0083] After performing the first doping fabrication process, the first mask pattern PR1 is removed. In some embodiments, the first mask pattern PR1 is removed by etching (e.g., ashing).

[0084] Please refer to Figure 5A and Figure 5B A second mask pattern PR2 is formed on the first region R1 and the second region R2 of the semiconductor material layer 110a, and the second mask pattern PR2 exposes the third region R3 of the semiconductor material layer 110a. In some embodiments, the second mask pattern PR2 is, for example, a patterned photoresist.

[0085] Using the second mask pattern PR2 as a mask, a second doping process is performed on the third region R3 of the semiconductor material layer 110a. The second doping process is, for example, P-type doping or N-type doping. In this embodiment, the second doping process differs from the first doping process, and the second doping process is an N-type doping process. In this embodiment, the second doping process forms a first doped region 112 in the third region R3.

[0086] At this point, the semiconductor layer 110, including the first doped region 112, the second doped region 116, and the transition region 114, is substantially complete, wherein the semiconductor material layer 110a (please refer to...) Figure 4A The third region R3 of the semiconductor material layer 110a corresponds to the position of the first doped region 112, the second region R2 of the semiconductor material layer 110a corresponds to the position of the second doped region 116, and the first region R1 of the semiconductor material layer 110a corresponds to the position of the transition region 114.

[0087] After performing the second doping fabrication process, the second mask pattern PR2 is removed. In some embodiments, the second mask pattern PR2 is removed by etching (e.g., graying).

[0088] Please refer to Figure 6A and Figure 6B An insulating material layer 120a is formed on the semiconductor layer 110. In some embodiments, the insulating material layer 120a includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials.

[0089] In some embodiments, the insulating material layer 120a includes hydrogen, and an annealing process is performed on the semiconductor layer 110 and the insulating material layer 120a to allow the hydrogen in the insulating material layer 120a to diffuse into the semiconductor layer 110, thereby repairing damage to the semiconductor layer 110 caused during the doping process. In some embodiments, the aforementioned annealing process involves heating the semiconductor layer 110 and the insulating material layer 120a to 400°C to 625°C using a rapid thermal annealing process.

[0090] Please refer to Figure 7A and Figure 7B An insulating material layer 120a is patterned to form an insulating structure 120 exposing a first doped region 112 and a second doped region 116. In this embodiment, a third mask pattern PR3 is formed on the insulating material layer 120a, and the insulating material layer 120a is etched one or more times using the third mask pattern PR3 as a mask to form a plurality of insulating structures 120, wherein the first opening O1 of each insulating structure 120 exposes the corresponding first doped region 112, and the second doped region 116 is exposed by the gaps between the insulating structures 120. In some embodiments, the third mask pattern PR3 is, for example, a patterned photoresist.

[0091] In some embodiments, the third mask pattern PR3 is removed after the patterned insulating material layer 120a. In some embodiments, the third mask pattern PR3 is removed by etching (e.g., graying).

[0092] Please refer to Figure 8A and Figure 8B A conductive layer is formed on the insulating structure 120 and the semiconductor layer 110, wherein the conductive layer includes a first electrode E1 located on the first doped region 112, a second electrode E2 located on the second doped region 116, and a reflective layer E3 located on the insulating structure 120.

[0093] In this embodiment, since there is a gap between the top surface of the insulating structure 120 and the top surface of the semiconductor layer 110, when the conductive layer is deposited, the reflective layer E3 located on the top surface of the insulating structure 120 will be separated from the first electrode E1 and the second electrode E2 located on the top surface of the semiconductor layer 110.

[0094] Please refer to Figure 9A and Figure 9B A dielectric layer 130 is formed on the semiconductor layer 110. In this embodiment, the dielectric layer 130 is formed on a portion of the first electrode E1, the second electrode E2, and the insulating structure 120. The dielectric layer 130 has a first via 132 overlapping the first electrode E1, and the dielectric layer 130 covers the top surface of the second electrode E2 and the top surface of the reflective layer E3.

[0095] Finally, please return to Figure 1A and Figure 1B The optical tweezers device 10 is substantially completed by providing a counter electrode 400 overlapping the first electrode E1; providing a buffer solution 200 between the counter electrode 400 and the first electrode E1 and between the counter electrode 400 and the dielectric layer 130; and providing a plurality of particles 300 in the buffer solution 200.

[0096] Figure 10 This is a cross-sectional schematic diagram of an optical tweezers device 20 according to an embodiment of the present invention. It must be noted here that... Figure 10 The embodiments follow Figure 1A , Figure 1B and Figure 2 The component reference numerals and partial contents of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here.

[0097] Figure 10 Optical tweezers device 20 and Figure 1A and Figure 1B The difference between the optical tweezers device 10 and the optical tweezers device 20 is that the positions of the N-type and P-type semiconductors in the semiconductor layer 110 of the optical tweezers device 10 are different from those in the semiconductor layer 110A of the optical tweezers device 20. The first doped region 112 and the second doped region 116 in the semiconductor layer 110 of the optical tweezers device 10 are N-type and P-type semiconductors, respectively, while the first doped region 112A and the second doped region 116A in the semiconductor layer 110A of the optical tweezers device 20 are P-type and N-type semiconductors, respectively.

[0098] exist Figure 10 In this embodiment, the first electrode E1 is electrically connected to a P-type semiconductor, while the second electrode E2 is electrically connected to an N-type semiconductor. In this embodiment, the surface of the induced polarization particle 300 is positively charged.

[0099] Figure 11 This is a cross-sectional schematic diagram of an optical tweezers device 30 according to an embodiment of the present invention. It must be noted here that... Figure 11 The embodiments follow Figure 1A , Figure 1B and Figure 2 The component reference numerals and partial contents of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here.

[0100] Figure 11 Optical tweezers device 30 and Figure 1A and Figure 1B The difference between the optical tweezers device 10 and the optical tweezers device 30 is that the semiconductor layer 110 of the optical tweezers device 10 includes a PIN diode, while the semiconductor layer 110B of the optical tweezers device 30 includes an NIN structure.

[0101] exist Figure 11 In this embodiment, the first doped region 112B and the second doped region 116B in the semiconductor layer 110B are both semiconductors of the same doping type, such as N-type semiconductors. The transition region 114B is an intrinsically semiconductor or a lightly doped P-type semiconductor. Figure 11 In this embodiment, both the first electrode E1 and the second electrode E2 are electrically connected to an N-type semiconductor.

[0102] In this embodiment, when a light beam shines on the NIN structure, the NIN structure generates a photocurrent, thereby attracting or repelling particles 300.

[0103] Figure 12 This is a cross-sectional schematic diagram of an optical tweezers device 40 according to an embodiment of the present invention. It must be noted here that... Figure 12 The embodiments follow Figure 1A , Figure 1B and Figure 2 The component reference numerals and partial contents of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here.

[0104] Figure 12 Optical tweezers device 40 and Figure 1A and Figure 1B The difference between the optical tweezers device 10 and the optical tweezers device 40 is that the semiconductor layer 110 of the optical tweezers device 10 includes a PIN diode, while the semiconductor layer 110C of the optical tweezers device 40 includes a PIP structure.

[0105] exist Figure 12In this embodiment, the first doped region 112C and the second doped region 116C in the semiconductor layer 110C are both semiconductors of the same doping type, such as P-type semiconductors. The transition region 114C is an intrinsic semiconductor or a lightly doped N-type semiconductor. Figure 12 In this embodiment, both the first electrode E1 and the second electrode E2 are electrically connected to a P-type semiconductor.

[0106] In this embodiment, when a light beam shines on the PIP structure, the PIP structure generates a photocurrent, thereby attracting or repelling particles 300.

[0107] Figures 13 to 17 This is a cross-sectional schematic diagram illustrating a method for manufacturing an optical tweezers device 50 according to an embodiment of the present invention. It must be noted here that... Figures 13 to 16 The embodiments follow Figure 1A , Figure 1B and Figure 2 The component reference numerals and partial contents of the embodiments are described below, wherein the same or similar reference numerals are used to represent the same or similar components, and descriptions of the same technical content are omitted. For explanations of the omitted parts, please refer to the foregoing embodiments, and will not be repeated here.

[0108] Please refer to Figures 13 to 15 In this embodiment, the insulating structure 220 includes a multilayer structure. For example, the method of forming the insulating structure 220 on the transition region 114 includes the following steps. Please refer to... Figure 13 A first insulating material layer 222a is formed on the semiconductor layer 110. A second insulating material layer 224a is formed on the first insulating material layer 222a. In some embodiments, the first insulating material layer 222a and the second insulating material layer 224a comprise different materials. For example, the first insulating material layer 222a comprises silicon oxide, and the second insulating material layer 224a comprises silicon nitride. A third mask pattern PR3 is formed on the second insulating material layer 224a, wherein the third mask pattern PR3 overlaps the transition region 114 of the semiconductor layer 110 in the normal direction ND. In some embodiments, the width of the third mask pattern PR3 is greater than or equal to the width of the transition region 114.

[0109] Please refer to Figure 13 and Figure 14Using the third mask pattern PR3 as a mask, a dry etching process is performed to pattern the first insulating material layer 222a and the second insulating material layer 224a. The patterned first insulating material layer 222b and the patterned second insulating material layer 224b expose the first doped region 112 and the second doped region 116. In some embodiments, the aforementioned dry etching process is an isotropic etching process (e.g., laser etching or plasma etching). In some embodiments, the first insulating material layer 222b partially covers the first doped region 112 and the second doped region 116.

[0110] Please refer to Figure 14 and Figure 15 Following the dry etching process, a wet etching process is performed using the third mask pattern PR3 as a mask to remove at least a portion of the patterned first insulating material layer 222b. In some embodiments, the patterned second insulating material layer 224b may also be partially removed in the wet etching process. In the wet etching process, the etching rate of the patterned first insulating material layer 222b is greater than the etching rate of the patterned second insulating material layer 224b. In other words, a larger portion of the first insulating material layer 222b is removed in the wet etching process. In some embodiments, the aforementioned wet etching process is an anisotropic etching process. In some embodiments, a 0.45% hydrofluoric acid solution is used for the wet etching process.

[0111] Multiple insulating structures 220 can be obtained through dry etching and wet etching processes. Each insulating structure 220 includes a first insulating layer 222 and a second insulating layer 224. The first insulating layer 222 is located between the second insulating layer 224 and the transition region 114. In this embodiment, both the first insulating layer 222 and the second insulating layer 224 are annular, and the width Wa of the first insulating layer 222 is smaller than the width Wb of the second insulating layer 224. In some embodiments, the thickness Ta of the first insulating layer 222 is greater than the thickness Tb of the second insulating layer 224. Therefore, this helps to make the insulating structure 220 have a cross-sectional shape that is narrower at the bottom and wider at the top after the wet etching process.

[0112] Please refer to Figure 16 A conductive layer is formed on the insulating structure 120 and the semiconductor layer 110, wherein the conductive layer includes a first electrode E1 located on the first doped region 112, a second electrode E2 located on the second doped region 116, and a reflective layer E3 located on the insulating structure 220.

[0113] In this embodiment, since there is a discontinuity between the top surface of the insulating structure 220 and the top surface of the semiconductor layer 110, the reflective layer E3 on the top surface of the insulating structure 220 will separate from the first electrode E1 and the second electrode E2 on the top surface of the semiconductor layer 110 during the deposition of the conductive layer. Because the width of the first insulating layer 222 is smaller than the width of the second insulating layer 224, the probability of the reflective layer E3 contacting the first electrode E1 and / or the second electrode E2 can be reduced, thereby reducing the risk of short circuits.

[0114] In this embodiment, there is a gap between the sidewall of the first electrode E1 and the sidewall of the first insulating layer 222, and there is also a gap between the sidewall of the second electrode E2 and the sidewall of the first insulating layer 222.

[0115] Please refer to Figure 17 A dielectric layer 130 is formed on the semiconductor layer 110. In this embodiment, the dielectric layer 130 is formed on the second electrode E2, the insulating structure 120, and the reflective layer E3. The dielectric layer 130 has a first via 132 overlapping the first electrode E1, and the dielectric layer 130 covers the top surface of the second electrode E2 and the top surface of the reflective layer E3. In some embodiments, a portion of the dielectric layer 130 fills the gap between the sidewall of the first electrode E1 and the sidewall of the first insulating layer 222, and the gap between the sidewall of the second electrode E2 and the sidewall of the first insulating layer 222. In the normal direction ND, a portion of the dielectric layer 130 is located between a portion of the second insulating layer 224 and a portion of the semiconductor layer 110. In some embodiments, a portion of the dielectric layer 130 is located between the first insulating layer 222 and the first electrode E1, and between the first insulating layer 222 and the second electrode E2.

[0116] Finally, a counter electrode 400 is provided overlapping the first electrode E1; a buffer solution 200 is provided between the counter electrode 400 and the first electrode E1 and between the counter electrode 400 and the dielectric layer 130; and a plurality of particles 300 are provided in the buffer solution 200. At this point, the optical tweezers device 50 is substantially completed.

[0117] In summary, the optical tweezers device of the present invention includes a reflective layer located on an insulating structure. By providing the reflective layer, when a light beam is irradiated onto the back of the optical tweezers device, the light beam passing through the transparent substrate, the semiconductor layer, and the insulating structure can be reflected by the reflective layer and return to the semiconductor layer. Therefore, the semiconductor layer can generate a large photocurrent.

Claims

1. An optical tweezers device, comprising: Transparent substrate; A semiconductor layer is located on the transparent substrate and includes a first doped region, a second doped region, and a transition region, wherein the transition region is located between the first doped region and the second doped region. The first electrode is located on the first doped region and is electrically connected to the first doped region; An insulating structure is located on the transition region, wherein the insulating structure has a first opening that overlaps the first electrode in the normal direction of the transparent substrate; as well as A reflective layer is located on the insulating structure and has a second opening that overlaps the first opening in the normal direction.

2. The optical tweezers device as claimed in claim 1, wherein the insulating structure includes a first insulating layer and a second insulating layer, the first insulating layer being located between the second insulating layer and the transition region, wherein the thickness of the first insulating layer is greater than the thickness of the second insulating layer.

3. The optical tweezers device as claimed in claim 2, wherein both the first insulating layer and the second insulating layer are annular, and the width of the first insulating layer is smaller than the width of the second insulating layer.

4. The optical tweezers device as described in claim 2, further comprising: A dielectric layer is located above the semiconductor layer and has a first via overlapping the first opening and the second opening in the normal direction, wherein in the normal direction, a portion of the dielectric layer is located between a portion of the second insulating layer and a portion of the semiconductor layer.

5. The optical tweezers device as described in claim 2, further comprising: A dielectric layer is located above the semiconductor layer and has a first through-hole that overlaps the first opening and the second opening in the normal direction, wherein a portion of the dielectric layer is located between the first insulating layer and the first electrode.

6. The optical tweezers device as claimed in claim 1, further comprising: The second electrode is located on the second doped region and electrically connected to the second doped region, wherein the first electrode has an island-like structure and the second electrode surrounds the first electrode.

7. The optical tweezers device of claim 1, wherein one of the first doped region and the second doped region is a P-type semiconductor, the other of the first doped region and the second doped region is an N-type semiconductor, and the transition region is an intrinsic semiconductor.

8. The optical tweezers device of claim 1, wherein the first doped region and the second doped region are both semiconductors of the same doping type, and the transition region is a semiconductor of a different doping type.

9. The optical tweezers device of claim 1, wherein the thickness of the insulating structure is greater than the thickness of the first electrode.

10. The optical tweezers device of claim 1, wherein the insulating structure surrounds the first electrode and the first opening, and the reflective layer surrounds the second opening.

11. A method for manufacturing an optical tweezers device, comprising: A semiconductor material layer is formed on a transparent substrate; A doping process is performed on the semiconductor material layer to form a semiconductor layer including a first doped region, a second doped region, and a transition region, wherein the transition region is located between the first doped region and the second doped region; An insulating structure is formed on the transition region, wherein the insulating structure has a first opening; A conductive layer is formed on the insulating structure and the semiconductor layer, wherein the conductive layer includes a first electrode located on the first doped region and a reflective layer located on the insulating structure, wherein the first opening of the insulating structure overlaps the first electrode in the normal direction of the transparent substrate, and the reflective layer has a second opening overlapping the first opening in the normal direction.

12. The method of manufacturing the optical tweezers device as claimed in claim 11, wherein the method of forming the insulating structure on the transition region comprises: A first insulating material layer is formed on the semiconductor layer; A second insulating material layer is formed on the first insulating material layer; A mask pattern is formed on the second insulating material layer, wherein the mask pattern overlaps the transition region of the semiconductor layer in the normal direction; Using the mask pattern as a mask, a dry etching process is performed to pattern the first insulating material layer and the second insulating material layer; as well as Following the dry etching process, a wet etching process is performed using the mask pattern as a mask to remove at least a portion of the first insulating material layer.

13. The method for manufacturing the optical tweezers device as claimed in claim 12, wherein in the wet etching process, the etching rate of the first insulating material layer is greater than the etching rate of the second insulating material layer.

14. The method for manufacturing the optical tweezers device as described in claim 11, further comprising: Provide a counter electrode that overlaps with the first electrode; A buffer solution is provided between the opposing electrode and the first electrode; as well as Multiple particles are provided in the buffer solution.

15. The method of manufacturing an optical tweezers device as claimed in claim 11, wherein the optical tweezers device is configured to allow the semiconductor layer to receive a light beam, the light beam entering the optical tweezers device from the side of the transparent substrate opposite to the semiconductor layer.

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