Exposure method for contact holes

Abstract

This application provides a method for exposing contact holes, comprising: providing a wafer, the wafer including a main wafer region and a wafer edge region, the wafer edge region forming yield chips and defective chips; setting a specific exposure area in the wafer edge region; in the process of exposing to form contact holes, selecting a specific exposure area in the specific exposure area for exposure, the selected exposure area being rectangular or square, the selected exposure area ensuring that the number of defective chips formed in the specific exposure area is less than a set value. This method avoids defect sources formed in the wafer edge region and ensures a high yield chip count.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing, and more particularly to a method for exposing contact holes. Background Technology

[0002] Power management chips, serving as the power supply hub and link for electronic products and equipment, are responsible for the conversion, distribution, detection, and control of the required electrical energy, making them indispensable key components in modern electronic products and equipment. Among these, MOS devices are the most commonly used device structure for this type of chip, especially high-voltage MOS power devices. Due to the high voltage withstand requirements of high-voltage MOS power devices, high-density contact holes are often designed in the circuit to reduce the thermal effects of current.

[0003] In the fabrication process of contact structures, an adhesive layer is typically filled inside the contact holes and on the wafer surface first. Then, a metal layer is deposited on the adhesive layer inside the contact holes to form the contact structure. In existing technologies, the metal layer often fails to fill sufficiently at the wafer edge, resulting in film gaps (film inhomogeneity) at the wafer edge. This leads to insufficient support between the film layers at the wafer edge, making the adhesive layer at the wafer edge prone to peeling off after etching and cleaning processes. This becomes a defect source, causing yield losses in the finished chip.

[0004] Therefore, developing an exposure method for contact holes to solve the defects caused by film peeling in the wafer edge region has become an urgent technical problem. Summary of the Invention

[0005] The technical problem to be solved by this application is to provide an exposure method for contact holes that can solve the defects caused by film peeling in the wafer edge region.

[0006] To solve the above-mentioned technical problems, this application provides an exposure method for contact holes, including:

[0007] A wafer is provided, the wafer including a wafer body region and a wafer edge region, the wafer edge region being formed into yield chips and defective chips;

[0008] A specific exposure area is set in the edge region of the wafer. In the process of forming contact holes by exposure, a selected exposure area is selected in the specific exposure area for exposure. The selected exposure area is rectangular or square. The selected exposure area makes the number of invalid chips formed in the specific exposure area less than a set value.

[0009] In some embodiments of this application, the specific exposure area is a region in the metal deposition process for forming contact holes where the metal deposition uniformity at the wafer edge is lower than a set uniformity.

[0010] In some embodiments of this application, the uniformity of the metal layer is determined by the surface morphology of the metal layer, wherein the set uniformity requires the surface height difference of the metal layer at different locations to be between 150 nm and 200 nm.

[0011] In some embodiments of this application, the specific exposure areas are uniformly distributed with the center of the wafer as the center.

[0012] In some embodiments of this application, the specific exposure area is the region at the edge of the wafer that does not include the positioning notch.

[0013] In some embodiments of this application, the specific exposure areas are symmetrically distributed relative to the two center lines of the wafer.

[0014] In some embodiments of this application, at least two of the specific exposure areas are located on one of the center lines of the wafer.

[0015] In some embodiments of this application, the specific exposure area includes the region where the positioning edge is located.

[0016] In some embodiments of this application, the set value is 1% to 5% of the total chip design on the entire wafer.

[0017] The contact hole exposure method described in this application involves setting a specific exposure area at the edge of the wafer. During the process of forming the contact hole, a selected exposure area is chosen within this specific exposure area. This selected exposure area is rectangular or square, and the number of defective chips formed within the specific exposure area is less than a set value. This method avoids defect sources formed at the wafer edge and ensures a high yield of chips. Attached Figure Description

[0018] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale. Wherein:

[0019] Figure 1 This is a schematic diagram of the cross-sectional structure of a wafer;

[0020] Figures 2 to 4 This is a schematic diagram of the wafer edge region during the contact hole formation process.

[0021] Figure 5 for Figure 3 Scanning electron microscope (SEM) image of the corresponding wafer edge region;

[0022] Figure 6 This is a diagram showing the distribution of chip defects in the wafer edge region caused by the absence of tungsten in the contact holes and the absence of the upper Al / Cu metal layer during chip manufacturing.

[0023] Figure 7 This is a topographic diagram of the defect;

[0024] Figure 8 This is a schematic diagram of the wafer planar structure described in an embodiment of this application;

[0025] Figure 9 This is a distribution diagram of the wafer body region and wafer edge region as described in the embodiments of this application;

[0026] Figure 10 This is a schematic diagram of another wafer planar structure described in an embodiment of this application;

[0027] Figure 11 A schematic diagram of a wafer planar structure as described in an embodiment of this application;

[0028] Figure 12a and Figure 12b These are wafer surface defect maps from the prior art and wafer surface defect maps from embodiments of this application, respectively. Detailed Implementation

[0029] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0030] In the back-end processes of current mature chip manufacturing technology, the Ti / TiN bonding layer is usually deposited directly onto the wafer surface. However, the metal layer (tungsten pillar, Al / Cu, etc.) is often underfilled in the wafer edge area, resulting in film defects (film inhomogeneity). This leads to insufficient interlayer support, and after etching and cleaning processes, the Ti / TiN layer in the wafer edge area is easily peeled off, becoming a defect source and causing a loss in the yield of the product chip.

[0031] Figure 1This is a schematic diagram of a cross-sectional structure of a wafer. The wafer includes a main wafer region 101 and a wafer edge region 102. Both the main wafer region 101 and the wafer edge region 102 include a substrate 100 and a dielectric layer 110 located on the substrate 100. Active devices, passive devices, etc., are formed in the substrate 100, and interconnect structures, etc., are formed in the dielectric layer 110. For simplicity, the accompanying drawing is attached. Figure 2 To be continued Figure 4 The structure of the wafer edge region 102 is shown only schematically.

[0032] Reference Appendix Figure 2 The dielectric layer 110 has contact holes 111 formed within it. In the wafer edge region 102, when the structure of the contact holes 111 is relatively dense, the adhesive layer 120 cannot effectively and uniformly cover the inner wall of the contact holes 111, but only covers part of the sidewall of the contact holes 111, and is largely deposited on the surface of the dielectric layer 110. In the subsequent process of depositing a metal layer 130 (e.g., tungsten, aluminum, and copper) in the contact holes, the metal layer 130 also cannot be uniformly and effectively filled in the contact holes 111, but continues to accumulate on the surface of the dielectric layer 110. Similarly, the film layers subsequently deposited in the wafer edge region 102, such as the second adhesive layer 140, the insulating material layer 150, and the third adhesive layer 160, also cannot be effectively filled, and are sparsely and irregularly accumulated in the wafer edge region 102.

[0033] Reference Appendix Figure 3 As shown, this is an appendix. Figure 2 The diagram shows the structure of the wafer edge region after etching. The third adhesive layer 160, the insulating material layer 150, the second adhesive layer 140, and a portion of the metal layer 120 are etched away to form trenches 170. (See attached diagram.) Figure 4 After a further cleaning process, the remaining insulating material layer 150 and metal layer 120 after etching are removed, leaving behind detached adhesive layer material 180. This detached adhesive layer material acts as a defect source in subsequent processes, causing contamination not only in parts of the chip at the wafer edge but also in the entire main area of ​​the wafer. (See attached reference.) Figure 5 As shown, Figure 3 The scanning electron microscope (SEM) image of the corresponding wafer edge region shows that the contact holes in the edge region are not effectively filled by the film layers, which are piled up on the surface of the dielectric layer, and the surface of each film layer is uneven.

[0034] Reference Appendix Figure 6The image shows the chip defect distribution in the wafer edge region caused by tungsten loss within contact holes and the absence of the upper Al / Cu metal layer during chip manufacturing. It can be seen that the contamination source film in the wafer edge region moves to the main wafer region in subsequent processes, resulting in numerous defects in the main wafer region as well. Figure 7 The applicant analyzed the elemental composition of the defect and found that the main components of the defect are Ti, N, and Si, proving that the defect is mainly the peeled-off adhesive layer.

[0035] Based on the analysis and research of the above-mentioned defects, the inventors proposed a contact hole structure confined exposure method to improve the yield of MOS power integrated devices, which is especially suitable for integrated devices with high-density contact hole structures.

[0036] The method for exposing contact holes described in this application includes: (refer to Appendix) Figure 8 As shown, a wafer is provided, the wafer including a main wafer region 11 and a wafer edge region 12, the wafer edge region 12 will form yield chips and defective chips; a specific exposure area 121 is set in the wafer edge region, in the process of exposing the mask pattern of the contact hole, a selected exposure area 1211 is selected in the specific exposure area 121 for exposure, the selected exposure area 1211 is rectangular or square, the selected exposure area 1211 makes the number of defective chips formed in the specific exposure area less than a set value.

[0037] like Figure 8 As shown in the embodiments of this application, the wafer includes a main wafer region 11 and a wafer edge region 12. The main wafer region 11 refers to the region containing only yield-quality chips, while the wafer edge region 12 includes yield-quality chips, as well as complete invalid chips used for FEC dicing and invalid chips used for physical wafer cutting. In this embodiment, all chips except yield-quality chips are considered invalid chips. Both the main wafer region 11 and the wafer edge region 12 are divided into several exposure units (shots), and the area of ​​each shot is substantially the same at different locations on the same wafer. (See attached figure.) Figure 9 As shown, each shot that constitutes the main wafer region 11 and the wafer edge region 12 is marked.

[0038] In the prior art, when forming contact holes on a dielectric layer, a patterned photoresist mask layer needs to be formed on the dielectric layer first. This photoresist mask layer covers the entire wafer. Whether in the main wafer region or the wafer edge region, the photomask used to form the patterned photoresist mask layer is the same. That is, the mask pattern formed in the main wafer region 11 and the wafer edge region 12 through the exposure and development process is identical. Therefore, defect sources are generated in the wafer edge region 12.

[0039] In this embodiment, a specific exposure area 121 is first set in the wafer edge region. During the process of exposing the mask pattern for forming contact holes, a selected exposure area 1211 is chosen within the specific exposure area 121 for exposure. The selected exposure area 1211 is rectangular or square, and the selected exposure area 1211 ensures that the number of defective chips formed within the specific exposure area is less than a set value. That is, in the specific exposure area 121, except for the selected exposure area 1211, other areas do not need to be exposed, thereby reducing or avoiding defect sources in the wafer edge region 12. The selection rule for the selected exposure area 1211 is to reduce the exposure area of ​​the wafer edge region 12 without reducing the yield of the chips. Therefore, the selection of the selected exposure area 1211 needs to ensure the number of yield chips as much as possible while reducing defect sources.

[0040] In this embodiment, the number of invalid chips in the selected exposure area 1211 is less than a set value, which is 1% to 5% of the total number of chips designed for the entire wafer, such as 2%, 3%, and 4%. In some embodiments of this application, the invalid chips are chips that are not exposed during the process of forming the mask pattern for the contact holes, thus preventing the formation of the designed contact holes at the designed locations. Yield chips refer to chips in areas where the entire process flow is followed.

[0041] The selected exposure area 1211 can be rectangular or square, and the area of ​​the selected exposure area 1211 can be an integer multiple of the area of ​​a single complete chip in the area, which can maximize the number of yield chips in the area.

[0042] In some embodiments of this application, the specific exposure area 121 is a region where the uniformity of the metal layer deposited at the wafer edge is less than a set uniformity in the metal layer deposition process for forming contact holes. At the wafer edge, the uniformity of the adhesion layer and the metal layer deposition varies at different locations, and the degree of film defects also differs. This application selects a specific exposure area based on the film uniformity of the metal layer deposited at different locations at the wafer edge. If the uniformity of the metal layer deposited at the wafer edge is greater than the set uniformity requirement, it is considered that no defect source is generated, or the occurrence of defect sources meets production requirements. The corresponding area is exposed in the same way as the main wafer area to maximize the number of yield chips. If the metal deposition uniformity at the wafer edge is less than the set uniformity requirement, it is considered that the adhesion layer in that area will become a defect source after subsequent etching and cleaning processes. Therefore, the exposure is adjusted to form the photoresist mask, exposing only the selected exposure area 1211, and not exposing other areas. The photoresist used in the photoresist mask is a positive photoresist.

[0043] In some embodiments of this application, the uniformity of the metal layer is determined by the surface morphology of the metal layer, for example, by SEM images. In the wafer edge region, the surface morphology is uneven; areas with larger undulations are areas of low uniformity, and areas with smaller undulations are areas of high uniformity. The set uniformity requires the surface height difference of the metal layer at different locations to be between 150 nm and 200 nm. For example, the set uniformity is a surface height difference of 160 nm, 170 nm, or 180 nm for the metal layer deposited at the wafer edge. Regions with a metal layer uniformity less than 160 nm, 170 nm, or 180 nm deposited at the wafer edge are selected as specific exposure areas 121.

[0044] In some embodiments of this application, the specific exposure area 121 is uniformly distributed around the center of the wafer. For example, see attached... Figure 10 As shown, the specific exposure area 121 includes three regions (see attached diagram). Figure 10 (As shown in the three dashed boxes), where the size of each dashed box is an integer multiple of the size of an exposure unit (shot). The three regions are evenly distributed along the edge of the wafer. Since the actual specific exposure area circled by the shot differs from the area of ​​121, the uniform distribution described in this embodiment refers to a relatively uniform distribution, not an absolutely uniform one.

[0045] In some embodiments of this application, the specific exposure area 121 may also include at least four, which are relatively evenly distributed in the wafer edge region.

[0046] In some embodiments of this application, the specific exposure area 121 does not include the region where the wafer edge has a positioning notch; that is, the specific exposure area is the region of the wafer edge that does not have a positioning notch. In other embodiments of this application, the specific exposure area 121 is preferably selected from the wafer edge region including the region where the positioning flat is located. After avoiding the region containing the notch, the specific exposure area 121 is preferably selected from symmetrical regions. The shape of the symmetrical region, the number of chips it includes, the chip distribution, and the situation of each shot are relatively consistent, which can simplify the pattern and structure of the photomask used in the exposure process.

[0047] In some embodiments of this application, the specific exposure areas 121 are symmetrically distributed relative to the two center lines of the wafer along the parallel dicing direction. For example, see attached... Figure 8As shown, two center lines are selected that pass through the wafer center and are perpendicular to each other in the horizontal (x-axis) and vertical (y-axis) directions. The specific exposure areas 121 are then symmetrically distributed relative to either the horizontal or vertical center line. (See attached diagram.) Figure 8 The area including the positioning edge is usually located in the shot where the vertical center line intersects with the wafer. There are multiple shots with the same positioning edge, which can make the area of ​​the selected exposure area 1211 basically the same, simplifying the pattern and structure of the photomask used in the exposure process.

[0048] In some embodiments of this application, at least two of the specific exposure areas 121 are located on one of the center lines of the wafer. For example... Figure 8 As shown, the vertical centerline includes at least two specific exposure areas 121.

[0049] In some embodiments of this application, the horizontal centerline and the vertical centerline of the wafer divide the wafer into four regions: one, two, three, and four. At least two of the specific exposure regions 121 are located in the region where the positioning edge of the wafer is located and in positions symmetrical to the region where the positioning edge is located.

[0050] In some embodiments of this application, the selected exposure area 1211 rectangles are all the same size. This allows for consistent mask pattern shapes and structures used in the exposure process, resulting in more consistent job conditions during exposure and making the entire process more convenient and time-saving.

[0051] In some embodiments of this application, the size of the selected exposure area 1211 rectangle varies. The area to be exposed can be determined based on the size of the selected exposure area 1211 at different locations, maximizing the increase in the number of yield chips and minimizing the number of defective chips.

[0052] Reference Appendix Figure 11The diagram illustrates the distribution of specific exposure areas 121 and selected exposure areas 1211 in one embodiment of this application. The region 122 containing the notch is not considered a specific exposure area, while regions 121a and 121b containing the positioning edges are preferably specific exposure areas. The area and number of selected exposure areas 1211 should aim to maximize the number of yield chips on the wafer while minimizing the number of defect sources. For example, two rectangular regions are selected as selected exposure areas 1211 from specific exposure areas 121a and 121b, respectively. The size of each selected exposure area 1211 is 1×5, equivalent to the size of 5 complete chips (dies). Specific exposure area 121c is 4×2, equivalent to the size of 8 complete chips (dies). Specific exposure area 121d is 1×5, equivalent to the size of 5 complete chips (dies). Specific exposure area 121e is 3×3, equivalent to the size of 9 complete chips (dies). Specific exposure area 121f is 1×2, equivalent to the size of 2 complete chips (dies). In this embodiment, by selecting the specific exposure area 121 and the selected exposure area 1211, the sources of defects are reduced, and the number of yield wafers in the wafer edge region is maximized. Figure 12a and 12b As shown, this reduces the number of wafer surface defects from existing technologies ( Figure 12a The number of 52 has been reduced to the embodiments of this application ( Figure 12b ) 2.

[0053] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0054] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.

[0055] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," as used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0056] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.

[0057] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

Claims

1. A method for exposing a contact hole, characterized in that, include: A wafer is provided, the wafer including a wafer body region and a wafer edge region, the wafer edge region being where invalid chips are formed; A specific exposure area is set in the edge region of the wafer. In the process of forming contact holes, a selected exposure area is selected in the specific exposure area for exposure. The selected exposure area is rectangular or square. The selected exposure area makes the number of invalid chips formed in the specific exposure area less than a set value. The specific exposure area is the area where the uniformity of the metal layer deposited at different positions in the edge region of the wafer is lower than the set uniformity in the metal layer deposition process of forming contact holes.

2. The exposure method for contact holes according to claim 1, characterized in that, The uniformity of the metal layer is determined by the surface morphology of the metal layer, wherein the set uniformity requires that the surface height difference of the metal layer at different locations be between 150nm and 200nm.

3. The exposure method for contact holes according to claim 2, characterized in that, The specific exposure area is uniformly distributed with the center of the wafer as the center.

4. The exposure method for contact holes according to claim 3, characterized in that, The specific exposure area is the region at the edge of the wafer that does not include the positioning notch.

5. The exposure method for contact holes according to claim 2, characterized in that, The specific exposure areas are symmetrically distributed relative to the two center lines of the wafer.

6. The exposure method for contact holes according to claim 5, characterized in that, At least two of the specific exposure areas are located on one of the center lines of the wafer.

7. The exposure method for contact holes according to claim 1, characterized in that, The specific exposure area includes the region where the positioning edge is located.

8. The exposure method for contact holes according to claim 1, characterized in that, The selected exposure area rectangles are all the same size.

9. The exposure method for contact holes according to claim 1, characterized in that, The set value is 1% to 5% of the total number of chips designed for the entire wafer.

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