An automotive chip functional safety verification platform, method, device and medium

Abstract

A functional safety verification platform, method, device and medium for a vehicle chip, the verification platform comprising a fault node extraction module, a fault simulation module and a result processing and report output module, which respectively extract faults in accordance with the requirements of the ISO26262 standard, perform multi-process parallel simulation acceleration and classify faults in accordance with the requirements of the ISO26262 standard, obtain functional safety indicators such as diagnostic coverage (DC) of the safety mechanism of the design under test, single-point fault metric (SPFM) and latent fault metric (LFM), and form a functional safety simulation analysis report; the fault node extraction and fault state classification modules all meet the requirements of the ISO26262 standard, overcoming the fact that existing technologies do not consider the related requirements of the ISO26262 standard; the parallel fault simulation acceleration method can improve the efficiency of fault simulation compared with existing technologies; the verification device and medium can perform functional safety verification of a vehicle chip based on the verification platform; and the present application has the advantages of strong pertinence of fault node extraction, high simulation efficiency and good reliability.

Description

Technical Field

[0001] This invention belongs to the field of functional safety verification technology for automotive-grade chips, and particularly relates to a functional safety verification platform, method, equipment and medium for automotive-grade chips. Background Technology

[0002] Functional safety in automotive-grade chips refers to the hardening of relevant functional modules during the development of automotive-grade chips using functional safety analysis methodologies. This ensures that the chip will not malfunction due to random hardware failures, thereby preventing threats to driver safety. Functional safety verification is the validation of the effectiveness of these hardening measures on the relevant functional modules.

[0003] Fault injection-based reliability assessment methods have played a positive role in reliability research in the past, serving as an effective means of verifying the reliability of models such as microprocessors and digital systems. Fault injection refers to the process of intentionally generating faults according to a selected fault model and applying them to a target system running a specific workload to accelerate the occurrence of errors and failures. Simultaneously, the system's design response and behavior to the injected faults are observed and statistically analyzed to provide relevant results to the experimenter. Fault injection tools can be categorized into hardware-based, software-based, and simulation-based methods based on their implementation. Hardware-based methods primarily inject faults at the hardware level using communication interfaces, pins, or host computers. Software-based methods inject faults within the software or operating system to evaluate software redundancy mechanisms or system robustness. Simulation-based methods simulate fault injection by modifying simulation data within a simulator to simulate the behavior of the tested object under fault conditions.

[0004] The existing technical solution mainly consists of six modules, which are divided into three parts: the fault injection preparation part, including the graphical interface, the syntax and semantic analysis tree, and the tool configuration; the fault injection control part, including fault injection management and the Modelsim simulator; and the result analysis part, including the result analyzer.

[0005] Disadvantage 1: Existing technologies do not take into account the application context of automotive functional safety certification. The research background of existing technologies mainly focuses on the impact of high-energy particles or neutrons on soft error effects of integrated circuits in near-Earth orbit operation scenarios such as aerospace and aviation. Therefore, the relevant functions of existing technologies differ from the functions required to be implemented in automotive functional safety standards.

[0006] Disadvantage 2: Existing technologies mention less about parallel fault simulation acceleration and fault injection space reduction, because fault injection has the problem of fault space "explosion". Therefore, it is necessary to consider how to reduce the fault injection space. However, existing technologies mention less about related reduction and acceleration technologies and they are not widely used, making it difficult to support large-scale fault injection activities.

[0007] Disadvantage 3: Existing technologies lack relevant methods for classifying fault states that meet automotive-grade functional safety standards. According to the definitions and requirements of the ISO 26262 standard, the impact of each injected fault on the circuit needs to be classified into corresponding fault states. Furthermore, based on the fault states, corresponding safety indicators such as fault coverage or diagnostic coverage of safety mechanisms need to be calculated to assess the chip's safety level. However, existing technologies primarily evaluate fault results based on indicators such as the chip's soft error rate, system fault detection rate, and recovery rate. Therefore, current technologies lack fault state classification techniques that meet automotive-grade functional safety standards.

[0008] Patent application CN116127883A discloses a fault injection simulation system and method for automotive-grade chips. By modularizing the automotive-grade chip, the complex automotive-grade chip is transformed into smaller modules. Through module-level simulation, functional simulation and fault injection simulation of the automotive-grade chip are realized, achieving comprehensive coverage of fault diagnosis. The overall SOC chip can easily reach the ASIL-D safety level. However, this invention also does not realize the automatic fault node extraction function that meets the requirements of ISO26262 standard, nor the related functions of outputting functional safety simulation verification indicators. Summary of the Invention

[0009] To overcome the shortcomings of the prior art, the present invention aims to provide a functional safety verification platform, method, device, and medium for automotive-grade chips. Through three modules—a fault node extraction module, a fault simulation module, and a result processing and report output module—faults are extracted, simulations are accelerated, and faults are classified. This yields functional safety indicators such as diagnostic coverage (DC), single point of failure metric (SPFM), and latent failure metric (LFM) for the safety mechanism of the design under test, and generates a functional safety simulation analysis report. The platform offers advantages such as automatically extracting fault nodes compliant with ISO 26262 standards, automatically generating injection files for two fault types compliant with ISO 26262 standards, improving the efficiency of fault simulation through parallel fault simulation, and outputting functional safety indicators for automotive-grade chips.

[0010] To achieve the above objectives, the present invention adopts the following technical solution:

[0011] A functional safety verification platform for automotive-grade chips includes a fault node extraction module, a fault simulation module, and a result processing and report output module. The fault node extraction module extracts fault nodes from the design in accordance with the requirements of ISO26262 standard. The fault simulation module combines multi-process parallel simulation acceleration and fault classification in accordance with the requirements of ISO26262 standard to obtain functional safety indicators such as diagnostic coverage (DC), single point of failure metric (SPFM), and latent failure metric (LFM) of the safety mechanism of the design under test. Finally, the result processing and report output module generates a functional safety simulation analysis report.

[0012] The fault node extraction module includes a lexical analysis section and a fault node extraction section, and conforms to the requirements of the ISO26262 standard, wherein:

[0013] The lexical analysis section performs lexical parsing on the input circuit design source file. It uses regular expression matching syntax to match variable names before and after keywords in Verilog syntax to obtain circuit design information, including input / output port names, connection names, and other information.

[0014] The fault node extraction section is divided into gate-level fault node extraction mode (GL) and register-transfer-level mode (RTL), wherein:

[0015] The gate-level fault node extraction mode (GL) extracts the input ports, output ports, and net variables in the design source file as nodes with permanent faults, and extracts the output terminals of the timing units in the design source file as nodes with transient faults.

[0016] Register Transfer Level (RTL) mode extracts input ports, output ports, net variables, and register type variables from the design source file as nodes of permanent faults, and extracts register type variables as nodes of transient faults.

[0017] The fault simulation module implements fault injection and fault simulation functions according to the injection mode. The fault injection mode includes two modes: user-defined mode and traversal injection mode. The user-defined mode allows users to form a fault list of fault activities by setting the injection position, injection time and fault type in the node database obtained by the fault node extraction module according to the functional safety verification requirements. The traversal injection mode automatically combines the node database extracted by the fault extraction module and injects all types of faults into all nodes in the database.

[0018] The result processing and report output module analyzes the fault-free and faulty simulation results at specified observation and detection points, classifies fault types according to the requirements for fault states in the ISO26262 standard, and calculates corresponding indicators such as diagnostic coverage (DC), single point of failure metric (SPFM), and latent failure metric (LFM) for the design under test based on different fault states in the fault list.

[0019] The fault node extraction section supports the extraction of cell ports, nets, and register variable nodes, including register transfer level and gate level netlists.

[0020] The injection location set in the node database obtained from the fault node extraction module includes detection point location information and observation point location information; the injection time and fault type include permanent faults or transient faults.

[0021] The verification method based on the above-mentioned functional safety verification platform for automotive-grade chips includes the following specific steps:

[0022] Step 1: Extraction of faulty nodes, the specific process is as follows:

[0023] First, the user modifies the relevant environment variables in the configuration file of the fault node extraction module, including the location of the source file and the design name;

[0024] Secondly, the node extraction script is run. After the fault node extraction module reads the circuit design file, it will select the gate-level or register-transfer-level working mode according to the type of design file input by the user.

[0025] Then, after copying the source file to the working directory, the lexical analysis part under the fault node extraction module is used to perform lexical analysis on the design file to obtain the circuit design information. The design information of multiple circuit modules contained in the design source file is merged to obtain node data. That is, node data is extracted through GL and RTL modes, and the node database is formed by grouping and organizing according to the hierarchical structure of the modules.

[0026] Finally, based on the node selection information in the user's configuration file, select a portion of the nodes in the node data to generate a fault injection list, thus completing the extraction of fault node information;

[0027] Step 2: The fault simulation module performs the simulation. The specific process is as follows:

[0028] The fault injection generation script combines the fault node information extracted by the fault extraction module in step one with the fault type and location information injected by the user in the fault simulation module to generate a fault model file that conforms to the ISO26262 standard. The script automatically configures the path of the design source file and calls the digital circuit simulator to perform fault-free simulation. Based on the detection point location information and observation point location information in the configuration file of the fault simulation module, the simulation results at the two locations are saved to obtain fault-free simulation data, which is used for comparison with subsequent faulty simulation data.

[0029] After the fault-free simulation is completed, the digital simulator will call the fault model file in the fault-free simulation process to realize fault simulation.

[0030] Step 3: The result processing and report output module classifies the fault types. The specific process is as follows:

[0031] The above-mentioned fault types are determined by the difference in simulation data at the detection point and the observation point between the fault injection simulation and the fault-free simulation in step two; the faults are classified into safety detection faults, safety undetected faults, dangerous detection faults, and dangerous undetected faults.

[0032] For safety detection failures, the data values ​​of the two simulations are the same at the observation point, but different at the detection point; for safety not detected failures, the data values ​​of the two simulations are the same at both the observation and detection points; for hazard detection failures, the data values ​​of the two simulations are different at both the observation and detection points; for hazard not detected failures, the data values ​​of the two simulations are different at both the observation and detection points.

[0033] Based on the ISO 26262 standard and the Failure Mode Assessment and Diagnostic Coverage Analysis (FMEDA) methodology, indicators such as diagnostic coverage (DC), single point of failure metric (SPFM), and latent failure metric (LFM) are calculated, and a functional safety simulation analysis report is generated.

[0034] According to the above verification method for the functional safety verification platform for automotive-grade chips, the simulation process of the fault simulation module in step two adopts a multi-process parallel simulation acceleration method. Specifically, it utilizes the independent characteristics between each fault simulation in the fault simulation activity, and uses a multi-process approach under the Linux operating system to establish a separate fault simulation process for each fault, thereby realizing a multi-process parallel fault simulation method.

[0035] The verification equipment for the aforementioned automotive-grade chip functional safety verification platform includes:

[0036] Memory, used to store computer programs;

[0037] A processor, configured to implement the verification method of the automotive-grade chip functional safety verification platform according to any one of claims 1 to 8 when executing the computer program.

[0038] A computer-readable storage medium for storing a computer program, which, when executed by a processor, enables functional safety verification of automotive-grade chips based on an automotive-grade chip functional safety verification platform.

[0039] Compared with the prior art, the present invention has the following advantages:

[0040] 1. Based on the requirements of ISO 26262, a complete fault equivalent model is constructed that conforms to the ISO 26262 standard and is compatible with mainstream digital integrated circuit simulators. Fault modeling, failure assessment, and safety analysis are performed for all possible failure scenarios in both permanent and transient fault models. This overcomes the limitations of existing technologies that do not consider compliance with the ISO 26262 standard and only model some failure scenarios in the two fault models. This invention is geared towards functional safety verification of automotive-grade chips, and the fault state classification modules all meet the fault state requirements of the ISO 26262 standard.

[0041] 2. This invention automatically extracts fault nodes that meet the requirements of the ISO26262 standard through the gate-level fault node extraction mode (GL) and register transfer level mode (RTL), which helps to improve the efficiency of fault simulation.

[0042] 3. This invention effectively accelerates the fault simulation process. The proposed parallel fault simulation acceleration method can improve the efficiency of fault simulation compared with the existing serial fault simulation technology.

[0043] 4. Based on the requirements of the ISO26262 standard, after the design of an automotive-grade chip is completed, functional safety verification of the safety mechanisms in the design is carried out. The functional safety verification platform for automotive-grade chips proposed in this invention can help engineers simulate and evaluate a series of functional safety indicators of the designed automotive-grade chips during the design phase.

[0044] 5. This invention analyzes the fault simulation results according to the requirements of ISO26262 standard to obtain the relevant functional safety indicators of the evaluation object; according to the requirements of ISO26262 standard, the fault simulation results are analyzed, and the faults are divided into different fault states such as safe fault, dangerous fault and latent fault, and the corresponding functional safety indicators are calculated according to the number of fault states.

[0045] In summary, this invention, based on the requirements of ISO26262 standard, addresses the problem of "exploding" fault space in fault injection, which is required by automotive functional safety standards. It reduces the fault injection space, supports large-scale fault injection activities, classifies fault states based on fault simulation results, and calculates corresponding functional safety indicators. This overcomes the lack of fault state classification that meets automotive-grade functional safety standards in existing technologies. It has the advantages of highly targeted fault node extraction, high simulation efficiency, and good reliability. Attached Figure Description

[0046] Figure 1 This is the functional safety simulation platform proposed in this invention.

[0047] Figure 2 This is a flowchart for extracting fault nodes.

[0048] Figure 3 This is a schematic diagram illustrating the principle of fault node extraction.

[0049] Figure 4 This is a flowchart of fault injection and invalid fault screening.

[0050] Figure 5 This is a schematic diagram of fault model generation and injection.

[0051] Figure 6 This is a schematic diagram of the generated fault list.

[0052] Figure 7 It is a flowchart for simulation data analysis and statistics.

[0053] Figure 8 This is a schematic diagram of the overall functional safety verification process. Detailed Implementation

[0054] The present invention will now be described in further detail with reference to the accompanying drawings.

[0055] like Figure 1As shown, a functional safety verification platform for automotive-grade chips includes a fault node extraction module, a fault simulation module, and a result processing and report output module. The fault node extraction module extracts fault nodes from the design in accordance with the requirements of the ISO26262 standard. The fault simulation module combines multi-process parallel simulation acceleration and fault classification in accordance with the requirements of the ISO26262 standard to obtain functional safety indicators such as diagnostic coverage (DC), single point of failure metric (SPFM), and latent failure metric (LFM) of the safety mechanism of the design under test. Finally, the result processing and report output module generates a functional safety simulation analysis report.

[0056] The fault node extraction module includes a lexical analysis section and a fault node extraction section, and conforms to the requirements of the ISO26262 standard. (See [link to relevant documentation]). Figure 2 , Figure 3 ,in:

[0057] The lexical analysis section performs lexical parsing on the input circuit design source file. It uses regular expression matching syntax to match variable names before and after keywords in Verilog syntax to obtain circuit design information, including input / output port names, connection names, and other information.

[0058] The fault node extraction section is divided into gate-level fault node extraction mode (GL) and register-transfer-level mode (RTL), wherein:

[0059] The gate-level fault node extraction mode (GL) extracts the input ports, output ports, and net variables in the design source file as nodes with permanent faults, and extracts the output terminals of the timing units in the design source file as nodes with transient faults.

[0060] Register Transfer Level (RTL) mode extracts input ports, output ports, net variables, and register type variables from the design source file as nodes of permanent faults, and extracts register type variables as nodes of transient faults.

[0061] See Figure 4 , Figure 5 As shown, the fault simulation module implements fault injection and fault simulation functions according to the injection mode. The fault injection mode includes two modes: user-defined and traversal injection. The user-defined mode allows users to define the injection location (including detection point location information and observation point location information), injection time, and fault type (permanent or transient) in the node database obtained from the fault node extraction module, according to the functional safety verification requirements, to form a fault list of fault activities. See [link to relevant documentation]. Figure 6 Iterates through the injection process, automatically combining the node database extracted by the fault extraction module to inject all types of faults into all nodes in the database.

[0062] The result processing and report output module analyzes the fault-free and faulty simulation results at specified observation and detection points, classifies fault types according to the requirements for fault states in the ISO26262 standard, and calculates corresponding indicators such as diagnostic coverage (DC), single point of failure metric (SPFM), and latent failure metric (LFM) for the design under test based on different fault states in the fault list.

[0063] The fault node extraction section supports the extraction of cell ports, nets, and register variable nodes, including register transfer level and gate level netlists.

[0064] The injection location set in the node database obtained from the fault node extraction module includes detection point location information and observation point location information; the injection time and fault type include permanent faults or transient faults.

[0065] The verification method based on the above-mentioned functional safety verification platform for automotive-grade chips includes the following specific steps:

[0066] Step 1: Extraction of faulty nodes, such as... Figure 2 , Figure 3 As shown, the specific process is as follows:

[0067] First, the user modifies the relevant environment variables in the configuration file of the fault node extraction module, including the location of the source file and the design name;

[0068] Secondly, the node extraction script is run. After the fault node extraction module reads the circuit design file, it will select the gate-level or register-transfer-level working mode according to the type of design file input by the user.

[0069] Then, after copying the source file to the working directory, the lexical analysis part under the fault node extraction module is used to perform lexical analysis on the design file to obtain the circuit design information. The design information of multiple circuit modules contained in the design source file is merged to obtain node data. That is, node data is extracted through GL and RTL modes, and the node database is formed by grouping and organizing according to the hierarchical structure of the modules.

[0070] Finally, based on the node selection information in the user's configuration file, select a portion of the nodes in the node data to generate a fault injection list, thus completing the extraction of fault node information;

[0071] like Figure 4 , Figure 5As shown, the fault simulation module implements fault injection and fault simulation functions according to the injection mode. The fault injection mode includes two modes: user-defined and traversal injection. The user-defined mode allows users to define the injection location (including detection point location information and observation point location information), injection time, and fault type (permanent or transient) in the node database obtained from the fault node extraction module, according to the functional safety verification requirements, to form a fault list of fault activities. See [link to relevant documentation]. Figure 6 Iterates through the injection process, automatically combining the node database extracted by the fault extraction module to inject all types of faults into all nodes in the database.

[0072] Step 2: The fault simulation module performs simulation, such as... Figure 7 As shown, the specific process is as follows:

[0073] The fault injection generation script combines the fault node information extracted by the fault extraction module in step one with the fault type and location information injected by the user in the fault simulation module to generate a fault model file that conforms to the ISO26262 standard. The script automatically configures the path of the design source file and calls the digital circuit simulator to perform fault-free simulation. Based on the detection point location information and observation point location information in the configuration file of the fault simulation module, the simulation results at the two locations are saved to obtain fault-free simulation data, which is used for comparison with subsequent faulty simulation data.

[0074] After the fault-free simulation is completed, the digital simulator will call the fault model file in the fault-free simulation process to realize fault simulation.

[0075] Step 3: The result processing and report output module classifies the fault types, such as... Figure 8 As shown, the specific process is as follows:

[0076] The above-mentioned fault types are determined by the difference in simulation data at the detection point and the observation point between the fault injection simulation and the fault-free simulation in step two; the faults are classified into safety detection faults, safety undetected faults, dangerous detection faults, and dangerous undetected faults.

[0077] For safety detection failures, the data values ​​of the two simulations are the same at the observation point, but different at the detection point; for safety not detected failures, the data values ​​of the two simulations are the same at both the observation and detection points; for hazard detection failures, the data values ​​of the two simulations are different at both the observation and detection points; for hazard not detected failures, the data values ​​of the two simulations are different at both the observation and detection points.

[0078] Based on the ISO 26262 standard and the Failure Mode Assessment and Diagnostic Coverage Analysis (FMEDA) methodology, indicators such as diagnostic coverage (DC), single point of failure metric (SPFM), and latent failure metric (LFM) are calculated, and a functional safety simulation analysis report is generated.

[0079] The simulation process of the fault simulation module adopts a multi-process parallel simulation acceleration method. Specifically, it utilizes the independent characteristics between each fault simulation in the fault simulation activity, and uses a multi-process approach under the Linux operating system to establish a separate fault simulation process for each fault, thereby realizing a multi-process parallel fault simulation method.

[0080] In summary, this invention, based on the requirements of ISO26262 standard, addresses the problem of "exploding" fault space in fault injection, which is required by automotive functional safety standards. It reduces the fault injection space, supports large-scale fault injection activities, classifies fault states based on fault simulation results, and calculates corresponding functional safety indicators. This overcomes the lack of fault state classification that meets automotive-grade functional safety standards in existing technologies. It has the advantages of highly targeted fault node extraction, high simulation efficiency, and good reliability.

[0081] Table 1 Fault Node Extraction Types

[0082]

Claims

1. A functional safety verification platform for automotive-grade chips, characterized in that, It includes a fault node extraction module, a fault simulation module, and a result processing and report output module; The fault node extraction module includes a lexical analysis section and a fault node extraction section, and conforms to the requirements of the ISO26262 standard: the lexical analysis section performs lexical analysis on the input circuit design source file, and obtains the input and output ports and connection information by matching the variable names before and after Verilog syntax keywords through regular expressions; the fault node extraction section is divided into gate-level fault node extraction mode (GL) and register transfer level mode (RTL). In GL mode, input ports, output ports, and net variables are extracted as permanent fault nodes, and the output terminals of timing units are extracted as transient fault nodes. In RTL mode, input ports, output ports, net variables, and register type variables are extracted as permanent fault nodes, and register type variables are extracted as transient fault nodes. The fault simulation module combines Linux multi-process parallel simulation acceleration to perform fault injection and simulation in accordance with the ISO26262 standard, either in user-defined mode or traversal injection mode. The result processing and report output module compares the results of fault-free simulation and faulty simulation at specified observation points and detection points. Based on the ISO26262 standard, the faults are classified into four categories: safe detection faults, safe undetected faults, dangerous detection faults, and dangerous undetected faults. Then, based on FMEDA, the diagnostic coverage (DC), single point of failure (SPFM), and potential fault (LFM) of the design under test are calculated to form a functional safety simulation analysis report.

2. The functional safety verification platform for automotive-grade chips according to claim 1, characterized in that, The fault node extraction module includes a lexical analysis section and a fault node extraction section, and conforms to the requirements of the ISO26262 standard, wherein: The lexical analysis section performs lexical parsing on the input circuit design source file. It obtains the circuit design information, including input and output port names and connection names, by matching variable names before and after keywords in Verilog syntax using regular expression matching syntax. The fault node extraction section is divided into gate-level fault node extraction mode (GL) and register-transfer level mode (RTL), where: The gate-level fault node extraction mode (GL) extracts the input ports, output ports, and net variables in the design source file as nodes with permanent faults, and extracts the output terminals of the timing units in the design source file as nodes with transient faults. Register Transfer Level (RTL) extracts input ports, output ports, net variables, and register type variables from the design source file as nodes of permanent faults, and extracts register type variables as nodes of transient faults.

3. The functional safety verification platform for automotive-grade chips according to claim 1, characterized in that, The fault simulation module implements fault injection and fault simulation functions according to the injection mode. The fault injection mode includes two modes: user-defined mode and traversal injection mode. The user-defined mode allows users to form a fault list of fault activities by setting the injection position, injection time and fault type in the node database obtained by the fault node extraction module according to the functional safety verification requirements. The traversal injection mode automatically combines the node database extracted by the fault extraction module and injects all types of faults into all nodes in the database.

4. The functional safety verification platform for automotive-grade chips according to claim 1, characterized in that, The result processing and report output module analyzes the fault-free and faulty simulation results at specified observation and detection points, classifies fault types according to the requirements for fault states in the ISO26262 standard, and calculates the corresponding diagnostic coverage (DC), single point fault metric (SPFM), and latent fault metric (LFM) for the design under test based on different fault states in the fault list.

5. The functional safety verification platform for automotive-grade chips according to claim 2, characterized in that, The fault node extraction section supports the extraction of cell ports, nets, and register variable nodes, including register transfer level and gate level netlists.

6. The functional safety verification platform for automotive-grade chips according to claim 3, characterized in that, The injection location set in the node database obtained from the fault node extraction module includes detection point location information and observation point location information; the injection time and fault type include permanent faults or transient faults.

7. The verification method for a functional safety verification platform for automotive-grade chips according to claim 2, characterized in that, The specific steps include: Step 1: Extract fault nodes using lexical analysis in GL / RTL dual mode, organize them into a node database according to module hierarchy, and generate a fault injection list; Step 2: Use the fault injection generation script to generate ISO26262 fault model files. First, run a fault-free simulation and save the observation point / detection point data. Then, call the simulator to run a fault-prone simulation for each fault separately. Step 3: Compare the differences between the observation point and the detection point for no fault / faulty conditions, and classify them into four categories: safe detection / safety not detected / hazardous detection / hazardous not detected. Calculate DC / SPFM / LFM according to ISO26262 and FMEDA and generate a report.

8. The verification method according to claim 7, characterized in that, Step 2 employs Linux multi-process parallelism: leveraging the independent nature of each fault simulation, a separate simulation process is created for each fault, and the fault-free simulation runs only once for reuse by all faults.

9. A verification device for a functional safety verification platform for automotive-grade chips, characterized in that, include: Memory, used to store computer programs; A processor, configured to perform functional safety verification of automotive-grade chips based on the verification platform of any one of claims 1 to 6 or the verification method of any one of claims 7 to 8 when executing the computer program.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium is used to store a computer program, which, when executed by a processor, is capable of performing functional safety verification of automotive-grade chips based on the verification platform of any one of claims 1 to 6 or the verification method of any one of claims 7 to 8.

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