Storage device instruction aggregation method and apparatus, computer device, and storage medium

Abstract

The application relates to the technical field of storage hardware, and discloses a storage device instruction aggregation method and device, computer equipment and a storage medium, the method comprising the following steps: acquiring a first number of submission instructions and the arrangement order of the submission instructions; executing the submission instructions to obtain the execution result of each submission instruction, generating a first number of completion instructions; in the case that all the execution results are execution successes, the first number of completion instructions are combined into a target completion instruction, and the target completion instruction is sent to a host end; in the case that the execution results are not all execution successes, a target position of the execution result when a first execution error occurs in the arrangement order is acquired, a target completion instruction and a failure instruction are determined according to the target position, and the target completion instruction and the failure instruction are sent to the host end or the failure instruction is sent to the host end. The application solves the problem that the CQE instructions of the storage device are returned to the host one by one, thereby reducing the throughput rate of a communication link.

Description

Technical Field

[0001] This invention relates to the field of storage hardware technology, and specifically to a storage device instruction aggregation method, apparatus, computer device, and storage medium. Background Technology

[0002] Communication between a Linux (an open-source operating system) host and a storage device based on the NVME (Non-Volatile Memory Express) protocol must be accomplished through an instruction queue located in the host memory. The instruction queue includes a commit queue and a completion queue.

[0003] Currently, the communication process between a Linux host and an NVMe-based storage device is as follows: The host needs to place the SQE (Submission Queue Entry) instruction to be executed by the storage device into the submission queue, and then instruct the storage device to read the SQE instruction from the submission queue. The controller inside the storage device reads the SQE instruction from the host's memory submission queue via PCIe (Peripheral Component Interconnect Express) messages, executes the instruction internally, and finally returns the completed instruction result, CQE (Completion Queue Entry), to the host's completion queue via PCIe messages, notifying the host that an I / O (Input / Output) interaction has been completed. In this process, the storage device's CQE instructions are returned to the host one by one, resulting in low throughput of the communication link, low I / O processing speed for the host, and high memory overhead.

[0004] Therefore, existing technologies suffer from the problem that CQE commands from storage devices are returned to the host one by one, resulting in low throughput of the communication link. Summary of the Invention

[0005] In view of this, the present invention provides a storage device instruction aggregation method, apparatus, computer device and storage medium to solve the problem that the low throughput of the communication link is caused by the CQE instructions of the storage device being returned to the host one by one.

[0006] In a first aspect, the present invention provides a storage device instruction aggregation method, which is applied to a storage device and includes:

[0007] Get the first number of commit commands and their order;

[0008] Execute the commit instructions, obtain the execution result of each commit instruction, and generate the first number of complete instructions;

[0009] If all execution results are successful, the first number of completion instructions are combined into a target completion instruction, and the target completion instruction is sent to the host.

[0010] If the execution results are not all successful, the target position of the first execution result that failed is obtained in the order of the order. The target completion instruction and failure instruction are determined according to the target position, and the target completion instruction and failure instruction are sent to the host or the failure instruction is sent to the host.

[0011] The storage device instruction aggregation method provided in this embodiment allows the host to continuously add execution instructions to the execution queue. The storage device retrieves a first number of execution instructions from the execution queue and executes them. If all executions are successful, the completion instructions corresponding to the multiple execution instructions are merged and sent to the host. If there are failed instructions, the target completion instruction and the failed instruction are sent to the host, or only the failed instruction is sent to the host. This effectively reduces the number of NVMe control instructions transmitted on the PCIe link, significantly improves the link throughput, and simultaneously increases the host's processing speed while reducing the host's memory overhead. It solves the problem in related technologies where CQE instructions from the storage device are returned to the host one by one, resulting in low throughput of the communication link.

[0012] In one optional implementation, the target position of the execution result when the first execution error occurs is obtained according to the order of the sequence. Based on the target position, a target completion instruction and a failure instruction are determined, and the target completion instruction and the failure instruction are sent to the host, or a failure instruction is sent to the host. This includes:

[0013] If the failure instruction is located at the first target position, and the number of completion instructions that existed before the failure instruction is greater than the first preset value, the completion instructions that existed before the failure instruction are combined into the target completion instruction, and the target completion instruction and the failure instruction are sent to the host.

[0014] If the failure instruction is located at the second target position, and the number of completion instructions that existed before the failure instruction is equal to the first preset value, then the completion instructions that existed before the failure instruction are taken as the target completion instructions, and the target completion instructions and the failure instructions are sent to the host.

[0015] If the failure instruction is located at the third target position, and the number of completion instructions that existed before the failure instruction is less than the first preset value, then the failure instruction will be sent to the host.

[0016] In this embodiment, based on the target location of the failed instruction, the number of completed instructions preceding the failed instruction is determined. If the number exceeds a first preset value, the completed instructions are merged into the target completed instruction. This improves the utilization rate of completed instructions on the host side, increases the rate at which the host side issues execution instructions, enhances the host's processing speed, and reduces the host's memory overhead.

[0017] In one optional implementation, combining a first number of completion instructions into a target completion instruction includes:

[0018] The time interval and quantity threshold for obtaining the merge completion instructions are used to merge the completion instructions to obtain the target completion instruction.

[0019] If the first number of completion instructions are all completion instructions within the time interval, and the first number is less than or equal to the number threshold, the first start completion instruction and the first end completion instruction among the first number of completion instructions are determined according to the order of arrangement.

[0020] Obtain the first command identifier of the first start completion instruction and the second command identifier of the first end completion instruction;

[0021] The command identifier of the preset completion instruction is modified to the second preset value, and the preset completion instruction is modified according to the first command identifier and the second command identifier to obtain the target completion instruction;

[0022] If the first number of completed instructions are all completed instructions within the time interval, and the first number is greater than the number threshold, then the first second number of completed instructions are obtained from the first number of completed instructions, where the second number is equal to the number threshold.

[0023] Based on the order of arrangement, determine the second start completion instruction and the second end completion instruction among the second number of completion instructions;

[0024] Obtain the third command identifier of the second start completion instruction and the fourth command identifier of the second end completion instruction;

[0025] The command identifier of the preset completion instruction is modified to the second preset value, and the preset completion instruction is modified according to the third and fourth command identifiers to obtain the target completion instruction.

[0026] In this implementation, completion instructions are merged into a target completion instruction based on the time interval and quantity threshold of the merged completion instructions. This effectively reduces the number of completion instruction transmissions on the communication link. After receiving the target completion instruction, the host can release multiple execution instructions at once, ensuring resources for high-speed subsequent I / O and improving the utilization rate of host resources per unit time. Furthermore, since completion instructions can be merged, the host can reduce the depth of each completion queue, thus reducing host-side memory usage.

[0027] In one alternative implementation, the completion instructions existing prior to the failure instruction are combined into a target completion instruction, including:

[0028] Based on the order of arrangement, determine the third start completion instruction and the third end completion instruction among the completion instructions that existed before the failure instruction;

[0029] Obtain the fifth command identifier of the third start completion instruction and the sixth command identifier of the third end completion instruction;

[0030] The command identifier of the preset completion instruction is modified to the second preset value, and the preset completion instruction is modified according to the fifth and sixth command identifiers to obtain the target completion instruction.

[0031] In this implementation, the completion instructions preceding the failed instruction are combined into a target completion instruction, and the error instruction is returned separately to the host. This allows the host to promptly release the corresponding execution instruction resources through the target completion instruction, ensuring resource availability for subsequent high-speed I / O. Simultaneously, identifying the execution instruction that malfunctioned through the error instruction facilitates further processing.

[0032] Secondly, the present invention provides a storage device instruction aggregation method, which is applied to a host side and includes:

[0033] Generate a commit instruction, which contains a unique identifier;

[0034] Add the commit command to the commit queue;

[0035] Send the first number of commit commands in the commit queue and their order to the storage device.

[0036] Retrieve the target completion instruction and / or failure instruction from the storage device and place the target completion instruction and / or failure instruction into the completion queue;

[0037] Based on the target completion instruction, determine the third number of target submission instructions and release the unique identifier contained in the target submission instructions.

[0038] The storage device instruction aggregation method provided in this embodiment allows the host to continuously add execution instructions to the execution queue. The storage device retrieves a first number of execution instructions from the execution queue and executes them. If all executions are successful, the completion instructions corresponding to the multiple execution instructions are merged and sent to the host. If there are failed instructions, the target completion instruction and the failed instruction are sent to the host, or only the failed instruction is sent to the host. This effectively reduces the number of NVMe control instructions transmitted on the PCIe link, significantly improves the link throughput, and simultaneously increases the host's processing speed while reducing the host's memory overhead. It solves the problem in related technologies where CQE instructions from the storage device are returned to the host one by one, resulting in low throughput of the communication link.

[0039] In one alternative implementation, the method further includes, before generating the commit instruction:

[0040] Determine whether the storage device can merge the instructions;

[0041] If the storage device can merge the completion instructions, obtain the time interval and number threshold of the merge completion instructions. The time interval and number threshold are used to merge the completion instructions to obtain the target completion instruction.

[0042] Send the time interval and quantity threshold to the storage device.

[0043] In this embodiment, when the host determines that the storage device can merge the completion instructions, it sets the time interval and number threshold for merging the completion instructions on the storage device, and controls the storage device to merge the completion instructions.

[0044] In one alternative implementation, generating a submission instruction includes:

[0045] Request an initial commit instruction from the resource pool, wherein the resource pool includes a first number of initial commit instructions, and the initial commit instruction contains a unique identifier;

[0046] Adjust the initial commit command to obtain the commit command, where the unique identifier of the commit command is the same as the unique identifier of the initial commit command.

[0047] In this implementation, an initial commit instruction is requested from the resource pool, and the initial commit instruction is adjusted to obtain the commit instruction. It is ensured that the unique identifier of the commit instruction is the same as the unique identifier of the initial commit instruction to avoid commit instructions with the same identifier appearing in the same commit queue.

[0048] In one alternative implementation, adjusting the initial commit instruction includes:

[0049] Modify the preset fields in the initial submission command to the third preset value, whereby the third preset value is used to determine whether the completion commands corresponding to the submission command can be merged.

[0050] In this embodiment, by modifying the preset field in the initial commit instruction to a third preset value, the storage device is notified that the completion instruction corresponding to the commit instruction can be merged, thus providing a basis for the storage device to merge CQE instructions in the future.

[0051] Thirdly, the present invention provides a storage device instruction aggregation apparatus, which is deployed on a storage device, the method comprising:

[0052] The first acquisition module is used to acquire a first number of submission instructions and the order in which the submission instructions are arranged.

[0053] The execution module is used to execute the submission instructions, obtain the execution result of each submission instruction, and generate a first number of completion instructions;

[0054] The first sending module is used to combine a first number of completion instructions into a target completion instruction and send the target completion instruction to the host if all execution results are successful.

[0055] The second sending module is used to obtain the target position of the first execution result that failed in the order of the order when the execution result is not all successful, determine the target completion instruction and the failure instruction based on the target position, and send the target completion instruction and the failure instruction to the host or send the failure instruction to the host.

[0056] Fourthly, the present invention provides a storage device instruction aggregation method, the device being deployed on a host side, the method comprising:

[0057] The generation module is used to generate submission instructions, where each submission instruction contains a unique identifier.

[0058] The `put` module is used to put commit commands into the commit queue;

[0059] The third sending module is used to send the first number of submission instructions in the submission queue and the order of the submission instructions to the storage device.

[0060] The second acquisition module is used to acquire the target completion instruction and / or failure instruction from the storage device and put the target completion instruction and / or failure instruction into the completion queue.

[0061] The release module is used to determine a third number of target submission instructions based on the target completion instructions, and to release the unique identifier contained in the target submission instructions.

[0062] Fifthly, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the computer instructions to perform the storage device instruction aggregation method of the first aspect or any corresponding embodiment described above.

[0063] In a sixth aspect, the present invention provides a computer-readable storage medium storing computer instructions, the computer instructions being used to cause a computer to execute the storage device instruction aggregation method of the first aspect or any corresponding embodiment thereof. Attached Figure Description

[0064] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0065] Figure 1 This is a schematic diagram of the interaction process between the host and storage device in the prior art according to an embodiment of the present invention;

[0066] Figure 2 This is a schematic diagram of the SQE and CQE message interaction process between the host and storage device in the prior art according to embodiments of the present invention;

[0067] Figure 3 This is a schematic diagram of a submission queue, a completion queue, and an SQE resource pool established by a multi-core host in the prior art according to embodiments of the present invention;

[0068] Figure 4 This is a flowchart illustrating a storage device instruction aggregation method applied to a storage device according to an embodiment of the present invention;

[0069] Figure 5 This is a schematic diagram of the SQE and CQE message interaction process between the host and storage device according to an embodiment of the present invention;

[0070] Figure 6 This is a schematic diagram illustrating the information contained in the completion instruction according to an embodiment of the present invention;

[0071] Figure 7 This is a flowchart illustrating a storage device instruction aggregation method applied to a host side according to an embodiment of the present invention.

[0072] Figure 8 These are the submission queue, completion queue, and SQE resource pool established by a multi-core host according to embodiments of the present invention;

[0073] Figure 9 This is a schematic diagram of the SQE and CQE message interaction process between the host and storage device according to an embodiment of the present invention;

[0074] Figure 10 This is a structural block diagram of a storage device instruction aggregation device deployed on a storage device according to an embodiment of the present invention;

[0075] Figure 11 This is a structural block diagram of a storage device instruction aggregation apparatus deployed on a host side according to an embodiment of the present invention;

[0076] Figure 12 This is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. Detailed Implementation

[0077] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0078] The command queue of a Linux host includes the SQ queue (Submission Queue, the queue for submitting NVMe protocol commands), also known as the commit queue, and the CQ queue (Completion Queue, the queue for completing NVMe protocol commands), also known as the completion queue. The existing interaction process between the host and storage device is as follows: Figure 1 As shown: The host generates an SQE instruction based on the read / write request to the storage device, places the SQE instruction to be executed on the storage device into the NVMe instruction request queue (SQ) in memory, and then notifies the storage device to read the SQE instruction from the SQ queue. The controller inside the storage device reads the SQE instruction from the host's memory SQ queue via PCIe message, executes the SQE instruction in the flash storage medium inside the storage device, generates a CQE instruction, and finally puts the executed CQE instruction into the host's CQ queue via PCIe message, notifying the host to complete an IO interaction. The host then receives a read / write response from the storage device.

[0079] The above message interaction method is a synchronous "request / response" message, with request and response instructions being 64 bytes and 16 bytes respectively. Because requests and responses are in a one-to-one correspondence, the depths of the SQ queue and CQ queue are also the same. The existing SQE and CQE message interaction flow between the host and storage device is as follows: Figure 2 As shown: The host first requests one SQE, then sends the SQE command to the storage device. The storage device processes the command, executes the SQE, and returns a CQE command. After receiving the CQE command, the host releases the SQE corresponding to the CQE command. The subsequent SQE and CQE message interaction process is the same as described above, and will not be repeated here.

[0080] To improve the concurrency performance of storage devices, the NVMe protocol supports the creation of up to 64,000 queues between the host and the storage device. The host can concurrently issue commands to all queues. A Linux host creates no more than the number of CPU cores based on the number of CPU cores in the current system. Each queue is bound to a CPU core, and all threads on that CPU core can simultaneously submit commands to that CPU's SQ queue. Furthermore, because the CID (Command ID, a unique identifier for an SQE within the SQ queue) of each SQE cannot be duplicated, the host pre-creates a resource pool of SQEs for each queue. The number of SQEs in the pool matches the queue depth, and each SQE is assigned a CID to distinguish different SQEs. These IDs are reused, but duplicate CIDs cannot appear in the SQ queue at the same time. Existing technologies for multi-core hosts establish commit queues, completion queues, and SQE resource pools as follows: Figure 3 As shown: In each core (including core0, core1, ..., coreN), the submission of SQEs by threads in the queue is synchronous. A thread first requests an SQE from the SQE resource pool, fills it with data, places it in the SQ queue, and then distributes the SQE to the storage device. Finally, the host or other storage device places the corresponding CQE into the CQ queue before releasing the SQE back to the resource pool. The SQE for this CID will then be reused. It is important to note that all SQE and CQE message passing must be done through the PCIe link.

[0081] This invention provides a storage device instruction aggregation method. The host can continuously add SQE instructions to the SQ queue. The storage device retrieves and executes the SQE instructions from the SQ queue. Then, the storage device merges the CQE instructions with consecutive CIDs and no errors from the multiple SQE instructions issued by the host into a single CQE instruction and returns it to the host. This combines PCIe messages that would otherwise need to be sent multiple times into one, without increasing the data size of this single PCIe message. This effectively reduces the number of NVMe control commands transmitted on the PCIe link, significantly improves link throughput, increases host processing speed, and reduces host memory overhead.

[0082] According to an embodiment of the present invention, a storage device instruction aggregation method embodiment is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a smart terminal with data processing capabilities. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than that shown here.

[0083] This embodiment provides a storage device instruction aggregation method applied to the storage device side, which can be used in the aforementioned smart terminal. Figure 4 This is a flowchart of a storage device instruction aggregation method according to an embodiment of the present invention, such as... Figure 4 As shown, the process includes the following steps:

[0084] Step S401: Obtain the first number of submission instructions and their order.

[0085] Specifically, the host continuously adds SQE instructions to the SQ queue, and the storage device obtains the first number of commit instructions (i.e., SQE instructions) from the SQ queue and executes them. It also needs to determine the order of the first number of SQE instructions obtained, which will be used to combine the commit instructions later. The first number means multiple, and there is no specific limit on the number here.

[0086] It should be noted that the transmission of all SQE and CQE commands in this invention must be through a PCIe link or a fabric link. The fabric link is a commonly used network bearer for the NVMe protocol, including fiber optic networks, transmission control protocol networks, etc.

[0087] Step S402: Execute the submission instructions, obtain the execution result of each submission instruction, and generate a first number of completion instructions.

[0088] Specifically, the first number of SQE instructions are executed, and the execution result of each SQE instruction is determined. The execution result includes execution success and execution error. A completion instruction (i.e., CQE instruction) corresponding to each SQE instruction is generated, and the number of CQE instructions is also the first number. Among them, CQE instructions that indicate execution success can be merged. Because CQE instructions that indicate execution error contain the reason for the execution error, CQE instructions that indicate execution error cannot be merged.

[0089] In step S403, if all execution results are successful, the first number of completion instructions are combined into a target completion instruction, and the target completion instruction is sent to the host.

[0090] Specifically, in combination Figure 5The host sends out 5 SQE instructions in sequence, in the order of ①, ②, ③, ④, and ⑤. If the execution result of the above 5 SQE instructions is successful, the corresponding CQE instructions of the above 5 SQE instructions are combined into a single CQE instruction as the target completion instruction, and the target completion instruction is returned to the host.

[0091] Step S404: If the execution results are not all successful, obtain the target position of the first execution result that failed in the order of the arrangement, determine the target completion instruction and the failure instruction based on the target position, and send the target completion instruction and the failure instruction to the host or send the failure instruction to the host.

[0092] Specifically, in the case of a CQE instruction that fails to execute, the target position of the first execution result that failed is retrieved in the order listed. Based on the target position, it is determined whether to generate a target completion instruction. If a target completion instruction is generated, both the target completion instruction and a failure instruction are sent to the host. If no target completion instruction is generated, only a failure instruction is sent to the host. For example: Figure 5 As shown, the host sends three SQE instructions sequentially, in the order of ⑥, ⑦, and ⑧. Instructions ⑥ and ⑦ execute successfully, while instruction ⑧ results in an error. The first instruction that fails occurs at the third target position in the sequence, making the third SQE instruction the failure instruction. This failure instruction is preceded by two successful SQE instructions: ⑥ and ⑦. Therefore, the CQE instructions corresponding to SQE instructions ⑥ and ⑦ are combined into a target completion instruction, and this target completion instruction, along with the failure instruction, is sent to the host.

[0093] The storage device instruction aggregation method provided in this embodiment allows the host to continuously add execution instructions to the execution queue. The storage device retrieves a first number of execution instructions from the execution queue and executes them. If all executions are successful, the completion instructions corresponding to the multiple execution instructions are merged and sent to the host. If there are failed instructions, the target completion instruction and the failed instruction are sent to the host, or only the failed instruction is sent to the host. This effectively reduces the number of NVMe control instructions transmitted on the PCIe link, significantly improves the link throughput, and simultaneously increases the host's processing speed while reducing the host's memory overhead. It solves the problem in related technologies where CQE instructions from the storage device are returned to the host one by one, resulting in low throughput of the communication link.

[0094] In some optional implementations, the target position of the execution result when the first execution error occurs is obtained according to the order of the arrangement. Based on the target position, the target completion instruction and the failure instruction are determined, and the target completion instruction and the failure instruction are sent to the host, or the failure instruction is sent to the host. This includes:

[0095] If the failure instruction is located at the first target position, and the number of completion instructions that existed before the failure instruction is greater than the first preset value, the completion instructions that existed before the failure instruction are combined into the target completion instruction, and the target completion instruction and the failure instruction are sent to the host.

[0096] If the failure instruction is located at the second target position, and the number of completion instructions that existed before the failure instruction is equal to the first preset value, then the completion instructions that existed before the failure instruction are taken as the target completion instructions, and the target completion instructions and the failure instructions are sent to the host.

[0097] If the failure instruction is located at the third target position, and the number of completion instructions that existed before the failure instruction is less than the first preset value, then the failure instruction will be sent to the host.

[0098] Specifically, if the storage device encounters an SQE execution error during the execution of the first number of SQE instructions, it retrieves the target location within the order of the execution result of the first error. Based on the target location, it determines whether to combine the CQE instructions into a target completion instruction. After the first number of SQE instructions are executed, the first number of CQE instructions are generated.

[0099] This invention designates the position where the number of previously existing completion instructions is greater than a first preset value as the first target position, for example: the third CQE instruction and subsequent CQE instructions in a first number of CQE instructions, where the first preset value is 1. The position where the number of previously existing completion instructions is equal to the first preset value is designated as the second target position, for example: the second CQE instruction in a first number of CQE instructions. The position where the number of previously existing completion instructions is less than the first preset value is designated as the third target position, for example: the first CQE instruction in a first number of CQE instructions.

[0100] If the failed instruction is located in the first target position, it means that the number of CQE instructions that existed before the failed instruction is greater than 1. Then, the CQE instructions corresponding to the SQEs before the failed SQE are merged into one CQE instruction as the target instruction and sent to the host. Then, the CQE of the failed SQE is sent to the host separately.

[0101] If the failure instruction is located at the second target position, it means that there is 1 CQE instruction before the failure instruction. In this case, the 1 CQE instruction before the failure instruction is taken as the target completion instruction, and the target completion instruction and the failure instruction are sent to the host.

[0102] If the failure instruction is located in the second target position, it means that the number of CQE instructions that existed before the failure instruction is 0, and only the failure instruction is sent to the host.

[0103] In this embodiment, based on the target location of the failed instruction, the number of completed instructions preceding the failed instruction is determined. If the number exceeds a first preset value, the completed instructions are merged into the target completed instruction. This improves the utilization rate of completed instructions on the host side, increases the rate at which the host side issues execution instructions, enhances the host's processing speed, and reduces the host's memory overhead.

[0104] In some alternative implementations, the first number of completion instructions are combined into a target completion instruction, including:

[0105] The time interval and quantity threshold for obtaining the merge completion instructions are used to merge the completion instructions to obtain the target completion instruction.

[0106] If the first number of completion instructions are all completion instructions within the time interval, and the first number is less than or equal to the number threshold, the first start completion instruction and the first end completion instruction among the first number of completion instructions are determined according to the order of arrangement.

[0107] Obtain the first command identifier of the first start completion instruction and the second command identifier of the first end completion instruction;

[0108] The command identifier of the preset completion instruction is modified to the second preset value, and the preset completion instruction is modified according to the first command identifier and the second command identifier to obtain the target completion instruction;

[0109] If the first number of completed instructions are all completed instructions within the time interval, and the first number is greater than the number threshold, then the first second number of completed instructions are obtained from the first number of completed instructions, where the second number is equal to the number threshold.

[0110] Based on the order of arrangement, determine the second start completion instruction and the second end completion instruction among the second number of completion instructions;

[0111] Obtain the third command identifier of the second start completion instruction and the fourth command identifier of the second end completion instruction;

[0112] The command identifier of the preset completion instruction is modified to the second preset value, and the preset completion instruction is modified according to the third and fourth command identifiers to obtain the target completion instruction.

[0113] Specifically, the storage device obtains the time interval M of the merge CQE command set by the host after initialization via the set feature command and the maximum number of CQEs that can be merged N. The maximum number of CQEs that can be merged is the quantity threshold.

[0114] If all SQE instructions execute successfully, then based on the host's set threshold N, the CQE instructions corresponding to N consecutive CID SQE instructions are merged into a single target completion instruction and sent to the host. If the number of CQE instructions to be merged within the time interval M is insufficient, all CQE instructions within that time interval are merged into a single target completion instruction and sent to the host. Then, the timer is restarted the next time an SQE instruction is received. The timer is used to determine the time interval. The method for merging CQE instructions is as follows: Modify the Command Identifier field of the standard CQE instruction (i.e., the default completion instruction) to the identifier of the merged CQE instruction, for example, it can be the largest CID + 1 in the SQE instruction. This way, when the host receives this CQE instruction, it will recognize that this CQE instruction is obtained by merging multiple CQE instructions. Simultaneously, fill the high 16 bits of DW1 of the default completion instruction with the Command Identifier of the starting CQE instruction, and fill the low 16 bits of DW1 with the Command Identifier of the ending CQE instruction. Here, DW is an abbreviation for Double Word, representing four bytes; in this invention, it represents the first four bytes of the SQE instruction. For example... Figure 6 As shown, the preset completion instructions include DW0, DW1, DW2, and DW3. Each DW contains 32 bits (0-31). CommandSpecific indicates the specific command, Reserved indicates a reserved field for the preset completion instructions, used to fill the command identifiers of the aforementioned start and end CQE instructions. SQ queue identifier (SQIdentifier) ​​indicates the ID of the SQ queue associated with the SQE instruction. SQ head pointer (SQHeadPointer) describes the position of the SQ queue head pointer. The return code (StatusField) indicates success or failure; if it fails, the specific reason for the failure is recorded. After the return code, P indicates whether the data in the queue has been processed. For example, P = 0 indicates that the data has been processed, and P = 1 indicates that it has not been processed.

[0115] If a first number of CQE instructions are all completion instructions within a time interval M, and the first number is equal to or less than a threshold N, then the first start completion instruction and the first end completion instruction are determined from the first number of CQE instructions according to their order. The first command identifier of the first start completion instruction and the second command identifier of the first end completion instruction are obtained. The command identifier of the preset completion instruction is modified to a second preset value, for example: the largest CID in the CQE instructions + 1. The first command identifier and the second command identifier are filled into the DW1 of the preset completion instruction to obtain the target completion instruction. For example: Figure 5 As shown, assuming the host sets the quantity threshold N to 5, and all 5 SQE instructions ①, ②, ③, ④, and ⑤ are executed successfully by the storage device, the storage device merges the CQE instructions corresponding to the 5 SQE instructions into a single CQE instruction and returns it to the host. The merged CQE instruction contains the results of ①, ②, ③, ④, and ⑤.

[0116] If the first number of CQE instructions are all the completion instructions within the time interval M, and the first number is greater than the number threshold N, then the first second number of CQE instructions are obtained from the first number of CQE instructions. The second number is equal to the number threshold N. The N CQE instructions are merged into the target completion instruction. The remaining CQE instructions are considered to determine whether they need to be merged into the target completion instruction based on the number threshold N.

[0117] Based on the order of arrangement, determine the second start completion instruction and the second end completion instruction from the second number of CQE instructions. Obtain the third command identifier of the second start completion instruction and the fourth command identifier of the second end completion instruction. Modify the command identifier of the preset completion instruction to a second preset value, for example: the largest CID in the SQE instruction + 1. Fill the DW1 of the preset completion instruction with the third and fourth command identifiers to obtain the target completion instruction.

[0118] In this implementation, completion instructions are merged into a target completion instruction based on the time interval and quantity threshold of the merged completion instructions. This effectively reduces the number of completion instruction transmissions on the communication link. After receiving the target completion instruction, the host can release multiple execution instructions at once, ensuring resources for high-speed subsequent I / O and improving the utilization rate of host resources per unit time. Furthermore, since completion instructions can be merged, the host can reduce the depth of each completion queue, thus reducing host-side memory usage.

[0119] In some optional implementations, completion instructions existing prior to the failure instruction are combined into a target completion instruction, including:

[0120] Based on the order of arrangement, determine the third start completion instruction and the third end completion instruction among the completion instructions that existed before the failure instruction;

[0121] Obtain the fifth command identifier of the third start completion instruction and the sixth command identifier of the third end completion instruction;

[0122] The command identifier of the preset completion instruction is modified to the second preset value, and the preset completion instruction is modified according to the fifth and sixth command identifiers to obtain the target completion instruction.

[0123] Specifically, if an error occurs during the execution of an SQE instruction, the CQE instructions corresponding to the SQE instructions preceding the erroneous SQE instruction are merged into a single CQE instruction and sent to the host. Then, the CQE instruction of the erroneous SQE is sent to the host separately.

[0124] If two or more CQE instructions precede the failed instruction, the completion instructions preceding the failed instruction are combined into the target completion instruction. The merging method is as follows: Based on the order of arrangement, determine the third start completion instruction and the third end completion instruction among the CQE instructions preceding the failed instruction. Obtain the fifth command identifier of the third start completion instruction and the sixth command identifier of the third end completion instruction. Modify the command identifier of the preset completion instruction to a second preset value, for example: the largest CID in the SQE instruction + 1. Fill the DW1 of the preset completion instruction with the fifth and sixth command identifiers to obtain the target completion instruction. Finally, send the target completion instruction and the failed instruction to the host, for example: Figure 5 As shown, the host sends three SQE instructions: ⑥, ⑦, and ⑧. ⑥ and ⑦ execute successfully, while ⑧ fails. Therefore, the CQE corresponding to ⑧ is an erroneous instruction. Since there are two completion instructions preceding the erroneous instruction, and the number is greater than one, the storage device merges the CQE instructions corresponding to ⑥ and ⑦ into one CQE and returns it to the host, while returning the erroneous instruction separately to the host.

[0125] In this implementation, the completion instructions preceding the failed instruction are combined into a target completion instruction, and the error instruction is returned separately to the host. This allows the host to promptly release the corresponding execution instruction resources through the target completion instruction, ensuring resource availability for subsequent high-speed I / O. Simultaneously, identifying the execution instruction that malfunctioned through the error instruction facilitates further processing.

[0126] This embodiment provides a storage device instruction aggregation method applied to the host side, which can be used in the aforementioned smart terminal. Figure 7 This is a flowchart of a storage device instruction aggregation method according to an embodiment of the present invention, such as... Figure 7 As shown, the process includes the following steps:

[0127] Step S701: Generate a submission instruction, wherein the submission instruction contains a unique identifier.

[0128] Step S702: Place the commit instruction into the commit queue.

[0129] Specifically, the Linux host creates no more than the number of CPU cores based on the current system's central processing unit (CPU) cores (core0, core1, ..., coreN). Each queue is bound to a specific CPU core, and all threads on that CPU core can simultaneously submit commands to that CPU's SQ queue. The submission of SQEs by threads on a single queue is synchronous: the thread first requests an SQE from the SQE resource pool, fills it with data, and then issues the SQE to the SQ queue. For example... Figure 8 As shown, core0 requests an SQE from the SQE resource pool and issues this SQE to the SQ queue. The steps for core1, ..., coreN are the same, and will not be repeated here.

[0130] Step S703: Send the first number of commit instructions in the commit queue and the order of the commit instructions to the storage device.

[0131] Specifically, the host sends the first number of commit instructions in the commit queue and their order to the storage device, or instructs the storage device to retrieve the first number of commit instructions (i.e., SQE instructions) from the SQ queue and execute them. It also needs to determine the order of the first number of SQE instructions obtained, which will be used to combine the commit instructions later.

[0132] It should be noted that the transmission of all SQE and CQE commands in this invention must be through a PCIe link or a fabric link. The fabric link is a network bearer method for the NVMe protocol, including fiber optic networks, transmission control protocol networks, etc.

[0133] Step S704: Obtain the target completion instruction and / or failure instruction from the storage device and put the target completion instruction and / or failure instruction into the completion queue.

[0134] Specifically, after receiving a first number of SQE instructions, the storage device executes them, generating a first number of CQE instructions. If all of the first number of CQE instructions execute successfully, the first number of consecutive, error-free CQE instructions with consecutive CIDs are merged into a single target completion instruction and returned to the host. The host then places the target completion instruction into the CQ queue. If any of the first number of CQE instructions fail, the number of completion instructions preceding the failed instruction is determined based on the target position of the failed instruction. If this number exceeds a first preset value, the completion instructions are merged into a single target completion instruction, and both the target completion instruction and the error instruction are sent to the host. The host then places both the target completion instruction and the error instruction into the CQ queue. If the number is less than the first preset value, only the error instruction is sent to the host.

[0135] The above process is as follows Figure 8 As shown, each core on the host side (including core0, core1, ..., coreN) puts CQE into the CQ queue and finally releases SQE to the SQE resource pool.

[0136] Step S705: Determine the third number of target submission instructions based on the target completion instructions, and release the unique identifier contained in the target submission instructions.

[0137] Specifically, if the target completion instruction is obtained by merging multiple CQE instructions, then a third number of target commit instructions (target SQE instructions) corresponding to the multiple CQE instructions are determined based on the target completion instruction, and the target SQE instructions are released to the SQE resource pool, i.e., the unique identifier (CID) contained in the target commit instruction is released. If the target completion instruction is only a single CQE instruction, then a third number of target commit instructions are determined based on the target completion instruction, and the target commit instruction corresponding to that CQE instruction is determined based on the target completion instruction, and the target commit instruction is released. The third number represents multiple instructions, and no specific limit is imposed here.

[0138] The above process is as follows Figure 9 As shown: The host requests an SQE and issues an SQE instruction to the storage device. The storage device processes the command and repeats the above process three times. The storage device returns a CQE instruction, which is obtained by merging the CQE instructions corresponding to the three SQE instructions. Therefore, based on this CQE instruction, three SQEs can be identified and released.

[0139] It's important to note that merging multiple consecutive, error-free SQE commands with consecutive CIDs sent by the host into a single CQE command returned to the host allows for the consolidation of multiple PCIe messages into one, without increasing the data size of this single PCIe message. This effectively reduces the transmission of NVMe CQE commands on the PCIe link. Upon receiving this single CQE command, the host can release multiple SQE resources at once, ensuring high-speed I / O for subsequent requests and significantly improving the utilization rate of host SQE resources per unit time. Furthermore, because CQE commands can be merged, the depth of the CQ queue that the host can establish for each SQ queue can be significantly reduced, decreasing host-side memory usage, especially useful in embedded systems where memory is limited.

[0140] The storage device instruction aggregation method provided in this embodiment allows the host to continuously add execution instructions to the execution queue. The storage device retrieves a first number of execution instructions from the execution queue and executes them. If all executions are successful, the completion instructions corresponding to the multiple execution instructions are merged and sent to the host. If there are failed instructions, the target completion instruction and the failed instruction are sent to the host, or only the failed instruction is sent to the host. This effectively reduces the number of NVMe control instructions transmitted on the PCIe link, significantly improves the link throughput, and simultaneously increases the host's processing speed while reducing the host's memory overhead. It solves the problem in related technologies where CQE instructions from the storage device are returned to the host one by one, resulting in low throughput of the communication link.

[0141] In some alternative implementations, the method further includes, before generating the commit instruction:

[0142] Determine whether the storage device can merge the instructions;

[0143] If the storage device can merge the completion instructions, obtain the time interval and number threshold of the merge completion instructions. The time interval and number threshold are used to merge the completion instructions to obtain the target completion instruction.

[0144] Send the time interval and quantity threshold to the storage device.

[0145] Specifically, the host first initializes. After initialization, the host uses the `identify` command to query whether the storage device supports the merging feature of CQE commands. If the storage device supports CQE command merging, the host uses the `set feature` command to set the time interval `M` for merging SQE commands. This means that if the host does not continuously issue SQE commands, all CQE commands corresponding to the current SQE commands will be merged and returned to the host within the time interval `M`. Additionally, the host also uses the `set feature` command to set the maximum number of CQE commands that the controller can merge to a threshold value `N`. The threshold value `N` cannot exceed the SQE queue depth. This parameter indicates that if the host continuously issues SQE commands, and the time interval `M` is not exceeded, the CQE commands corresponding to N consecutive SQE commands can be merged into one. This parameter can be used for performance tuning of the NVMe storage device. Finally, the time interval `M` and the threshold value `N` are sent to the storage device.

[0146] In this embodiment, when the host determines that the storage device can merge the completion instructions, it sets the time interval and number threshold for merging the completion instructions on the storage device, and controls the storage device to merge the completion instructions.

[0147] In some optional implementations, a submission instruction is generated, including:

[0148] Request an initial commit instruction from the resource pool, wherein the resource pool includes a first number of initial commit instructions, and the initial commit instruction contains a unique identifier;

[0149] Adjust the initial commit command to obtain the commit command, where the unique identifier of the commit command is the same as the unique identifier of the initial commit command.

[0150] Specifically, the CID of each SQE in each SQ queue cannot be duplicated. Therefore, the host pre-creates a resource pool of SQEs for each queue. The number of SQEs in the pool is consistent with the queue depth. Each SQE is assigned a CID (CommandID, the unique identifier of the SQE in the SQ queue) to distinguish different SQEs. These IDs are reused.

[0151] The host requests an initial commit instruction from the resource pool, adjusts the initial commit instruction, fills in the data in the initial commit instruction, writes the read / write storage device request on the host, and obtains the commit instruction. The unique identifier of the commit instruction is the same as the unique identifier of the initial commit instruction, both of which are the same CID in the resource pool.

[0152] In this implementation, an initial commit instruction is requested from the resource pool, and the initial commit instruction is adjusted to obtain the commit instruction. It is ensured that the unique identifier of the commit instruction is the same as the unique identifier of the initial commit instruction to avoid commit instructions with the same identifier appearing in the same commit queue.

[0153] In some alternative implementations, the initial submission command is modified, including:

[0154] Modify the preset fields in the initial submission command to the third preset value, whereby the third preset value is used to determine whether the completion commands corresponding to the submission command can be merged.

[0155] Specifically, before issuing the SQE command to the SQ queue, the host adjusts the initial commit command, including modifying a preset field in the initial commit command to a third preset value. The preset field is, for example, a reserved field (bit 10) of DW0, and the third preset value is, for example, 0 or 1. The reserved field (bit 10) of DW0 indicates that the CQE command corresponding to this SQE command can be merged. This way, when the controller in the storage device receives the SQE command, it will recognize that the CQE command corresponding to this SQE command can be merged.

[0156] In this embodiment, by modifying the preset field in the initial commit instruction to a third preset value, the storage device is notified that the completion instruction corresponding to the commit instruction can be merged, thus providing a basis for the storage device to merge CQE instructions in the future.

[0157] This embodiment also provides a storage device instruction aggregation apparatus for implementing the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that implements a predetermined function. Although the apparatus described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0158] This embodiment provides a storage device instruction aggregation device deployed on a storage device. The device is deployed on the storage device itself, such as... Figure 10 As shown, it includes:

[0159] The first acquisition module 1001 is used to acquire a first number of submission instructions and the order in which the submission instructions are arranged.

[0160] The execution module 1002 is used to execute the submission instructions, obtain the execution result of each submission instruction, and generate a first number of completion instructions;

[0161] The first sending module 1003 is used to combine a first number of completion instructions into a target completion instruction and send the target completion instruction to the host if all execution results are successful.

[0162] The second sending module 1004 is used to obtain the target position of the first execution result that failed in the order of the order when the execution result is not all successful, determine the target completion instruction and the failure instruction according to the target position, and send the target completion instruction and the failure instruction to the host or send the failure instruction to the host.

[0163] In some alternative implementations, the second transmitting module 1004 includes:

[0164] The first sending unit is configured to combine the existing completion instructions before the failure instruction into a target completion instruction if the failure instruction is located at the first target position and the number of completion instructions before the failure instruction is greater than a first preset value, and send the target completion instruction and the failure instruction to the host.

[0165] The second sending unit is used to send the completion instructions that existed before the failure instruction as the target completion instruction if the failure instruction is located at the second target position and the number of completion instructions that existed before the failure instruction is equal to the first preset value, and then send the target completion instruction and the failure instruction to the host.

[0166] The third sending unit is used to send the failure instruction to the host if the failure instruction is located at the third target position and the number of completion instructions existing before the failure instruction is less than a first preset value.

[0167] In some alternative implementations, the first transmitting module 1003 includes:

[0168] The first acquisition unit is used to acquire the time interval and quantity threshold of the merge completion instruction, wherein the time interval and quantity threshold are used to merge the completion instructions to obtain the target completion instruction;

[0169] The first determining unit is used to determine the first start completion instruction and the first end completion instruction among the first number of completion instructions according to the arrangement order, when the first number of completion instructions is all completion instructions within the time interval and the first number is less than or equal to the number threshold.

[0170] The second acquisition unit is used to acquire the first command identifier of the first start completion instruction and the second command identifier of the first end completion instruction;

[0171] The unit is used to modify the command identifier of the preset completion instruction to a second preset value, and modify the preset completion instruction according to the first command identifier and the second command identifier to obtain the target completion instruction;

[0172] The third acquisition unit is used to acquire the first second number of completion instructions from the first number of completion instructions when the first number of completion instructions is all completion instructions within the time interval and the first number is greater than the number threshold, wherein the second number is equal to the number threshold.

[0173] The second determining unit is used to determine the second start completion instruction and the second end completion instruction among the second number of completion instructions according to the arrangement order;

[0174] The fourth acquisition unit is used to acquire the third command identifier of the second start completion instruction and the fourth command identifier of the second end completion instruction;

[0175] The modification unit is used to modify the command identifier of the preset completion instruction to a second preset value, and modify the preset completion instruction according to the third command identifier and the fourth command identifier to obtain the target completion instruction.

[0176] In some alternative implementations, the first transmitting unit includes:

[0177] The determination submodule is used to determine the third start completion instruction and the third end completion instruction among the completion instructions that exist before the failure instruction, according to the order of arrangement.

[0178] The acquisition submodule is used to acquire the fifth command identifier of the third start completion instruction and the sixth command identifier of the third end completion instruction;

[0179] The submodule is used to modify the command identifier of the preset completion instruction to the second preset value, and modify the preset completion instruction according to the fifth command identifier and the sixth command identifier to obtain the target completion instruction.

[0180] This embodiment provides a storage device instruction aggregation device deployed on the host side. The device is deployed on the host side, such as... Figure 11 As shown, it includes:

[0181] The generation module 1101 is used to generate a submission instruction, wherein the submission instruction contains a unique identifier;

[0182] Insert module 1102, which is used to put the commit command into the commit queue;

[0183] The third sending module 1103 is used to send the first number of submission instructions in the submission queue and the order of the submission instructions to the storage device.

[0184] The second acquisition module 1104 is used to acquire the target completion instruction and / or failure instruction from the storage device and put the target completion instruction and / or failure instruction into the completion queue.

[0185] Release module 1105 is used to determine a third number of target submission instructions based on the target completion instructions, and release the unique identifier contained in the target submission instructions.

[0186] In some alternative embodiments, the device further includes:

[0187] The judgment module is used to determine whether the storage device can complete the merging of instructions;

[0188] The third acquisition module is used to acquire the time interval and quantity threshold of the merged completion instructions if the storage device can merge the completion instructions. The time interval and quantity threshold are used to merge the completion instructions to obtain the target completion instruction.

[0189] The fourth sending module is used to send the time interval and quantity threshold to the storage device.

[0190] In some optional implementations, the generation module 1101 includes:

[0191] The application unit is used to apply for an initial submission instruction from the resource pool, wherein the resource pool includes a first number of initial submission instructions, and the initial submission instruction contains a unique identifier;

[0192] The adjustment unit is used to adjust the initial submission instruction to obtain the submission instruction, wherein the unique identifier of the submission instruction is the same as the unique identifier of the initial submission instruction.

[0193] In some optional implementations, the adjustment unit includes:

[0194] The modification submodule is used to change the preset fields in the initial submission command to a third preset value. The third preset value is used to determine whether the completion command corresponding to the submission command can be merged.

[0195] Further functional descriptions of the above modules and units are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0196] In this embodiment, the storage device instruction aggregation device is presented in the form of a functional unit. Here, a unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0197] This invention also provides a computer device having the above-described features. Figure 10 and Figure 11 The storage device instruction aggregation device is shown.

[0198] Please see Figure 12 , Figure 12This is a schematic diagram of the structure of a computer device provided in an optional embodiment of the present invention, such as... Figure 12 As shown, the computer device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 12 Take a processor 10 as an example.

[0199] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0200] The memory 20 stores instructions executable by at least one processor 10 to cause at least one processor 10 to perform the method shown in the above embodiments.

[0201] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0202] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0203] The computer device also includes a communication interface 30 for communicating with other devices or communication networks.

[0204] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded via a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods shown in the above embodiments.

[0205] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A method for aggregating instructions for a storage device, characterized in that, The method is applied to a storage device, and the method includes: Obtain a first number of submission instructions and their order; Execute the submission instructions to obtain the execution result of each submission instruction, and generate a first number of completion instructions; If all execution results are successful, the first number of completion instructions are combined into a target completion instruction, and the target completion instruction is sent to the host. If the execution results are not all successful, the target position of the first execution result that failed is obtained according to the order of the order. The target completion instruction and the failure instruction are determined according to the target position, and the target completion instruction and the failure instruction are sent to the host or the failure instruction is sent to the host. The step of combining the first number of completion instructions into a target completion instruction includes: obtaining a time interval and a quantity threshold for merging the completion instructions, wherein the time interval and the quantity threshold are used to merge the completion instructions to obtain the target completion instruction; when the first number of completion instructions are all completion instructions within the time interval, and the first number is less than or equal to the quantity threshold, determining a first start completion instruction and a first end completion instruction among the first number of completion instructions according to the arrangement order; obtaining a first command identifier of the first start completion instruction and a second command identifier of the first end completion instruction; modifying the command identifier of the preset completion instruction to a second preset value, and modifying it according to the first command identifier and the second command identifier. The preset completion instruction is used to obtain the target completion instruction; when the first number of completion instructions are all completion instructions within the time interval, and the first number is greater than the number threshold, the first second number of completion instructions are obtained from the first number of completion instructions, wherein the second number is equal to the number threshold; according to the arrangement order, the second start completion instruction and the second end completion instruction are determined from the second number of completion instructions; the third command identifier of the second start completion instruction and the fourth command identifier of the second end completion instruction are obtained; the command identifier of the preset completion instruction is modified to the second preset value, and the preset completion instruction is modified according to the third command identifier and the fourth command identifier to obtain the target completion instruction.

2. The method according to claim 1, characterized in that, The step of obtaining the target position within the order in which the execution result of the first execution error occurs, determining the target completion instruction and the failure instruction based on the target position, and sending the target completion instruction and the failure instruction to the host or sending the failure instruction to the host includes: If the failure instruction is located at the first target position, and the number of completion instructions preceding the failure instruction is greater than a first preset value, the completion instructions preceding the failure instruction are combined into the target completion instruction, and the target completion instruction and the failure instruction are sent to the host. If the failure instruction is located at the second target position, and the number of completion instructions that existed before the failure instruction is equal to the first preset value, then the completion instructions that existed before the failure instruction are taken as the target completion instruction, and the target completion instruction and the failure instruction are sent to the host. If the failure instruction is located at the third target position, and the number of completion instructions preceding the failure instruction is less than a first preset value, then the failure instruction is sent to the host.

3. The method according to claim 2, characterized in that, The step of combining the completion instructions that existed prior to the failure instruction into the target completion instruction includes: Based on the arrangement order, determine the third start completion instruction and the third end completion instruction among the completion instructions that exist before the failure instruction; Obtain the fifth command identifier of the third start completion instruction and the sixth command identifier of the third end completion instruction; The command identifier of the preset completion instruction is modified to the second preset value, and the preset completion instruction is modified according to the fifth command identifier and the sixth command identifier to obtain the target completion instruction.

4. The method according to claim 1, characterized in that, The method also includes the following steps performed on the host side: Generate a submission instruction, wherein the submission instruction contains a unique identifier; Place the submission instruction into the submission queue; Send the first number of submission instructions in the submission queue and the order in which the submission instructions are arranged to the storage device. Obtain the target completion instruction and / or failure instruction from the storage device, and put the target completion instruction and / or failure instruction into the completion queue; Based on the target completion instruction, a third number of target submission instructions are determined, and the unique identifier contained in the target submission instructions is released.

5. The method according to claim 4, characterized in that, Prior to generating the submission instruction, the method further includes: Determine whether the storage device can merge and complete the instruction; If the storage device can merge the completion instructions, it obtains the time interval and quantity threshold for merging the completion instructions, wherein the time interval and the quantity threshold are used to merge the completion instructions to obtain the target completion instruction; The time interval and the quantity threshold are sent to the storage device.

6. The method according to claim 4, characterized in that, The generation of the submission instruction includes: Request an initial submission instruction from a resource pool, wherein the resource pool includes a first number of initial submission instructions, and the initial submission instruction contains a unique identifier; The initial commit instruction is adjusted to obtain the commit instruction, wherein the unique identifier of the commit instruction is the same as the unique identifier of the initial commit instruction.

7. The method according to claim 6, characterized in that, The adjustment of the initial submission instruction includes: The preset field in the initial submission instruction is modified to a third preset value, wherein the third preset value is used to determine that the completion instructions corresponding to the submission instruction can be merged.

8. A storage device instruction aggregation apparatus, characterized in that, The device is deployed on a storage device, and the device includes: The first acquisition module is used to acquire a first number of submission instructions and the order in which the submission instructions are arranged. An execution module is used to execute the submission instructions, obtain the execution result of each submission instruction, and generate a first number of completion instructions; The first sending module is configured to, when all execution results are successful, combine the first number of completion instructions into a target completion instruction and send the target completion instruction to the host. The second sending module is used to, when the execution results are not all successful, obtain the target position of the first execution result that failed in the order of the order, determine the target completion instruction and the failure instruction based on the target position, and send the target completion instruction and the failure instruction to the host or send the failure instruction to the host. The first sending module includes: a first acquisition unit, configured to acquire a time interval and a quantity threshold for merging the completion instructions, wherein the time interval and the quantity threshold are used to merge the completion instructions to obtain the target completion instruction; a first determination unit, configured to determine a first start completion instruction and a first end completion instruction among the first number of completion instructions according to the arrangement order, provided that the first number of completion instructions are all completion instructions within the time interval and the first number is less than or equal to the quantity threshold; a second acquisition unit, configured to acquire a first command identifier of the first start completion instruction and a second command identifier of the first end completion instruction; and a obtaining unit, configured to modify the command identifier of a preset completion instruction to a second preset value, and modify the preset completion instruction according to the first command identifier and the second command identifier. The system is configured to: obtain the target completion instruction; a third acquisition unit, configured to acquire the first second number of completion instructions from the first number of completion instructions when the first number of completion instructions are all completion instructions within the time interval and the first number is greater than the number threshold, wherein the second number is equal to the number threshold; a second determination unit, configured to determine the second start completion instruction and the second end completion instruction from the second number of completion instructions according to the arrangement order; a fourth acquisition unit, configured to acquire the third command identifier of the second start completion instruction and the fourth command identifier of the second end completion instruction; and a modification unit, configured to modify the command identifier of the preset completion instruction to the second preset value, and modify the preset completion instruction according to the third command identifier and the fourth command identifier to obtain the target completion instruction.

9. The apparatus according to claim 8, characterized in that, The device also includes the following modules deployed on the host: A generation module is used to generate a submission instruction, wherein the submission instruction contains a unique identifier; The module is used to put the submission instruction into the submission queue; The third sending module is used to send the first number of submission instructions in the submission queue and the order in which the submission instructions are arranged to the storage device. The second acquisition module is used to acquire the target completion instruction and / or failure instruction from the storage device, and put the target completion instruction and / or the failure instruction into the completion queue. The release module is used to determine a third number of target submission instructions based on the target completion instructions, and release the unique identifier contained in the target submission instructions.

10. A computer device, characterized in that, include: A memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the computer instructions to perform the storage device instruction aggregation method according to any one of claims 1 to 7.

11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing a computer to execute the storage device instruction aggregation method according to any one of claims 1 to 7.

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