Random data generation method and circuit based on fast and slow clocks

Abstract

The application discloses a random data generation circuit based on fast and slow clocks, comprising: a reset circuit, which is used for providing a digital reset pulse for digital and analog circuits, so that the whole random data generation circuit based on fast and slow clocks works normally; an oscillator circuit, which is used for providing a stable slow clock for a phase-locked loop and a digital circuit after the digital reset pulse ends; the phase-locked loop, which is used for providing a fast clock for the digital circuit to use for counting after being locked; a photoelectric detector, which is used for providing a trigger pulse for a readout circuit in the digital circuit after the reset is quenched due to dark noise; the readout circuit, which is used for starting timing when the trigger pulse is triggered, ending timing when the next system clock rising edge arrives, measuring the time interval of two signals as a random number and outputting. The application also provides a corresponding random data generation method based on fast and slow clocks.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and more specifically, relates to a method and circuit for generating random data based on fast and slow clocks. Background Technology

[0002] Random numbers play a crucial role in information security and cryptography. While deterministic mathematical algorithms can generate pseudo-random numbers, their predictability makes them difficult to secure. Therefore, designing a chip solution for generating random data is of great significance.

[0003] Random numbers are a widely used fundamental resource with broad and important applications in many fields such as quantum communication, cryptography, and traditional information security. The randomness guarantee of quantum random number generators stems from the principles of quantum physics. By measuring the inherent randomness of quantum physical systems, they generate truly random numbers, which possess unpredictability, non-repeatability, and unbiasedness. Their randomness is guaranteed by the fundamental principles of quantum mechanics, giving them a greater advantage over other random number generation techniques and thus higher security, making them particularly suitable for applications with high randomness requirements.

[0004] Quantum random number applications require random number schemes that are low-cost, low-power, small in size, and highly stable and reliable.

[0005] Currently, based on the generation methods and characteristics of the output sequences, random number generation methods can be divided into two main categories: pseudo-random number generators and physical random number generators. Physical random numbers are based on the randomness of some non-deterministic objective physical phenomena, including atmospheric noise, electronic noise, circuit jitter, etc. These random number generators produce random numbers by detecting the results of these physical phenomena. Furthermore, if these physical phenomena are quantum phenomena, then this type of physical random number generator is called a quantum random number generator. These physical phenomena include quantum physical processes such as tunneling, vacuum fluctuations, and phase noise. Due to the intrinsic randomness of quantum mechanics in quantum physical processes, quantum random numbers are generally considered to possess true randomness, are unpredictable, and are an ideal type of random number generator.

[0006] Randomness is an intrinsic property of many quantum phenomena, such as the fundamental quantum state collapse, quantum tunneling, and the uncertainty principle of observables. Since the quantum random number generator scheme based on single-photon branching path selection was proposed in 2000, quantum random source schemes based on different physical systems have been proposed successively. However, most of them require a light source in their design. The stability of the light source, especially under conditions that can exhibit quantum properties, is very difficult to guarantee, and the construction of the light source itself makes it difficult to integrate the entire random number generator system. The quantum tunneling effect under a certain potential barrier is a major intrinsic randomness in quantum mechanics. For example, the widely used InGaAs / InP avalanche diode has a fixed potential barrier (under a certain voltage). Moreover, the tunneling effect of free carriers in the avalanche diode is also an important part of dark counting.

[0007] Time-to-Digital Converter (TDC) technology is based on the delay line structure proposed by R. Nutt in 1968. It is a time measurement method that uses the absolute transmission time of a signal through a logic gate circuit. In the early days, coaxial cables were used to implement the delay line. With the development of integrated circuits, this type of timer was ported to integrated circuits, making it easy to integrate and chip-scale. Summary of the Invention

[0008] In view of the above-mentioned defects or improvement needs of the existing technology, the present invention provides a random data generation method and circuit based on fast and slow clocks, the purpose of which is to realize a miniaturized and chip-based random data generation scheme in the absence of a light source.

[0009] To achieve the above objectives, according to one aspect of the present invention, a random data generation circuit based on fast and slow clocks is provided, comprising analog circuitry and digital circuitry. The analog circuitry includes a reset circuit, an oscillator circuit, a phase-locked loop, and a photodetector. The digital circuitry includes a readout circuit, wherein: The reset circuit is used to provide digital reset pulses to digital and analog circuits, so that the entire random data generation circuit based on fast and slow clocks can work normally. The oscillator circuit is used to provide a stable slow clock for the phase-locked loop and digital circuits after the digital reset pulse ends. The phase-locked loop is used to provide a fast clock for the digital circuit to use for counting after being locked; The photodetector is used to provide a trigger pulse to the readout circuit in the digital circuit after the reset due to dark noise quenching. The readout circuit is used to start timing when the trigger pulse arrives and to end timing when the next rising edge of the system clock arrives, measuring the time interval between the two signals as a random number and outputting it.

[0010] In one embodiment of the present invention, the analog circuit further includes a charge pump and a dark count control circuit. The charge pump starts working after the digital reset pulse ends, the overbias voltage gradually increases to a preset voltage, the photodetector begins to exhibit dark noise triggering, and the dark count control circuit controls the dark noise count rate of the photodetector array by feedback control of the charge pump voltage.

[0011] In one embodiment of the present invention, the photodetector is a photodetector array composed of multiple photodetectors.

[0012] In one embodiment of the present invention, the analog circuit further includes a low-dropout linear regulator, which is used to provide a suitable circuit bias for the analog circuit.

[0013] In one embodiment of the present invention, the photodetector array is a single-photon avalanche diode (SPAD) array.

[0014] In one embodiment of the present invention, the readout circuit is implemented based on a time-to-digital converter.

[0015] In one embodiment of the present invention, the oscillator circuit oscillates at a frequency of 25MHz, and the output frequency of the phase-locked loop is 1GHz.

[0016] In one embodiment of the present invention, the low-dropout linear regulator provides a circuit bias of 1.8V to the circuit.

[0017] According to another aspect of the present invention, a method for generating random data based on fast and slow clocks is also provided, comprising: (1) After power-on, the low-dropout linear regulator provides a suitable circuit bias for the analog circuit; (2) The reset circuit provides a reset pulse for the digital and analog circuits, so that the entire random data generation circuit based on fast and slow clocks can work normally; (3) After the digital reset pulse ends, the oscillator circuit starts to oscillate, providing a stable slow clock for the phase-locked loop and digital circuit. After the phase-locked loop is locked, it also provides a fast clock for the digital circuit to use for counting. (4) After the digital reset pulse ends, the charge pump starts to work, the overbias voltage gradually increases to the preset voltage, the photodetector begins to show dark noise triggering, and at the same time the dark counting control circuit controls the voltage of the charge pump through feedback to control the dark noise counting rate of the photodetector array. (5) When the photodetector is reset due to dark noise quenching, a trigger pulse is provided to the readout circuit, and the readout circuit starts timing. When the next rising edge of the system clock arrives, the readout circuit ends timing, measures the time interval between the two signals as a random number and outputs it to the external chip. (6) Read out the circuit reset, repeat steps (4) and (5) to generate random numbers in a loop.

[0018] In summary, the technical solutions conceived by this invention have the following beneficial effects compared with the prior art: (1) Easier to miniaturize and implement on a chip: This random number generator method does not require a light source, only the measurement end is retained. Therefore, the driving current and temperature control parts required to maintain the stable operation of the light source can be omitted. Moreover, the laser tube itself is often relatively large, making it difficult to miniaturize and implement many quantum random number noise source schemes based on light source measurement. In this invention, the analog-to-digital conversion circuit (i.e., the readout circuit) is implemented using time-to-digital conversion technology (TDC). Time-to-digital conversion modules (chips) already have mature products and technologies. Therefore, the random number generator implemented using this method can be miniaturized and implemented on a chip. (2) The present invention adopts a light source-free design, which makes engineering implementation simpler: Most quantum random number noise source schemes based on light sources measure the phase noise of the light source and convert it into quantum random numbers. However, the signal emitted by the light source also contains classical noise in addition to quantum phase noise. It is necessary to calibrate the light source intensity to improve the proportion of quantum noise. At the same time, the stability requirement of the light source intensity is extremely important. From the perspective of engineering implementation, its complexity is significantly higher than the light source-free method of the present invention. (3) The present invention uses a fast and slow clock design for counting. The fast and slow clocks can perform high-speed timing through the fast clock, and the slow clock can perform low-power operation for data reading and data processing. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of a random data generation circuit based on fast and slow clocks provided by the present invention; Figure 2 This is a schematic diagram illustrating the post-processing principle after random data generation in an embodiment of the present invention. Figure 3 This is a flowchart illustrating a random data generation method based on fast and slow clocks provided by the present invention. Figure 4 This is a specific implementation example diagram of a random data generation circuit based on fast and slow clocks provided by the present invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0021] Example 1 like Figure 1 The diagram shown is a structural schematic of a random data generation circuit based on fast and slow clocks provided by the present invention. The random data generation circuit based on fast and slow clocks includes analog circuits and digital circuits. The analog circuit includes a reset circuit, an oscillator circuit, a phase-locked loop, and a photodetector. The digital circuit includes a readout circuit, wherein: The reset circuit is used to provide digital reset pulses for digital and analog circuits, so that the entire random data generation circuit based on fast and slow clocks can work normally. The oscillator circuit is used to provide a stable slow clock for the phase-locked loop and digital circuits after the digital reset pulse ends. The phase-locked loop is used to provide a fast clock for the digital circuit to use for counting after being locked; The photodetector is used to provide a trigger pulse to the readout circuit in the digital circuit after the reset due to dark noise quenching. The photodetector can be a single photodetector or an array of multiple photodetectors. For example, the photodetector array can be a single-photon avalanche diode (SPAD) array.

[0022] The readout circuit is used to start timing when the trigger pulse arrives and to end timing when the next rising edge of the system clock arrives, measuring the time interval between the two signals as a random number and outputting it.

[0023] The readout circuit is implemented based on a linear feedback shift register.

[0024] Furthermore, such as Figure 1 As shown, the analog circuit also includes a charge pump and a dark count control circuit. The charge pump starts working after the digital reset pulse ends, and the overbias voltage gradually increases to a preset voltage, triggering dark noise in the photodetector. The dark count control circuit controls the dark noise count rate of the photodetector by feedback control of the charge pump voltage.

[0025] Furthermore, such as Figure 1 As shown, the analog circuit also includes a low-dropout linear regulator, which is used to provide a suitable circuit bias for the analog circuit.

[0026] Preferably, the low-dropout linear regulator provides a 1.8V circuit bias to the circuit. The oscillator circuit oscillates at a frequency of 25MHz, and the phase-locked loop outputs a frequency of 1GHz.

[0027] Furthermore, due to the presence of classical noise and the imperfections of the devices, the original data generated by the random data generation circuit based on fast and slow clocks inevitably contains a certain bias. It is necessary to perform certain data post-processing operations to extract randomness so that the final quantum random number sequence satisfies statistical uniformity and meets the requirements for the use of random numbers in cryptography.

[0028] Two problems need to be solved in randomness extraction: (1) how many random numbers can be extracted; and (2) how to guarantee randomness. The solution adopted in this invention is to use the entropy source evaluation method to calculate the proportion of extractable random numbers; and to use an information-theoretically secure randomness extractor based on the Toeplitz matrix method to extract random numbers. Both of these methods are internationally recognized as the most secure methods or among the most secure methods.

[0029] Currently, there are numerous randomness extraction schemes, with mainstream schemes including the logical XOR method, the m-LSB method, the Toeplitz matrix method, and the Trevisan extraction method. The Toeplitz matrix method and the Trevisan extraction method possess theoretical information-theoretic security. This invention employs a Toeplitz matrix-based method that balances speed and security.

[0030] like Figure 2 The diagram shows the post-processing logic flow of this invention. Each input consists of n bits of raw data, the output sequence is m bits, and R is the extraction ratio. .

[0031] Where n is the number of columns in the matrix, and m is the number of rows in the matrix. A Toeplitz matrix is ​​a matrix of the following form:

[0032] The values ​​of the diagonals from left to right and from top to bottom are all the same, that is... It consists of a length of The 0 / 1 sequence is defined, and is sometimes also written as: 0 / 1 sequence This is called the definition vector or seed of the Toeplitz matrix. To improve security, the seed is provided by a true random number generator, and the actual post-processing is performed according to a fixed data block size.

[0033] Input: n-bit 0 / 1 raw data sequence It can be directly regarded as a row vector.

[0034] Output: m-bit 0 / 1 quantum random number sequence It is calculated according to the following formula. .

[0035] Example 2 like Figure 3 The diagram shows a flowchart illustrating a random data generation method based on fast and slow clocks provided by the present invention. This method is implemented based on the aforementioned random data generation circuit based on fast and slow clocks and includes: (1) After power-on, the low-dropout linear regulator provides a suitable circuit bias for the analog circuit; (2) The reset circuit provides a reset pulse for the digital and analog circuits, so that the entire random data generation circuit based on fast and slow clocks can work normally; (3) After the digital reset pulse ends, the oscillator circuit starts to oscillate, providing a stable slow clock for the phase-locked loop and digital circuit. After the phase-locked loop is locked, it also provides a fast clock for the digital circuit to use for counting. (4) After the digital reset pulse ends, the charge pump starts to work, the overbias voltage gradually increases to the preset voltage, the photodetector begins to show dark noise triggering, and at the same time the dark counting control circuit controls the voltage of the charge pump through feedback to control the dark noise counting rate of the photodetector array. (5) When the photodetector is reset due to dark noise quenching, a trigger pulse is provided to the readout circuit, and the readout circuit starts timing. When the next rising edge of the system clock arrives, the readout circuit ends timing, measures the time interval between the two signals as a random number and outputs it to the external chip.

[0036] Because the arrival time of the dark pulse is quantum random, the time interval between the dark pulse and the fixed clock is unpredictable. When the photodetector in the photodetector array is reset due to dark noise quenching, it provides a trigger pulse to the readout circuit, which starts timing. When the next rising edge of the system clock arrives, the readout circuit stops timing, measures the time interval between the two signals as a random number, and outputs it off-chip.

[0037] (6) Read out the circuit reset, repeat steps (4) and (5) to generate random numbers in a loop.

[0038] Example 3 like Figure 4 As shown, this embodiment of the invention provides a scheme for a random data generation circuit based on fast and slow clocks, the specific implementation of which is as follows: The first step is that after power-on, the low-dropout linear regulator provides a circuit bias of 1.8V to the circuit; The second step is that the reset circuit provides reset pulses to the digital and analog circuits to enable the chip to work normally. Third, after the digital reset pulse ends, the oscillator circuit starts oscillating at a frequency of 25MHz to provide a stable clock for the phase-locked loop and digital circuits. After the phase-locked loop with an output frequency of 1GHz is locked, it also provides a fast clock for the digital circuits to use for counting. The phase-locked loop also provides a reference bias voltage for the replicated ring oscillator, so that the clock in the replicated phase-locked loop can rotate stably. The rotation frequency is also 1GHz when the timing starts (it should be noted that in this invention, 25MHz and 1GHz can be changed and adjusted according to process requirements). In the fourth step, after the digital reset pulse ends, the charge pump starts to work, the overbias voltage gradually increases to the preset voltage, and the single-photon avalanche diode (SPAD) array begins to exhibit dark noise triggering. At the same time, the dark count control circuit can control the voltage of the charge pump through feedback, thereby controlling the dark noise count rate of the photodetector array. Fifth, because the arrival time of the dark pulse exhibits quantum randomness, the time interval between the dark pulse and the fixed clock is unpredictable. When the photodetectors in the photodetector array are reset due to dark noise quenching, a trigger pulse is provided to the readout circuit based on the time-to-digital converter (TDC). The readout circuit begins timing, and the replicated phase-locked loop performs a stable 1 GHz toggle, also providing a 1 GHz timing clock for the time-to-digital converter (TDC). When the next rising edge of the system clock arrives, the readout circuit stops timing, measures the time interval between the two signals as a random number, and outputs it off-chip.

[0039] Step 6: Reset the time-to-digital converter, and repeat steps 4 and 5 to generate random numbers in a loop.

[0040] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A random data generation circuit based on fast and slow clocks, characterized in that, It includes analog circuits and digital circuits. The analog circuits include a reset circuit, an oscillator circuit, a phase-locked loop, and a photodetector. The digital circuits include a readout circuit, wherein: The reset circuit is used to provide digital reset pulses to digital and analog circuits, so that the entire random data generation circuit based on fast and slow clocks can work normally. The oscillator circuit is used to provide a stable slow clock for the phase-locked loop and digital circuits after the digital reset pulse ends. The phase-locked loop is used to provide a fast clock for the digital circuit to use for counting after being locked; The photodetector is used to provide a trigger pulse to the readout circuit in the digital circuit after the reset due to dark noise quenching. The readout circuit is used to start timing when the trigger pulse arrives, and to end timing when the next rising edge of the system clock arrives. It measures the time interval between the two signals as a random number and outputs it. The analog circuit also includes a charge pump and a dark count control circuit. The charge pump starts working after the digital reset pulse ends, and the overbias voltage gradually increases to a preset voltage, triggering dark noise in the photodetector. The dark count control circuit controls the dark noise count rate of the photodetector array by controlling the voltage of the charge pump through feedback. The analog circuit also includes a low-dropout linear regulator, which is used to provide a suitable circuit bias for the analog circuit.

2. The random data generation circuit based on fast and slow clocks as described in claim 1, characterized in that, The photodetector is a photodetector array composed of multiple photodetectors.

3. The random data generation circuit based on fast and slow clocks as described in claim 2, characterized in that, The photodetector array is a single-photon avalanche diode (SPAD) array.

4. The random data generation circuit based on fast and slow clocks as described in claim 1, characterized in that, The readout circuit is implemented based on a time-to-digital converter.

5. The random data generation circuit based on fast and slow clocks as described in claim 1, characterized in that, The oscillator circuit oscillates at a frequency of 25MHz, and the phase-locked loop outputs at a frequency of 1GHz.

6. The random data generation circuit based on fast and slow clocks as described in claim 1, characterized in that, The low-dropout linear regulator provides a 1.8V circuit bias to the circuit.

7. A method for generating random data based on a fast / slow clock based on the random data generation circuit based on any one of claims 1-6, characterized in that, include: (1) After power-on, the low-dropout linear regulator provides a suitable circuit bias for the analog circuit; (2) The reset circuit provides a reset pulse for the digital and analog circuits, so that the entire random data generation circuit based on fast and slow clocks can work normally; (3) After the digital reset pulse ends, the oscillator circuit starts to oscillate, providing a stable slow clock for the phase-locked loop and digital circuit. After the phase-locked loop is locked, it also provides a fast clock for the digital circuit to use for counting. (4) After the digital reset pulse ends, the charge pump starts to work, the overbias voltage gradually increases to the preset voltage, the photodetector begins to show dark noise triggering, and at the same time the dark count control circuit controls the voltage of the charge pump through feedback to control the dark noise count rate of the photodetector array. (5) When the photodetector is reset due to dark noise quenching, a trigger pulse is provided to the readout circuit, and the readout circuit starts timing. When the next rising edge of the system clock arrives, the readout circuit ends timing, measures the time interval between the two signals as a random number and outputs it to the external chip. (6) Read out the circuit reset, repeat steps (4) and (5) to generate random numbers in a loop.

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