Serial interface circuit
By using a design that shares transistors in the bias circuit and differential circuit in the serial interface circuit, the problems of large size and high load capacitance in the existing MIPI and LVDS interface circuits are solved, achieving circuit compactness and signal compatibility.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI ANLOGIC INFOTECH CO LTD
- Filing Date
- 2023-07-03
- Publication Date
- 2026-07-31
AI Technical Summary
Existing interface circuits that are compatible with both MIPI and LVDS require an external resistor network to implement differential signals using two single-ended I/O pins, resulting in a large circuit size and high parasitic load capacitance.
A bias circuit is used to provide a bias signal for the IO interface driver circuit. The LVDS signal is output through the first differential circuit and the MIPI signal is output through the second differential circuit. The first transistor and the second transistor are used together, reducing the use of external resistor networks.
While being compatible with LVDS and MIPI signals, it reduces circuit size and parasitic load capacitance, and avoids changing the common-mode voltage of the IO interface driver circuit under a fixed output current.
Smart Images
Figure CN117130960B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of electronic circuit technology, and more particularly to a serial interface circuit. Background Technology
[0002] MIPI (Mobile Industry Processor Interface) is an alliance established in 2003 by companies such as ARM, Nokia, ST, and TI. Its purpose is to standardize internal mobile phone interfaces such as camera, display, and RF / baseband interfaces, thereby reducing the complexity of mobile phone design and increasing design flexibility. MIPI electrical signals are characterized by small differential amplitude and low common-mode voltage. Typical output high voltage is 0.3V, and low voltage is 0.1V. LVDS (Low-Voltage Differential Signaling) is a signal transmission mode level standard proposed by National Semiconductor (NS, now TI) in 1994. It uses extremely low voltage swing for high-speed differential data transmission, enabling point-to-point or point-to-multipoint connections. It has advantages such as low power consumption, low bit error rate, low crosstalk, and low radiation. Compared to MIPI electrical signals, LVDS electrical signals are characterized by larger differential amplitude and higher common-mode voltage. Typical output high voltage is 1.425V, and low voltage is 1.075V. With the rapid development of mobile electronic devices, the MIPI interface, as a new high-speed interface for mobile devices, is increasingly used, especially the MIPI output interface, which is widely used for image acquisition and display, and screen display control of electronic devices. However, existing interface circuits that are compatible with both MIPI and LVDS require an external resistor network to implement differential signals using two single-ended I / Os, and also require an additional pull-down module to obtain the required output. Therefore, existing interface circuits that are compatible with both MIPI and LVDS are relatively large in size, resulting in high parasitic load capacitance. Summary of the Invention
[0003] This invention provides a serial interface circuit to solve the technical problem of high parasitic load capacitance in existing interface circuits that are compatible with both MIPI and LVDS.
[0004] To address the aforementioned technical problems, embodiments of the present invention provide a serial interface circuit, comprising: a bias circuit and an I / O interface driving circuit; wherein, the I / O interface driving circuit comprises: a first transistor, a second transistor, a first differential circuit, and a second differential circuit;
[0005] The first terminal of the first transistor is connected to a voltage source, and the second terminal of the first transistor is connected to the first terminal of the first differential circuit and the first terminal of the second differential circuit, respectively.
[0006] The first terminal of the second transistor is connected to the second terminal of the first differential circuit and the second terminal of the second differential circuit, respectively, and the second terminal of the second transistor is grounded;
[0007] The bias circuit is used to convert the first reference voltage into a first differential bias signal and transmit the first differential bias signal to the IO interface driver circuit; and to convert the second reference voltage into a second differential bias signal and transmit the second differential bias signal to the IO interface driver circuit.
[0008] The first differential circuit is used to output an LVDS signal when the first transistor and the second transistor receive a first differential bias signal;
[0009] The second differential circuit is used to output a MIPI signal when the first transistor and the second transistor receive the second differential bias signal.
[0010] This invention employs a bias circuit to provide a bias signal for the I / O interface driver circuit, thereby enabling the I / O interface bias circuit to output an LVDS signal through a first differential circuit and a MIPI signal through a second differential circuit based on the bias signal. While being compatible with both LVDS and MIPI differential signals, this invention avoids changing the common-mode voltage of the I / O interface driver circuit under the premise of a fixed output current, thus eliminating the need for an external resistor network. Furthermore, the first and second differential circuits share the first and second transistors, further reducing the circuit size and thus reducing parasitic load capacitance.
[0011] Furthermore, the bias circuit includes: a first input terminal, a second input terminal, a first output terminal, and a second output terminal; the IO interface driving circuit includes: a first input terminal, a second input terminal, a first output terminal, and a second output terminal.
[0012] While the first input terminal of the bias circuit receives a first high level, the second input terminal of the bias circuit receives a first low level; or, while the first input terminal of the bias circuit receives a second high level, the second input terminal of the bias circuit receives a second low level; the first reference voltage includes: the first high level and the first low level; the second reference voltage includes: the second high level and the second low level;
[0013] The first output terminal of the bias circuit is connected to the first input terminal of the IO interface driver circuit, and the second output terminal of the bias circuit is connected to the second input terminal of the IO interface driver circuit.
[0014] The control terminal of the first transistor is the first input terminal of the IO interface driver circuit;
[0015] The control terminal of the second transistor is the second input terminal of the IO interface driver circuit;
[0016] The first output terminal and the second output terminal of the IO interface driver circuit output LVDS signal or MIPI signal.
[0017] Furthermore, the first differential circuit includes: a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; the second differential circuit includes: the fifth transistor, the sixth transistor, a seventh transistor, and an eighth transistor;
[0018] The first terminal of the third transistor is connected to the first terminal of the fourth transistor, the first terminal of the seventh transistor, and the first terminal of the eighth transistor, and together they form the first terminal of the first differential circuit.
[0019] The first terminal of the fifth transistor is connected to the second terminal of the third transistor and the second terminal of the seventh transistor, and together they form the first output terminal of the IO interface driver circuit.
[0020] The first terminal of the sixth transistor is connected to the second terminal of the fourth transistor and the second terminal of the eighth transistor, and together they form the second output terminal of the IO interface driver circuit.
[0021] The second terminal of the fifth transistor and the second terminal of the sixth transistor together constitute the second terminal of the first differential circuit.
[0022] In this invention, the first differential circuit and the second differential circuit share the second transistor, the fifth transistor, and the sixth transistor, thereby using the same pull-down path, further reducing the size of the IO interface driver circuit and reducing parasitic load capacitance.
[0023] Furthermore, the bias circuit includes: a first replication bias circuit, a second replication bias circuit, and a first resistor;
[0024] Wherein, the input terminal of the first replication bias circuit is the first input terminal of the bias circuit;
[0025] The output terminal of the first replication bias circuit is the first output terminal of the bias circuit;
[0026] The first terminal of the first replication bias circuit is connected to the voltage source;
[0027] The second terminal of the first replication bias circuit is connected to the first terminal of the first resistor;
[0028] The input terminal of the second replication bias circuit is the second input terminal of the bias circuit;
[0029] The output terminal of the second replication bias circuit is the second output terminal of the bias circuit;
[0030] The first terminal of the second replication bias circuit is connected to the second terminal of the first resistor;
[0031] The second terminal of the second replication bias circuit is grounded;
[0032] The first replication bias circuit is used to convert the first high level into a high level in the first differential bias signal; and to convert the second high level into a high level in the second differential bias signal;
[0033] The second replication bias circuit is used to convert the first low level to a low level of the first differential bias signal; and to convert the second low level to a low level of the second differential bias signal.
[0034] This invention uses a first and a second copy bias circuit to provide a bias signal to the IO interface driver circuit, thereby changing the differential voltage output by the IO interface driver circuit and realizing the conversion of the output signal. While being compatible with LVDS and MIPI signals, it avoids changing the output differential voltage of the IO interface driver circuit under the premise of fixed output current. As a result, it eliminates the need for an external resistor network, reduces the circuit size, and reduces parasitic load capacitance.
[0035] Furthermore, the first replication bias circuit includes: a first operational amplifier, a ninth transistor, a tenth transistor, and an eleventh transistor;
[0036] Wherein, the inverting input terminal of the first operational amplifier is the input terminal of the first replication bias circuit;
[0037] The output terminal of the first operational amplifier is connected to the control terminal of the ninth transistor, and the output terminal of the first operational amplifier is the output terminal of the first replication bias circuit.
[0038] The first terminal of the ninth transistor is the first terminal of the first replication bias circuit;
[0039] The second terminal of the ninth transistor is connected to the first terminal of the tenth transistor and the first terminal of the eleventh transistor, respectively.
[0040] The second terminal of the tenth transistor is connected to the second terminal of the eleventh transistor and the output terminal of the first operational amplifier, respectively, and together they form the second terminal of the first replication bias circuit.
[0041] Furthermore, the ninth transistor and the first transistor are both PMOS transistors with the same width-to-length ratio; the tenth transistor, the third transistor, and the fourth transistor are all PMOS transistors with the same width-to-length ratio; the eleventh transistor, the seventh transistor, and the eighth transistor are all NMOS transistors with the same width-to-length ratio.
[0042] Furthermore, the second replication bias circuit includes: a second operational amplifier, a twelfth transistor, and a thirteenth transistor;
[0043] Wherein, the inverting input terminal of the second operational amplifier is the input terminal of the second copy bias circuit;
[0044] The output terminal of the second operational amplifier is connected to the control terminal of the twelfth transistor, and the output terminal of the second operational amplifier is the output terminal of the second replication bias circuit;
[0045] The first terminal of the twelfth transistor is connected to the second terminal of the thirteenth transistor;
[0046] The second terminal of the twelfth transistor is the second terminal of the second replication bias circuit;
[0047] The first terminal of the thirteenth transistor is connected to the non-inverting input terminal of the second operational amplifier, together forming the first terminal of the second replication bias circuit.
[0048] Furthermore, the twelfth transistor and the second transistor are both NMOS transistors with the same width-to-length ratio, and the thirteenth transistor, the fifth transistor, and the sixth transistor are all NMOS transistors with the same width-to-length ratio.
[0049] Furthermore, the serial interface circuit also includes: a first transmission line, a second transmission line, and a terminating differential resistor;
[0050] The first output terminal of the IO interface driver circuit is connected to the first end of the first transmission line.
[0051] The second end of the first transmission line is connected to the first end of the terminating differential resistor;
[0052] The second output terminal of the IO interface driver circuit is connected to the second terminal of the second transmission line;
[0053] The second end of the second transmission line is connected to the second end of the terminating differential resistor.
[0054] Furthermore, the terminal differential resistor and the first resistor have the same resistance value. Attached Figure Description
[0055] Figure 1A schematic diagram of one embodiment of the serial interface circuit provided by the present invention;
[0056] Figure 2 A schematic diagram of the connection relationship of an embodiment of the serial interface circuit provided by the present invention;
[0057] Figure 3 A schematic diagram showing the connection relationship of another embodiment of the serial interface circuit provided by the present invention;
[0058] Figure 4 This is a schematic diagram of the LVDS mode of the serial interface circuit of the present invention;
[0059] Figure 5 This is a schematic diagram of the MIPI mode of the serial interface circuit of the present invention;
[0060] Figure 6 This is a schematic diagram of the differential voltage control circuit of the prior art CN114759890A;
[0061] Figure 7 This is a schematic diagram of the LVDS transmitter in the prior art CN114153263A;
[0062] Figure 8 This is a schematic diagram of a general interface circuit for MIPI signal output compatible with the existing technology CN107341118A. Detailed Implementation
[0063] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0064] Please refer to Figure 1 This is a schematic diagram of a serial interface circuit according to an embodiment of the present invention. The serial interface circuit includes: a bias circuit and an I / O interface driving circuit; wherein, the I / O interface driving circuit includes: a first transistor, a second transistor, a first differential circuit, and a second differential circuit.
[0065] The first terminal of the first transistor is connected to a voltage source, and the second terminal of the first transistor is connected to the first terminal of the first differential circuit and the first terminal of the second differential circuit, respectively.
[0066] The first terminal of the second transistor is connected to the second terminal of the first differential circuit and the second terminal of the second differential circuit, respectively, and the second terminal of the second transistor is grounded;
[0067] The bias circuit is used to convert the first reference voltage into a first differential bias signal and transmit the first differential bias signal to the IO interface driver circuit; and to convert the second reference voltage into a second differential bias signal and transmit the second differential bias signal to the IO interface driver circuit.
[0068] The first differential circuit is used to output an LVDS signal when the first transistor and the second transistor receive a first differential bias signal;
[0069] The second differential circuit is used to output a MIPI signal when the first transistor and the second transistor receive the second differential bias signal.
[0070] In this embodiment, a bias circuit is used to provide a bias signal to the I / O interface driver circuit, thereby enabling the I / O interface bias circuit to output an LVDS signal through a first differential circuit and a MIPI signal through a second differential circuit based on the bias signal; please refer to Figure 8 The diagram below illustrates a general interface circuit for MIPI-compatible signal output, as described in prior art CN107341118A. This circuit uses two single-ended I / O pins to implement a pair of differential signals, constituting a pseudo-differential application. It requires an external resistor network and its speed cannot exceed 800 Mbps. In contrast, this invention, while compatible with both LVDS and MIPI differential signals, avoids changing the common-mode voltage of the I / O interface driver circuit while maintaining a fixed output current, thus eliminating the need for an external resistor network. Please refer to... Figure 6 The diagram shows a differential voltage control circuit of the prior art CN114759890A, which requires four modules to achieve the required IOUT, increasing the area of the interface circuit. In contrast, the first differential circuit and the second differential circuit in this embodiment of the invention share the first transistor and the second transistor, further reducing the circuit size and thus reducing parasitic load capacitance.
[0071] Please refer to Figure 2 This is a schematic diagram of the connection relationship of an embodiment of the serial interface circuit provided by the present invention. Vref generation is a reference voltage, including a first reference voltage for switching LVDS mode and a second reference voltage for switching MIPI mode; Replica Bias is the bias circuit in this embodiment; IO Driver is the IO interface driver circuit in this embodiment; Board is a circuit board; Transition Line is a transmission line; Terminal R is a terminating differential resistor; the bias circuit includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal; the IO interface driver circuit includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal.
[0072] While the first input terminal of the bias circuit receives a first high level, the second input terminal of the bias circuit receives a first low level; or, while the first input terminal of the bias circuit receives a second high level, the second input terminal of the bias circuit receives a second low level; the first reference voltage includes: the first high level and the first low level; the second reference voltage includes: the second high level and the second low level;
[0073] The first output terminal of the bias circuit is connected to the first input terminal of the IO interface driver circuit, and the second output terminal of the bias circuit is connected to the second input terminal of the IO interface driver circuit.
[0074] The control terminal of the first transistor is the first input terminal of the IO interface driver circuit;
[0075] The control terminal of the second transistor is the second input terminal of the IO interface driver circuit;
[0076] The first output terminal and the second output terminal of the IO interface driver circuit output LVDS signal or MIPI signal.
[0077] Please refer to Figure 3 This is a schematic diagram of the connection relationship of another embodiment of the serial interface circuit provided by the present invention; wherein, pbias and nbias together constitute a differential bias signal, DP is the first output terminal of the IO interface driver circuit, and DN is the second output terminal of the IO interface driver circuit; the first differential circuit includes: a third transistor PM1, a fourth transistor PM2, a fifth transistor NM1, and a sixth transistor NM2; the second differential circuit includes: the fifth transistor NM1, the sixth transistor NM2, the seventh transistor NM3, and the eighth transistor NM4;
[0078] The first terminal of the third transistor PM1 is connected to the first terminal of the fourth transistor PM2, the first terminal of the seventh transistor NM3, and the first terminal of the eighth transistor NM4, and together they form the first terminal of the first differential circuit.
[0079] The first terminal of the fifth transistor NM1 is connected to the second terminal of the third transistor PM1 and the second terminal of the seventh transistor NM3, and together they form the first output terminal of the IO interface driver circuit.
[0080] The first terminal of the sixth transistor NM2 is connected to the second terminal of the fourth transistor PM2 and the second terminal of the eighth transistor NM4, and together they form the second output terminal of the IO interface driver circuit.
[0081] The second terminal of the fifth transistor NM1 and the second terminal of the sixth transistor NM2 together constitute the second terminal of the first differential circuit.
[0082] In this embodiment, the second differential circuit includes: the fifth transistor NM1, the sixth transistor NM2, the seventh transistor NM3, and the eighth transistor NM4;
[0083] The drain of the seventh transistor NM3 and the drain of the eighth transistor NM4 together form the first terminal of the second differential circuit.
[0084] The source of the seventh transistor NM3 is connected to the drain of the fifth transistor NM1, and together they form the first output terminal of the second differential circuit.
[0085] The source of the eighth transistor NM4 is connected to the drain of the sixth transistor NM2, and together they form the second output terminal of the second differential circuit.
[0086] The source of the fifth transistor NM1 and the source of the sixth transistor NM2 together form the second terminal of the second differential circuit.
[0087] In this embodiment, the first differential circuit and the second differential circuit share the second transistor NM0, the fifth transistor NM1 and the sixth transistor NM2, thereby using the same pull-down path, further reducing the size of the IO interface driver circuit and reducing parasitic load capacitance.
[0088] In this embodiment, the second differential circuit may further consist of a seventh transistor NM3, an eighth transistor NM4, a ninth NMOS transistor, and a tenth NMOS transistor; wherein the drain of the seventh transistor NM3 and the drain of the eighth transistor NM4 together constitute the first terminal of the second differential circuit; the source of the seventh transistor NM3 is connected to the drain of the ninth NMOS transistor and together constitutes the first output terminal of the second differential circuit; the source of the eighth transistor NM4 is connected to the drain of the tenth NMOS transistor and together constitutes the second output terminal of the second differential circuit; and the source of the ninth NMOS transistor and the source of the tenth NMOS transistor together constitute the second terminal of the second differential circuit.
[0089] Please refer to Figure 4 The diagram shows the LVDS mode of the serial interface circuit of the present invention. When it is necessary to send an LVDS signal, a first reference voltage LVDS Mode of 1.425V and a first low level of 1.075V can be input to the bias circuit. At this time, the seventh transistor NM3 and the eighth transistor NM4 are turned off, so that the first differential circuit, the first transistor PM0 and the second transistor NM0 together form an LVDS driving circuit. The first output terminal and the second output terminal of the IO interface driving circuit output the LVDS signal.
[0090] Please refer to Figure 5 The diagram shows the MIPI mode of the serial interface circuit of the present invention. When it is necessary to send a MIPI signal, a second reference voltage MIPI Mode of 0.3V and 0.1V low level can be input to the bias circuit. At this time, the third transistor PM1 and the fourth transistor PM2 are turned off so that the second differential circuit, the first transistor PM0 and the second transistor NM0 together form the MIPI driving circuit. The first output terminal and the second output terminal of the IO interface driving circuit output the MIPI signal.
[0091] In this embodiment, the bias circuit includes: a first replication bias circuit, a second replication bias circuit, and a first resistor Replica R;
[0092] Wherein, the input terminal of the first replication bias circuit is the first input terminal of the bias circuit;
[0093] The output terminal of the first replication bias circuit is the first output terminal of the bias circuit;
[0094] The first terminal of the first replication bias circuit is connected to the voltage source;
[0095] The second terminal of the first replication bias circuit is connected to the first terminal of the first resistor Replica R;
[0096] The input terminal of the second replication bias circuit is the second input terminal of the bias circuit;
[0097] The output terminal of the second replication bias circuit is the second output terminal of the bias circuit;
[0098] The first terminal of the second replication bias circuit is connected to the second terminal of the first resistor Replica R;
[0099] The second terminal of the second replication bias circuit is grounded;
[0100] The first replication bias circuit is used to convert the first high level into a high level in the first differential bias signal; and to convert the second high level into a high level in the second differential bias signal;
[0101] The second replication bias circuit is used to convert the first low level to a low level of the first differential bias signal; and to convert the second low level to a low level of the second differential bias signal.
[0102] In this embodiment, a first and a second replication bias circuit are used to provide bias signals to the I / O interface driver circuit, thereby changing the differential voltage output by the I / O interface driver circuit and realizing the conversion of the output signal. This avoids changing the output signal while maintaining compatibility with LVDS and MIPI signals, under the premise of a fixed output current.
[0103] The I / O interface driver circuit outputs differential voltage, thus eliminating the need for an external resistor network, reducing circuit size, and decreasing parasitic load capacitance.
[0104] In this embodiment, the first replication bias circuit includes: a first operational amplifier op1, a ninth transistor PPM0, a tenth transistor PPM1, and an eleventh transistor NNM2.
[0105] Wherein, the inverting input terminal of the first operational amplifier op1 is the input terminal of the first copy bias circuit;
[0106] The output terminal of the first operational amplifier op1 is connected to the control terminal of the ninth transistor PPM0, and the output terminal of the first operational amplifier op1 is the output terminal of the first replication bias circuit.
[0107] The first terminal of the ninth transistor PPM0 is the first terminal of the first replication bias circuit.
[0108] The second terminal of the ninth transistor PPM0 is connected to the first terminal of the tenth transistor PPM1 and the first terminal of the eleventh transistor NNM2, respectively.
[0109] The second terminal of the tenth transistor PPM1 is connected to the second terminal of the eleventh transistor NNM2 and the output terminal of the first operational amplifier op1, respectively, and together they form the second terminal of the first replication bias circuit.
[0110] In this embodiment, the ninth transistor PPM0 and the first transistor PM0 are both PMOS transistors with the same width-to-length ratio; the tenth transistor PPM1, the third transistor PM1 and the fourth transistor PM2 are all PMOS transistors with the same width-to-length ratio; the eleventh transistor NNM2, the seventh transistor NM3 and the eighth transistor NM4 are all NMOS transistors with the same width-to-length ratio.
[0111] In this embodiment, the first terminal of the first transistor PM0, the third transistor PM1, the fourth transistor PM2, the ninth transistor PPM0, and the tenth transistor PPM1 are all sources, the second terminal of all are drains, and the control terminal of all are gates.
[0112] In this embodiment, the second replication bias circuit includes: a second operational amplifier op2, a twelfth transistor NNM0, and a thirteenth transistor NNM1;
[0113] Wherein, the inverting input terminal of the second operational amplifier op2 is the input terminal of the second copy bias circuit;
[0114] The output terminal of the second operational amplifier op2 is connected to the control terminal of the twelfth transistor NNM0, and the output terminal of the second operational amplifier op2 is the output terminal of the second replication bias circuit;
[0115] The first terminal of the twelfth transistor NNM0 is connected to the second terminal of the thirteenth transistor NNM1;
[0116] The second terminal of the twelfth transistor NNM0 is the second terminal of the second replication bias circuit;
[0117] The first terminal of the thirteenth transistor NNM1 is connected to the non-inverting input terminal of the second operational amplifier op2, together forming the first terminal of the second replication bias circuit.
[0118] In this embodiment, the twelfth transistor NNM0 and the second transistor NM0 are both NMOS transistors with the same width-to-length ratio, and the thirteenth transistor NNM1, the fifth transistor NM1, and the sixth transistor NM2 are all NMOS transistors with the same width-to-length ratio. Please refer to... Figure 7 The diagram shows an LVDS transmitter from the prior art CN114153263A. This LVDS transmitter cannot achieve signal switching between LVDS and MIPI. Furthermore, its bias circuits 301 and 303 both ignore the effect of the on-resistance of the M7 / M8 and M9 / M10 switches in the interface circuit 302, which leads to inaccurate output from the biased interface circuit. In contrast, the embodiment of this invention standardizes the size of the transistors used in the bias circuit and the IO interface driver circuit, thus ensuring the accuracy of the output results.
[0119] In this embodiment, the first terminal of the second transistor NM0, the fifth transistor NM1, the sixth transistor NM2, the seventh transistor NM3, the eighth transistor NM4, the eleventh transistor NNM2, the twelfth transistor NNM0, and the thirteenth transistor NNM1 are all drains, the second terminal of all are sources, and the control terminal of all are gates.
[0120] Please refer to Figure 4The diagram illustrates the LVDS mode of the serial interface circuit of this invention. When an LVDS signal needs to be transmitted, in addition to inputting a first reference voltage (LVDS Mode: 1.425V high level, 1.075V low level) to the bias circuit, a low level (e.g., 0V) is also input to the gate of the tenth transistor PPM1 and the gate of the eleventh transistor NNM2 to turn off the eleventh transistor NNM2. This allows the ninth transistor PPM0, the tenth transistor PPM1, the twelfth transistor NNM0, the thirteenth transistor NNM1, and the first resistor Replica R to form a feedback path, thereby outputting different first bias signals and second bias signals according to different first and second reference voltages. The gate of the thirteenth transistor NNM1 is kept at a high level, such as 1.8V.
[0121] Please refer to Figure 5 This is a schematic diagram of the MIPI mode of the serial interface circuit of the present invention. When a MIPI signal needs to be sent, a second reference voltage (MIPI Mode: 0.3V high level, 0.1V low level) can be input to the bias circuit. A high level, for example, 1.8V, is also input to the gate of the tenth transistor PPM1 and the gate of the eleventh transistor NNM2 to turn off the tenth transistor PPM1. This allows the ninth transistor PPM0, the eleventh transistor NNM2, the twelfth transistor NNM0, the thirteenth transistor NNM1, and the first resistor Replica R to form a feedback path, thereby outputting different first and second bias signals according to different first and second reference voltages. The gate of the thirteenth transistor NNM1 is kept at a high level, such as 1.8V.
[0122] By using the embodiments of the present invention, the required first bias signal and second bias signal can be obtained simply by adjusting the first reference voltage and the second reference voltage, thereby realizing the switching of the output signal and enabling more flexible configuration of common-mode voltage and differential-mode voltage.
[0123] In this embodiment, the consistent dimensions of different components ensure that the signals output by the IO interface driver circuit meet the LVDS and MIPI protocols.
[0124] In this embodiment, the serial interface circuit further includes: a first transmission line, a second transmission line, and a terminating differential resistor Terminal R;
[0125] The first output terminal of the IO interface driver circuit is connected to the first end of the first transmission line.
[0126] The second end of the first transmission line is connected to the first end of the terminal differential resistor Terminal R;
[0127] The second output terminal of the IO interface driver circuit is connected to the second terminal of the second transmission line;
[0128] The second end of the second transmission line is connected to the second end of the terminal differential resistor Terminal R.
[0129] In this embodiment, the terminal differential resistor Terminal R and the first resistor Replica R have the same resistance value.
[0130] In this embodiment, the first resistor Replica R is 50-150Ω, preferably 100Ω; the terminal differential resistor Terminal R is 50-150Ω, preferably 100Ω.
[0131] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. In particular, it should be noted that any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention for those skilled in the art.
Claims
1. A serial interface circuit, characterized in that, include: Bias circuit and I / O interface driving circuit; wherein, the I / O interface driving circuit includes: a first transistor, a second transistor, a first differential circuit and a second differential circuit; The first terminal of the first transistor is connected to a voltage source, and the second terminal of the first transistor is connected to the first terminal of the first differential circuit and the first terminal of the second differential circuit, respectively. The first terminal of the second transistor is connected to the second terminal of the first differential circuit and the second terminal of the second differential circuit, respectively, and the second terminal of the second transistor is grounded; The bias circuit is used to convert the first reference voltage into a first differential bias signal and transmit the first differential bias signal to the IO interface driver circuit; and to convert the second reference voltage into a second differential bias signal and transmit the second differential bias signal to the IO interface driver circuit. The first differential circuit is used to output an LVDS signal when the first transistor and the second transistor receive a first differential bias signal; the first differential circuit includes: a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; the second differential circuit includes: the fifth transistor, the sixth transistor, a seventh transistor, and an eighth transistor; The drain of the third transistor is connected to the drain of the fourth transistor, the drain of the seventh transistor, and the drain of the eighth transistor, and together they form the first terminal of the first differential circuit. The first terminal of the fifth transistor is connected to the second terminal of the third transistor and the second terminal of the seventh transistor, and together they form the first output terminal of the IO interface driver circuit. The first terminal of the sixth transistor is connected to the second terminal of the fourth transistor and the second terminal of the eighth transistor, and together they form the second output terminal of the IO interface driver circuit. The source of the fifth transistor and the source of the sixth transistor together form the second terminal of the first differential circuit; The drain of the seventh transistor and the drain of the eighth transistor together form the first terminal of the second differential circuit; The source of the fifth transistor and the source of the sixth transistor together form the second terminal of the second differential circuit; The second differential circuit is used to output a MIPI signal when the first transistor and the second transistor receive the second differential bias signal.
2. The serial interface circuit as described in claim 1, characterized in that, The bias circuit includes: a first input terminal, a second input terminal, a first output terminal, and a second output terminal; the IO interface driver circuit includes: a first input terminal, a second input terminal, a first output terminal, and a second output terminal. While the first input terminal of the bias circuit receives a first high level, the second input terminal of the bias circuit receives a first low level; or, while the first input terminal of the bias circuit receives a second high level, the second input terminal of the bias circuit receives a second low level; the first reference voltage includes: the first high level and the first low level; the second reference voltage includes: the second high level and the second low level; The first output terminal of the bias circuit is connected to the first input terminal of the IO interface driver circuit, and the second output terminal of the bias circuit is connected to the second input terminal of the IO interface driver circuit. The control terminal of the first transistor is the first input terminal of the IO interface driver circuit; The control terminal of the second transistor is the second input terminal of the IO interface driver circuit; The first output terminal and the second output terminal of the IO interface driver circuit output LVDS signal or MIPI signal.
3. The serial interface circuit as described in claim 2, characterized in that, The bias circuit includes: a first replication bias circuit, a second replication bias circuit, and a first resistor; Wherein, the input terminal of the first replication bias circuit is the first input terminal of the bias circuit; The output terminal of the first replication bias circuit is the first output terminal of the bias circuit; The first terminal of the first replication bias circuit is connected to the voltage source; The second terminal of the first replication bias circuit is connected to the first terminal of the first resistor; The input terminal of the second replication bias circuit is the second input terminal of the bias circuit; The output terminal of the second replication bias circuit is the second output terminal of the bias circuit; The first terminal of the second replication bias circuit is connected to the second terminal of the first resistor; The second terminal of the second replication bias circuit is grounded; The first replication bias circuit is used to convert the first high level into a high level in the first differential bias signal; and to convert the second high level into a high level in the second differential bias signal; The second replication bias circuit is used to convert the first low level to a low level of the first differential bias signal; and to convert the second low level to a low level of the second differential bias signal.
4. The serial interface circuit as described in claim 3, characterized in that, The first replication bias circuit includes: a first operational amplifier, a ninth transistor, a tenth transistor, and an eleventh transistor; Wherein, the inverting input terminal of the first operational amplifier is the input terminal of the first replication bias circuit; The output terminal of the first operational amplifier is connected to the control terminal of the ninth transistor, and the output terminal of the first operational amplifier is the output terminal of the first replication bias circuit. The first terminal of the ninth transistor is the first terminal of the first replication bias circuit; The second terminal of the ninth transistor is connected to the first terminal of the tenth transistor and the first terminal of the eleventh transistor, respectively. The second terminal of the tenth transistor is connected to the second terminal of the eleventh transistor and the output terminal of the first operational amplifier, respectively, and together they form the second terminal of the first replication bias circuit.
5. The serial interface circuit as described in claim 4, characterized in that, The ninth transistor and the first transistor are both PMOS transistors with the same width-to-length ratio; the tenth transistor, the third transistor, and the fourth transistor are all PMOS transistors with the same width-to-length ratio; the eleventh transistor, the seventh transistor, and the eighth transistor are all NMOS transistors with the same width-to-length ratio.
6. The serial interface circuit as described in claim 3, characterized in that, The second replication bias circuit includes: a second operational amplifier, a twelfth transistor, and a thirteenth transistor; Wherein, the inverting input terminal of the second operational amplifier is the input terminal of the second copy bias circuit; The output terminal of the second operational amplifier is connected to the control terminal of the twelfth transistor, and the output terminal of the second operational amplifier is the output terminal of the second replication bias circuit; The first terminal of the twelfth transistor is connected to the second terminal of the thirteenth transistor; The second terminal of the twelfth transistor is the second terminal of the second replication bias circuit; The first terminal of the thirteenth transistor is connected to the non-inverting input terminal of the second operational amplifier, together forming the first terminal of the second replication bias circuit.
7. The serial interface circuit as described in claim 6, characterized in that, The twelfth transistor and the second transistor are both NMOS transistors with the same width-to-length ratio, and the thirteenth transistor, the fifth transistor, and the sixth transistor are all NMOS transistors with the same width-to-length ratio.
8. The serial interface circuit as described in claim 3, characterized in that, Also includes: First transmission line, second transmission line, and terminating differential resistor; The first output terminal of the IO interface driver circuit is connected to the first end of the first transmission line. The second end of the first transmission line is connected to the first end of the terminating differential resistor; The second output terminal of the IO interface driver circuit is connected to the second terminal of the second transmission line; The second end of the second transmission line is connected to the second end of the terminating differential resistor.
9. The serial interface circuit as described in claim 8, characterized in that, The terminal differential resistor has the same resistance value as the first resistor.