Chip verification method, system, real-time microprocessor, medium and program product

Abstract

The application relates to a chip verification method, system, real-time microprocessor, storage medium and program product. The method comprises the following steps: reading output interface signals of each sub-module of a design under test through a script; generating output interfaces of a reference model according to the output interface signals of each sub-module of the design under test through the script, wherein the output interfaces of the reference model correspond to the output interfaces of the design under test one by one; comparing the output interface signals of each sub-module of the design under test and signals output by the output interfaces of the reference model in a score board through the script to obtain a verification result. According to the method, transplantation and reuse can be completed through a script in different projects, and a verification system does not need to be completely rearranged, so that the verification efficiency is greatly improved.

Description

Technical Field

[0001] This application relates to the field of chip verification technology, and in particular to a chip verification method, system, real-time microprocessor, medium, and program product. Background Technology

[0002] In recent years, with the continuous increase in chip integration, the functional complexity of chips has also increased significantly, making the chip design process more prone to errors and verification work more challenging. In integrated circuit design, verification accounts for more than half of the entire design cycle. As chip integration continues to increase, a large number of chip sub-modules may be integrated within the chip (design under test). For modules with high timing requirements, verification necessitates checking the correctness of the output of each module in the design under test every clock cycle.

[0003] In traditional technologies, verifying the design under test (DUT) requires building a verification platform. A traditional verification platform typically includes the following basic elements: stimuli (generated by an agent), a reference model, and a scoreboard. The stimuli generate all possible test scenarios, the DUT implements the relevant functionalities using RTL (a hardware representation language), the reference model predicts the design's functionality, and the scoreboard compares the predicted output of the reference model with the output of the DUT. If they match, the function is normal; otherwise, either the reference model or the DUT is faulty, and the source of the problem needs to be identified. Input refers to the stimuli entering the DUT through its ports; output refers to the output from the DUT through its output ports.

[0004] However, traditional verification platforms require rewriting the verification environment for each project, which is extremely inefficient. Summary of the Invention

[0005] Therefore, it is necessary to provide a chip verification method, system, real-time microprocessor, medium, and program product that can improve verification efficiency to address the above-mentioned technical problems.

[0006] In a first aspect, this application provides a chip verification method, the method comprising:

[0007] The script reads the output interface signals of each submodule of the design under test.

[0008] The script generates the output interface of the reference model based on the output interface signals of each sub-module of the design under test. The output interface of the reference model corresponds one-to-one with the output interface of the design under test.

[0009] The script compares the output interface signals of each submodule of the design under test with the output interface signals of the reference model in the scoring board to obtain the verification results.

[0010] In one embodiment, the step of generating a reference model output interface via a script based on the output interface signals of each submodule of the design under test includes:

[0011] The script generates the output interface of the design under test based on the output interface signals of each sub-module of the design under test.

[0012] The script generates a signal declaration for a reference model based on the output interface of the design under test.

[0013] The script generates the output interface of the reference model based on the output interface of the design under test, and assigns the declared signals of the reference model to the output interface of the reference model. The signal assignments of the reference model correspond one-to-one with the output interface of the reference model.

[0014] In one embodiment, the step of comparing the output interface signals of each submodule of the design under test with the output interface signals of the reference model in the scoring board via a script to obtain the verification results includes:

[0015] The script generates a real-time comparison function for the interface in the scoreboard.

[0016] The real-time comparison function of the interface compares the output interface signals of each sub-module of the design under test with the output interface signals of the reference model to obtain the verification results.

[0017] In one embodiment, the step of generating a real-time comparison function for the interface in the scoreboard via script includes:

[0018] The real-time comparison clock is determined in the scoreboard using a script;

[0019] The timing of the comparison is determined from the clock using a script;

[0020] The script generates a real-time comparison function based on the clock, the timing of the comparison, the output interface of the design under test, and the output interface of the reference model.

[0021] In one embodiment, the step of generating a real-time comparison function for the interface in the scoreboard via script includes:

[0022] A real-time comparison function, including an error reporting mechanism, is generated via script;

[0023] The verification results are obtained by comparing the output interface signals of each submodule of the design under test with the output interface signals of the reference model in the scoring board using a script, including:

[0024] The script compares the output interface signals of each sub-module of the design under test with the output interface signals of the reference model in the scoring board.

[0025] When the output interface signals of each sub-module of the design under test are inconsistent with the output interface signals of the reference model, error information is output through the error reporting mechanism of the real-time comparison function.

[0026] In one embodiment, the step of generating a real-time comparison function for the interface in the scoreboard via script includes:

[0027] A real-time comparison function, including an error counting mechanism, is generated using a script;

[0028] The verification results are obtained by comparing the output interface signals of each submodule of the design under test with the output interface signals of the reference model in the scoring board using a script, including:

[0029] The script compares the output interface signals of each sub-module of the design under test with the output interface signals of the reference model in the scoring board.

[0030] When the output interface signals of each sub-module of the design under test are inconsistent with the output interface signals of the reference model, the error counting mechanism of the real-time comparison function is used to count the number of errors.

[0031] When the number of errors counted by the error counting mechanism exceeds the threshold, the verification process stops.

[0032] Secondly, this application also provides a chip verification system, the system comprising:

[0033] The excitation module is used to generate excitation signals for the corresponding test scenarios;

[0034] The design under test has its input terminal connected to the output terminal of the excitation module, and its output terminal connected to the input terminal of the script module.

[0035] The reference model has its input end connected to the output end of the excitation module, and its output end connected to the first input end of the model output interface module.

[0036] The model output interface has a second input terminal connected to the first output terminal of the script module, and an output terminal connected to the first input terminal of the scoreboard.

[0037] The design under test has an output interface, with its input end connected to the second output end of the script module and its output end connected to the second input end of the scoring board.

[0038] The script module has its third output terminal connected to the second input terminal of the scoreboard;

[0039] The scoring board is used to compare the output interface signals of each sub-module of the design under test with the output interface signals of the reference model based on the control of the script module to obtain the verification results.

[0040] The script module is used to implement the chip verification method described above.

[0041] Thirdly, this application also provides a real-time microcontroller, including a memory storing a computer program, wherein the real-time microcontroller executes the computer program to implement the steps of the method in any of the above embodiments.

[0042] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a microcontroller, implements the steps of the methods in any of the above embodiments.

[0043] Fifthly, this application also provides a computer program product, including a computer program that, when executed by a microcontroller, implements the steps of the methods in any of the above embodiments.

[0044] The aforementioned chip verification method, system, real-time microprocessor, medium, and program products read the output interface signals of each sub-module of the design under test (DUT) through a script. Based on these output interface signals, an output interface of a reference model is generated. The script then directly compares the output interface signals of each sub-module of the DUT with the output interface signals of the reference model on the scoring board to obtain the verification results. This method allows for portability and reuse across different projects using only a script, eliminating the need for a complete redeployment of the verification system and significantly improving verification efficiency. Attached Figure Description

[0045] Figure 1 This is a structural diagram of a chip verification system in one embodiment;

[0046] Figure 2 This is a flowchart illustrating a chip verification method in one embodiment;

[0047] Figure 3 A flowchart of the reference model output interface generation steps in one embodiment;

[0048] Figure 4 A flowchart of the signal comparison steps in one embodiment;

[0049] Figure 5 This is an internal structure diagram of a real-time control microcontroller in one embodiment. Detailed Implementation

[0050] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0051] This application provides a chip verification system, which includes an excitation module 100, a design under test 200, a reference model 300, a model output interface 400, a design under test output interface 500, a script module 600, and a scoring board 700.

[0052] The excitation module 100 generates excitation signals for the corresponding test scenario. The input terminal of the design under test (DUT) 200 is connected to the output terminal of the excitation module 100, and the output terminal is connected to the input terminal of the script module 600. The input terminal of the reference model 300 is connected to the output terminal of the excitation module 100, and the output terminal is connected to the first input terminal of the model output interface 400 module. The second input terminal of the model output interface 400 is connected to the first output terminal of the script module 600, and the output terminal is connected to the first input terminal of the scoring board 700. The input terminal of the DUT output interface 500 is connected to the second output terminal of the script module 600, and the output terminal is connected to the second input terminal of the scoring board 700. The third output terminal of the script module 600 is connected to the second input terminal of the scoring board 700. The scoring board 700 is used to compare the output interface signals of the DUT 200 and the output interface signals of the reference model 300 based on the control of the script module 600 to obtain the verification results. The script module 600 is used to read the output interface signals of each sub-module of the design under test (DUT) through a script. Based on these output interface signals, the script generates the output interface of the reference model 300. The output interface of the reference model 300 corresponds one-to-one with the output interface of the DUT. In this way, the script compares the output interface signals of each sub-module of the DUT with the output interface signals of the reference model 300 in the scoring board 700 to obtain the verification results. This allows for portability and reuse in different projects simply by using the script, without the need for a complete redeployment of the verification system, thus significantly improving verification efficiency.

[0053] The design under test 200 can integrate a large number of chip sub-modules, and the correctness of the output of each sub-module of the design under test 200 can be verified in every clock cycle.

[0054] The script module 600 can parse the output signals of each sub-module of the design under test 200, generate the output interface of the design under test 200 based on the output signals of each sub-module, generate the signal declaration of the reference model 300 based on the output structure of the design under test 200, generate the output interface of the reference model 300 according to the output interface of each sub-module of the design under test 200, and establish a one-to-one correspondence between the declared signals of the reference model 300 and the output interface of the reference model 300. Since the reference model 300 belongs to the software category and the design under test 200 belongs to the hardware category, the signal changes seen from the waveform are limited to hardware signals. However, by assigning the output signals of the reference model 300 to the hardware interface, the software signals can be hardwareized, improving the efficiency of environment debugging.

[0055] In one optional embodiment, the output interface signal of the design under test 200 is compared with the output interface signal of the reference model 300 in the scoring board 700, and the verification result is obtained through a script. The script can generate a real-time interface comparison function in the scoring board 700, thus automating the comparison task and significantly improving verification efficiency while shortening the chip development cycle.

[0056] Specifically, the real-time comparison function of this interface can be generated by a script, including generating a real-time comparison clock in the scoring board 700 by a script; determining the timing of the comparison from the clock by a script; and generating a real-time comparison function based on the clock, the timing of the comparison, the output interface of the design under test 200, and the output interface of the reference model 300 by a script.

[0057] In one alternative embodiment, the real-time comparison function of the interface can also implement an error reporting mechanism, for example, by generating a real-time comparison function including an error reporting mechanism via a script.

[0058] In one alternative embodiment, the real-time comparison function of the interface can also implement an error counting mechanism, for example, by generating a real-time comparison function including an error counting mechanism through a script.

[0059] The script in the script module 600 can be burned into the verification system via a terminal, which can be, but is not limited to, various personal computers, laptops, smartphones, tablets, etc.

[0060] In one embodiment, such as Figure 2 As shown, a chip verification method is provided, which is applied to... Figure 1 Taking script module 600 as an example, the explanation includes the following steps:

[0061] S202: Read the output interface signals of each submodule of the design under test through a script.

[0062] Specifically, the Design Under Test (DUT) refers to a chip, which can integrate numerous chip sub-modules. The DUT is implemented in hardware. The DUT's output interface signals are hardware outputs. When the DUT integrates numerous chip sub-modules, the DUT's output interface signals include the output interface signals of those sub-modules. These DUT output interface signals need to be obtained via scripts at different clock cycles.

[0063] S204: The script generates the output interface of the reference model based on the output interface signals of each sub-module of the design under test. The output interface of the reference model corresponds one-to-one with the output interface of the design under test.

[0064] Specifically, the output interface of the reference model is obtained through script assignment. That is, the script declares the output signal of the reference model based on the output interface signal of the design under test, and then assigns the output signal of the reference model to the output interface of the reference model. It should be noted that the output interface of the reference model is also generated by the script based on the output interface of the design under test. In this way, the output interface of the reference model corresponds one-to-one with the output interface of the design under test, and the output interface of the reference model also corresponds one-to-one with the declared output signal of the reference model.

[0065] The reference model belongs to the software category, while the design under test belongs to the hardware category. The signal changes observed in the waveform are limited to hardware signals. In this embodiment, by assigning the output signal of the reference model to the hardware interface, the software signal can be hardwareized, thereby improving the efficiency of environmental debugging.

[0066] S206: The output interface signals of each sub-module of the design under test are compared with the output interface signals of the reference model in the scoring board using a script to obtain the verification results.

[0067] Specifically, after determining the output signal of the reference model's output interface through the script, the output interface signals of each sub-module of the design under test are compared with the output interface signals of the reference model in the scoring board to obtain the verification results. The task of real-time comparison is realized in the scoring board. It can be ported and reused in different projects as long as it is done through the script, which greatly improves the verification efficiency.

[0068] The chip verification method described above reads the output interface signals of each sub-module of the design under test (DUT) through a script. Based on these signals, it generates the output interface of a reference model. The script then directly compares the output interface signals of each sub-module of the DUT with the output interface signals of the reference model on the scoring board to obtain the verification results. This method can be ported and reused in different projects using only a script, without the need to completely redeploy the verification system, thus significantly improving verification efficiency.

[0069] In one embodiment, combined Figure 3 As shown, Figure 3 This is a flowchart of a reference model output interface generation step in one embodiment. In this embodiment, the reference model output interface generation step involves generating a reference model output interface using a script based on the output interface signals of each sub-module of the design under test. The step includes:

[0070] S302: Generate the output interface of the design under test based on the output interface signals of each submodule of the design under test using a script.

[0071] Specifically, in this embodiment, the output interface signals of each sub-module of the design under test are parsed by a script, and the output interface of the design under test is generated by parsing the output interface signals of each sub-module.

[0072] S304: Generates signal declarations for a reference model based on the output interface of the design under test using a script.

[0073] The signal declaration is based on the reference model, which is implemented in software. The output signals of the reference model are declared based on the output interface signals of each submodule, so that the output signals of the reference model correspond to the output signals of the design under test. The output signals of the reference model and the output signals of the design under test are in one-to-one correspondence.

[0074] S306: The script generates the output interface of the reference model based on the output interface of the design under test, and assigns the declared signals of the reference model to the output interface of the reference model. The signal assignments of the reference model correspond one-to-one with the output interface of the reference model.

[0075] In this embodiment, the output interface of the reference model is generated by the script based on the output interface of the design under test. The output interface of the reference model corresponds one-to-one with the output interface of the design under test.

[0076] After determining the output signals and output interfaces of the reference model, a connection is established between the output signals and output interfaces of the reference model. That is, the output signals of the reference model are assigned to the output interfaces of the reference model. The signal assignments declared by the reference model correspond one-to-one with the output interfaces of the reference model. In this way, the signals declared by the reference model also correspond one-to-one with the output signals of the design under test.

[0077] One point to note is that the output interface of the reference model and the output interface of the design under test can have the same name and the same suffix, because they come from different hardware interface layers, the compilation system can distinguish them, and their scopes are different.

[0078] To illustrate how a script can generate the output interface of a reference model based on the output interface of the design under test, an example is given: (The output interface of the design under test is as follows:)

[0079] interface dut_output_if();

[0080] logic dut_out_a;

[0081] logic dut_out_b;

[0082] logic dut_out_c; ......

[0084] endinterface

[0085] Then, based on the output interface of the design under test, the script automatically generates the output interface of the reference model, as follows:

[0086] interface ref_output_if();

[0087] logic ref_out_a;

[0088] logic ref_out_b;

[0089] logic ref_out_c; ......

[0091] endinterface

[0092] In the above embodiments, by assigning the output signal of the reference model to the hardware interface, the software signal can be hardwareized, improving the efficiency of environment debugging; and the output interface of the reference model can be automatically generated by the script, without having to redeploy the verification environment for each project, which improves the reusability of the verification environment and thus improves the verification efficiency.

[0093] In one embodiment, combined Figure 4 As shown, Figure 4 This is a flowchart of a signal comparison step in one embodiment. In this embodiment, the signal comparison step involves comparing the output interface signals of each submodule of the design under test with the output interface signals of the reference model in the scoring board using a script to obtain verification results. The steps include:

[0094] S402: Generates a real-time comparison function for the interface in the scoreboard via a script.

[0095] Specifically, the real-time comparison function is generated in the scoring board. It can be generated based on the output interface of the design under test and the output interface of the reference model, and is used to compare the signals output by the output interface of the design under test with the signals output by the output interface of the reference model.

[0096] S404: Based on the real-time interface comparison function, the output interface signals of each sub-module of the design under test are compared with the output interface signals of the reference model to obtain the verification results.

[0097] Specifically, in this embodiment, the process of comparing the signals output by the output interface of the design under test with the signals output by the output interface of the reference model via script is a parallel comparison, and it is a real-time comparison. For example, it can be implemented using the syntax of dedicated parallel threads in the SystemVerilog language, such as fork...join.

[0098] In the above embodiments, the output interface signals of each sub-module of the design under test are automatically compared with the output interface signals of the reference model through scripts, thereby improving the efficiency of verification.

[0099] In one embodiment, generating a real-time comparison function for the interface in the scoreboard via a script includes: determining the clock for real-time comparison in the scoreboard via a script; determining the timing of the comparison from the clock via a script; and generating a real-time comparison function based on the clock, the timing of the comparison, the output interface of the design under test, and the output interface of the reference model via a script.

[0100] Specifically, the real-time comparison function can generate the clock frequency and clock name for real-time comparison. The timing of the comparison can be selected, such as the rising or falling edge of the clock. Therefore, the script pre-determines the real-time comparison clock in the scoring board; the script determines the comparison timing from the clock. Thus, the script generates the real-time comparison function based on the clock, the comparison timing, the output interface of the design under test (DUT), and the output interface of the reference model. This real-time comparison function enables automatic comparison of the output signals of each submodule of the DUT with the output signals of the reference model, thereby improving verification efficiency.

[0101] In one embodiment, a real-time interface comparison function is generated in the scoring board via a script, including: generating a real-time comparison function with an error reporting mechanism via a script; comparing the output interface signals of each sub-module of the design under test with the output interface signals of the reference model in the scoring board via a script to obtain verification results, including: comparing the output interface signals of each sub-module of the design under test with the output interface signals of the reference model in the scoring board via a script; and outputting error information through the error reporting mechanism of the real-time comparison function when the output interface signals of each sub-module of the design under test and the output interface signals of the reference model are inconsistent.

[0102] Specifically, in this embodiment, the real-time comparison function can also implement a comparison failure error reporting mechanism. When the output interface signals of each sub-module of the design under test are inconsistent with the output interface signals of the reference model, the error information is output through the error reporting mechanism of the real-time comparison function to prompt the user, so that the user can check the design under test and the reference model to determine the source of the error.

[0103] In the above embodiments, if a signal comparison fails, the verification environment will report an error. You can choose to terminate the comparison, check for problems in the environment or design, and continue the simulation comparison after the problem is resolved.

[0104] In one embodiment, a real-time interface comparison function is generated in the scoring board via a script, including: generating a real-time comparison function including an error counting mechanism via a script; comparing the output interface signals of each sub-module of the design under test with the output interface signals of the reference model in the scoring board via a script to obtain verification results, including: comparing the output interface signals of each sub-module of the design under test with the output interface signals of the reference model via a script in the scoring board; when the output interface signals of each sub-module of the design under test and the output interface signals of the reference model are inconsistent, counting the number of errors through the error counting mechanism of the real-time comparison function; when the number of errors counted by the error counting mechanism is greater than a threshold, controlling the verification to stop.

[0105] In this embodiment, error messages can also be counted, so that when the number of errors exceeds a threshold, the verification is stopped.

[0106] In the above embodiments, if a signal comparison fails, the verification environment will report an error. You can choose to terminate the comparison, check for problems in the environment or design, and continue the simulation comparison after the problem is resolved.

[0107] For ease of understanding, a complete embodiment is provided for illustration:

[0108] Step 1: Analyze the output interface signals of each submodule of the design under test using a script.

[0109] Step 2: Generate the output interface of the design under test by analyzing the output interface signals of each sub-module obtained in Step 1.

[0110] Step 3: Generate the signal declaration of the reference model using the output interface signals of each submodule obtained from Step 1.

[0111] Step 4: Generate the output interface of the reference model based on the output interface of the sub-module under test.

[0112] Step 5: Assign the reference model signals declared via script to the reference model output interface, establishing a one-to-one mapping relationship. This approach has a significant advantage: it facilitates environment debugging via waveforms. The reference model belongs to the software domain, while the design under test (DUT) belongs to the hardware domain. Signal changes observed in waveforms are limited to hardware signals. However, by assigning the reference model's output signals to the hardware interface, software signals can be hardwareized, improving environment debugging efficiency.

[0113] Step Six: Utilize a script to implement a real-time comparison function in the scoring board, combining the output interfaces of each sub-module of the design under test generated in Step Two and the output interface of the reference model generated in Step Four. The specific implementation details of this interface function include:

[0114] 1. The clock frequency and clock name used for real-time comparison.

[0115] 2. Choose the timing for comparison, such as the rising edge or falling edge of the clock.

[0116] 3. Implement a mechanism to report errors when comparison fails.

[0117] 4. An optional upper limit for the error count can trigger a simulation stop.

[0118] In the above embodiments, a reference model interface is automatically generated via script, enabling real-time comparison in the scoring board. This interface can be ported and reused across different projects using scripts, significantly improving verification efficiency. By organizing a large number of signals requiring comparison into two interfaces and automating the comparison task via scripts, verification efficiency is greatly improved, and the chip development cycle is shortened.

[0119] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0120] In one embodiment, a real-time microcontroller is provided, the internal structure of which can be as follows: Figure 5 As shown, the real-time microcontroller includes a processor, memory, and input / output interfaces. The processor, memory, and input / output interfaces are connected via a system bus. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The input / output interfaces of the real-time microcontroller are used for exchanging information between the processor and external devices. The communication interface of the computer device is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, NFC (Near Field Communication), or other technologies. When the computer program is executed by the real-time microcontroller, it implements a chip verification method.

[0121] Those skilled in the art will understand that Figure 5 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. A specific real-time microcontroller may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0122] In one embodiment, a real-time microcontroller is provided, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to perform the following steps: reading the output interface signals of each sub-module of the design under test (DUT) via a script; generating the output interface of a reference model based on the output interface signals of each sub-module of the DUT via the script, wherein the output interface of the reference model corresponds one-to-one with the output interface of the DUT; and comparing the output interface signals of each sub-module of the DUT with the output signals of the reference model in a scoring board via a script to obtain a verification result.

[0123] In one embodiment, the process of generating a reference model output interface based on the output interface signals of each sub-module of the design under test (DUT) when the processor executes a computer program includes: generating the DUT output interface based on the output interface signals of each sub-module of the DUT; generating a signal declaration of the reference model based on the DUT output interface; generating the reference model output interface based on the DUT output interface, and assigning the declared signals of the reference model to the reference model output interface, wherein the signal assignments of the declared signals of the reference model correspond one-to-one with the output interface of the reference model.

[0124] In one embodiment, when the processor executes a computer program, it compares the output interface signals of each submodule of the design under test with the output interface signals of the reference model in the scoring board using a script to obtain verification results. This includes: generating a real-time interface comparison function in the scoring board using a script; and comparing the output interface signals of each submodule of the design under test with the output interface signals of the reference model based on the real-time interface comparison function to obtain verification results.

[0125] In one embodiment, the real-time comparison function for generating interfaces in the scoreboard via a script, implemented by the processor executing a computer program, includes: determining the clock for real-time comparison in the scoreboard via a script; determining the timing of comparison from the clock via a script; and generating the real-time comparison function based on the clock, the timing of comparison, the output interface of the design under test, and the output interface of the reference model via a script.

[0126] In one embodiment, the real-time interface comparison function implemented by the processor when executing the computer program, which generates the interface in the scoring board via a script, includes: generating a real-time comparison function including an error reporting mechanism via a script; the comparison of the output interface signals of each sub-module of the design under test and the output interface signals of the reference model in the scoring board via a script, which is implemented by the processor when executing the computer program, to obtain verification results, includes: comparing the output interface signals of each sub-module of the design under test and the output interface signals of the reference model via a script in the scoring board; and outputting error information through the error reporting mechanism of the real-time comparison function when the output interface signals of each sub-module of the design under test and the output interface signals of the reference model are inconsistent.

[0127] In one embodiment, the real-time interface comparison function implemented by the processor when executing the computer program, which generates the interface in the scoring board via a script, includes: generating a real-time comparison function including an error counting mechanism via a script; and comparing the output interface signals of each sub-module of the design under test with the output interface signals of the reference model in the scoring board via a script, to obtain verification results, which includes: comparing the output interface signals of each sub-module of the design under test with the output interface signals of the reference model via a script in the scoring board; when the output interface signals of each sub-module of the design under test and the output interface signals of the reference model are inconsistent, counting the number of errors through the error counting mechanism of the real-time comparison function; and stopping the verification when the number of errors counted by the error counting mechanism exceeds a threshold.

[0128] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a real-time microcontroller, it performs the following steps: reading the output interface signals of each sub-module of the design under test (DUT) through a script; generating the output interface of a reference model based on the output interface signals of each sub-module of the DUT through the script, wherein the output interface of the reference model corresponds one-to-one with the output interface of the DUT; and comparing the output interface signals of each sub-module of the DUT with the output signals of the reference model in a scoring board through the script to obtain the verification result.

[0129] In one embodiment, when the computer program is executed by the real-time microcontroller, the process of generating a reference model output interface based on the output interface signals of each sub-module of the design under test (DUT) via a script includes: generating the DUT output interface via a script based on the output interface signals of each sub-module of the DUT; generating a signal declaration of the reference model based on the DUT output interface via a script; generating the reference model output interface via a script based on the DUT output interface, and assigning the declared signals of the reference model to the reference model output interface, wherein the signal assignments of the declared signals of the reference model correspond one-to-one with the output interface of the reference model.

[0130] In one embodiment, when the computer program is executed by the real-time microcontroller, it compares the output interface signals of each submodule of the design under test with the output interface signals of the reference model in the scoring board through a script to obtain verification results. This includes: generating a real-time interface comparison function in the scoring board through a script; and comparing the output interface signals of each submodule of the design under test with the output interface signals of the reference model based on the real-time interface comparison function to obtain verification results.

[0131] In one embodiment, the real-time comparison function for generating interfaces in the scoreboard via a script, implemented by the computer program executed by the real-time microcontroller, includes: determining the clock for real-time comparison in the scoreboard via a script; determining the timing of comparison from the clock via a script; and generating the real-time comparison function based on the clock, the timing of comparison, the output interface of the design under test, and the output interface of the reference model via a script.

[0132] In one embodiment, the real-time interface comparison function generated by the computer program in the scoring board via script, implemented when the computer program is executed by the real-time microcontroller, includes: generating a real-time comparison function including an error reporting mechanism via script; comparing the output interface signals of each sub-module of the design under test with the output interface signals of the reference model in the scoring board via script, and obtaining verification results, including: comparing the output interface signals of each sub-module of the design under test with the output interface signals of the reference model in the scoring board via script; and outputting error information through the error reporting mechanism of the real-time comparison function when the output interface signals of each sub-module of the design under test and the output interface signals of the reference model are inconsistent.

[0133] In one embodiment, the real-time interface comparison function generated in the scoring board via script, implemented by the computer program executed by the real-time microcontroller, includes: generating a real-time comparison function including an error counting mechanism via script; comparing the output interface signals of each sub-module of the design under test with the output interface signals of the reference model in the scoring board via script, and obtaining verification results, including: comparing the output interface signals of each sub-module of the design under test with the output interface signals of the reference model via script in the scoring board; when the output interface signals of each sub-module of the design under test and the output interface signals of the reference model are inconsistent, counting the number of errors through the error counting mechanism of the real-time comparison function; when the number of errors counted by the error counting mechanism is greater than a threshold, controlling the verification to stop.

[0134] In one embodiment, a computer program product is provided, including a computer program that, when executed by a real-time microcontroller, performs the following steps: reading the output interface signals of each submodule of the design under test (DUT) via a script; generating the output interface of a reference model based on the output interface signals of each submodule of the DUT via the script, wherein the output interface of the reference model corresponds one-to-one with the output interface of the DUT; and comparing the output interface signals of each submodule of the DUT with the output signals of the reference model in a scoring board via the script to obtain a verification result.

[0135] In one embodiment, when the computer program is executed by the real-time microcontroller, the process of generating a reference model output interface based on the output interface signals of each sub-module of the design under test (DUT) via a script includes: generating the DUT output interface via a script based on the output interface signals of each sub-module of the DUT; generating a signal declaration of the reference model based on the DUT output interface via a script; generating the reference model output interface via a script based on the DUT output interface, and assigning the declared signals of the reference model to the reference model output interface, wherein the signal assignments of the declared signals of the reference model correspond one-to-one with the output interface of the reference model.

[0136] In one embodiment, when the computer program is executed by the real-time microcontroller, it compares the output interface signals of each submodule of the design under test with the output interface signals of the reference model in the scoring board through a script to obtain verification results. This includes: generating a real-time interface comparison function in the scoring board through a script; and comparing the output interface signals of each submodule of the design under test with the output interface signals of the reference model based on the real-time interface comparison function to obtain verification results.

[0137] In one embodiment, the real-time comparison function for generating interfaces in the scoreboard via a script, implemented by the computer program executed by the real-time microcontroller, includes: determining the clock for real-time comparison in the scoreboard via a script; determining the timing of comparison from the clock via a script; and generating the real-time comparison function based on the clock, the timing of comparison, the output interface of the design under test, and the output interface of the reference model via a script.

[0138] In one embodiment, the real-time interface comparison function generated by the computer program in the scoring board via script, implemented when the computer program is executed by the real-time microcontroller, includes: generating a real-time comparison function including an error reporting mechanism via script; comparing the output interface signals of each sub-module of the design under test with the output interface signals of the reference model in the scoring board via script, and obtaining verification results, including: comparing the output interface signals of each sub-module of the design under test with the output interface signals of the reference model in the scoring board via script; and outputting error information through the error reporting mechanism of the real-time comparison function when the output interface signals of each sub-module of the design under test and the output interface signals of the reference model are inconsistent.

[0139] In one embodiment, the real-time interface comparison function generated in the scoring board via script, implemented by the computer program executed by the real-time microcontroller, includes: generating a real-time comparison function including an error counting mechanism via script; comparing the output interface signals of each sub-module of the design under test with the output interface signals of the reference model in the scoring board via script, and obtaining verification results, including: comparing the output interface signals of each sub-module of the design under test with the output interface signals of the reference model via script in the scoring board; when the output interface signals of each sub-module of the design under test and the output interface signals of the reference model are inconsistent, counting the number of errors through the error counting mechanism of the real-time comparison function; when the number of errors counted by the error counting mechanism is greater than a threshold, controlling the verification to stop.

[0140] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0141] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0142] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A chip verification method, characterized in that, The method includes: The script reads the output interface signals of each submodule of the design under test. The script generates the output interface of the reference model based on the output interface signals of each sub-module of the design under test. The output interface of the reference model corresponds one-to-one with the output interface of the design under test. The script compares the output interface signals of each sub-module of the design under test with the output interface signals of the reference model in the scoring board to obtain the verification results. The step of generating a reference model output interface via script based on the output interface signals of each sub-module of the design under test includes: The script generates the output interface of the design under test based on the output interface signals of each sub-module of the design under test. The script generates a signal declaration for a reference model based on the output interface of the design under test. The script generates the output interface of the reference model based on the output interface of the design under test, and assigns the declared signals of the reference model to the output interface of the reference model. The declared signals of the reference model correspond one-to-one with the output interface of the reference model. The verification results are obtained by comparing the output interface signals of each submodule of the design under test with the output interface signals of the reference model in the scoring board using a script, including: The script generates a real-time comparison function for the interface in the scoreboard. The real-time comparison function of the interface compares the output interface signals of each sub-module of the design under test with the output interface signals of the reference model to obtain the verification results.

2. The method according to claim 1, characterized in that, The method of generating a real-time comparison function in the scoreboard via script includes: The real-time comparison clock is determined in the scoreboard using a script; The timing of the comparison is determined from the clock using a script; The script generates a real-time comparison function based on the clock, the timing of the comparison, the output interface of the design under test, and the output interface of the reference model.

3. The method according to claim 1, characterized in that, The method of generating a real-time comparison function in the scoreboard via script includes: A real-time comparison function, including an error reporting mechanism, is generated via script; The verification results are obtained by comparing the output interface signals of each submodule of the design under test with the output interface signals of the reference model in the scoring board using a script, including: The script compares the output interface signals of each sub-module of the design under test with the output interface signals of the reference model in the scoring board. When the output interface signals of each sub-module of the design under test are inconsistent with the output interface signals of the reference model, error information is output through the error reporting mechanism of the real-time comparison function.

4. The method according to claim 1, characterized in that, The method of generating a real-time comparison function in the scoreboard via script includes: A real-time comparison function, including an error counting mechanism, is generated using a script; The verification results are obtained by comparing the output interface signals of each submodule of the design under test with the output interface signals of the reference model in the scoring board using a script, including: The script compares the output interface signals of each sub-module of the design under test with the output interface signals of the reference model in the scoring board. When the output interface signals of each sub-module of the design under test are inconsistent with the output interface signals of the reference model, the error counting mechanism of the real-time comparison function is used to count the number of errors. When the number of errors counted by the error counting mechanism exceeds the threshold, the verification process stops.

5. A chip verification system, characterized in that, The system includes: The excitation module is used to generate excitation signals for the corresponding test scenarios; The design under test has its input terminal connected to the output terminal of the excitation module, and its output terminal connected to the input terminal of the script module. The reference model has its input end connected to the output end of the excitation module, and its output end connected to the first input end of the model output interface module. The model output interface has a second input terminal connected to the first output terminal of the script module, and an output terminal connected to the first input terminal of the scoreboard. The design under test has an output interface, with its input end connected to the second output end of the script module and its output end connected to the second input end of the scoring board. The script module has its third output terminal connected to the third input terminal of the scoring board; The scoring board is used to compare the output interface signals of each sub-module of the design under test with the output interface signals of the reference model based on the control of the script module to obtain the verification results. The script module is used to implement the chip verification method according to any one of claims 1 to 4.

6. A real-time microcontroller, comprising a memory storing a computer program, characterized in that, When the real-time microcontroller executes the computer program, it implements the steps of the method according to any one of claims 1 to 4.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the microcontroller, it implements the steps of the method according to any one of claims 1 to 4.

8. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the microcontroller, it implements the steps of the method according to any one of claims 1 to 4.

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