A timing-driven force-directed layout method

Abstract

The application discloses a timing-driven force-directed layout method, which comprises the following steps: firstly, generating a circuit netlist by processing a to-be-processed circuit; secondly, randomly laying out logic units in the circuit netlist to obtain a to-be-optimized layout result; thirdly, calculating the resultant force borne by each logic unit in the to-be-optimized layout result, and calculating a new layout position of the logic unit in the to-be-optimized layout result based on the resultant force to obtain another to-be-optimized layout result; fourthly, performing legalization processing on the another to-be-optimized layout result to obtain a legalization result, which is taken as a new to-be-optimized layout result; and finally, obtaining a target layout result when the total bus length of the circuit in the another to-be-optimized layout result and the total bus length of the circuit in the legalization result converge to a specific standard. The force guide part introduced in the application can make the logic unit move in the direction of optimizing the line length and the time delay cost, effectively shorten the layout time, and obtain a higher-quality layout result.

Description

Technical Field

[0001] This invention belongs to the field of computer-aided design technology, specifically relating to a time-driven force-oriented layout method. Background Technology

[0002] Typically, implementing circuit design on an FPGA (Field Programmable Gate Array) chip involves a series of compilation processes, including behavioral synthesis, process mapping, packaging, placement, and routing. Among these, the "placement" stage is one of the most critical and time-consuming stages. During placement, optimizations can be made to target parameters such as trace length, timing, area, or power consumption based on actual needs.

[0003] Currently, analytical placement algorithms are a common type of FPGA placement method. Each iteration includes a placement optimization phase and a validation phase. In the placement optimization phase, a suitable cost function is defined for the placement problem, and the cost function is minimized through numerical optimization methods to obtain the optimal placement solution. In the validation phase, cell overlap is eliminated to obtain a valid version of the optimal placement. However, general analytical placement algorithms are only suitable for optimizing placement problems with a single objective. When facing multiple optimization objectives, the cost function becomes complex, requiring mathematical methods to transform it into an easier-to-solve form. This process is obscure, complex, and time-consuming. Therefore, a pressing issue is how to achieve a high-quality placement solution while reducing placement time when facing multiple optimization objectives. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a time-driven force-oriented layout method. The technical problem to be solved by this invention is achieved through the following technical solution:

[0005] This invention provides a time-driven force-oriented layout method, the method comprising:

[0006] After performing behavioral synthesis, process mapping, and packaging on the circuit to be processed, a circuit netlist is generated, which includes a set of logic cells and a set of nets.

[0007] Randomly arrange the logical units in the set of logical units to obtain the layout result to be optimized;

[0008] Calculate the net force, critical connection force, and pseudo connection force on each logic unit in the layout result to be optimized, and calculate the net force based on this. The net force is used to guide the logic units in the layout result to be optimized to move in the direction of the bus length and timing of the optimized circuit.

[0009] Based on the combined force, the new layout positions of the logic units in the layout result to be optimized are calculated to obtain another layout result to be optimized.

[0010] Another layout result to be optimized is legalized to obtain a legalized result, which is used as a new layout result to be optimized.

[0011] When the bus length of the circuit in another layout result to be optimized and the bus length of the circuit in the legalized result converge to a specific standard, the target layout result is obtained.

[0012] In one embodiment of the present invention, when calculating the net force along the x-direction, the calculation of the net force on each logic unit in the layout result to be optimized includes:

[0013] Using formula Calculate the net force on each logical unit in the layout to be optimized;

[0014] Where nets represents the set of nets connected to the current logical unit. The network force exerted on the current logic unit by the net n (n≥1) is calculated using the following formula:

[0015] Among them, w n C represents the weight of net n in the net set. max Δx represents the maximum connection length of the circuit in the layout result to be optimized, and Δx represents the length of the bounding box of the net n along the x direction.

[0016] In one embodiment of the present invention, when calculating the critical connection force along the x-direction, the calculation of the critical connection force on each logic unit in the layout result to be optimized includes:

[0017] Using formula Calculate the critical connection forces on each logical unit in the layout result to be optimized;

[0018] Where Δx′ represents the distance between the source logic unit and the target logic unit along the x-direction, C max w represents the maximum connection length of the circuit in the layout result to be optimized. c The connection weights are represented by the following formula:

[0019]

[0020] Here, Criticality(i,j) represents the criticality of the connection from logic unit i to j, θ represents the criticality threshold, and μ is a tradeoff factor that represents the importance of timing optimization relative to line length optimization.

[0021] In one embodiment of the present invention, when calculating the pseudo-connection force along the x-direction, the calculation of the pseudo-connection force on each logic unit in the layout result to be optimized includes...

[0022] Using formula Calculate the pseudo-connection force on each logical unit in the layout result to be optimized;

[0023] Among them, w ρ Let x represent the pseudo-connection weight, and let x represent the current position of the logical unit. legal This indicates the legal position of the logical unit.

[0024] In one embodiment of the present invention, when calculating the resultant force along the x-direction, the calculation of the network resultant force, critical connection force, and pseudo-connection force on each logic unit in the layout result to be optimized, and the calculation of the resultant force based on this, includes:

[0025] Using formula Calculate the resultant force;

[0026] Among them, w p Indicates the weight of pseudo-connections. The network resultant force along the x-direction of the logical units described in the layout to be optimized is... The critical connection force along the x-direction experienced by the logic unit. The pseudo-connection force along the x-direction experienced by the logic unit.

[0027] In one embodiment of the present invention, the step of calculating the new layout positions of the logic units in the layout result to be optimized based on the resultant force, to obtain another layout result to be optimized, includes:

[0028] Calculate the estimated value of the first-order moment and the estimated value of the second-order original moment of the resultant force;

[0029] Based on the estimated values ​​of the first-order moments and the second-order primitive moments, the new layout positions of the logic units in the layout result to be optimized are calculated, resulting in another layout result to be optimized.

[0030] In one embodiment of the present invention, calculating the estimated value of the first-order moment and the estimated value of the second-order primitive moment of the resultant force includes:

[0031] Through formula m l =β1·m l-1 +(1-β1)·g l Calculate the estimated value of the first moment;

[0032] Through formula Calculate the estimated value of the second-order primitive moments;

[0033] Among them, g l The resultant force F represents x合 m0 = 0, v0 = 0; parameters β1, β2 ∈ [0, 1), respectively represent m l and v l The exponential decay rate, where l represents the number of cycles.

[0034] In one embodiment of the present invention, calculating the new layout positions of the logic cells in the layout result to be optimized based on the estimated values ​​of the first-order moments and the second-order primitive moments includes:

[0035] Using formula Calculate the new layout position of the logic unit in the layout result to be optimized; where λ represents the step size, ε is a specified value, and l represents the number of iterations.

[0036] In one embodiment of the present invention, the specific standard includes:

[0037] The ratio of the bus length of the circuit in the layout optimization result to the bus length of the circuit in the legalization result is within a preset value range.

[0038] Alternatively, the bus length of the circuit may not be optimized in the validation results of consecutive iterations within a preset number of iterations.

[0039] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0040] This invention provides a timing-driven force-oriented layout method. First, after behavioral synthesis, process mapping, and packaging of the circuit to be processed, a circuit netlist is generated, which includes a set of logic cells and a set of nets. Next, the logic cells in the set of logic cells are randomly placed to obtain a layout result to be optimized. Then, the netlist calculates the netlist force, critical connection force, and pseudo-connection force on each logic cell in the layout result to be optimized, and calculates the netlist force based on this. This netlist force can guide the logic cells in the layout result to move in the direction of the optimized circuit's bus length and timing. Based on the netlist force, the new layout position of the logic cells in the layout result to be optimized is calculated, resulting in another layout result to be optimized. Then, the other layout result to be optimized can be legalized to obtain a legalized result, which serves as a new layout result to be optimized. When the bus length of the circuit in the other layout result to be optimized converges to a specific criterion with the bus length of the circuit in the legalized result, the target layout result is obtained. Because this invention introduces a force-guided module (network resultant force, critical connection force, and pseudo-connection force), the logic units can be moved in the direction of optimizing line length and latency costs to obtain the layout solution with optimal cost. This replaces the process of constructing and minimizing the cost function in traditional analytical layout algorithms, eliminating the need to solve a nonlinear cost function. Therefore, it can effectively shorten the layout time and obtain higher-quality layout results when dealing with dual-objective optimization of line length and timing.

[0041] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0042] Figure 1 This is a flowchart illustrating a timing-driven force-guided layout method provided in an embodiment of the present invention.

[0043] Figure 2 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0044] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0045] Figure 1 This is a schematic flowchart of a time-driven force-guided layout method provided in an embodiment of the present invention.

[0046] like Figure 1 As shown, an embodiment of the present invention provides a time-driven force-guided layout method including:

[0047] S100: After performing behavioral synthesis, process mapping and packaging on the circuit to be processed, a circuit netlist is generated. The circuit netlist includes a set of logic cells and a set of nets.

[0048] S102. Randomly arrange the logic units in the above logic unit set to obtain the layout result to be optimized.

[0049] In this embodiment, the set of logic units C and the set of nets N form a circuit netlist for any net n∈N.

[0050] S104. Calculate the net force, critical connection force and pseudo connection force on each logic unit in the layout result to be optimized, and calculate the net force based on this. The net force is used to guide the logic unit in the layout result to be optimized to move in the direction of the bus length and timing of the optimized circuit.

[0051] In this embodiment, the smallest rectangular frame containing all the logic units connected to any net n is called the bounding box of the net. To reduce line length costs, the net exerts a pulling force perpendicular to the boundary inward on the logic units on its bounding box, called the network force. It should be noted that each logic unit may have multiple nets connected to it, so it is necessary to calculate the net resultant force on the logic unit. To optimize circuit timing, i.e., reduce critical path delay, all critical connections exert a force on the source logic unit and the target logic unit, called the critical connection force. To ensure that the layout result to be optimized obtained in step S106 and the legalization result obtained in step S108 gradually converge, a pseudo-connection is added between the logic unit and its legal position. The force exerted by this pseudo-connection on the logic unit is called the pseudo-connection force, which is used to prevent the logic unit from deviating too far from its legal position.

[0052] Specifically, if calculating the net force along the x-direction, the net force on each logic unit in the layout to be optimized can be calculated using the following formula:

[0053]

[0054] Where nets represents the set of nets connected to the current logical unit. The network force exerted on the current logic unit by the net n (n≥1) is calculated using the following formula:

[0055] Among them, w n C represents the weight of net n in the net set. max Δx represents the maximum connection length of the circuit in the layout result to be optimized, and Δx represents the length of the bounding box of net n along the x-direction.

[0056] If we calculate the critical connection force along the x-direction, then when calculating the critical connection force on each logic unit in the layout to be optimized, we can use the formula... Calculate the critical connection forces on each logical unit in the layout to be optimized.

[0057] Where Δx′ represents the distance between the source logic unit and the target logic unit along the x-direction, C max w represents the maximum connection length of the circuit in the layout result to be optimized. c The connection weights are represented by the following formula:

[0058]

[0059] Here, Criticality(i,j) represents the criticality of the connection from logic unit i to j, θ represents the criticality threshold, and μ is a tradeoff factor that represents the importance of timing optimization relative to line length optimization.

[0060] If we calculate the pseudo-connection force along the x-direction, then when calculating the pseudo-connection force on each logic unit in the layout to be optimized, we can use the formula... Calculate the pseudo-connection force on each logical unit in the layout to be optimized.

[0061] Among them, w ρ Let x represent the pseudo-connection weight, and let x represent the current position of the logical unit. legal Indicates the legal location of a logic unit.

[0062] The net force along the x-direction is obtained. Key Connectivity and pseudo-connectivity Then, the resultant force F of the logic unit along the x-direction can be calculated. x合 F x合 It can be used to calculate the new x-coordinate of this logic unit.

[0063] Specifically, formulas can be used Calculate the resultant force along the x-direction; where w p Indicates the weight of pseudo-connections. The net force along the x-direction of the logical units in the layout to be optimized is the net force of the network. The critical connection force along the x-direction experienced by the logic unit. The pseudo-connection force along the x-direction experienced by the logic unit.

[0064] Similarly, the net force, critical connection force, and pseudo connection force acting on the logic unit along the y-direction can be calculated, and thus F can be obtained. y合 F y合 It can be used to calculate the new y-coordinate of this logic unit.

[0065] S106. Based on the above combined forces, calculate the new layout position of each logical unit in the layout result to be optimized, and obtain another layout result to be optimized.

[0066] In this embodiment, the new position of the logic unit can be calculated based on the resultant force of the logic unit along the x-direction and the resultant force along the y-direction obtained above, that is, the new x-coordinate and y-coordinate of the logic unit can be calculated.

[0067] Specifically, we can first calculate the estimated value of the first moment and the estimated value of the second original moment of the above resultant force, and then, based on the estimated value of the first moment and the estimated value of the second original moment, calculate the new layout position of the logic unit in the layout result to be optimized, and obtain another layout result to be optimized.

[0068] Furthermore, the estimation of the first moment and the second primitive moment of the resultant force can be performed in the following manner:

[0069] Through formula m l =β1·m l-1 +(1-β1)·g l Calculate the estimated value of the first moment using the formula. Calculate the estimated values ​​of the second-order primitive moments.

[0070] In this embodiment, the resultant force F x合 Consider it as an approximate first-order gradient g l That is, g l The resultant force F can be represented as x合 m0 = 0, v0 = 0; parameters β1, β2 ∈ [0, 1), for example β1 can be 0.9, β2 can be 0.999, representing m l and v l The exponential decay rate, where l represents the number of cycles.

[0071] Furthermore, based on the estimated value of the first moment m calculated above... l And the estimated value of the second-order primitive moments v l Calculate the new layout positions of the logical units in the layout result to be optimized:

[0072] Using formula Calculate the new layout position of the logic unit in the layout result to be optimized; where λ represents the step size, which can be set to 1 for example, ε is a specified value that can be set according to experimental results or experience, and is generally a very small number, and l represents the number of iterations.

[0073] Clearly, guiding the movement of logic units through the resultant force is a process of optimizing layout. However, under normal circumstances, a single movement of a logic unit along the direction of the resultant force cannot achieve optimal line length and latency costs. Therefore, a preset loop value L can be used. inner , l≤L inner L innerThe initial value can be set according to experience or needs, and this embodiment does not impose any restrictions.

[0074] For example, in this embodiment, when L inner If the initial value is set to 200, it means that x needs to be calculated 200 times in the first loop. l That is, the logic unit moves 200 times along the direction of the resultant force to obtain a better line length and latency cost, resulting in another layout result to be optimized.

[0075] S108. Legalize another layout result to be optimized to obtain a legalized result, which is then used as a new layout result to be optimized.

[0076] In this embodiment, if there is logical unit overlap in another layout result to be optimized obtained in step S106, the layout is said to be invalid. That is, the legalization process is responsible for eliminating all logical unit overlaps in another layout result to be optimized.

[0077] As described above, after 200 position shifts, the line length and timing cost in the next layout result to be optimized obtained in step S106 are basically at an optimal level. However, in the process of legalizing and eliminating the overlap of logic units in the next "layout result to be optimized", the results of the previous layout optimization may be destroyed. Therefore, after obtaining the legalized result, the legalized result is used as the new layout result to be optimized, and the process is repeated in step S104 to recalculate the resultant force on the logic unit.

[0078] S110. When the bus length of the circuit in another layout result to be optimized converges to a specific standard with the bus length of the circuit in the legalized result, the target layout result is obtained; otherwise, proceed to step S104 to continue execution.

[0079] In this embodiment, specific criteria can be set according to actual needs or experience. For example, it can be that the ratio of the bus length of the circuit in the layout optimization result to the bus length of the circuit in the legalization result is within a preset value range, or it can be that the bus length of the circuit in the legalization result has not been optimized in a preset number of iterations.

[0080] Here is a complete example:

[0081] If L innerThe initial value is 200. After executing step S102, the first loop is performed, that is, steps S104 to S106 are executed 200 times. In other words, the logic unit is moved 200 times along the direction of the resultant force, resulting in the second layout result to be optimized (corresponding to another "layout result to be optimized" in step S106). Then, the second layout result to be optimized is legalized to obtain the third layout result to be optimized (corresponding to the "legalized result" in step S108). At this point, steps S104 to S108 have been executed once.

[0082] Next, we can determine whether the second and third layout results to be optimized have converged:

[0083] The following two situations can be considered as convergence:

[0084] (1)HPWL opt / HPWL legal ∈(0.8,1],

[0085] (2) HPWL in k consecutive iterations legal None of them were optimized, including HPWL. opt HPWL legal These represent the bus length of the circuit in the layout to be optimized and the bus length of the circuit in the legalized result, respectively. The value of k can be set according to the actual situation or experience. For example, k = 5.

[0086] If convergence is achieved, the target layout result is obtained, and the process ends. If convergence is not achieved, the next iteration of the loop begins.

[0087] It is understandable that after each iteration of steps S104 to S108, L inner The value of L will decrease, which can be expressed by formula L. inner =max(0.8·L) inner Calculate L (100) inner The value of . In other words, as the layout quality improves, the logic units will require fewer moves to achieve optimal performance in the next layout optimization.

[0088] The next cycle will be as follows:

[0089] Steps S104 to S106 are executed repeatedly. inner =max(0.8·L) inner After 100 iterations, another "layout result to be optimized" is obtained in step S106. Then, the layout result to be optimized is legalized to obtain the "legalized result" in step S108, and the current loop ends. Then, it continues to judge whether the result of step S106 and the result of step S108 converge, and so on...

[0090] The timing-driven force-oriented placement method provided by this invention first performs behavioral synthesis, process mapping, and packaging on the circuit to be processed to generate a circuit netlist, which includes a set of logic cells and a set of nets. Next, the logic cells in the set of logic cells are randomly placed to obtain a placement result to be optimized. Then, the netlist calculates the netlist force, critical connection force, and pseudo-connection force on each logic cell in the placement result to be optimized, and calculates the netlist force based on this. This netlist force can guide the logic cells in the placement result to move in the direction of the optimized circuit's bus length and timing. Based on the netlist force, the new placement position of the logic cells in the placement result to be optimized is calculated, resulting in another placement result to be optimized. Then, this new placement result to be optimized is legalized to obtain a legalized result, which serves as a new placement result to be optimized. When the bus length of the circuit in the new placement result to be optimized and the bus length of the circuit in the legalized result converge to a specific criterion, the target placement result is obtained. Because this invention introduces a force-guided module (network resultant force, critical connection force, and pseudo-connection force), the logic units can be moved in the direction of optimizing line length and latency costs to obtain the layout solution that optimizes cost. This replaces the process of constructing and minimizing the cost function in traditional analytical layout algorithms, eliminating the need to solve a nonlinear cost function. Therefore, it can effectively shorten the layout time and obtain higher-quality layout results when dealing with dual-objective optimization of line length and timing.

[0091] Optionally, in this embodiment, after obtaining the target layout result, a low-temperature simulated annealing algorithm can be executed to locally optimize the obtained target layout result.

[0092] Specifically, the initial temperature is set to T0, for example, the value of T0 could be 1×10⁻⁶. -7 In each iteration, for each unit, a matching position is randomly selected within its swap radius to attempt a swap or move. If the layout is optimized, the swap or move is accepted; otherwise, it is considered unlikely to be accepted. After traversing all logical units, a new target layout result is obtained. If the line length and latency cost of the new target layout result are smaller than the original layout, the previous target layout result is updated with the new target layout result, and the next iteration begins; otherwise, the iteration stops, and the algorithm terminates.

[0093] It is easy to understand that when the low-temperature simulated annealing algorithm is executed for the first time, the target layout result obtained in step S110 is locally optimized. In the later iterations, the new target layout result obtained after the previous execution of the low-temperature simulated annealing algorithm is locally optimized.

[0094] The time-driven force-directed placement method proposed in this invention first uses a force-directed algorithm to quickly obtain a high-quality placement solution, and then uses a low-temperature simulated annealing algorithm for local optimization to obtain a higher-quality placement scheme. This invention improves upon traditional analytical placement algorithms and combines the advantages of low-temperature simulated annealing in quickly and effectively optimizing local placements, thereby effectively shortening placement time while ensuring placement quality.

[0095] In addition, during the experiment, we used the Yosys+nextpnr tool as the implementation platform for the algorithm and compared the timing-driven force-directed placement method with the existing placement algorithm HeAP+SA of Yosys+nextpnr to verify the effectiveness of the present invention. The experiment used the Xilinx Artix-7 series FPGA chip xc7a100tcsg324-1, and randomly selected 17 test circuits from ISCAS standard circuits and VPR circuits, as shown in Table 1. Among them, 9 circuits with forms such as s820 and s1423 are ISCAS standard circuits, and the remaining 8 circuits are VPR circuits.

[0096] Table 1. Test circuits used in the experiment.

[0097] Test circuit Number of logic units Number of IOBs s820 163 39 s1423 189 24 s1488 218 29 cordic 419 105 s9234 443 77 s5378 526 86 rs_decoder_1 985 20 LU8PEEng 1070 216 LU64PEEng 1178 216 s13207 1184 216 sha 1292 74 des_area 1303 190 s15850 1390 229 cf_cordic_v_18_18_18 2502 111 s38584 2523 292 s38417 3021 136 des_perf 10335 186

[0098] The comparative experimental results of the timing-driven force-directed placement method (force-directed + SA) and the HeAP + SA algorithm provided in this embodiment of the invention in terms of placement time, critical path delay, and bus length are shown in Tables 2, 3, and 4, respectively. Each experimental data point is the arithmetic mean of ten tests performed on the corresponding circuit. As shown in the tables, compared with the existing placement algorithm HeAP + SA in Yosys + NextPnr, the timing-driven force-directed placement algorithm reduces placement time by 28.88% and critical path delay by 6.53%. The reciprocal of the critical path delay is the circuit's clock frequency, which is an important indicator for evaluating circuit performance. Based on the experimental results, the placement algorithm proposed in this invention can effectively accelerate placement speed and improve circuit performance.

[0099] Table 2 Layout Time

[0100]

[0101] Table 3 Critical Path Delay

[0102]

[0103] Table 4 Bus Length After Wiring

[0104]

[0105] The experimental conclusions are as follows:

[0106] (1) The timing-driven force-oriented placement method proposed in this invention uses a force-oriented algorithm to replace the process of constructing and minimizing the cost function in traditional analytical placement, thus eliminating the need to solve a complex nonlinear cost function. It can not only conveniently handle the dual-objective optimization problem of line length and timing, but also effectively shorten the placement time and reduce the critical path delay of the circuit.

[0107] (2) The introduction of critical connection forces in the timing-driven force-oriented layout method is to optimize the critical path delay of the circuit. Under the action of critical connection forces, the delay of all critical connections in the circuit is shortened, while the delay of some non-critical connections increases without affecting the overall clock cycle of the circuit. The impact of this layout change on the bus length is uncertain, so the bus length of some test circuits in the experimental results is optimized.

[0108] This invention also provides an electronic device, such as... Figure 2 As shown, it includes a processor 201, a communication interface 202, a memory 203, and a communication bus 204, wherein the processor 201, the communication interface 202, and the memory 203 communicate with each other through the communication bus 204.

[0109] Memory 203 is used to store computer programs;

[0110] When processor 201 executes a program stored in memory 203, it performs the following steps:

[0111] After performing behavioral synthesis, process mapping, and packaging on the circuit to be processed, a circuit netlist is generated, which includes a set of logic cells and a set of nets.

[0112] Randomly arrange the logical units in the set of logical units to obtain the layout result to be optimized;

[0113] Calculate the net force, critical connection force, and pseudo connection force on each logic unit in the layout result to be optimized, and calculate the net force based on this. The net force is used to guide the logic units in the layout result to be optimized to move in the direction of the bus length and timing of the optimized circuit.

[0114] Based on the combined force, the new layout positions of the logic units in the layout result to be optimized are calculated to obtain another layout result to be optimized.

[0115] Another layout result to be optimized is legalized to obtain a legalized result, which is used as a new layout result to be optimized.

[0116] When the bus length of the circuit in another layout result to be optimized and the bus length of the circuit in the legalized result converge to a specific standard, the target layout result is obtained.

[0117] The communication bus mentioned in the above electronic devices can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in the diagram, but this does not mean that there is only one bus or one type of bus.

[0118] The communication interface is used for communication between the aforementioned electronic devices and other devices.

[0119] The memory may include random access memory (RAM) or non-volatile memory (NVM), such as at least one disk storage device. Optionally, the memory may also be at least one storage device located remotely from the aforementioned processor.

[0120] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0121] The method provided in this invention can be applied to electronic devices. Specifically, the electronic device can be a desktop computer, a portable computer, a smart mobile terminal, a server, etc. No limitation is made herein; any electronic device that can implement this invention falls within the protection scope of this invention.

[0122] For the embodiments of the device / electronic device / storage medium, since they are basically similar to the method embodiments, the description is relatively simple, and relevant parts can be referred to in the description of the method embodiments.

[0123] It should be noted that the electronic device in the embodiments of the present invention is an electronic device that applies the above-described time-driven force-directed layout method. Therefore, all embodiments of the above-described time-driven force-directed layout method are applicable to the electronic device and can achieve the same or similar beneficial effects.

[0124] The terminal device provided by the embodiments of the present invention can display proper nouns and / or fixed phrases for users to select, thereby reducing user input time and improving user experience.

[0125] This terminal device exists in various forms, including but not limited to:

[0126] (1) Mobile communication devices: These devices are characterized by their mobile communication capabilities and primarily aim to provide voice and data communication. These terminals include: smartphones (e.g., iPhones), multimedia phones, feature phones, and low-end phones, etc.

[0127] (2) Ultra-mobile personal computer devices: These devices fall under the category of personal computers, possessing computing and processing capabilities, and generally also have mobile internet access features. These terminals include PDAs, MIDs, and UMPCs, such as the iPad.

[0128] (3) Portable entertainment devices: These devices can display and play multimedia content. This category includes: audio and video players (such as iPods), handheld game consoles, e-books, as well as smart toys and portable car navigation devices.

[0129] (4) Other electronic devices with data interaction functions.

[0130] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0131] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0132] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0133] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0134] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0135] Although this application has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the accompanying drawings, disclosure, and appended claims, will understand and implement other variations of the disclosed embodiments in carrying out the claimed application. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0136] Those skilled in the art will understand that embodiments of this application can be provided as methods, apparatus (devices), or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects, all of which are collectively referred to herein as "modules" or "systems." Furthermore, this application can take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The computer program may be stored / distributed in a suitable medium, provided with or as part of other hardware, or may take other distribution forms, such as via the Internet or other wired or wireless telecommunications systems.

[0137] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (devices), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0138] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0139] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0140] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A timing-driven force-directed layout method, characterized in that, The time-driven force-oriented layout method includes: After performing behavioral synthesis, process mapping, and packaging on the circuit to be processed, a circuit netlist is generated, which includes a set of logic cells and a set of nets. Randomly arrange the logical units in the set of logical units to obtain the layout result to be optimized; Calculate the net force, critical connection force, and pseudo connection force on each logic unit in the layout result to be optimized, and calculate the net force based on this. The net force is used to guide the logic units in the layout result to be optimized to move in the direction of the bus length and timing of the optimized circuit. Based on the combined force, the new layout positions of the logic units in the layout result to be optimized are calculated to obtain another layout result to be optimized. Another layout result to be optimized is legalized to obtain a legalized result, which is used as a new layout result to be optimized. When the bus length of the circuit in another layout result to be optimized and the bus length of the circuit in the legalized result converge to a specific standard, the target layout result is obtained; When calculating the net force along the x-direction, the calculation of the net force on each logic unit in the layout result to be optimized includes: Using formula Calculate the net network force on each logical unit in the layout to be optimized; wherein, This represents the set of nets connected to the current logical unit. This represents the network force exerted on the current logic unit by the net n, where n≥1. , This represents the weight of net n in the net set. This represents the maximum connection length of the circuit in the layout result to be optimized. The length of the bounding box of net n along the x-direction is represented; when calculating the critical connection force along the x-direction, the calculation of the critical connection force on each logical unit in the layout result to be optimized includes: Using formula Calculate the critical connection forces on each logical unit in the layout result to be optimized; in, This represents the distance between the source logic unit and the target logic unit along the x-direction. The connection weights are represented by the following formula: ； in, This indicates the criticality of the connection from logic unit i to j. Indicates the criticality threshold. The weighting factor represents the importance of timing optimization relative to line length optimization; When calculating the pseudo-connection force along the x-direction, the calculation of the pseudo-connection force on each logic unit in the layout result to be optimized includes... Using formula Calculate the pseudo-connection force on each logical unit in the layout result to be optimized; wherein, The pseudo-connection weight is represented by , and x represents the current position of the logical unit. This indicates the legal position of the logical unit.

2. The time-driven force-guided layout method according to claim 1, characterized in that, When calculating the resultant force along the x-direction, the calculation involves determining the network resultant force, critical connection force, and pseudo-connection force on each logic unit in the layout to be optimized, and based on this, calculating the resultant force, including: Using formula Calculate the resultant force; in, Indicates the weight of pseudo-connections. The network resultant force along the x-direction of the logical units described in the layout to be optimized is... The critical connection force along the x-direction experienced by the logic unit. The pseudo-connection force along the x-direction experienced by the logic unit.

3. The time-driven force-guided layout method according to claim 2, characterized in that, Based on the combined force, the new layout positions of the logic units in the layout result to be optimized are calculated to obtain another layout result to be optimized, including: Calculate the estimated value of the first-order moment and the estimated value of the second-order original moment of the resultant force; Based on the estimated values ​​of the first-order moments and the second-order primitive moments, the new layout positions of the logic units in the layout result to be optimized are calculated, resulting in another layout result to be optimized.

4. The time-driven force-guided layout method according to claim 3, characterized in that, The calculation of the estimated value of the first-order moment and the estimated value of the second-order primitive moment of the resultant force includes: Through formula Calculate the estimated value of the first moment; Through formula Calculate the estimated value of the second-order primitive moments; in, The resultant force , , ;parameter , respectively represent and The exponential decay rate, Indicates the number of iterations.

5. The time-driven force-guided layout method according to claim 4, characterized in that, The calculation of the new layout positions of the logic cells in the layout result to be optimized, based on the estimated values ​​of the first-order moments and the second-order primitive moments, includes: Using formula Calculate the new layout positions of the logical units in the layout result to be optimized; wherein, Indicates step size, For a specified value, Indicates the number of iterations.

6. The time-driven force-guided layout method according to claim 1, characterized in that, The specific criteria include: The ratio of the bus length of the circuit in the layout optimization result to the bus length of the circuit in the legalization result is within the preset value range; Alternatively, the bus length of the circuit may not be optimized in the validation results of consecutive iterations within a preset number of iterations.

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