Display device

Abstract

The present invention relates to a display device. Each pixel circuit includes a drive transistor, a first switch transistor, and a second switch transistor. The drive transistor includes a first gate electrode and a second gate electrode. The first switch transistor is connected to a first data line and the first gate electrode, and is controlled to be turned on or off in accordance with a scan signal supplied to a scan line. The second switch transistor is connected to a second data line and the second gate electrode, and is controlled to be turned on or off in accordance with the scan signal supplied to the scan line. For at least a part of a gray scale range of the light emitting element from a lowest gray scale level to a highest gray scale level including the lowest gray scale level, a voltage of a second data signal is varied in a direction opposite to a variation of a voltage of a first data signal.

Description

Technical Field

[0001] This invention relates to display devices. Background Technology

[0002] Organic light-emitting diode (OLED) devices are current-driven light-emitting devices, thus eliminating the need for a backlight. Furthermore, OLED devices offer advantages such as low power consumption, wide viewing angles, and high contrast; they are expected to contribute significantly to the development of flat panel display devices.

[0003] Active matrix (AM) OLED display devices include transistors for selecting pixels and driving transistors for supplying current to the pixels. The transistors in OLED display devices are thin-film transistors (TFTs); typically, low-temperature polycrystalline silicon (LTPS) TFTs and / or oxide semiconductor TFTs are used. For medium to large-sized OLED display devices such as industrial monitors, PC monitors, and TV monitors, backplanes including oxide semiconductor TFTs are more frequently used because array processing can be performed on large mother glass at low temperatures. Summary of the Invention

[0004] The amount of illumination current supplied to the OLED element is controlled by the driving transistor. Therefore, it is important to properly generate the control signals for driving the transistor to meet the grayscale levels of the OLED element.

[0005] One aspect of the present invention is a display device, comprising: a display panel; and a control circuit configured to control the display panel, wherein the display panel includes: a plurality of light-emitting elements and a plurality of pixel circuits, each pixel circuit being configured to control the light emission of the light-emitting elements; a first data line for supplying a first data signal to the plurality of pixel circuits; a second data line for supplying a second data signal to the plurality of pixel circuits; and scan lines for controlling the plurality of pixel circuits, wherein each pixel circuit is connected to one or more scan lines, and includes: a driving transistor including a first gate electrode facing a semiconductor layer through a first gate insulating layer and a second gate electrode facing the semiconductor layer through a second gate insulating layer, the driving transistor being configured to control a driving current to be supplied to the light-emitting elements; and a first switching transistor connected to the first data line. The control circuit is configured to: supply a first data signal to the first gate electrode via the first data line and a second data line, and control the first switching transistor to be turned on or off according to a scan signal supplied to the scan line; and a second switching transistor connected to the second data line and the second gate electrode, and controlling the second switching transistor to be turned on or off according to the scan signal supplied to the scan line, wherein the control circuit is configured to: supply a first data signal to the first gate electrode via the first data line when the first switching transistor is turned on, and then turn the first switching transistor off; supply a second data signal to the second gate electrode via the second data line when the second switching transistor is turned on, and then turn the second switching transistor off; and control the first data signal and the second data signal supplied to each pixel circuit such that the voltage of the second data signal varies with the voltage of the first data signal according to a predetermined relationship between the first data signal and the second data signal.

[0006] One aspect of the present invention is a display device, comprising: a display panel; and a control circuit configured to control the display panel, wherein the display panel includes: a plurality of light-emitting elements and a plurality of pixel circuits, each pixel circuit being configured to control the light emission of the light-emitting elements; a data line for supplying a first data signal and a second data signal to the plurality of pixel circuits; and a first scan line and a second scan line for controlling the plurality of pixel circuits, wherein each pixel circuit includes: a driving transistor, the driving transistor including a first gate electrode facing a semiconductor layer through a first gate insulating layer and a second gate electrode facing the semiconductor layer through a second gate insulating layer, the driving transistor being configured to control a driving current to be supplied to the light-emitting elements; and a first switching transistor connected to the data line and the first gate electrode, according to... A first scan signal supplied to a first scan line controls the first switching transistor to be turned on or off; and a second switching transistor, connected to the data line and the second gate electrode, controls the second switching transistor to be turned on or off according to a second scan signal supplied to a second scan line, wherein the control circuit is configured to: supply a first data signal to the first gate electrode through the data line when the first switching transistor is turned on, and then turn the first switching transistor off; supply a second data signal to the second gate electrode through the data line when the second switching transistor is turned on, and then turn the second switching transistor off; and control the first data signal and the second data signal supplied to each pixel circuit such that the voltage of the second data signal varies with the voltage of the first data signal according to a predetermined relationship between the first data signal and the second data signal.

[0007] One aspect of the present invention is a display device, comprising: a display panel; and a control circuit configured to control the display panel, wherein the display panel includes a plurality of light-emitting elements and a plurality of pixel circuits, each pixel circuit being configured to control the light emission of the light-emitting elements, wherein each pixel circuit includes a driving transistor configured to control a driving current to be supplied to the light-emitting elements, wherein the driving transistor includes a first gate electrode facing a semiconductor layer through a first gate insulating layer and a second gate electrode facing the semiconductor layer through a second gate insulating layer, wherein the driving transistor is configured to control the driving current to be supplied to the light-emitting elements while supplying a first data signal to the first gate electrode and a second data signal to the second gate electrode, wherein the control circuit is configured to control each pixel circuit using a display mode selected from a plurality of display modes, wherein the plurality of display modes are defined by different relationships between the first data signal and the second data signal and different relationships between the first data signal and the brightness level of the light-emitting elements, and wherein the control circuit is configured to control the first data signal and the second data signal to generate a driving current for each pixel circuit.

[0008] One aspect of the present invention improves the display quality of a display device.

[0009] It should be understood that the above general description and the following detailed description are exemplary and explanatory, and not intended to limit the invention. Attached Figure Description

[0010] Figure 1 An example configuration of an OLED display device as a display device is schematically shown;

[0011] Figure 2 An example of the configuration of a pixel circuit and its control signals in one embodiment of this specification is shown;

[0012] Figure 3 It is a schematic cross-sectional view showing the cross-sectional structure of the driving transistor;

[0013] Figure 4 It is used for control Figure 2 The timing diagram of the signals of the pixel circuit shown;

[0014] Figure 5 Simulation results are provided showing the relationship between the first data signal Vdata1 and the lighting current supplied from the driving transistor to the OLED element when different second data signals Vdata2 are supplied.

[0015] Figure 6 It is a schematic illustration of how it is viewed in the stacking direction. Figure 2 The pixel circuit shown is a planar view of the device's planar structure;

[0016] Figure 7 Schematic illustration along Figure 6 The cross-sectional structure of section line VII-VII' in the middle;

[0017] Figure 8 Schematic illustration along Figure 6 The cross-sectional structure of section lines VIII-VIII' in the middle;

[0018] Figure 9 An example of the configuration of the pixel circuit and its control signals in another embodiment of this specification is shown;

[0019] Figure 10 It is used for driving Figure 9 The timing diagram of the pixel circuit is shown.

[0020] Figure 11 It is a schematic illustration of how it is viewed in the stacking direction. Figure 9 The pixel circuit shown is a planar view of the device's planar structure;

[0021] Figure 12 An example of the circuit configuration of the display device is shown schematically;

[0022] Figure 13 An example configuration of the circuitry in a data driver for outputting a first data signal Vdata1 and a second data signal Vdata2 to a pixel circuit column is shown.

[0023] Figure 14 An example of the relationship between the first data signal Vdata1 and the second data signal Vdata2 is shown;

[0024] Figure 15 An example of the configuration of the pixel circuit and its control signals in another embodiment of this specification is shown;

[0025] Figure 16 This illustrates yet another configuration example of the pixel circuitry;

[0026] Figure 17 It is used for driving Figure 16 The timing diagram of the pixel circuit is shown.

[0027] Figure 18 It is a schematic illustration of how it is viewed in the stacking direction. Figure 16 The pixel circuit shown is a planar view of the device's planar structure;

[0028] Figure 19An example of the relationship between the first data signal Vdata1 and the second data signal Vdata2 is shown;

[0029] Figure 20 It is shown Figure 19 A graph showing the effect of the relationship between the first and second data signals in the data;

[0030] Figure 21 An example illustrating the relationship between gray levels and the first data signal Vdata1 is shown;

[0031] Figure 22 An example of the relationship between the second data signal Vdata2 and the first data signal Vdata1 is shown when displaying without using HDR driver;

[0032] Figure 23 An example of the relationship between the control voltage Vdata2 and the grayscale voltage Vdata1 in HDR mode is shown;

[0033] Figure 24 Examples of the relationship between grayscale voltage Vdata1 and illumination current I_oled (brightness) in HDR mode and examples of the relationship between grayscale voltage Vdata1 and illumination current I_oled (brightness) in standard mode are shown.

[0034] Figure 25 An example configuration of a micro LED pixel circuit is shown;

[0035] Figure 26 This is a plan view schematically illustrating an example of the structure of a micro LED pixel circuit;

[0036] Figure 27 It is along Figure 26 A cross-sectional view of section line Y-Y' in the diagram;

[0037] Figure 28 This is a perspective view schematically showing the display area of ​​a micro LED display device;

[0038] Figure 29 It is along Figure 28 A cross-sectional view of section line A-A' in the diagram;

[0039] Figure 30 An example of a data drive is shown; and

[0040] Figure 31 The image shown includes regions with different emission levels. Detailed Implementation

[0041] In the following description, embodiments will be illustrated with reference to the accompanying drawings. Common elements in the drawings are indicated by the same reference numerals, and some elements in the drawings are enlarged in size or shape for clarity of understanding.

[0042] The following discloses techniques for improving the control of the lighting current of the light-emitting element in an electroluminescent display device. An electroluminescent display device is a display device that utilizes a light-emitting element that emits light in response to a lighting current, such as an organic light-emitting diode (OLED) display device.

[0043] In one embodiment of this specification, the driving transistor has a dual-gate structure. In other words, each driving transistor includes a first gate electrode and a second gate electrode sandwiching a channel region. A gate insulating layer is located between the first gate electrode and the channel region, and between the second gate electrode and the channel region.

[0044] The driving transistor controls the brightness of the light emitted from the light-emitting element by supplying a lighting current corresponding to the light emission level. The lighting current varies according to the gate voltage of the first and second gate electrodes of the driving transistor.

[0045] The control circuit of the display device supplies a first data signal (first gate voltage) to the first gate electrode and a second data signal (second gate voltage) to the second gate electrode. The first gate voltage is at a value corresponding to a desired gray level. The gray level is related to the brightness level of the light emitted by the light-emitting element. Lower gray levels are used for darker light, while higher gray levels are used for brighter light.

[0046] For at least a portion of the grayscale range (brightness range), the second data signal varies with the first data signal. This variation of the second data signal according to the first data signal allows the subthreshold factor of the driving transistor to be controlled at a desired value.

[0047] One embodiment of this specification controls a first data signal and a second data signal supplied to each pixel circuit such that the voltage of the second data signal varies with the voltage of the first data signal according to a predetermined relationship between the first and second data signals. The second data signal varies in a different manner than the first data signal.

[0048] In one embodiment of this specification, the second data signal changes in polarity opposite to the first data signal. In other words, the second data signal decreases as the first data signal increases, and increases as the first data signal decreases. In one embodiment of this specification, a portion of the grayscale range is a continuous range from the lowest grayscale level to a first grayscale level higher than the lowest grayscale level (referred to as the low grayscale range). The first grayscale level can be the highest grayscale level, such that the second data signal changes in polarity opposite to the first data signal throughout the grayscale range. The first grayscale level can be an intermediate grayscale level between the lowest and highest grayscale levels. In this case, the second data signal can be fixed within a range higher than the first grayscale level or change with the same polarity as the first data signal.

[0049] The first data signal is denoted as Vdata1, and the second data signal is denoted as Vdata2. The low grayscale range data signals Vdata1 and Vdata2 can have the following relationship: Vdata2 = V0 + k × Vdata1, where V0 is a constant and k is a negative coefficient. The relationship between Vdata1 and Vdata2 can be expressed by a function given according to the design of the OLED display device.

[0050] Supplying a gate voltage with opposite polarity to the driving transistor with a dual-gate structure increases the subthreshold factor of the driving transistor, enabling the supply of a lighting current to the light-emitting element that more precisely corresponds to the gray level. In particular, this control in the low grayscale range increases the potential difference (voltage difference) between gray levels, thereby facilitating light emission control in the low grayscale range. Therefore, luminance MURA (uniformity) in the display can be effectively reduced.

[0051] Oxide-semiconductor thin-film transistors (TFTs) typically have a subthreshold factor of less than 0.2V / decade. For this reason, the gate voltage control described above provides a significant effect, especially for pixel circuits that use oxide-semiconductor TFTs as driving transistors.

[0052] A driving transistor is required to maintain a first data signal and a second data signal during one or more frame periods. In one embodiment of this specification, the pixel circuit includes a first switching transistor and a second switching transistor. The first switching transistor turns on / off the electrical connection between its first gate electrode and a data line used to transmit the first data signal. The second switching transistor turns on / off the electrical connection between its second gate electrode and a data line used to transmit the second data signal.

[0053] The data line used to transmit the first data signal and the data line used to transmit the second data signal can be the same data line or different data lines. When the first switching transistor is in the ON state, it supplies the first data signal from the data line to the first gate electrode. After supplying the first data signal, the first switching transistor is turned off. When the second switching transistor is in the ON state, it supplies the second data signal from the data line to the second gate electrode. After supplying the second data signal, the second switching transistor is turned off.

[0054] Therefore, the first data signal and the second data signal are held at the first gate electrode and the second gate electrode for one frame period. Within one frame, the display device sequentially selects pixel rows and writes the data signal to all pixel rows. The display device holds the data signal in all pixel rows to maintain the displayed image until the next data signal is written. The data signal used to display the image is generated based on frames of video data received from an external source.

[0055] The method for controlling a driving transistor with a dual-gate structure and the pixel circuit including such a driving transistor can be applied to display devices with different types of light-emitting elements other than OLED elements.

[0056] Display device configuration

[0057] Figure 1 An example configuration of an OLED display device 10 as a display device is shown schematically. Figure 1 The horizontal direction in the diagram is the X-axis direction, while the vertical direction is the Y-axis direction, which is perpendicular to the X-axis direction. The OLED display device 10 includes a thin-film transistor (TFT) substrate 100 on which OLED elements (light-emitting elements) are fabricated, and an encapsulation substrate 150 for encapsulating the OLED elements.

[0058] The space between the TFT substrate 100 and the packaging substrate 150 is filled with an inert gas such as dry nitrogen and sealed. Instead of the packaging substrate 150, a structural packaging unit with a different structure can be used, such as a structural packaging unit utilizing thin-film encapsulation.

[0059] Scanning circuits 131 and 132, a driver IC 134, and a demultiplexer 136 are disposed around the cathode electrode region 114, outside the display region 125 of the TFT substrate 100. The driver IC 134 is connected to an external device via a flexible printed circuit (FPC) 135. The scanning circuits 131 and 132 drive the scan lines on the TFT substrate 100.

[0060] The driver IC 134 is, for example, equipped with an anisotropic conductive film (ACF). The driver IC 134 provides power and timing signals (control signals) to the scan circuits 131 and 132, and also provides data signals to the demultiplexer 136.

[0061] Demultiplexer 136 outputs the output of one pin of driver IC 134 sequentially to d data lines (d is an integer greater than 1). Demultiplexer 136 changes the output data lines of the data signal from driver IC 134 d times in each scan period to drive d times the number of data lines of the output pin of driver IC 134.

[0062] Display area 125 includes multiple OLED elements and multiple pixel circuits for controlling the emission of light from the multiple OLED elements. In an example of a color OLED display device, each OLED element emits light of one color: red, blue, or green. The multiple pixel circuits constitute a pixel circuit array. For example, the multiple OLED elements and multiple pixel circuits are arranged in a matrix.

[0063] As described later, each pixel circuit includes a driving TFT (driving transistor) with a dual-gate structure and two switching transistors, each switching transistor being connected between one of the two gate electrodes of the driving TFT and a common or different data line. Each of the two switching transistors is turned on / off, such that a data signal is supplied to the associated gate electrode and held at that gate electrode for one frame. The data signal (gate voltage) at the two gate electrodes analogously changes the conductance of the driving TFT to supply a forward bias current to the OLED element corresponding to the grayscale level.

[0064] Pixel circuit configuration

[0065] Figure 2 An example configuration of a pixel circuit and its control signals in one embodiment of this specification is shown. The pixel circuit is included in the l-th pixel circuit row (l is an integer). The pixel circuit includes four transistors (TFTs) M1 to M4, each transistor having a gate electrode, a source region, and a drain region. In this example, all transistors M1 to M4 are n-type TFTs. The n-type TFT can be an oxide semiconductor TFT.

[0066] Transistor M1 is a driving transistor used to control the amount of illumination current of OLED element E1. Transistor M1 has a dual-gate structure including a first gate electrode G1 and a second gate electrode G2. The drain region of driving transistor M1 is connected to power line 241 for transmitting the positive power supply potential PVDD. Driving transistor M1 controls the amount of illumination current to be supplied from power line 241 to OLED element E1 based on the gate voltage at gate electrodes G1 and G2.

[0067] The pixel circuit includes storage capacitor elements Cst1 and Cst2. Storage capacitor element Cst1 is the third capacitor element, and it is connected between the power supply line 241, which transmits the positive power supply potential PVDD, and the first gate electrode G1 of the driving transistor M1. Storage capacitor element Cst1 maintains the voltage between the first gate electrode G1 of the driving transistor M1 and the power supply line 241. The drain region of the driving transistor M1 is connected to the power supply line 241, and the drain potential is the positive power supply potential PVDD.

[0068] The gate voltage of the first gate electrode G1 is maintained by the charge stored in the storage capacitor element Cst1 and the gate capacitor of the first gate electrode G1. The gate voltage of the first gate electrode G1 depends on the value of the first data signal Vdata1 transmitted by the first data line 201. According to the design, the storage capacitor element Cst1 can be removed.

[0069] Storage capacitor Cst2 is the fourth capacitor element, connected between the power supply line 241 used to transmit the positive power supply potential PVDD and the second gate electrode G2 of the driving transistor M1. Storage capacitor Cst2 maintains the voltage between the second gate electrode G2 of the driving transistor M1 and the power supply line 241.

[0070] The gate voltage of the second gate electrode G2 is maintained by the charge stored in the storage capacitor element Cst2 and the gate capacitor of the second gate electrode G2. The gate voltage of the second gate electrode G2 depends on the value of the second data signal Vdata2 transmitted by the second data line 202. In one embodiment of this specification, the capacitance and area of ​​the storage capacitor element Cst2 are smaller than those of the storage capacitor element Cst1. This configuration facilitates the implementation of the pixel circuit while enabling proper control of the driving transistor M1. Depending on the design, the storage capacitor element Cst2 can be removed.

[0071] Transistor M2 is a first switching transistor used to select the pixel circuit to be supplied with the first data signal Vdata1 and to apply the first data signal (voltage) Vdata1 to the first gate electrode G1. One of the source / drain regions of transistor M2 is connected to the node between the first gate electrode G1 and the first storage capacitor element Cst1, and the other is connected to the data line 201 for transmitting the first data signal Vdata1.

[0072] The gate electrode of transistor M2 is connected to transmission line 212 for transmitting the selection signal S2 from scan circuit 131. Transistor M2 is controlled by selection signal S2. When transistor M2 is turned on, transistor M2 supplies the first data signal Vdata1 supplied from driver IC 134 through data line 201 to the first gate electrode G1 and the first storage capacitor element Cst1.

[0073] Transistor M4 is a second switching transistor used to select the pixel circuit to be supplied with the second data signal Vdata2 and to apply the second data signal (voltage) Vdata2 to the second gate electrode G2. One of the source / drain regions of transistor M4 is connected to the node between the second gate electrode G2 and the second storage capacitor element Cst2, and the other is connected to the data line 202 for transmitting the second data signal Vdata2.

[0074] The gate electrode of transistor M4 is connected to transmission line 212 for transmitting the selection signal S2 from scan circuit 131. Transistor M4 is controlled by selection signal S2. When transistor M4 is turned on, transistor M4 supplies the second data signal Vdata2 supplied from driver IC 134 through data line 202 to the second gate electrode G2 and the second storage capacitor element Cst2.

[0075] The cathode of OLED element E1 is connected to power line 204, which supplies the cathode power potential PVEE. Figure 2 In the example, the anode of OLED element E1 is connected to the source region of driving transistor M1. Transistor M3 is used to supply a reset potential Vrst to the source region of driving transistor M1 and the anode of OLED element E1.

[0076] One of the source / drain regions of transistor M3 is connected to power line 242 for transmitting the reset potential Vrst, and the other is connected to the source region of driving transistor M1 and the anode of OLED element E1. The reset potential Vrst can be equal to or lower than the cathode power supply potential PVEE. When these potentials are equal (e.g., at ground potential), a transmission line (power line) can be shared between the reset potential Vrst and the cathode power supply potential PVEE. The cathode power supply potential PVEE can be referred to as the negative power supply potential compared to the positive power supply potential PVDD.

[0077] The gate electrode of transistor M3 is connected to control signal line 213 for transmitting selection signal S3, and transistor M3 is controlled by selection signal S3. When transistor M3 is turned on by selection signal S3 from scan circuit 131, transistor M3 supplies the reset potential Vrst transmitted by power supply line 242 to the source region of driving transistor M1 and the anode of OLED element E1.

[0078] The pixel circuit includes capacitor elements C1 and C2. These capacitor elements may have equal capacitance and area. Capacitor element C1 is the first capacitor element and is connected between the first gate electrode G1 and the source region of the driving transistor M1. Capacitor element C2 is the second capacitor element and is connected between the second gate electrode G2 and the source region of the driving transistor M1.

[0079] As described above, the source region of the driving transistor M1 is temporarily charged to the reset potential Vrst. When the OLED element E1 emits light, the source potential of the driving transistor M1 increases to a potential VA determined by the value of the lighting current (driving current). Therefore, the potential change (VA – Vrst) is added to the gate potential of the driving transistor M1 through capacitors C1 and C2 (bootstrapping), thereby achieving constant current operation of the driving transistor M1.

[0080] Structure of driving transistors

[0081] Figure 3 This is a schematic cross-sectional view showing the cross-sectional structure of the driving transistor M1. A base coating UL is deposited on top of the insulating substrate SUB, and the driving transistor M1 is fabricated on it. In this specification, the side further away from the substrate is referred to as the upper side, and the side closer to the substrate is referred to as the lower side.

[0082] The driving transistor M1 includes a second gate electrode G2 and a gate insulating layer GI2 located between the second gate electrode G2 and the oxide semiconductor layer OS. The second gate electrode G2 is the bottom gate electrode. The gate insulating layer GI2 is also referred to as the second gate insulating layer or the bottom gate insulating layer. The oxide semiconductor layer OS is made of metal oxide.

[0083] The oxide semiconductor layer OS includes a source region SR, a drain region DR, and a channel region CR. The channel region CR is located between the source region SR and the drain region DR in the in-plane direction. The second gate insulating layer GI2 can be a silicon oxide film, or a stack of a silicon oxide film (upper side) and a silicon nitride film (lower side).

[0084] The oxide semiconductor layer OS is directly disposed above (in contact with) the second gate insulating layer GI2. An example of a metal oxide is indium gallium zinc oxide (IGZO). The source region SR and drain region DR are made of metal oxide with reduced resistance. The channel region CR is made of metal oxide (semiconductor) with unreduced resistance.

[0085] The second gate electrode G2 is positioned opposite the channel region CR, separated by the second gate insulating layer GI2. The second gate electrode G2, the second gate insulating layer GI2, and the channel region CR are stacked sequentially from the bottom (the side closer to the substrate). The second gate insulating layer GI2 is in contact with the channel region CR and the second gate electrode G2. The second gate electrode G2 is supplied with a signal voltage corresponding to the second data signal Vdata2.

[0086] The driving transistor M1 also includes a first gate electrode G1 and a gate insulating layer GI1 located in the in-plane direction between the first gate electrode G1 and the channel region CR. The first gate electrode G1 is the top gate electrode. The gate insulating layer GI1 is also referred to as the first gate insulating layer or the top gate insulating layer.

[0087] The first gate insulating layer GI1 can be a silicon oxide film, a silicon nitride film, or a stack of silicon oxide and silicon nitride films. The channel region CR, the first gate insulating layer GI1, and the first gate electrode G1 are stacked sequentially from the bottom (the side closer to the substrate). The first gate insulating layer GI1 is in contact with the channel region CR and the first gate electrode G1.

[0088] The first gate electrode G1 is supplied with a signal voltage corresponding to the first data signal Vdata1. The first gate electrode G1 can be used as a mask (self-aligned) for generating the source region SR and the drain region DR. The first gate electrode G1 also blocks external light from reaching the channel region CR.

[0089] The first gate electrode G1 and the layer below it are covered by an interlayer insulating layer ILD and a passivation layer PAS above the ILD. The ILD and PAS are insulating layers. The source electrode SE extends through the ILD and the first gate insulating layer GI1 and contacts the source region SR. The drain electrode DE extends through the ILD and the first gate insulating layer GI1 and contacts the drain region DR.

[0090] operation of pixel circuit

[0091] Figure 4 It is used for control Figure 2 The timing diagram of the signals of the pixel circuit shown is shown. Figure 4 This is a timing diagram of the pixel circuit used to select the l-th row and write the data signal into it. Specifically, Figure 4 The timing sequence of selection signal S2, selection signal S3, first data signal Vdata1, and second data signal Vdata2 is shown. The intervals between the vertical dashed lines are equal, and each interval represents a 1-hour time period.

[0092] The period before time T0 is the light-emitting period. Selection signals S2 and S3 are at low levels. During this period, transistors M2 to M4 are off. Therefore, the gate voltages of the first gate electrode G1 and the second gate electrode G2 are maintained. A constant lighting current corresponding to the level of the data signal is supplied from power line 241 to OLED element E1 through driving transistor M1, causing OLED element E1 to emit light.

[0093] The period from time T0 to time T1 is the reset period. Immediately after time T0, the selection signal S3 changes from low to high. The selection signal S2 remains low. In response to the change in the selection signal S3, transistor M3 turns on. Transistors M2 and M4 remain off. Because transistor M3 is on, the source region of driving transistor M1 and the anode of OLED element E1 are reset to the reset potential Vrst.

[0094] Immediately before time T1, the selection signal S3 changes from high to low, and transistor M3 is turned off. Immediately after time T1, the selection signal S2 changes from low to high. In response to the change in the selection signal S2, transistors M2 and M4 are turned on.

[0095] The first data signal Vdata1 is supplied to the first gate electrode G1 through the transistor M2, which is in the ON state. Simultaneously, the second data signal Vdata2 is supplied to the second gate electrode G2 through the transistor M4, which is in the ON state. The first data signal Vdata1 and the second data signal Vdata2 change to correspond to the voltage of the associated pixel row with a period of 1H. As described above, the first data signal Vdata1 and the second data signal Vdata2 change in opposite polarities for each pixel.

[0096] Figure 5 Simulation results are provided showing the relationship between the first data signal Vdata1 and the illumination current supplied from the driving transistor M1 to the OLED element E1 when different second data signals Vdata2 are supplied. The horizontal axis of the graph represents the first data signal Vdata1, and the vertical axis represents the logarithmic value of the illumination current.

[0097] Curve 351 shows the relationship between the first data signal Vdata1 and the lighting current when the second data signal Vdata2 = 6.0 + Vdata1. Curve 352 shows the relationship between the first data signal Vdata1 and the lighting current when the second data signal Vdata2 = 6.0. Curve 353 shows the relationship between the first data signal Vdata1 and the lighting current when the second data signal Vdata2 = 6.0 – 0.5 * Vdata1. Curve 354 shows the relationship between the first data signal Vdata1 and the lighting current when the second data signal Vdata2 = 6.0 – Vdata1.

[0098] exist Figure 5 In the examples provided, the second data signal Vdata2 in each curve is given by V0 + k * Vdata1, where V0 is 6.0 and k is a curve-specific value. As the value of k decreases, the slope of the curve becomes less steep; in other words, the threshold voltage Vth driving the transistor becomes higher, and the subthreshold factor (S-factor) becomes larger. As can be observed from these simulation results, the second data signal Vdata2, which has the characteristic of depending on the level of the first data signal Vdata1 and increasing the threshold voltage Vth, can increase the S-factor of the driving transistor. The S-factor can be controlled by a scaling factor k, for which any value can be chosen that is optimal for display performance.

[0099] Device structure of pixel circuit

[0100] Figure 6 It is a schematic illustration of how it is viewed in the stacking direction. Figure 2 The pixel circuit shown is a planar view of its planar structure. Figure 6 The storage capacitor element Cst2 is omitted. Transistors M2, M3, and M4 have a dual-gate structure; the same control signal is supplied to the top and bottom gate electrodes of each transistor.

[0101] Figure 6 The diagram illustrates the oxide semiconductor layer (OS) and conductor layer in a pixel circuit. Squares with diagonal lines represent contact areas between different conductor layers. These contact areas are conductive regions located within vias that extend through one or more insulating layers in the stacking direction. Elements made of the same material and included in the pattern within the same layer are represented by lines of the same type.

[0102] Transmission lines 212T and 212B are used to transmit the selection signal S2. Transmission lines 213T and 213B are used to transmit the selection signal S3. The first data line 201 is used to transmit the first data signal Vdata1, and the second data line 202 is used to transmit the second data signal Vdata2. The power line 241 is used to transmit the positive power supply potential PVDD, and the power line 242 is used to transmit the reset potential Vrst.

[0103] For reference Figure 2 As described, the pixel circuit includes transistors M1 to M4. The semiconductor layer of these transistors is part of the oxide semiconductor layer OS. As described above, the driving transistor M1 includes a first gate electrode G1 and a second gate electrode G2. The second gate electrode G2 and transmission lines 212B and 213B are included in the pattern of the first metal layer. The first gate electrode G1, transmission lines 212B and 213B, and power line 242 are included in the pattern of the second metal layer. Data lines 201 and 202 and power line 241 are included in the pattern of the third metal layer. These metal layers are laid in the order of the first metal layer, the second metal layer, and the third metal layer, starting from the side closer to the insulating substrate.

[0104] Contact region CONT1 is the contact region between one of the source / drain regions of transistor M2 and the first data line 201. Contact region CONT2 is the contact region between one of the source / drain regions of transistor M4 and the second data line 202. Contact region CONT3 is the contact region between the anode electrode RE of the OLED element and the pixel circuit. The anode electrode RE is located above the third metal layer.

[0105] Figure 7 Schematic illustration along Figure 6 The cross-sectional structure of section line VII-VII' in the middle. Figure 7 Transistors M1, M2, and M4 are primarily shown. A stacked structure of pixel circuits is fabricated on a substrate SUB made of polyimide or glass. A base coating UL, which may be a silicon nitride layer, is disposed on the substrate SUB.

[0106] The first metal layer is laid over the base layer UL. Specifically, in Figure 7 The diagram shows transmission line 212B for transmitting the selection signal S2 and the second gate electrode G2 of the driving transistor M1. (See diagram for reference.) Figure 7 As shown, a portion of transmission line 212B corresponds to the bottom gate electrode of transistors M2 and M4. The first metal layer can be made of a metal such as W, Mo, or Ta, or an alloy thereof.

[0107] A gate insulating layer GI2 is deposited to cover the first metal layer. The gate insulating layer GI2 can be made of silicon oxide or silicon nitride. An oxide semiconductor layer OS is deposited above the gate insulating layer GI2. The oxide semiconductor layer OS includes source / drain regions with reduced resistance and channel regions with high resistance, each channel region being sandwiched between two source / drain regions. Furthermore, a gate insulating layer GI1 is deposited to cover the oxide semiconductor layer OS. The gate insulating layer GI1 can be made of silicon oxide or silicon nitride.

[0108] The second metal layer is deposited above the gate insulating layer GI1. Specifically, in Figure 7 The diagram shows the transmission line 212T for transmitting the selection signal S2 and the first gate electrode G1 of the driving transistor M1. (See diagram for reference.) Figure 7 As shown, a portion of transmission line 212T corresponds to the top gate electrode of transistors M2 and M4. The second metal layer can be made of a metal such as W, Mo, or Ta, or an alloy thereof.

[0109] An interlayer insulating layer (ILD) is laid up to cover the second metal layer. The ILD can be made of silicon oxide or silicon nitride. A third metal layer is disposed on top of the ILD. The third metal layer can be a single Al layer or a multilayer structure of Ti / Al / Ti.

[0110] Included Figure 7 The components in the third metal layer shown are transmission line 201 for the first data signal Vdata1, transmission line 202 for the second data signal Vdata2, and power line 241. Furthermore, Figure 7 The diagram shows an interconnection region IC1 between one of the source / drain regions of transistor M2 and the first gate electrode G1 of driving transistor M1, and an interconnection region IC2 between one of the source / drain regions of transistor M4 and the second gate electrode G2 of driving transistor M1.

[0111] Each of transmission lines 201 and 202 is in direct contact with the oxide semiconductor layer OS via a contact hole extending through the interlayer insulating layer ILD and the gate insulating layer GI1. Interconnect region IC1 is in direct contact with the oxide semiconductor layer OS of transistor M2 via a contact hole extending through the interlayer insulating layer ILD and the gate insulating layer GI1, and is also in direct contact with the first gate electrode G1 of driving transistor M1 via a contact hole extending through the interlayer insulating layer ILD.

[0112] Interconnect region IC2 is in direct contact with oxide semiconductor layer OS of transistor M4 through contact holes extending through interlayer insulating layer ILD and gate insulating layer GI1, and is also in direct contact with second gate electrode G2 of driving transistor M1 through contact holes extending through interlayer insulating layer ILD and gate insulating layers GI1 and GI2.

[0113] The passivation layer PAS and the planarization layer PLN above the passivation layer PAS are configured to cover layers below these layers. The passivation layer PAS and the planarization layer PLN can be made of organic or inorganic insulators. The anode electrode RE of the OLED element is disposed above the planarization layer PLN. The anode electrode RE can have an ITO / Ag / ITO or IZO / Ag / IZO structure.

[0114] Figure 8 Schematic illustration along Figure 6 The cross-sectional structure of section lines VIII-VIII' in the diagram. Figure 8 The main components shown are transistor M3, capacitor C2, storage capacitor Cst1, and driving transistor M1. The following mainly describes... Figure 7 Components not shown in the diagram.

[0115] The first metal layer includes a transmission line 213B for transmitting the selection signal S3 and an electrode for the capacitor element C2. A portion of the transmission line 213B corresponds to the bottom gate electrode of the transistor M3. The capacitor element C2 consists of the electrode in the first metal layer, one of the source / drain regions of the transistor M3, and the gate insulating layer GI2 therebetween.

[0116] The second metal layer includes a power line 242 for transmitting the reset potential Vrst and a transmission line 213T for transmitting the selection signal S3. A portion of the transmission line 213T corresponds to the top gate electrode of the transistor M3.

[0117] The third metal layer includes an interconnect region IC3 between the power line 242 and the source / drain regions of the transistor M3. The interconnect region IC3 is in direct contact with the oxide semiconductor layer OS of the transistor M3 through contact holes extending through the interlayer insulating layer ILD and the gate insulating layer GI1, and is also in direct contact with the power line 242 through contact holes extending through the interlayer insulating layer ILD.

[0118] A portion of the power supply line 241 used for the positive power supply potential corresponds to the electrode of the storage capacitor element Cst1. The storage capacitor element Cst1 consists of the power supply line 241, the first gate electrode G1 of the driving transistor M1, and the interlayer insulating layer ILD between them.

[0119] Pixel circuit configuration example

[0120] Figure 9 An example configuration of a pixel circuit and its control signals according to another embodiment of this specification is shown. This pixel circuit compensates for variations in the threshold voltage Vth of the drive transistor M1. The main description is related to... Figure 2 The differences in the pixel circuit configuration shown are as follows. Besides... Figure 2In addition to the pixel circuitry, the pixel circuitry also includes transistors M5 and M6. Transistors M5 and M6 are n-type TFTs. Furthermore, a transmission line 214 for transmitting the selection signal S4 and a power line 243 for transmitting the reference power supply potential Vref are added. The value of the reference power supply potential Vref can be a value between the positive power supply potential PVDD and the reset power supply potential Vrst, for example, a value a few volts higher than the reset power supply potential Vrst.

[0121] Transistor M5 is connected to the first gate electrode G1 of the driving transistor M1. Figure 9 (The reference numeral is omitted in the accompanying drawing) is between the power supply line 243 used for the reference power supply potential. The gate electrode of transistor M5 is connected to the transmission line 214 used for the selection signal S4. Transistor M6 is connected to the second gate electrode G2 of the driving transistor M1 ( Figure 9 (The reference numeral is omitted in the attached figure) is between the power supply line 243 used for the reference power supply potential. The gate electrode of transistor M6 is connected to the transmission line 214 used for the selection signal S4.

[0122] Figure 10 It is used for driving Figure 9 The timing diagram of the pixel circuit is shown. Specifically, Figure 10 The time variations of the selection signals S2, S3, and S4, and the data signals Vdata1 and Vdata2, for the (n-1)th pixel circuit row, the nth pixel circuit row, and the (n+1)th pixel circuit row are shown. The same type of selection signal used for two adjacent pixel circuit rows is offset in phase by 1H.

[0123] The control of the pixel circuit in the nth pixel circuit row is described by way of example. At time T10, the selection signal S4(n) changes from low to high. In response, transistors M5 and M6 are turned on. Additionally, the selection signal S3(n) changes from low to high. In response, transistor M3 is turned on. The selection signal S2(n) remains low, and transistors M2 and M4 remain off.

[0124] At time T11, which is 2 hours later than time T10, the selection signal S3(n) changes from high to low. The selection signal S4(n) remains high, and the selection signal S2(n) remains low. In response to the change in the selection signal S3(n), transistor M3 is turned off.

[0125] At time T12, which is 5 hours later than time T11, selection signal S4(n) remains high. Selection signals S3(n) and S2(n) remain low. During the period from time T11 to T12, storage capacitors Cst1 and Cst2 are used to compensate for the voltage charging of the threshold voltage Vth on the first and second gate sides of the driving transistor M1.

[0126] At time T13, which is 1 hour later than time T12, the selection signal S4(n) changes from high to low. In response to the change in selection signal S4(n), transistors M5 and M6 are turned off. The selection signal S2(n) changes from low to high. The selection signal S3(n) remains low. In response to the change in selection signal S2(n), transistors M2 and M4 are turned on. Data signals Vdata1 and Vdata2 are written to the pixel circuit.

[0127] At time T14, which is 1 hour later than time T13, selection signal S2(n) changes from high to low. Selection signals S4(n) and S3(n) remain low. In response to the change in selection signal S2(n), transistors M2 and M4 are turned off. The light-emitting period of the nth pixel circuit row begins at time T14.

[0128] Figure 11 It is a schematic illustration of how it is viewed in the stacking direction. Figure 9 The pixel circuit device in the diagram is a planar diagram of the device's planar structure. Figure 11 The storage capacitor element Cst2 is omitted. Figure 6 In the example of pixel circuits, the same components are represented by the same reference numerals, even if they have different shapes. Besides... Figure 6 In addition to the components of the pixel circuit, Figure 11 It also includes transistors M5 and M6, transmission lines 214T and 214B for the selection signal S4, and a power line 243 for the reference power supply potential Vref. Transistors M5 and M6 are oxide semiconductor TFTs.

[0129] Transistors M5 and M6 have a dual-gate structure; the top and bottom gate electrodes of each transistor are supplied with the same control signal. Transmission lines 214T and 214B are used to transmit the selection signal S4. A portion of transmission line 214T corresponds to the top gate electrode of transistor M5, while another portion corresponds to the top gate electrode of transistor M6. A portion of transmission line 214B corresponds to the bottom gate electrode of transistor M5, while another portion corresponds to the bottom gate electrode of transistor M6. Transmission line 214B is included in a first metal layer, and transmission line 214T is included in a second metal layer.

[0130] Power line 243 for the reference power supply potential Vref is included in the second metal layer. Interconnect region IC4 connects power line 243 to one of the source / drain regions of transistor M5 via contact regions. Interconnect region IC5 connects power line 243 to one of the source / drain regions of transistor M6 via contact regions.

[0131] Figure 12An example of the circuit configuration of a display device is schematically shown. The pixel circuitry therein has... Figure 9 The configuration shown. The display area of ​​this display device includes pixel circuits 370 arranged in a matrix. Figure 12 In the illustration, as an example, one of the pixel circuits is provided with reference numeral 370. The number of pixel circuits and the size of each pixel circuit differ from the actual figures.

[0132] The control circuitry includes a data driver 371, a power supply circuit 372, and scanning circuits 361, 362, and 363, all disposed outside the display area. The data driver 371 outputs a first data signal Vdata1 and a second data signal Vdata2 to each pixel circuit column. The power supply circuit 352 supplies a positive power supply potential PVDD, a reference power supply potential Vref, and a reset power supply potential Vrst to the pixel circuit 370. The data driver 351 and the power supply circuit 352 can be included in a driver IC 134.

[0133] Scanning circuit 361 outputs selection signal S2 sequentially for each pixel circuit row. Scanning circuit 362 outputs selection signal S4 sequentially for each pixel circuit row. Scanning circuit 363 outputs selection signal S3 sequentially for each pixel circuit row.

[0134] Figure 13 An example configuration of a circuit for outputting a first data signal Vdata1 and a second data signal Vdata2 to a pixel circuit column is shown. This circuit is included in a data driver 351. The data driver 351 includes a first DA converter (DAC1) 401, a second DA converter (DAC2) 402, a first buffer amplifier 405, and a second buffer amplifier 406. A reference potential Vo and a ground potential are supplied to the first DA converter 401 to perform DA conversion. A reference potential Vo and a ground potential are supplied to the second DA converter 402 to perform DA conversion.

[0135] A first DA converter 401 converts digital data into an analog signal. A first buffer amplifier 405 amplifies the analog signal from the first DA converter 401 (including amplifying it to the same intensity) and outputs the first data signal Vdata1 to the data line. A second DA converter 402 converts the aforementioned digital data into another analog signal. A second buffer amplifier 406 amplifies the analog signal from the second DA converter 402 (including amplifying it to the same intensity) and outputs the second data signal Vdata2 to the data line. The desired characteristics of the relationship between the first data signal Vdata1 and the second data signal Vdata2 can be selected by appropriately choosing the reference potential to be supplied to the second DA converter 402.

[0136] Figure 14An example of the relationship between the first data signal Vdata1 and the second data signal Vdata2 is shown. The horizontal axis of the graph represents the first data signal Vdata1, and the vertical axis represents the second data signal Vdata2. The solid line 451 represents the relationship Vdata2 = V0 – Vdata1. The dashed line 452 represents the relationship Vdata2 = V0 + k * Vdata1 (k < –1). In the relationship represented by the double-dotted line 453, Vdata2 decreases linearly with the increase of Vdata1 in the low-level region and becomes a constant value starting from a certain gray level.

[0137] In one embodiment of this specification, Vdata2 varies in polarity opposite to Vdata1 within at least a portion of the grayscale (brightness) range of the OLED element used to display an image, encompassing a series of consecutive lowest grayscale levels. In other words, within a portion of the range including the lowest grayscale levels of the OLED element, the rate of change of Vdata2 relative to Vdata1 is less than 0. This configuration increases the potential difference (voltage difference) between grayscale levels and facilitates light emission control, particularly in the low grayscale range. Therefore, non-uniformity in the display can be effectively reduced.

[0138] The relationship between Vdata2 and Vdata1 is not limited to Figure 14 The example provided is as follows. For instance, in at least a portion of the grayscale range, Vdata2 may decrease non-linearly as Vdata1 increases. The rate of change of Vdata2 relative to Vdata1 may not exceed 0 across the entire grayscale range from the lowest to the highest grayscale level, or the rate of change may be positive for a portion of the grayscale range.

[0139] Figure 15 An example configuration of a pixel circuit and its control signals in another embodiment of this specification is shown. This pixel circuit is included in the l-th pixel circuit row (l is an integer). The following description mainly focuses on... Figure 2 The differences in pixel circuits.

[0140] Figure 15 The pixel circuit in the image is replaced by the driving transistor M11 used for the p-type TFT. Figure 2 The driving transistor M1 is replaced by storage capacitors Cst11 and Cst12. Figure 2 It is obtained by storing capacitor elements Cst1 and Cst2 in the middle. Figure 2 Capacitors C1 and C2 were removed.

[0141] Transistor M11 is a driving transistor that controls the amount of illumination current supplied to OLED element E1. Transistor M11 has a dual-gate structure. The source region of driving transistor M11 is connected to power line 241 for transmitting the positive power supply potential PVDD. Driving transistor M11 controls the amount of illumination current supplied from power line 241 to OLED element E1 based on the gate voltages at the two gate electrodes G11 and G12.

[0142] The pixel circuit includes storage capacitors Cst11 and Cst12. Storage capacitor Cst11 is connected between power line 241, which transmits the positive power supply potential PVDD, and the first gate electrode G11 of the driving transistor M11. Storage capacitor Cst11 stores the voltage between the first gate electrode G11 of the driving transistor M11 and power line 241. The source region of the driving transistor M11 is connected to power line 241, and its source potential is the positive power supply potential PVDD.

[0143] The storage capacitor element Cst11, together with the gate capacitor of the first gate electrode G11, maintains the gate voltage of the first gate electrode G11. The gate voltage of the first gate electrode G11 depends on the value of the first data signal Vdata1 transmitted by the first data line 201. Depending on the design, the storage capacitor element Cst11 can be removed.

[0144] The storage capacitor element Cst12 is connected between the power supply line 241, which is used to transmit the positive power supply potential PVDD, and the second gate electrode G12 of the driving transistor M11. The storage capacitor element Cst12 stores the voltage between the second gate electrode G12 of the driving transistor M11 and the power supply line 241.

[0145] The storage capacitor element Cst12, together with the gate capacitor of the second gate electrode G12, maintains the gate voltage of the second gate electrode G12. The gate voltage of the second gate electrode G12 depends on the value of the second data signal Vdata2 transmitted by the second data line 202. In one embodiment of this specification, the capacitance and area of ​​the storage capacitor element Cst12 are smaller than those of the storage capacitor element Cst11. This configuration facilitates the implementation of the pixel circuit while enabling proper control of the driving transistor M11. Depending on the design, the storage capacitor element Cst12 can be removed.

[0146] One of the source / drain regions of transistor M2 is connected to the node between the first gate electrode G11 and the first storage capacitor element Cst11, and the other (drain or source region) is connected to the data line 201 for transmitting the first data signal Vdata1. When transistor M2 is turned on, transistor M2 supplies the first data signal Vdata1 from driver IC 134 through data line 201 to the first gate electrode G11 and the first storage capacitor element Cst11.

[0147] One of the source / drain regions of transistor M4 is connected to the node between the second gate electrode G12 and the second storage capacitor element Cst12, and the other is connected to the data line 202 for transmitting the second data signal Vdata2. When transistor M4 is turned on, transistor M4 supplies the second data signal Vdata2 from driver IC 134 through data line 202 to the second gate electrode G12 and the second storage capacitor element Cst12.

[0148] exist Figure 15 In this example, the anode of OLED element E1 is connected to the drain region of driving transistor M11. One of the source / drain regions of transistor M3 is connected to power line 242 for transmitting the reset potential Vrst, and the other is connected to the drain region of driving transistor M11 and the anode of OLED element E1. When transistor M3 is turned on by the selection signal S3 from scan circuit 131, it supplies the reset potential Vrst transmitted by power line 242 to the drain region of driving transistor M11 and the anode of OLED element E1.

[0149] Used for control Figure 15 The timing diagram of the pixel circuit signals in the diagram can be compared with... Figure 4 The timing diagrams provided are the same.

[0150] Next, we will describe another configuration example of the pixel circuit. Figure 16 This shows yet another example of a pixel circuit configuration. Figure 16 The pixel circuitry receives the first data signal Vdata1 and the second data signal Vdata2 via a common data line. This configuration achieves a smaller number of data lines. The following mainly describes the relationship with... Figure 2 The differences in pixel circuits.

[0151] The gate electrode of transistor M4 is connected to transmission line 211 for transmitting the selection signal S1, and transistor M4 is turned on / off by the selection signal S1. The selection signal S1 can be supplied from a scan circuit (not shown). Transmission line 211 is different from transmission line 212 for selection signal S2 and transmission line 213 for selection signal S3. Common data line 205 transmits the first data signal Vdata1 and the second data signal Vdata2 in a time-division manner. One of the source / drain regions of transistor M2 and one of the source / drain regions of transistor M4 are connected to common data line 205. (The last sentence appears to be incomplete and possibly refers to a separate process.) Figure 2 The storage capacitor element Cst2 is shown in the figure.

[0152] Figure 17 It is used for driving Figure 16 The timing diagram of the pixel circuit is shown. Specifically, Figure 17 The time variations of selection signals S1, S2, and S3, and data signals Vdata1 and Vdata2, for the (n-1)th pixel circuit row, the nth pixel circuit row, and the (n+1)th pixel circuit row are shown. Selection signals of the same type for two adjacent pixel circuit rows are phase-shifted by 2H.

[0153] The control of the pixel circuit in the nth pixel circuit row is described by way of example. At time T20, the selection signal S3(n) changes from low to high. In response, transistor M3 turns on. Selection signals S1(n) and S2(n) remain low; transistors M2 and M4 remain off.

[0154] At time T21, which is 1 hour later than time T20, the selection signal S1(n) changes from low to high. The selection signal S3(n) remains high, while the selection signal S2(n) remains low. In response to the change in the selection signal S1(n), transistor M4 turns on. The second data signal Vdata2 is written to the pixel circuit through transistor M4.

[0155] At time T22, which is 1 hour later than time T21, selection signal S1(n) changes from high to low, and selection signal S2(n) changes from low to high. Selection signal S3(n) remains high. In response to the change in selection signal S1(n), transistor M4 is turned off. In response to the change in selection information S2(n), transistor M2 is turned on. The first data signal Vdata1 is written to the pixel circuit through transistor M2.

[0156] At time T23, which is 1 hour later than time T22, the selection signal S2(n) changes from high to low. The selection signal S1(n) remains low, and the selection signal S3(n) remains high. In response to the change in the selection signal S2(n), transistor M2 is turned off.

[0157] At time T24, which is 1 hour later than time T23, selection signal S3(n) changes from high to low. Selection signals S1(n) and S2(n) remain low. In response to the change in selection signal S3(n), transistor M3 is turned off. The light-emitting period of the nth pixel circuit row begins at time T24.

[0158] Figure 18 It is a schematic illustration of how it is viewed in the stacking direction. Figure 16 The pixel circuit shown is a planar diagram of its planar structure. Figure 6 In the example of pixel circuits, the same elements are represented by the same reference numerals, even though they have different shapes. Figure 18 Including replacement Figure 6 The common data line 205 of the data lines 201 and 202 in the middle, and also includes transmission lines 211B and 211T for selecting signal S1.

[0159] One of the source / drain regions of transistor M2 is connected to the common data line 205 via contact region CONT5. One of the source / drain regions of transistor M4 is connected to the common data line 205 via contact region CONT6.

[0160] Transmission lines 211T and 211B transmit the selection signal S1. A portion of transmission line 211T corresponds to the top gate electrode of transistor M4, and a portion of transmission line 211B corresponds to the bottom gate electrode of transistor M4. Transmission line 211B is included in a first metal layer, and transmission line 211T is included in a second metal layer.

[0161] Figure 19 An example of the relationship between the first data signal Vdata1 and the second data signal Vdata2 is shown. The horizontal axis of the graph represents the first data signal Vdata1, and the vertical axis represents the second data signal Vdata2. Figure 19 In the example, the function representing the relationship between the first data signal Vdata1 and the second data signal Vdata2 consists of two consecutive linear functions. Specifically, these two linear functions are represented by line 471 in the low grayscale region and by line 472 in the high grayscale region.

[0162] The relationship represented by line 471 is Vdata2 = V0 + η0 * Vdata1 (η0 < 0). The relationship represented by line 472 is Vdata2 = V0 + η1 * Vdata1 (η1 > 0). In the relationship represented by line 471, Vdata2 decreases linearly as Vdata1 increases. In the relationship represented by line 472, Vdata2 increases linearly as Vdata1 increases.

[0163] exist Figure 19 In the example, in the low grayscale range used to display images on OLED elements, or in the range where Vdata1 ranges from 0V to 4V, Vdata2 varies in polarity opposite to Vdata1. This configuration provides a large potential (voltage) difference between adjacent grayscale levels in the low grayscale range, which helps with light emission control in the low grayscale range and effectively reduces non-uniformity in the display. In the high grayscale range, Vdata2 varies with the same polarity as Vdata1. This configuration prevents a reduction in maximum brightness. It can be understood from this description that... Figure 19 The example of the relationship in the data expands the range of data to mitigate brightness variations only in low grayscale areas, while preventing a decrease in maximum brightness.

[0164] Figure 20 It is shown Figure 19 The graph shows the effect of the relationship between the first and second data signals. The horizontal axis represents the first data signal Vdata1, and the vertical axis represents the current I_oled supplied to the OLED element. When the current I_oled is large, the brightness of the OLED element is high. Curve 481 indicates that... Figure 19 The relationship between the first data signal Vdata1 and the second data signal Vdata2, and the relationship between the first data signal Vdata1 and the current I_oled. Figure 19 The first and second data signals in the data can extend the data range only within the low grayscale range.

[0165] The data signal in High Dynamic Range (HDR) mode is described below. HDR mode selectively increases the brightness of bright pixels without altering the brightness of dark pixels to extend the dynamic range of the displayed image. When displaying an image with large brightness differences in standard mode, adjusting the bright areas of the image for comfortable viewing can cause the dark areas to become distorted, while adjusting the dark areas for comfortable viewing can cause the bright areas to become washed out. HDR mode achieves comfortable display without sacrificing either the dark or bright areas. The control circuitry, including the driver IC 134, selects one mode from multiple modes for each pixel based on instructions from an external system. Mode selection can be performed for the entire display area. Three or more modes can be defined, and the relationship between the first data signal and the second data signal can differ between these modes.

[0166] As described above, the driving method in one embodiment of this specification determines a combination of a first data signal Vdata1 and a second data signal Vdata2 individually for each pixel to provide pixel-specific voltage-luminance characteristics. This means that the driving method is applicable to HDR driving (HDR mode). An example of HDR driving is described below.

[0167] Figure 21 An example illustrating the relationship between gray levels and the first data signal Vdata1 is shown. Figure 21 In the example, the first data signal Vdata1 increases linearly with increasing gray level. This relationship can be common to both standard and HDR modes. In other words, the relationship between video data (and thus the gray level) and the first data signal can be common to all modes.

[0168] Figure 22 An example of the relationship between the second data signal Vdata2 and the first data signal Vdata1 is shown in a display using a standard gamma value of 2.2 without HDR driving. The first data signal Vdata1 is also referred to as the grayscale voltage, and the second data signal Vdata2 is also referred to as the control voltage. As described above, the first data signal Vdata1 is determined based on the grayscale level of the pixels determined from the video data. The second data signal (control voltage) Vdata2 is determined based on the first data signal (grayscale voltage) Vdata1 according to a predetermined function.

[0169] exist Figure 22 In the example, the rate of increase of the control voltage Vdata2 is essentially constant (linearly changing) above a specific gray level voltage. Below that specific gray level voltage, the control voltage Vdata2 increases linearly with the increase of the gray level voltage Vdata1, and its rate of change is higher than that in the high gray level voltage range.

[0170] Figure 23 An example of the relationship between the control voltage Vdata2 and the grayscale voltage Vdata1 in HDR mode is shown. Within the range of 2V to 4V for the grayscale voltage Vdata1, the control voltage Vdata2 decreases and changes in the opposite polarity (direction) to the grayscale voltage Vdata1. In the high grayscale voltage range, including the highest grayscale voltage and above 4V for Vdata1, Vdata2 increases in a superlinear manner as Vdata1 increases. (Superlinearity is above linearity, and superlinearity means that it ultimately grows faster than any linear function.) Figure 22 Compared to the standard mode shown, the difference between the highest and lowest values ​​of the control voltage Vdata2 is larger.

[0171] Figure 24 Example 491 illustrates the relationship between grayscale voltage Vdata1 and illumination current I_oled (brightness) in HDR mode, and example 492 illustrates the relationship between grayscale voltage Vdata1 and illumination current I_oled (brightness) in standard mode. In HDR mode, the maximum brightness is higher compared to standard mode, and the rate of change of illumination current relative to grayscale voltage Vdata1 is smoother. This smoother change in illumination current reduces noticeable display non-uniformity in the low to medium brightness range and achieves high maximum brightness. As described above, the display mode is defined by the different relationships between the first data signal and the second data signal, and the different relationships between the first data signal and the brightness level of the light-emitting element.

[0172] The first data signal Vdata1 and the second data signal Vdata2 are coordinated differently, and switching is performed according to the pixel. Figure 22 and Figure 23 The characteristics of this feature allow each pixel to have different voltage-luminance characteristics (modes). For example, in an image that is generally dark but has very bright areas (such as a picture of fireworks in a night scene), the dynamic range of the displayed image can be expanded by increasing the brightness of the bright pixels without changing the brightness of the dark pixels; a more realistic image can be displayed.

[0173] The following describes a configuration example using micro-LED chips (elements) instead of OLED elements as the light-emitting element. A micro-LED chip is an element that incorporates inorganic compound semiconductors as the light-emitting material. Compared to OLED elements, micro-LED chips are highly reliable and exhibit minimal reduction in luminous efficiency even when driven to emit light at high intensity for extended periods. Therefore, they are advantageous for electroluminescent display devices with a wide dynamic range. The aforementioned control of the light-emitting element via first and second data signals is applicable to micro-LED display devices employing micro-LED chips as the light-emitting element.

[0174] Figure 25 An example configuration of a micro LED pixel circuit is shown. The main description is related to... Figure 9 The difference lies in the pixel circuitry. This micro LED pixel circuitry includes replacing... Figure 9 The OLED element E1 in the pixel circuit has an LED chip L1. The LED chip L1 is connected to the pixel circuit via pads 247 and 248. Pad 247 connects the anode of the LED chip L1 to the connection nodes of capacitor elements C1 and C2 and transistor M1.

[0175] Pad 248 connects the cathode of LED chip L1 to the cathode line CA used to transmit the cathode power potential PVEE. Similar to the other configuration examples described above, the data line used to transmit the first data signal and the data line used to transmit the second data signal can be the same data line or different data lines. In the case of a common data line, the first and second data signals are transmitted in a time-division multiplexing manner.

[0176] Figure 26 This is a plan view schematically illustrating an example of the structure of a micro LED pixel circuit. Figure 27 It is along Figure 26 A cross-sectional view of section line Y-Y' in [the image / data]. Figure 26 In this configuration, transmission lines S31 and S32 are used to transmit the selection signal S3. Transmission lines S21 and S22 are used to transmit the selection signal S2. The cathode line CA is disposed on the TFT substrate. The TFT substrate and the LED chip L1 are electrically connected through pads 247 and 248 disposed on the TFT substrate.

[0177] Reference Figure 27 Contact area CONT7 interconnects the source / drain regions and conductive regions of the connecting electrode CT, transistors M1 and M3. Contact area CONT8 interconnects pad 247 and the connecting electrode CT. Contact area CONT9 interconnects pad 248 and the cathode line CA.

[0178] LED chip L1 includes an anode AE, a cathode CE, and a light-emitting layer E5 covering the anode AE ​​and cathode CE. The anode AE ​​and cathode CE are physically and electrically connected to pads 247 and 248, respectively, via solder SOL.

[0179] The cathode line CA is positioned between the insulating substrate SUB of the TFT substrate and the LED chip L1. The LED chip L1 is electrically connected to the pixel circuit via pads 247 and 248. A patterned anisotropic conductive film (ACF) or soldering can be used for this connection. Gap spaces without pads are filled with resin filler.

[0180] Figure 28 This is a perspective view schematically showing the display area of ​​the micro LED display device. Red LED chip 601R, green LED chip 601G, and blue LED chip 601B are arranged in a matrix on the TFT substrate 605. Figure 28 It also includes a data or power line 611 and a transmission line 612. For illustration, pads 247 and 248 exposed when the LED chip is removed are shown. Figure 29 It is along Figure 28The cross-sectional view is shown along section line A-A'. The area between LED chips 601R, 601G, and 601B mounted on the TFT substrate 605 is filled with a separator material 603. The separator material 603 is a black material such as black resin to reduce surface reflectivity.

[0181] Figure 30 An example of a data driver is shown. An example of controlling grayscale characteristics by supplying the same grayscale voltage Vdata1 to all pixels and supplying different control voltages Vdata2 to each pixel is described here. The calculation unit 651 determines whether to apply standard or HDR characteristics on a pixel-by-pixel basis based on the display mode control signal, and consults a predefined conversion table TBL with grayscale data D1 to generate control data D2.

[0182] Different conversion tables (TBLs) are provided for each display mode, and each conversion table specifies the relationship between grayscale data D1 and control data D2. The conversion tables (TBLs) are defined numerically. Figure 22 or Figure 23 The functional relationship is shown in the figure.

[0183] The first DA converter 401 is supplied with a maximum potential Vmax1 and a minimum potential Vmin1 for D / A conversion. The second DA converter 402 is supplied with a maximum potential Vmax2 and a minimum potential Vmin2. The first DA converter 401 outputs a grayscale voltage Vdata1 based on the input grayscale data D1. The second DA converter 402 outputs a control voltage Vdata2 based on the input control data D2.

[0184] By combining a TFT substrate employing the driving method according to the embodiments of this specification with highly reliable micro-LEDs, an electroluminescent display device with a wide dynamic brightness range is obtained. Furthermore, this combination allows the displayed image to encompass areas with different grayscale characteristics, such as... Figure 31 The standard mode display area 701 and the HDR mode display area 702 are shown in the diagram.

[0185] As described above, embodiments of the present invention have been presented; however, the present invention is not limited to the foregoing embodiments. Those skilled in the art can readily modify, add to, or transform each element in the foregoing embodiments within the scope of the present invention. A portion of the configuration of one embodiment may be replaced with the configuration of another embodiment, or the configuration of one embodiment may be incorporated into the configuration of another embodiment.

Claims

1. A display device, comprising: Display panel; as well as A control circuit, configured to control the display panel. The display panel includes: Multiple light-emitting elements and multiple pixel circuits, each pixel circuit being configured to control the light emission of the light-emitting elements; A first data line is used to supply a first data signal to the plurality of pixel circuits; A second data line, the second data line being used to supply a second data signal to the plurality of pixel circuits; and Scan lines, which are used to control the plurality of pixel circuits. Each pixel circuit is connected to one or more scan lines and includes: A driving transistor, the driving transistor including a first gate electrode facing the semiconductor layer through a first gate insulating layer and a second gate electrode facing the semiconductor layer through a second gate insulating layer, the driving transistor being configured to control the driving current to be supplied to the light-emitting element; A first switching transistor, connected to a first data line and a first gate electrode, is controlled to be turned on or off according to a scan signal supplied to the scan line; and A second switching transistor, connected to a second data line and a second gate electrode, is controlled to turn on or off according to a scan signal supplied to the scan line. The control circuit is configured as follows: When the first switching transistor is turned on, a first data signal is supplied to the first gate electrode through the first data line, and then the first switching transistor is turned off. When the second switching transistor is turned on, a second data signal is supplied to the second gate electrode through the second data line, and then the second switching transistor is turned off. Controlling the supply of the first data signal and the second data signal to each pixel circuit such that the voltage of the second data signal varies with the voltage of the first data signal according to a predetermined relationship between the first data signal and the second data signal; and The first data signal and the second data signal are controlled such that, for at least a portion of the grayscale range of the light-emitting element from the lowest grayscale level to the highest grayscale level, the voltage of the second data signal changes in the opposite direction to the change in the voltage of the first data signal, wherein the portion of the grayscale range includes the lowest grayscale level.

2. The display device according to claim 1, in, The driving transistor is an n-type thin-film transistor, and Each pixel circuit also includes: A first capacitor element is connected between the first gate electrode and the source region of the driving transistor; and A second capacitor element is connected between the second gate electrode of the driving transistor and the source region.

3. The display device according to claim 2, wherein, The driving transistor is an oxide semiconductor thin-film transistor.

4. The display device according to claim 2, wherein, Each pixel circuit also includes a third capacitor element connected between the first gate electrode and the drain region of the driving transistor.

5. The display device according to claim 4, wherein, Each pixel circuit also includes a fourth capacitor element connected between the second gate electrode of the driving transistor and the drain region.

6. The display device according to claim 5, wherein, The capacitance of the fourth capacitor element is less than the capacitance of the third capacitor element.

7. The display device according to claim 1, wherein, The control circuit is configured to generate the second data signal based on the first data signal and the display mode control signal.

8. The display device according to claim 1, wherein, The light-emitting element is an inorganic LED or an organic LED.

9. A display device, comprising: Display panel; as well as A control circuit, configured to control the display panel. The display panel includes: Multiple light-emitting elements and multiple pixel circuits, each pixel circuit being configured to control the light emission of the light-emitting elements; Data lines, the data lines being used to supply first data signals and second data signals to the plurality of pixel circuits; and A first scan line and a second scan line, which are used to control the plurality of pixel circuits. Each pixel circuit includes: A driving transistor, the driving transistor including a first gate electrode facing the semiconductor layer through a first gate insulating layer and a second gate electrode facing the semiconductor layer through a second gate insulating layer, the driving transistor being configured to control the driving current to be supplied to the light-emitting element; A first switching transistor, connected to a data line and a first gate electrode, is controlled to be turned on or off according to a first scan signal supplied to a first scan line; and A second switching transistor, connected to the data line and the second gate electrode, is controlled to turn on or off according to a second scan signal supplied to the second scan line. The control circuit is configured as follows: When the first switching transistor is turned on, a first data signal is supplied to the first gate electrode through the data line, and then the first switching transistor is turned off. When the second switching transistor is turned on, a second data signal is supplied to the second gate electrode through the data line, and then the second switching transistor is turned off. Controlling the supply of the first data signal and the second data signal to each pixel circuit such that the voltage of the second data signal varies with the voltage of the first data signal according to a predetermined relationship between the first data signal and the second data signal; and The first data signal and the second data signal are controlled such that, for at least a portion of the grayscale range of the light-emitting element from the lowest grayscale level to the highest grayscale level, the voltage of the second data signal changes in the opposite direction to the change in the voltage of the first data signal, wherein the portion of the grayscale range includes the lowest grayscale level.

10. The display device according to claim 9, in, The driving transistor is an n-type thin-film transistor, and Each pixel circuit also includes: A first capacitor element is connected between the first gate electrode and the source region of the driving transistor; and A second capacitor element is connected between the second gate electrode of the driving transistor and the source region.

11. The display device according to claim 10, wherein, The driving transistor is an oxide semiconductor thin-film transistor.

12. The display device according to claim 10, wherein, Each pixel circuit also includes a third capacitor element connected between the first gate electrode and the drain region of the driving transistor.

13. The display device according to claim 12, wherein, Each pixel circuit also includes a fourth capacitor element connected between the second gate electrode of the driving transistor and the drain region.

14. The display device according to claim 13, wherein, The capacitance of the fourth capacitor element is less than the capacitance of the third capacitor element.

15. The display device according to claim 9, wherein, The control circuit is configured to generate the second data signal based on the first data signal and the display mode control signal.

16. The display device according to claim 9, wherein, The light-emitting element is an inorganic LED or an organic LED.

17. A display device, comprising: Display panel; as well as A control circuit, configured to control the display panel. The display panel includes multiple light-emitting elements and multiple pixel circuits, each pixel circuit being configured to control the light emission of the light-emitting elements. Each pixel circuit includes a driving transistor configured to control the driving current supplied to the light-emitting element. The driving transistor includes a first gate electrode facing the semiconductor layer through a first gate insulating layer and a second gate electrode facing the semiconductor layer through a second gate insulating layer. The driving transistor is configured to control the driving current to be supplied to the light-emitting element while supplying a first data signal to the first gate electrode based on grayscale data and supplying a second data signal to the second gate electrode based on control data generated from the grayscale data. The control circuit is configured to control each pixel circuit using a display mode selected from multiple display modes. The plurality of display modes are defined by the different relationships between the first data signal and the second data signal, and by the different relationships between the first data signal and the brightness level of the light-emitting element. The control circuit is configured to control the first data signal and the second data signal to generate a drive current for each pixel circuit.

18. The display device according to claim 17, wherein, The relationship between the video data and the first data signal is common to all of the multiple display modes.

19. The display device according to claim 17 or 18, wherein, In at least a portion of the grayscale range of the light-emitting element, from the lowest grayscale level to the highest grayscale level, the voltage of the second data signal changes in the opposite direction to the change in the voltage of the first data signal, and the portion of the grayscale range includes the lowest grayscale level.

20. The display device according to claim 17 or 18, wherein, In at least a portion of the grayscale range of the light-emitting element, from the lowest grayscale level to the highest grayscale level, the voltage of the second data signal varies in a superlinear manner relative to the voltage of the first data signal, the portion of the grayscale range including the highest grayscale level.

21. The display device according to claim 17, wherein, The control circuit is configured to generate the second data signal based on the first data signal and the display mode control signal.

22. The display device according to claim 17, wherein, The light-emitting element is an inorganic LED or an organic LED.

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