Data driver and LED device comprising the same

Abstract

A data driver and an LED device including the same are provided. The data driver includes a white data voltage output circuit having a first A channel for outputting a first white data voltage and a first B channel for outputting a second white data voltage different from the first white data voltage, and red, green, and blue data voltage output circuits for outputting red, green, and blue data voltages, respectively, wherein one of the first A channel and the first B channel operates in a first driving condition, and the first A channel and the first B channel operate together in a second driving condition.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2022-0064016, filed on May 25, 2022, which is incorporated herein by reference as if fully set forth herein. Technical Field

[0003] This disclosure relates to data drivers and light-emitting display (LED) devices including such data drivers. Background Technology

[0004] With the development of information technology, the market for display devices, which serve as a medium connecting users and information, is growing. As a result, display devices such as LEDs, quantum dot displays (QDDs), and liquid crystal displays (LCDs) are being used more and more frequently.

[0005] Each of the aforementioned display devices includes: a display panel comprising sub-pixels, a driver that outputs drive signals for driving the display panel, and a power supply that generates power to be supplied to the display panel or the driver.

[0006] In such a display device, when the subpixels formed in the display panel are supplied with driving signals such as scanning signals and data signals, a selected subpixel can display an image by transmitting light or by directly emitting light. Summary of the Invention

[0007] Therefore, this disclosure relates to data drives and display devices including such data drives, which substantially eliminate one or more problems caused by the limitations and disadvantages of the prior art.

[0008] One objective of this disclosure is to express various image data signal formats (RGB / YCbCr 4:4:4 / YCbCr 4:2:2 / YCbCr4:2:0) while selectively driving the display panel using either a 120Hz or 240Hz drive frequency without requiring a new design or alteration to the display panel. Another objective of this disclosure is to minimize the increase in the chip size of the data driver by minimizing the increase in the number of circuits required when selectively driving the display panel using either a 120Hz or 240Hz drive frequency.

[0009] Other advantages, objects, and features of this disclosure will be set forth in part in the description which follows, and will become apparent in part to those skilled in the art upon examination of the following, or may be learned from practice of this disclosure. The objects and other advantages of this disclosure may be realized and obtained by means of the structures particularly pointed out in its written description and claims and the accompanying drawings.

[0010] To achieve these and other advantages and for the purposes of this disclosure, as embodied and broadly described herein, a data driver includes: a white data voltage output circuit having a first channel A for outputting a first white data voltage and a second channel B for outputting a second white data voltage different from the first white data voltage; and a red data voltage output circuit, a green data voltage output circuit, and a blue data voltage output circuit, respectively, for outputting red data voltage, green data voltage, and blue data voltage, wherein one of the first channel A and the second channel B operates under a first driving condition, and the first channel A and the second channel B operate simultaneously under a second driving condition.

[0011] The first driving condition can be a first frequency, and the second driving condition can be a second frequency higher than the first frequency.

[0012] The white data voltage output circuit may include: a first A latch and a first B latch, the first A latch being configured to sample a first white data signal, and the first B latch being configured to sample a second white data signal; a second A latch and a second B latch, the second A latch being configured to hold the first white data signal output from the first A latch, and the second B latch being configured to hold the second white data signal output from the first B latch; a third A converter and a third B converter, the third A converter being configured to convert the first white data signal output from the second A latch into a first... The system includes a first white data voltage and a second white data voltage. The first white data voltage is amplified by a second converter B, which is configured to convert the second white data signal output from the second latch B into a second white data voltage. The system also includes an A amplifier and a B amplifier, where the A amplifier is configured to amplify the first white data voltage output from the A converter and the B amplifier is configured to amplify the second white data voltage output from the B converter. The system further includes an A switch and a B switch, where the A switch is configured to output the first white data voltage output from the A amplifier via an output terminal and the B switch is configured to output the second white data voltage output from the B amplifier via an output terminal.

[0013] The white data voltage output circuit may include: a first A latch and a first B latch, the first A latch being configured to sample a first white data signal, and the first B latch being configured to sample a second white data signal; a second A latch and a second B latch, the second A latch being configured to hold the first white data signal output from the first A latch, and the second B latch being configured to hold the second white data signal output from the first B latch; a first A switch and a second B switch, the first A switch being configured to transmit the first white data signal output from the second A latch to a converter, and the second B switch being configured to transmit the second white data signal output from the second B latch to the converter; a converter being configured to convert the first white data signal transmitted from the first A switch into a first white data voltage or to convert the second white data signal transmitted from the second B switch into a second white data voltage; an amplifier being configured to amplify the first white data voltage or the second white data voltage output from the converter; and a switch being configured to output the first white data voltage or the second white data voltage output from the amplifier through an output terminal.

[0014] Under the first driving condition, one of switches A and B can be turned on, and under the second driving condition, both switches A and B can be turned on.

[0015] In another aspect of this disclosure, a light-emitting display (LED) device includes: a display panel configured to display an image; and a data driver connected to a data line of the display panel, wherein the data driver includes: a white data voltage output circuit having a first A channel for outputting a first white data voltage and a second B channel for outputting a second white data voltage different from the first white data voltage; and a red data voltage output circuit, a green data voltage output circuit, and a blue data voltage output circuit for outputting red data voltage, green data voltage, and blue data voltage, respectively, and wherein one of the A channel and the B channel operates under a first driving condition, and the A channel and the B channel operate simultaneously under a second driving condition.

[0016] The first driving condition can be a first frequency, and the second driving condition can be a second frequency higher than the first frequency.

[0017] The white data voltage output circuit may include: a first A latch and a first B latch, the first A latch being configured to sample a first white data signal, and the first B latch being configured to sample a second white data signal; a second A latch and a second B latch, the second A latch being configured to hold the first white data signal output from the first A latch, and the second B latch being configured to hold the second white data signal output from the first B latch; a third A converter and a third B converter, the third A converter being configured to convert the first white data signal output from the second A latch into a first... The system includes a first white data voltage and a second white data voltage. The first white data voltage is amplified by a second converter B, which is configured to convert the second white data signal output from the second latch B into a second white data voltage. The system also includes an A amplifier and a B amplifier, where the A amplifier is configured to amplify the first white data voltage output from the A converter and the B amplifier is configured to amplify the second white data voltage output from the B converter. The system further includes an A switch and a B switch, where the A switch is configured to output the first white data voltage output from the A amplifier via an output terminal and the B switch is configured to output the second white data voltage output from the B amplifier via an output terminal.

[0018] The white data voltage output circuit may include: a first A latch and a first B latch, the first A latch being configured to sample a first white data signal, and the first B latch being configured to sample a second white data signal; a second A latch and a second B latch, the second A latch being configured to hold the first white data signal output from the first A latch, and the second B latch being configured to hold the second white data signal output from the first B latch; a first A switch and a second B switch, the first A switch being configured to transmit the first white data signal output from the second A latch to a converter, and the second B switch being configured to transmit the second white data signal output from the second B latch to the converter; a converter being configured to convert the first white data signal transmitted from the first A switch into a first white data voltage or to convert the second white data signal transmitted from the second B switch into a second white data voltage; an amplifier being configured to amplify the first white data voltage or the second white data voltage output from the converter; and a switch being configured to output the first white data voltage or the second white data voltage output from the amplifier through an output terminal.

[0019] Under the first driving condition, one of switches A and B can be turned on, and under the second driving condition, both switches A and B can be turned on.

[0020] When the data driver operates under the first driving condition, it can output red data voltage, green data voltage, and blue data voltage together with one of the first white data voltage and the second white data voltage.

[0021] When the data driver operates under the second driving condition, it can output a first white data voltage, a second white data voltage, a red data voltage, a green data voltage, and a blue data voltage.

[0022] When the data driver operates under the second driving condition, it can alternately control channel A and channel B.

[0023] When the display panel is operating under the second driving condition, it can store the first white data voltage and the second white data voltage one line at a time, and it can store the red data voltage, green data voltage and blue data voltage two lines at a time.

[0024] It should be understood that the foregoing general description and the following detailed description of this disclosure are exemplary and illustrative, and are intended to provide further explanation of the claimed disclosure. Attached Figure Description

[0025] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the disclosure and, together with the specification, serve to explain the principles of the disclosure. In the drawings:

[0026] Figure 1 It is a block diagram schematically showing the configuration of the LED device, and Figure 2 yes Figure 1 A schematic diagram of the sub-pixel configuration is shown in the figure;

[0027] Figure 3 and Figure 4 This is a diagram illustrating the configuration of a gate-in-panel (GIP) type scan driver, and Figure 5 This is a diagram showing an example layout of a GIP-type scan driver;

[0028] Figure 6 and Figure 7 It is a diagram used to describe the pixels and pixel layout examples set on the display panel;

[0029] Figure 8 This is an example diagram showing a sub-pixel with compensation circuitry, and Figure 9 This is an example diagram showing a sub-pixel with compensation circuitry and a data driver for driving the sub-pixel;

[0030] Figure 10 It is a graph used to illustrate the difference between the shape of a data signal and the corresponding amount of data, and Figure 11 It is a diagram used to describe the driving conditions for each type of input data signal;

[0031] Figure 12This is a diagram showing the display panel of an LED device according to a first embodiment of the present disclosure, and Figure 13 This is a diagram illustrating a data driver for an LED device according to a first embodiment of the present disclosure;

[0032] Figure 14 This is a driving waveform diagram used to describe the operation and result output of the first switching group included in the data driver when driving an LED device at a driving frequency of 120Hz, according to a first embodiment of the present disclosure. Figure 15 It is a drive waveform diagram used to describe the operation and result output of the first switch group included in the data driver when driving an LED device at a drive frequency of 240Hz, according to a first embodiment of the present disclosure.

[0033] Figure 16 This is a diagram illustrating a data driver for an LED device according to a second embodiment of this disclosure; and

[0034] Figure 17 This is a drive waveform diagram used to describe the operation and result output of the first and second switch groups included in the data driver when driven at a drive frequency of 120Hz according to the second embodiment of this disclosure. Figure 18 It is a drive waveform diagram used to describe the operation of the first and second switch groups included in the data driver and the resulting output when driven at a drive frequency of 240Hz according to the second embodiment of the present disclosure. Detailed Implementation

[0035] Reference will now be made in detail to preferred embodiments of the present disclosure, examples of which are shown in the accompanying drawings. Where possible, the same reference numerals will be used throughout the drawings to refer to the same or similar parts.

[0036] The display device according to this disclosure can be implemented as a television, video player, personal computer (PC), home theater, automotive electrical system, or smartphone, but is not limited thereto. The display device according to this disclosure can be implemented as an LED, QDD, or LCD. For ease of description, a direct-emitting LED device based on inorganic or organic light-emitting diodes will be used hereinafter as an example of a display device according to this disclosure.

[0037] Figure 1 It is a block diagram schematically showing the configuration of the LED device, and Figure 2 yes Figure 1 The diagram shows a schematic configuration of the sub-pixels.

[0038] like Figure 1 and Figure 2As shown, the LED device may include an image supplier 110, a timing controller 120, a scan driver 130, a data driver 140, a display panel 150, and a power supply 180.

[0039] The image supply unit (unit or main system) 110 can output various drive signals together with externally supplied image data signals or image data signals stored in the internal memory. The image supply unit 110 can supply data signals and various drive signals to the timing controller 120.

[0040] The timing controller 120 can output a gate timing control signal GDC for controlling the operating timing of the scan driver 130, a data timing control signal DDC for controlling the operating timing of the data driver 140, and various synchronization signals (vertical synchronization signal Vsync and horizontal synchronization signal Hsync). The timing controller 120 can supply the data signal DATA supplied from the image supply 110 together with the data timing control signal DDC to the data driver 140. The timing controller 120 can be in the form of an integrated circuit (IC) and mounted on a printed circuit board, but is not limited thereto.

[0041] The scan driver 130 can output a scan signal (or scan voltage) in response to the gate timing control signal GDC supplied from the timing controller 120. The scan driver 130 can supply scan signals to the sub-pixels included in the display panel 150 through scan lines SL1 to SLm. The scan driver 130 can be in the form of an IC, or it can be directly formed on the display panel 150 in a GIP manner, but is not limited thereto.

[0042] The data driver 140 can sample and latch the data signal DATA in response to the data timing control signal DDC supplied from the timing controller 120, convert the resulting digital data signal into an analog data voltage based on a gamma reference voltage, and output the converted analog data voltage. The data driver 140 can supply the data voltage to the sub-pixels included in the display panel 150 via data lines DL1 to DLn. The data driver 140 can be in the form of an IC and mounted on the display panel 150 or mounted on a printed circuit board, but is not limited thereto.

[0043] Power supply 180 can generate a first power with a high potential and a second power with a low potential based on an externally supplied external input voltage, and output the generated first power and second power through a first power line EVDD and a second power line EVSS, respectively. Power supply 180 can generate and output the voltage required to drive scan driver 130 (e.g., scan voltage including scan high voltage and scan low voltage) or the voltage required to drive data driver 140 (e.g., drain voltage including drain voltage and half-drain voltage), as well as the first power and the second power.

[0044] The display panel 150 can display an image in response to a drive signal including a scan signal and a data voltage, a first power supply, and a second power supply. The sub-pixels of the display panel 150 emit light directly. The display panel 150 can be manufactured based on a rigid or flexible substrate such as glass, silicon, or polyimide. The emitting sub-pixels can include red, green, and blue pixels, or can include red, green, blue, and white pixels.

[0045] For example, a sub-pixel SP can be connected to a first data line DL1, a first scan line GL1, a first power line EVDD, and a second power line EVSS, and can include a pixel circuit composed of a switching transistor, a driving transistor, a capacitor, an organic light-emitting diode, etc. The sub-pixel SP used in LED devices emits light directly and therefore has a complex circuit configuration. Furthermore, various compensation circuits exist to compensate for the degradation of not only the emitting organic light-emitting diode but also the degradation of the driving transistor that supplies the driving current required to drive the organic light-emitting diode. In this regard, it should be noted that the sub-pixel SP is simply shown in block form.

[0046] Meanwhile, the timing controller 120, scan driver 130, data driver 140, etc., have been described as having separate configurations. However, depending on the implementation method of the LED device, one or more of the timing controller 120, scan driver 130, and data driver 140 can be integrated into a single IC.

[0047] Figure 3 and Figure 4 This is a diagram used to describe the configuration of a GIP-type scan driver, and Figure 5 This is a diagram showing an example layout of a GIP-type scan driver.

[0048] like Figure 3As shown, a GIP-type scan driver may include a shift register 131 and a level shifter 135. The level shifter 135 can generate a drive clock signal Clk and a start signal Vst based on a signal output from a timing controller 120 and a voltage output from a power supply 180. The drive clock signal Clk can be generated in the form of J different phases (where J is an integer greater than or equal to 2), such as two phases, four phases, and eight phases.

[0049] The shift register 131 can operate based on the signals Clk and Vst output from the level converter 135, and output scan signals Scan[1] to Scan[m] that can turn on or off the transistors formed on the display panel. The shift register 131 can be formed on the display panel in a GIP manner and in the form of a thin film.

[0050] like Figure 3 and Figure 4 As shown, unlike shift register 131, level shifter 135 can be a standalone IC or can be included in power supply 180. However, this is merely an example, and level shifter 135 is not limited thereto.

[0051] like Figure 5 As shown, in a GIP-type scan driver, shift registers 131a and 131b for outputting scan signals can be located in the non-display area NA of the display panel 150. An example is given where shift registers 131a and 131b are located in the non-display areas NA on the left and right sides. However, shift registers 131a and 131b can also be located in the non-display areas NA on the upper and lower sides of the display panel 150, and can also be located in the display area AA of the display panel 150.

[0052] Figure 6 and Figure 7 It is a diagram used to describe the pixels and pixel layout examples set on the display panel.

[0053] like Figure 6 As shown, the LED device can display images based on a display panel 150 comprising pixels arranged in a matrix. A pixel disposed on the display panel 150 may include a white sub-pixel SPw, a red sub-pixel SPr, a green sub-pixel SPg, and a blue sub-pixel SPb.

[0054] like Figure 7 As shown in (a) to (d), according to the implementation method of the display panel, the layout order of the white sub-pixel SPw, red sub-pixel SPr, green sub-pixel SPg and blue sub-pixel SPb in a pixel PIX can be varied based on the horizontal direction.

[0055] Figure 8 This is an example diagram showing a sub-pixel with compensation circuitry, and Figure 9 This is an example diagram showing a sub-pixel with compensation circuitry and a data driver for driving the sub-pixel.

[0056] like Figure 8 As shown, a sub-pixel SP may include a switching transistor TR, a driving transistor DT, a sensing transistor ST, a capacitor CST, and an organic light-emitting diode OLED.

[0057] The driving transistor DT may have a gate electrode connected to a first electrode of the capacitor CST, a first electrode connected to a first power line EVDD, and a second electrode connected to an anode electrode of the organic light-emitting diode OLED. The capacitor CST may have a first electrode connected to the gate electrode of the driving transistor DT and a second electrode connected to the anode electrode of the organic light-emitting diode OLED. The organic light-emitting diode OLED may have an anode electrode connected to the second electrode of the driving transistor DT and a cathode electrode connected to a second power line EVSS.

[0058] The switching transistor TR may have a gate electrode connected to the first scan line SL1, a first electrode connected to the first data line DL1, and a second electrode connected to the gate electrode of the driving transistor DT. The sensing transistor ST may have a gate electrode connected to the first scan line SL1, a first electrode connected to the first reference line REF1, and a second electrode connected to the anode electrode of the organic light-emitting diode OLED. The switching transistor TR and the sensing transistor ST may be simultaneously turned on in response to a first scan signal applied through the first scan line SL1.

[0059] The sensing transistor ST is an additional compensation circuit provided to compensate for the degradation of the driving transistor DT or the organic light-emitting diode (OLED) (in terms of threshold voltage, etc.). The sensing transistor ST can initiate physical threshold voltage sensing based on the source follower operation of the driving transistor DT. The sensing transistor ST can obtain the sensed value by operating at a sensing node defined between the driving transistor DT and the OLED.

[0060] like Figure 9 As shown, multiple pixels can be set in the display area of ​​the display panel 150. A pixel P may include a white subpixel SPW, a red subpixel SPR, a green subpixel SPG, and a blue subpixel SPB.

[0061] The white sub-pixel SPW, red sub-pixel SPR, green sub-pixel SPG, and blue sub-pixel SPB can be individually connected to the first data line DL1, the second data line DL2, the third data line DL3, and the fourth data line DL4, respectively. However, the white sub-pixel SPW, red sub-pixel SPR, green sub-pixel SPG, and blue sub-pixel SPB can be collectively connected to the first reference line REF1 to share the first reference line REF1. That is, the total of four sub-pixels SPW, SPR, SPG, and SPB included in a pixel PIX can have a structure where they are connected to the panel sensing circuit SEN of the data driver 140 via a first reference line REF1.

[0062] The data driver 140 can be connected to the display panel 150. The panel sensing circuit SEN of the data driver 140 can acquire sensing values ​​from at least one of the white sub-pixel SPW, red sub-pixel SPR, green sub-pixel SPG, and blue sub-pixel SPB via the first reference line REF1.

[0063] The panel driving circuit of the data driver 140 may include a white data voltage output unit DV1[W], a red data voltage output unit DV2[R], a green data voltage output unit DV3[G], and a blue data voltage output unit DV4[B]. The white data voltage output unit DV1[W], the red data voltage output unit DV2[R], the green data voltage output unit DV3[G], and the blue data voltage output unit DV4[B] can output data voltages during the data writing period of the display panel 150.

[0064] The white data voltage output unit DV1[W] supplies white data voltage to the white sub-pixel SPW connected to the first data line DL1. The red data voltage output unit DV2[R] supplies red data voltage to the red sub-pixel SPR connected to the second data line DL2. The green data voltage output unit DV3[G] supplies green data voltage to the green sub-pixel SPG connected to the third data line DL3. The blue data voltage output unit DV4[B] supplies blue data voltage to the blue sub-pixel SPB connected to the fourth data line DL4.

[0065] Figure 10 It is a graph showing the difference between the shape of the data signal and the corresponding amount of data, and Figure 11 It is a graph describing the driving conditions for each type of input data signal.

[0066] like Figure 10As shown, the data signal used to display an image can include a luminance component (Y (luminance)) and a chrominance component (Cb and Cr (chrominance)). Thus, the data signal YCbCr of the original image produced through video production can be in a 4:4:4 format.

[0067] However, in broadcast and video media, to reduce data transmission capacity, a portion can be omitted from the original image's data signal YCbCr to obtain a 4:2:0 format, which can then be transmitted. This method of reducing only the chromaticity components (Cb and Cr (chromaticity)) while maintaining the luminance component (Y (luminance)) is called chromaticity subsampling.

[0068] Figure 10 This is an example of a chroma subsampling method, where the ratio of luminance (Y), color 1 (Cb), and color 2 (Cr) included in the original image's data signal YCbCr is compressed from a 4:4:4 format to a 4:2:0 (or 4:2:2) format. (See example in...) Figure 10 As can be seen, although the data volume of the YCbCr data signal in the 4:4:4 format is 100%, by downsampling it to the 4:2:0 format, the data volume of the YCbCr data signal can be reduced to 50%. In this way, since the data processing capability can be reduced by downsampling the image, both the image transmitting side and the image receiving side can have many advantages in terms of signal processing.

[0069] like Figure 11 As shown, the data signal can be applied to the image supplier 110 at a resolution of 4K, a drive frequency of 120Hz, and 10 data bits in a 4:4:4 format, or at a resolution of 4K, a drive frequency of 240Hz, and 10 data bits in a 4:2:0 format.

[0070] Furthermore, as can be seen from examining the data signals supplied from the image supplier 110 to the timing controller 120, both the 4:4:4 and 4:2:0 formats can have 12 data bits. In this case, the timing controller 120 can recognize the 4:4:4 format as a standard image and the 4:2:0 format as a custom image.

[0071] Thus, display devices such as LED devices can employ selective driving methods to express images based on a data signal in a 4:4:4 format driven at a driving frequency of 120 Hz, or based on a data signal in a 4:2:0 format driven at a driving frequency of 240 Hz.

[0072] Thus, since the data signal can be applied at a driving frequency of 120Hz in a 4:4:4 ratio or at a driving frequency of 240Hz in a 4:2:0 ratio, it is preferable to implement an LED device that allows for selective driving methods to be used based on the characteristics of the input data signal.

[0073] However, in order to employ a selective driving method based on the characteristics of the data signal, some improvements are needed, which are proposed below. However, for ease of description, the reference... Figure 8 and Figure 9 The subpixel-based display panel 150 described will be used as an example.

[0074] Figure 12 This is a diagram showing the display panel of an LED device according to a first embodiment of the present disclosure, and Figure 13 This is a diagram illustrating a data driver for an LED device according to a first embodiment of the present disclosure.

[0075] like Figure 12 As shown, the display panel 150 according to the first embodiment can be implemented based on a white sub-pixel SPW, a red sub-pixel SPR, a green sub-pixel SPG, and a blue sub-pixel SPB. The white sub-pixel SPW, red sub-pixel SPR, green sub-pixel SPG, and blue sub-pixel SPB can be respectively connected to first data lines DL1 to eighth data lines DL8, etc., arranged in the vertical direction. The white sub-pixel SPW, red sub-pixel SPR, green sub-pixel SPG, and blue sub-pixel SPB can be respectively connected to first scan line SL1, second scan line SL2, etc., arranged in the horizontal direction.

[0076] The white subpixel SPW, red subpixel SPR, green subpixel SPG, and blue subpixel SPB can be connected to the first power line EVDD, which is set in the vertical and horizontal directions. These four subpixels can also be connected to the first reference line REF1, the second reference line REF2, etc., so that all four subpixels are connected to each line. For example, a first pixel individually connected to the first data line DL1 through the fourth data line DL4 can be collectively connected to the first reference line REF1, while a second pixel individually connected to the fifth data line DL5 through the eighth data line DL8 can be collectively connected to the second reference line REF2.

[0077] The data driver 140 may include a first white data voltage output unit DV1[W], a first red data voltage output unit DV2[R], a first panel sensing circuit unit SEN1, a first green data voltage output unit DV3[G], a first blue data voltage output unit DV4[B], a second white data voltage output unit DV5[W], a second red data voltage output unit DV6[R], a second panel sensing circuit unit SEN2, a second green data voltage output unit DV7[G], a second blue data voltage output unit DV8[B], etc.

[0078] like Figure 13 As shown, the data driver 140 according to the first embodiment may include a shift register SR, a first data latch LAT1, a second data latch LAT2, a DA converter DAC, a voltage amplifier AMP, a switch group SWG1, etc.

[0079] The shift register SR can be used to control the operation of at least one of the first latch LAT1 or the second latch LAT2 based on the horizontal synchronization signal and the horizontal clock signal supplied from the timing controller.

[0080] The first data latch LAT1 can be used to configure a line of data signals by sampling the data signals supplied from the timing controller. The first data latch LAT1 is used to sample the data signals and can therefore be defined as a sampling latch. The first data latch LAT1 includes a plurality of first latches, and among the first latches, the first latch that samples a data signal of a specific color (e.g., a white data signal) can be divided into a first A latch LAT1a and a first B latch LAT1b.

[0081] The second data latch LAT2 can be used to hold the data signal transmitted from the first data latch LAT1 and transmit the data signal to the DA converter DAC. The second data latch LAT2 is used to hold the data signal and can therefore be defined as a holding latch. The second data latch LAT2 includes multiple second latches, and among the second latches, the second latch that holds a data signal of a specific color (e.g., a white data signal) can be divided into a second A latch LAT2a and a second B latch LAT2b.

[0082] The DC converter DAC can be used to convert digital data signals transmitted from the second data latch LAT2 into analog data voltages and output the analog data voltages. The DC converter DAC can be combined with a gamma unit set internally or externally to convert digital data signals into analog data voltages. The DC converter DAC includes multiple converters, and among the converters, the converter that converts data signals of a specific color (e.g., white data signals) can be divided into converter A DAC1a and converter B DAC1b.

[0083] A voltage amplifier AMP can be used to amplify and output the data voltage transmitted from a DA converter DAC. A voltage amplifier AMP comprises multiple amplifiers, and within the amplifiers, the amplifier that amplifies a data signal of a specific color (e.g., a white data signal) can be divided into amplifier A AMPa and amplifier B AMPb.

[0084] The switch group SWG1 can be used to output white, red, green, and blue data voltages from the voltage amplifier AMP by connecting to the output terminals of data lines DL1 to DL8. The switch group SWG1 includes multiple switches, and among the switches, the switch that outputs a specific color data voltage (e.g., white data voltage) can be designated as switch A SWa and switch B SWb.

[0085] According to the first embodiment, the data driver 140 may include two channels in a white data voltage output circuit for driving white sub-pixels. A first A latch LAT1a, a second A latch LAT2a, an A converter DAC1a, an A amplifier AMPa, and an A switch SWa may define the A channel, while a first B latch LAT1b, a second B latch LAT2b, a B converter DAC1b, a B amplifier AMPb, and a B switch SWb may define the B channel.

[0086] Channel A can output a first white data voltage, and channel B can output a second white data voltage. Furthermore, the first and second white data voltages can have different gradients. Channels A and B can operate selectively based on the driving frequency (driving conditions) used to drive the LED device, as will be described below.

[0087] Figure 14 This is a driving waveform diagram used to describe the operation and result output of the first switching group included in the data driver when driving an LED device at a driving frequency of 120Hz, according to a first embodiment of the present disclosure. Figure 15It is a drive waveform diagram used to describe the operation and result output of the first switch group included in the data driver when driving an LED device at a drive frequency of 240Hz, according to a first embodiment of the present disclosure.

[0088] like Figure 13 and Figure 14 As shown, when the LED device is driven at a driving frequency of 120Hz as the first frequency, scan signals SCAN[n] to SCAN[n+3] can be output to sequentially generate high voltages. Referring to scan signals SCAN[n] to SCAN[n+3], the number of times high voltages are generated by the previously generated scan signal (e.g., SCAN[n]) and the subsequent scan signal to be generated (e.g., SCAN[n+1]) may partially overlap with each other.

[0089] The data enable signal DE can be generated during the vertical synchronization signal period, which can be divided into a vertical blanking period (when no valid signal is output) and a valid data period (when a valid signal is output). For reference, Figure 14 The data enable signal DE shown represents the state that occurs during the valid data period.

[0090] During the valid data period of the data enable signal DE, the source output enable signal SOE can be generated within a unit time of 1H. Furthermore, the second data latch LAT2 of the data driver 140 can output a data signal based on the source output enable signal SOE.

[0091] Meanwhile, when the LED device is driven at a driving frequency of 120Hz, the scan signals SCAN[n] to SCAN[n+3] can maintain a high voltage for a time of 2H (=7.4μs), and the data enable signal DE and the source output enable signal SOE can be generated every 1H (=3.7μs). However, this disclosure is not limited thereto.

[0092] According to the first driving condition of the first embodiment, in the switch group SWG1, the switch SW for outputting red data voltage, green data voltage and blue data voltage [R / G / B] and the Ath switch SWA for outputting the first white data voltage [Wa] can be turned on at the same time every 1H in response to the Ath switch signal and the switch signal SWA&SW.

[0093] On the other hand, in switch group SWG1, switch B SWb, which is used to output the second white data voltage [Wb], can remain off in response to switch B signal SWb. Meanwhile, in Figure 14 Since the Ath switch signal SWA and the switch signal SW are generated in the same form, it should be noted that these signals are shown and described together.

[0094] The A-th switch signal and the switch signals SWA&SW can be generated with a phase opposite to that of the source output enable signal SOE. For example, when the source output enable signal SOE is generated high, the A-th switch signal and the switch signals SWA&SW can be generated low, and when the source output enable signal SOE is generated low, the A-th switch signal and the switch signals SWA&SW can be generated high.

[0095] When switch A, SWA, and switch SW operate under the conditions described above, data driver 140 can output the first white data voltage, red data voltage, green data voltage, and blue data voltage [Wa / R / G / B] through the output terminal OUTPUT for each row (e.g., [n-2], [n-1], and [n] to [n+3]).

[0096] Referring to the above description, when driving the LED device at a driving frequency of 120Hz, the data driver 140 can output a first white data voltage [Wa] by driving only the A channel (or output a second white data voltage [Wb] using only the B channel). The first white data voltage, red data voltage, green data voltage, and blue data voltage [Wa / R / G / B] output from the output terminal OUTPUT of the data driver 140 can be changed every 1H.

[0097] When the data driver 140 outputs a data voltage in the manner described above, the display panel can display images in response to all image data signal formats (RGB / YCbCr 4:4:4 / YCbCr 4:2:2 / YCbCr 4:2:0).

[0098] like Figure 13 and Figure 15 As shown, when the LED device is driven at a driving frequency of 240Hz as the second frequency, scan signals SCAN[n] to SCAN[n+3] can be output to sequentially generate high voltages. Referring to scan signals SCAN[n] to SCAN[n+3], the number of times high voltages are generated for previously generated scan signals (e.g., SCAN[n]) and subsequent scan signals (e.g., SCAN[n+1]) may partially overlap with each other.

[0099] The data enable signal DE can be generated during the vertical synchronization signal period, which can be divided into a vertical blanking period (when no valid signal is output) and a valid data period (when a valid signal is output). For reference, Figure 15 The data enable signal DE shown represents the state that occurs during the valid data period.

[0100] During the valid data period of the data enable signal DE, the source output enable signal SOE can be generated within a time unit of 1H. Furthermore, the second data latch LAT2 of the data driver 140 can output a data signal based on the source output enable signal SOE.

[0101] Meanwhile, when the LED device is driven at a driving frequency of 240Hz, the scan signals SCAN[n] to SCAN[n+3] can maintain a high voltage for a time of 2H (=3.7μs), the data enable signal DE can be generated every 2H (=3.7μs), and the source output enable signal SOE can be generated every 1H (=1.85μs). However, this disclosure is not limited thereto.

[0102] According to the second driving condition of the first embodiment, in the switch group SWG1, the switch SW used to output red data voltage, green data voltage, and blue data voltage [R / G / B] can be turned on every 2H in response to the switch signal SW. Furthermore, the A switch SWa used to output the first white data voltage [Wa] and the B switch SWb used to output the second white data voltage [Wb] can be turned on individually every 1H (alternating between them with a period of 1H). Therefore, when the A switch SWa is first generated high, the B switch SWb can be generated low, and when the A switch SWa is generated low for the second time, the B switch SWb can be generated high. Moreover, the periods when the A switch SWa and the B switch SWb are generated high can correspond to the periods when the source output enable signal SOE is generated low.

[0103] When switch A SWa, switch B SWb and switch SW operate under the above conditions, the data driver 140 can alternately output the first white data voltage and the second white data voltage [Wa / Wb] through the output terminal OUTPUT, and can continuously output the red data voltage, green data voltage and blue data voltage [R / G / B].

[0104] Referring to the above description, when driving the LED device at a driving frequency of 240Hz, the data driver 140 can alternately drive the A channel and the B channel (the two channels are driven together and alternately) at a time period of 1H to individually output the first white data voltage and the second white data voltage [Wa / Wb] to be supplied to the white sub-pixels of each row (e.g., [n-2], [n-1], and [n] to [n+8]). That is, the first white data voltage [Wa] and the second white data voltage [Wb] output from the output terminal OUTPUT of the data driver 140 can be changed every 1H (e.g., Wa is output to [n-2], and Wb is output to [n-1]). As a result, white data voltages of different gradients can be applied to white sub-pixels that are perpendicularly adjacent to each other. On the other hand, the red data voltage, green data voltage, and blue data voltage [R / G / B] output from the output terminal OUTPUT of the data driver 140 can be changed every 2H. As a result, red, green, and blue data voltages of the same gradient can be applied to red, green, and blue sub-pixels that are perpendicular to each other.

[0105] Meanwhile, when the red data voltage, green data voltage, and blue data voltage [R / G / B] change every 2H, and the first white data voltage [Wa] and the second white data voltage [Wb] change every 1H, the data transmission bandwidth can be increased (e.g., an increase of approximately 25% based on the EPI bandwidth) compared to the 120Hz driving condition.

[0106] When the data driver 140 outputs a data voltage in the manner described above, the display panel can express an image optimized for the chroma subsampling image data signal format (YCbCr 4:2:0).

[0107] In the following description, a second embodiment of the present disclosure will be presented. However, the description will primarily focus on configurations or methods that differ from the first embodiment. Therefore, the first embodiment applies to the parts not described in the second embodiment.

[0108] Figure 16 This is a diagram illustrating a data driver for an LED device according to a second embodiment of the present disclosure.

[0109] like Figure 16 As shown, the data driver 140 according to the second embodiment may include a shift register SR, a first data latch LAT1, a second data latch LAT2, a second switch group SWG2, a DA converter DAC, a voltage amplifier AMP, and the first switch group SWG1, etc.

[0110] The second switch group SWG2 can be used to selectively transmit a data signal of a specific color (e.g., a white data signal) output from the second data latch LAT2 to the DA converter DAC. The second switch group SWG2 includes a plurality of second switches, which can be divided into a first switch SWa connected to the second A latch LAT2a and a second switch SWb connected to the second B latch LAT2b.

[0111] The DC-DC converter (DAC) can be used to convert digital data signals transmitted from the second data latch (LAT2) and the second switch group (SWG2) into analog data voltages and output these analog data voltages. The DC-DC converter (DAC) can be combined with a gamma unit (providing a gamma reference voltage) configured internally or externally to the data driver (140) to convert digital data signals into analog data voltages. The DC-DC converter (DAC) may include multiple converters.

[0112] A voltage amplifier (AMP) can be used to amplify and output the data voltage transmitted from a DA converter (DAC). An AMP can comprise multiple amplifiers.

[0113] The first switch group SWG1 can be used to output white, red, green, and blue data voltages from the voltage amplifier AMP via the output terminals connected to data lines DL1 to DL8. The first switch group SWG1 may include multiple first switches.

[0114] According to the second embodiment, the data driver 140 may include two channels in the white data voltage output circuit for driving the white sub-pixel. The first A latch LAT1a, the second A latch LAT2a, and the A switch SWa may be defined as the A channel, while the first B latch LAT1b, the second B latch LAT2b, and the B switch SWb may be defined as the B channel.

[0115] Channel A can output a first white data voltage, and channel B can output a second white data voltage. Furthermore, the first and second white data voltages can have different gradients. Channels A and B can operate selectively based on the driving frequency (driving conditions) used to drive the LED device, as will be described below.

[0116] Figure 17 This is a drive waveform diagram used to describe the operation and result output of the first and second switch groups included in the data driver when driven at a drive frequency of 120Hz according to the second embodiment of this disclosure. Figure 18It is a drive waveform diagram used to describe the operation of the first and second switch groups included in the data driver and the resulting output when driven at a drive frequency of 240Hz according to the second embodiment of the present disclosure.

[0117] like Figure 16 and Figure 17 As shown, when the LED device is driven at a driving frequency of 120Hz as the first frequency, scan signals SCAN[n] to SCAN[n+3] can be output to sequentially generate high voltages. Referring to scan signals SCAN[n] to SCAN[n+3], the number of times high voltages are generated by the previously generated scan signal (e.g., SCAN[n]) and the subsequent scan signal to be generated (e.g., SCAN[n+1]) may partially overlap with each other.

[0118] The data enable signal DE can be generated during the vertical synchronization signal period, which can be divided into a vertical blanking period (when no valid signal is output) and a valid data period (when a valid signal is output). For reference, Figure 17 The data enable signal DE shown represents the state that occurs during the valid data period.

[0119] When the LED device is driven at a driving frequency of 120 Hz, the scan signals SCAN[n] to SCAN[n+3] can maintain a high voltage for a time of 2H (=7.4 μs), and the data enable signal DE and the source output enable signal SOE can be generated every 1H (=3.7 μs). However, this disclosure is not limited thereto.

[0120] According to the first driving condition of the second embodiment, in the second switch group SWG2, the A switch SWA for outputting the first white data signal can remain on in response to the A switch signal SWA being high. On the other hand, in the second switch group SWG2, the B switch SWb for outputting the second white data signal can remain off in response to the B switch signal SWb being low.

[0121] In the first switch group SWG1, the switch SW used to output the red, green, and blue data voltages [R / G / B] and the switch SW used to output the first white data voltage [Wa] can be turned on evenly every 1H in response to the switch signal SW. Meanwhile, in Figure 17 Since the switches SW used to output the first white data voltage, red data voltage, green data voltage, and blue data voltage [Wa / R / G / B] are generated in the same form, it should be noted that these signals are shown and described together.

[0122] The A-th switch signal and the switch signals SWA&SW can be generated with a phase opposite to that of the source output enable signal SOE. For example, when the source output enable signal SOE is generated high, the A-th switch signal and the switch signals SWA&SW can be generated low, and when the source output enable signal SOE is generated low, the A-th switch signal and the switch signals SWA&SW can be generated high.

[0123] When the A-th switch SWa and the B-th switch SWb operate under the above conditions, the data driver 140 can output the first white data voltage, red data voltage, green data voltage and blue data voltage [Wa / R / G / B] through the output terminal OUTPUT for each row (e.g. [n-2], [n-1] and [n] to [n+3]).

[0124] Referring to the above description, when driving the LED device at a driving frequency of 120Hz, the data driver 140 can output a first white data voltage [Wa] by driving only the A channel (or output a second white data voltage [Wb] using only the B channel). Here, the first white data voltage, red data voltage, green data voltage, and blue data voltage [Wa / R / G / B] output from the output terminal OUTPUT of the data driver 140 can be changed every 1H.

[0125] When the data driver 140 outputs a data voltage in the manner described above, the display panel can display images in response to all image data signal formats (RGB / YCbCr 4:4:4 / YCbCr 4:2:2 / YCbCr 4:2:0).

[0126] like Figure 16 and Figure 17 As shown, when the LED device is driven at a driving frequency of 240Hz as the second frequency, scan signals SCAN[n] to SCAN[n+3] can be output to sequentially generate high voltages. Referring to scan signals SCAN[n] to SCAN[n+3], the number of times high voltages are generated by the previously generated scan signal (e.g., SCAN[n]) and the subsequent scan signal to be generated (e.g., SCAN[n+1]) may partially overlap with each other.

[0127] The data enable signal DE can be generated during the vertical synchronization signal period, which can be divided into a vertical blanking period (when no valid signal is output) and a valid data period (when a valid signal is output). For reference, Figure 17 The data enable signal DE shown represents the state that occurs during the valid data period.

[0128] During the valid data period of the data enable signal DE, the source output enable signal SOE can be generated within a time unit of 1H. Furthermore, the second data latch LAT2 of the data driver 140 can output a data signal based on the source output enable signal SOE.

[0129] Meanwhile, when the LED device is driven at a driving frequency of 240Hz, the scan signals SCAN[n] to SCAN[n+3] can maintain a high voltage for a time of 2H (=3.7μs), the data enable signal DE can be generated every 2H (=3.7μs), and the source output enable signal SOE can be generated every 1H (=1.85μs). However, this disclosure is not limited thereto.

[0130] According to the second driving condition of the second embodiment, in the second switch group SWG2, the A switch SWA for outputting the first white data voltage and the B switch SWb for outputting the second white data voltage can be turned on individually every 2H (alternatingly turned on at a period of 2H). Therefore, when the A switch SWA is first generated high, the B switch SWb can be generated low, and when the A switch SWA is generated low a second time, the B switch SWb can be generated high. In other words, when the first white data voltage is applied to an odd-numbered row based on the scan line, the A switch SWA can be turned on, and when the second white data voltage is applied to an even-numbered row, the B switch SWb can be turned on (or conversely, when the first white data voltage is applied to an even-numbered row based on the scan line, the A switch SWA can be turned on, and when the second white data voltage is applied to an odd-numbered row, the B switch SWb can be turned on).

[0131] In the first switch group SWG1, the switch SW used to output the first white data voltage [Wa] or the second white data voltage [Wb] can be turned on individually every 2H (alternating between each for time 1H within the 2H period). For this purpose, the switching signal SW applied to the switch SW used to output the first white data voltage [Wa] or the second white data voltage [Wb] can be generated with a phase opposite to the source output enable signal SOE. In the first switch group SWG1, the switches SW used to output the red data voltage, green data voltage, and blue data voltage [R / G / B] can be turned on every 2H.

[0132] When switch A SWa, switch B SWb and switch SW operate under the above conditions, the data driver 140 can alternately output the first white data voltage and the second white data voltage [Wa / Wb] through the output terminal OUTPUT, and can continuously output the red data voltage, green data voltage and blue data voltage [R / G / B].

[0133] Referring to the above description, when driving the LED device at a driving frequency of 240Hz, the data driver 140 can alternately drive the A channel and the B channel (the two channels are driven together and alternately) at a time period of 1H to individually output the first white data voltage and the second white data voltage [Wa / Wb] to be supplied to the white sub-pixels of each row (e.g., [n-2], [n-1], and [n] to [n+8]). That is, the first white data voltage [Wa] and the second white data voltage [Wb] output from the output terminal OUTPUT of the data driver 140 can be changed every 1H (e.g., Wa is output to [n-2], and Wb is output to [n-1]). As a result, white data voltages of different gradients can be applied to white sub-pixels that are perpendicularly adjacent to each other. On the other hand, the red data voltage, green data voltage, and blue data voltage [R / G / B] output from the output terminal OUTPUT of the data driver 140 can be changed every 2H. As a result, red, green, and blue data voltages of the same gradient can be applied to red, green, and blue sub-pixels that are perpendicular to each other.

[0134] When the data driver 140 outputs a data voltage in the manner described above, the display panel can express an image optimized for the chroma subsampling image data signal format (YCbCr 4:2:0).

[0135] In the second embodiment, the second switch group SWG2 is disposed between the second data latch LAT2 and the DA converter DAC, and the switches are selectively driven according to the driving conditions. Therefore, the increase in the number of DA converters DAC and voltage amplifiers AMP required to drive the white sub-pixel can be minimized. That is, the increase in the chip size of the data driver 140 can be minimized.

[0136] As described above, this disclosure has the following advantages: it allows for the selective driving of a display panel using either a 120Hz or 240Hz driving frequency while simultaneously expressing various image data signal formats (RGB / YCbCr4:4:4 / YCbCr4:2:2 / YCbCr4:2:0) without requiring a new design or alteration to the display panel. Furthermore, this disclosure has the advantage of minimizing the increase in the number of circuits required when selectively driving the display panel using either a 120Hz or 240Hz driving frequency, thereby minimizing the increase in the chip size of the data driver.

[0137] It will be apparent to those skilled in the art that various modifications and variations can be made to this disclosure without departing from its spirit or scope. Therefore, this disclosure is intended to cover modifications and variations thereof, provided they fall within the scope of the appended claims and their equivalents.

Claims

1. A data driver, comprising: A white data voltage output circuit having a first channel A for outputting a first white data voltage and a second channel B for outputting a second white data voltage different from the first white data voltage; and Red data voltage output circuit, green data voltage output circuit, and blue data voltage output circuit are used to output red data voltage, green data voltage, and blue data voltage respectively. Specifically, under a first driving condition, one of the A-channels and the B-channels operates, and under a second driving condition, the A-channels and the B-channels operate together. in, The first driving condition is a first frequency; and the second driving condition is a second frequency higher than the first frequency.

2. The data driver according to claim 1, wherein, The white data voltage output circuit includes: A first latch and a first B latch, wherein the first A latch is configured to sample a first white data signal and the first B latch is configured to sample a second white data signal; A second A latch and a second B latch, wherein the second A latch is configured to hold the first white data signal output from the first A latch, and the second B latch is configured to hold the second white data signal output from the first B latch; A converter and B converter, wherein the A converter is configured to convert the first white data signal output from the second A latch into the first white data voltage, and the B converter is configured to convert the second white data signal output from the second B latch into the second white data voltage; Amplifier A and Amplifier B, wherein Amplifier A is configured to amplify the first white data voltage output from A converter A, and Amplifier B is configured to amplify the second white data voltage output from B converter B; and Switch A and switch B, wherein switch A is configured to output the first white data voltage output from amplifier A via an output terminal, and switch B is configured to output the second white data voltage output from amplifier B via the output terminal.

3. The data driver according to claim 2, wherein, Under the first driving condition, one of the A switches and the B switches is turned on, and under the second driving condition, both the A switches and the B switches are turned on.

4. The data driver according to claim 1, wherein, The white data voltage output circuit includes: A first latch and a first B latch, wherein the first A latch is configured to sample a first white data signal and the first B latch is configured to sample a second white data signal; A second A latch and a second B latch, wherein the second A latch is configured to hold the first white data signal output from the first A latch, and the second B latch is configured to hold the second white data signal output from the first B latch; Switch A and Switch B, wherein Switch A is configured to transmit the first white data signal output from the second A latch to the converter, and Switch B is configured to transmit the second white data signal output from the second B latch to the converter; The converter is configured to convert the first white data signal transmitted from the A switch into the first white data voltage, or to convert the second white data signal transmitted from the B switch into the second white data voltage. An amplifier configured to amplify either the first white data voltage or the second white data voltage output from the converter; and A switch configured to output either the first white data voltage or the second white data voltage from the amplifier via an output terminal.

5. The data driver according to claim 4, wherein, Under the first driving condition, one of the A switches and the B switches is turned on, and under the second driving condition, both the A switches and the B switches are turned on.

6. A light-emitting LED display device, comprising: Display panel, the display panel being configured to display images; as well as A data driver, which is connected to the data cable of the display panel, wherein: The data driver includes: A white data voltage output circuit having a first channel A for outputting a first white data voltage and a second channel B for outputting a second white data voltage different from the first white data voltage; and Red data voltage output circuit, green data voltage output circuit, and blue data voltage output circuit are used to output red data voltage, green data voltage, and blue data voltage respectively. Under a first driving condition, one of the A and B channels operates, and under a second driving condition, the A and B channels operate together. Wherein, the first driving condition is a first frequency, and the second driving condition is a second frequency higher than the first frequency.

7. The LED device according to claim 6, wherein, The white data voltage output circuit includes: A first latch and a first B latch, wherein the first A latch is configured to sample a first white data signal and the first B latch is configured to sample a second white data signal; A second A latch and a second B latch, wherein the second A latch is configured to hold the first white data signal output from the first A latch, and the second B latch is configured to hold the second white data signal output from the first B latch; A converter and B converter, wherein the A converter is configured to convert the first white data signal output from the second A latch into the first white data voltage, and the B converter is configured to convert the second white data signal output from the second B latch into the second white data voltage; Amplifier A and Amplifier B, wherein Amplifier A is configured to amplify the first white data voltage output from A converter A, and Amplifier B is configured to amplify the second white data voltage output from B converter B; and Switch A and switch B, wherein switch A is configured to output the first white data voltage output from amplifier A via an output terminal, and switch B is configured to output the second white data voltage output from amplifier B via the output terminal.

8. The LED device according to claim 7, wherein, Under the first driving condition, one of the A switches and the B switches is turned on, and under the second driving condition, the A switches and the B switches are turned on.

9. The LED device according to claim 6, wherein, The white data voltage output circuit includes: A first latch and a first B latch, wherein the first A latch is configured to sample a first white data signal and the first B latch is configured to sample a second white data signal; A second A latch and a second B latch, wherein the second A latch is configured to hold the first white data signal output from the first A latch, and the second B latch is configured to hold the second white data signal output from the first B latch; Switch A and Switch B, wherein Switch A is configured to transmit the first white data signal output from the second A latch to the converter, and Switch B is configured to transmit the second white data signal output from the second B latch to the converter; The converter is configured to convert the first white data signal transmitted from the A switch into the first white data voltage, or to convert the second white data signal transmitted from the B switch into the second white data voltage. An amplifier configured to amplify either the first white data voltage or the second white data voltage output from the converter; and A switch configured to output either the first white data voltage or the second white data voltage from the amplifier via an output terminal.

10. The LED device according to claim 9, wherein, Under the first driving condition, one of the A switches and the B switches is turned on, and under the second driving condition, both the A switches and the B switches are turned on.

11. The LED device according to claim 6, wherein, When the data driver operates under the first driving condition, it outputs the red data voltage, the green data voltage, and the blue data voltage, together with one of the first white data voltage and the second white data voltage.

12. The LED device according to claim 6, wherein, When the data driver operates under the second driving condition, it outputs the first white data voltage, the second white data voltage, the red data voltage, the green data voltage, and the blue data voltage.

13. The LED device according to claim 12, wherein, When the data driver operates under the second driving condition, it alternately controls the A channel and the B channel.

14. The LED device according to claim 12, wherein, When the display panel operates under the second driving condition, it stores the first white data voltage and the second white data voltage one line at a time, and stores the red data voltage, the green data voltage and the blue data voltage two lines at a time.

15. A light-emitting display device, comprising: A display panel, comprising white sub-pixels, red sub-pixels, green sub-pixels, and blue sub-pixels, wherein the white sub-pixels, red sub-pixels, green sub-pixels, and blue sub-pixels are respectively connected to one or more data lines arranged in the vertical direction and one or more scan lines arranged in the horizontal direction; and The data driver according to any one of claims 1 to 5 is connected to the data cable of the display panel.

Images