Storage device, electronic device including the same, and operating method thereof

Abstract

An electronic device including a storage device and an operating method thereof can be provided. The storage device can include a memory controller including a plurality of functions configured to be identified as a plurality of storage devices logically separated from each other by an external host, a resource manager configured to store characteristic values and resource values respectively corresponding to the plurality of functions, and a command processor configured to, when a command respectively corresponding to the plurality of functions is received from the external host, prioritize processing of a command corresponding to a first function having a lowest resource value among the plurality of functions based on the resource values, and update the resource value of the first function by accumulating the characteristic value of the first function in the resource value of the first function.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2022-0064263, filed on May 25, 2022, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The various embodiments of this disclosure generally relate to an electronic device, and more specifically to a storage device, an electronic device including the storage device, and a method of operating the same. Background Technology

[0004] A storage device is a device that stores data under the control of a host device such as a computer or smartphone. A storage device may include a memory device that stores the data therein and a memory controller that controls the memory device. Memory devices can be classified as volatile memory devices and non-volatile memory devices.

[0005] A volatile memory device is a memory device that stores data only when power is supplied and loses the data stored therein when the power supply is interrupted. Examples of volatile memory devices can include static random access memory (SRAM) and dynamic random access memory (DRAM).

[0006] Non-volatile memory devices are memory devices in which the data stored is retained even when the power supply is interrupted. Examples of non-volatile memory devices can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), and flash memory. Summary of the Invention

[0007] Various embodiments of this disclosure relate to a storage device for reducing command latency, an electronic device including the storage device, and a method of operating the same.

[0008] One embodiment of this disclosure may provide a memory controller. The memory controller may include: a plurality of functions configured to be identified by an external host as a plurality of logically separate storage devices; a resource manager configured to store feature values ​​and resource values ​​therein, both of which correspond to each of the plurality of functions; and a command processor configured to receive commands from the external host corresponding to the plurality of functions, prioritizing the processing of commands corresponding to a first function among the plurality of functions by referring to the resource values ​​corresponding to the plurality of functions; and updating the resource values ​​of the first function by adding the feature value of the first function to the resource values ​​of the first function.

[0009] One embodiment of this disclosure provides a method for operating a memory controller including multiple functions, which are identified by an external host as multiple storage devices that are logically separated from each other. The method may include: receiving commands from the external host corresponding to the multiple functions; prioritizing the processing of commands among the received commands that correspond to a first function having the lowest resource value among the multiple functions by referring to resource values ​​corresponding to the multiple functions; and updating the resource value of the first function by adding a feature value of the first function to the resource value of the first function.

[0010] One embodiment of this disclosure may provide a storage device. The storage device may include a memory device and a memory controller. The memory device includes a plurality of memory blocks, wherein the memory controller may include: a plurality of functions configured to be identified by an external host as a plurality of logically separate storage devices; a resource manager configured to store feature values ​​and resource values ​​therein, the feature values ​​and resource values ​​corresponding to each of the plurality of functions; and a command processor configured to prioritize, among commands corresponding to the plurality of functions and received from the external host, commands corresponding to the plurality of functions, a command corresponding to a first function having the lowest resource value, by referring to the resource values ​​corresponding to the plurality of functions, and to update the resource values ​​of the first function by adding the feature value of the first function to the resource values ​​of the first function. Attached Figure Description

[0011] Figure 1 This is a diagram illustrating a storage device according to an embodiment of the present disclosure.

[0012] Figure 2 The illustration shows an embodiment according to the present disclosure. Figure 1 A diagram of the memory controller.

[0013] Figure 3 This is a diagram illustrating a memory device according to an embodiment of the present disclosure.

[0014] Figure 4 This is a diagram illustrating the connection relationship between a functional controller and a memory device according to an embodiment of the present disclosure.

[0015] Figure 5 This is a diagram illustrating the operation of a memory controller according to an embodiment of the present disclosure.

[0016] Figure 6 The illustration shows an embodiment according to the present disclosure. Figure 5 A diagram illustrating the operation of the memory controller.

[0017] Figure 7This is an operation flowchart of a memory controller according to an embodiment of the present disclosure. Detailed Implementation

[0018] The specific structural or functional descriptions of the embodiments of this disclosure described herein are provided as examples to illustrate embodiments based on the concept of this disclosure. Embodiments based on the concept of this disclosure may be practiced in various forms and should not be construed as limited to the embodiments described herein.

[0019] Figure 1 This is a diagram illustrating a storage device 100 according to an embodiment of the present disclosure.

[0020] refer to Figure 1 Storage device 100 may include a memory controller 110 and a memory device 120. Storage device 100 may be a device that stores data under the control of an external host 101, such as a mobile phone, smartphone, MP3 player, laptop computer, desktop computer, game console, television (TV), tablet PC, or in-vehicle infotainment system. Alternatively, storage device 100 may be a device that stores data under the control of an external host 101, such as a server or data center where a large amount of data is stored in one location.

[0021] Storage device 100 can be manufactured as any of various types of storage devices depending on the host interface used for communication with external host 101. For example, storage device 100 can be implemented as any of various types of storage devices, such as solid-state drives (SSDs), multimedia cards (such as MMC, embedded MMC (eMMC), reduced-size MMC (RS-MMC), or micro-MMC), secure digital cards (such as SD, mini-SD, or micro-SD), universal storage bus (USB) storage devices, universal flash memory (UFS) devices, PCMCIA card-type storage devices, peripheral component interconnect (PCI) card-type storage devices, PCI rapid (PCI-E) card-type storage devices, compact flash (CF) cards, smart media cards, and memory sticks.

[0022] Storage device 100 can be manufactured in any of a variety of package types. For example, storage device 100 can be manufactured in any of a variety of package types, such as point-of-purchase (POP), system-in-package (SIP), system-on-a-chip (SOC), multi-chip package (MCP), chip-on-board (COB), wafer-level fabrication package (WFP), and wafer-level stacked package (WSP).

[0023] The memory device 120 can store data. The memory device 120 can operate under the control of the memory controller 110. The memory device 120 may include a memory cell array (not shown) comprising a plurality of memory cells for storing data.

[0024] Each memory cell can be implemented as a single-level cell (SLC) capable of storing one data bit, a multi-level cell (MLC) capable of storing two data bits, a three-level cell (TLC) capable of storing three data bits, or a four-level cell (QLC) capable of storing four data bits.

[0025] A memory cell array (not shown) may include multiple memory blocks. Each memory block may include multiple memory cells. Each memory block may include multiple pages. In one embodiment, a page may be a unit for storing data in the memory device 120 or a unit for reading data stored in the memory device 120. A memory block may be a unit for erasing data.

[0026] In one embodiment, the memory device 120 may take many alternative forms, such as Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate Generation 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR) SDRAM, Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, Vertical NAND flash memory, NOR flash memory, Resistive RAM (RRAM), Phase Change RAM (PRAM), Magnetoresistive RAM (MRAM), Ferroelectric RAM (FRAM), or Spin-Torque RAM (STT-RAM). For ease of explanation, this specification is based on the case where the memory device 120 is NAND flash memory.

[0027] Memory device 120 can receive commands and addresses from memory controller 110 and can access regions of the memory cell array selected by the addresses. Memory device 120 can perform operations instructed by commands on the regions selected by the addresses. For example, memory device 120 can perform write operations (i.e., programming operations), read operations, and erase operations. During a programming operation, memory device 120 can program data into the regions selected by the addresses. During a read operation, memory device 120 can read data from the regions selected by the addresses. During an erase operation, memory device 120 can erase data stored in the regions selected by the addresses.

[0028] The memory controller 110 can control the overall operation of the storage device 100.

[0029] When power is applied to storage device 100, memory controller 110 can run firmware (FW). When storage device 120 is a flash memory device, memory controller 110 can run firmware such as flash translation layer (FTL) to control communication between external host 101 and storage device 120.

[0030] In one embodiment, the memory controller 110 may receive data and logical block addresses (LBAs) from an external host 101 and may translate the logical block addresses (LBAs) into physical block addresses (PBAs) that indicate the addresses of memory cells included in the memory device 120 and in which data is to be stored.

[0031] The memory controller 110 can control the memory device 120 to perform programming, reading, or erasing operations in response to requests received from the external host 101. During a programming operation, the memory controller 110 can provide the memory device 120 with programming commands, physical block addresses, and data. During a reading operation, the memory controller 110 can provide the memory device 120 with reading commands and physical block addresses. During an erasing operation, the memory controller 110 can provide the memory device 120 with erasing commands and physical block addresses.

[0032] In one embodiment, memory controller 110 may internally generate commands, addresses, and data regardless of whether a request is received from external host 101, and may send them to memory device 120. For example, memory controller 110 may provide memory device 120 with the necessary commands, addresses, and data to perform programming operations, read operations, and erase operations involved in wear leveling, read recycling, garbage collection, etc.

[0033] In one embodiment, the memory controller 110 can control two or more memory devices 120. In this case, the memory controller 110 can control the memory devices 120 according to an interleaving scheme to improve operational performance. The interleaving scheme can be a scheme for controlling the memory devices 120 such that the operation of at least two memory devices 120 overlaps with each other.

[0034] External host 101 can communicate with storage device 100 using at least one of various communication standards or interfaces, such as Universal Serial Bus (USB), Serial AT Attachment (SATA), Serial Attached SCSI (SAS), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI High Speed ​​(PCIe), Non-Volatile Memory High Speed ​​(NVMe), Universal Flash Memory (UFS), Secure Digital Storage (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Low Load DIMM (LRDIMM) communication methods.

[0035] In this specification, although the storage device 100 and the external host 101 are described as communicating data via a UFS communication interface for ease of explanation, the embodiments of this disclosure are not limited to data communication via a UFS communication interface. Specifically, the storage device 100 and the external host 101 may perform data communication using commands defined as Protocol Information Units (hereinafter referred to as "PIUs"). A PIU may be a data packet generated according to predefined rules.

[0036] A PIU can be a command that allows an external host 101 or storage device 100 to request or instruct the execution of an operation, or a command in response to such a request or instruction. In one embodiment, various PIUs can be defined according to their use and purpose. For example, a PIU can be one of a query request PIU, a command PIU, a response PIU, a data output PIU, a data input PIU, and a prepare-to-transmit PIU.

[0037] In one embodiment, the query request PIU may include a device descriptor for providing various parameters of the storage device 100. The device descriptor may include information indicating whether the storage device 100 is a storage device 100 that supports Advanced Replay Protection Memory Block (RPMB) mode.

[0038] The minimum size of a PIU can be 32 bytes, and the maximum size can be 65,600 bytes. The format of a PIU can vary in size depending on its type.

[0039] The memory controller 110 may include a command processor 111 and a function controller 112. The command processor 111 may couple the external host 101 to the function controller 112 by performing communication with the external host 101. The function controller 112 may control at least one memory block included in the memory device 120 in response to commands received from the external host 101. The configuration and operation of the command processor 111 and the function controller 112 will be described below. Figure 2and Figure 5 Provide a detailed description.

[0040] Figure 2 The illustration shows an embodiment according to the present disclosure. Figure 1 A diagram of the memory controller 110.

[0041] refer to Figure 2 The memory controller 110 may include a command processor 111 and a function controller 112. The command processor 111 and the function controller 112 may be electrically connected to each other.

[0042] Command processor 111 may include resource manager 111-1, command queue 111-2, and scheduler 111-3. The hardware configuration included in command processor 111 is not limited to... Figure 2 As illustrated in the diagram. In one example, the resource manager 111-1 and the scheduler 111-3 can be integrated into a single module that manages resource values ​​and the execution order of commands. In one example, the scheduler 111-3 can be identified as a command queue manager.

[0043] In one example, the resource value can be the sum of the feature values ​​of a function. For instance, the resource value of a first function can be the value accumulated by the feature values ​​of the first function each time a command corresponding to the first function is processed.

[0044] The function controller 112 may include multiple functions, including a first function 112-1, a second function 112-2, a third function 112-3, ..., an nth function 112-n. In this disclosure, the term "function" may be a "physical function" or "PF". The multiple functions included in the function controller 112 may be identified by the external host 101 as multiple logically separate storage devices. That is, the multiple functions may be different storage devices relative to the external host 101.

[0045] Resource Manager 111-1 can store feature values ​​and resource values ​​corresponding to multiple functions 112-1 to 112-n respectively. In one example, the multiple functions 112-1 to 112-n can have different feature values. For example, the feature value of the first function 112-1 can be 50, the feature value of the second function 112-2 can be 100, and the feature value of the third function 112-3 can be 120.

[0046] In one example, the feature values ​​of multiple functions 112-1 to 112-n can be determined based on the average amount of data processed by functions 112-1 to 112-n respectively and the corresponding weights of functions 112-1 to 112-n. The corresponding weights of multiple functions 112-1 to 112-n can be based on data from an external host (e.g., Figure 1The type of command received by the external host 101 determines the command. In one example, commands received from the external host by multiple functions 112-1 to 112-n may include programming commands, read commands, or erase commands.

[0047] In one example, the memory controller 110 can adjust the occupancy percentage of multiple functions 112-1 to 112-n by adjusting the corresponding characteristic values ​​of multiple functions 112-1 to 112-n.

[0048] In one example, the resource values ​​of multiple functions 112-1 to 112-n can be stored on a storage device (e.g., Figure 1 The storage device 100 is initialized when it starts up. For example, when the storage device starts up with the resource value of the first function 112-1 being 250 and the resource value of the second function 112-2 being 300, the resource values ​​of the first function 112-1 and the second function 112-2 can be initialized to 0.

[0049] When command processor 111 is from an external host (e.g., Figure 1 When the external host 101 receives a command, the command queue 111-2 can store the commands sequentially according to the order in which the command processor 111 receives the commands. For example, when the command processor 111 sequentially receives programming commands, read commands, and read commands from the external host, the command queue 111-2 can store programming commands, read commands, and read commands sequentially.

[0050] External host 101 may include multiple hosts. In one example, multiple commands received from multiple hosts may be stored in command queue 111-2 in the order in which command processor 111 receives the commands. For example, when command processor 111 receives a first command from a first host and subsequently receives a second command from a second host, command queue 111-2 may store the first and second commands sequentially.

[0051] Scheduler 111-3 can determine whether to execute multiple commands stored in command queue 111-2. In one example, scheduler 111-3 can determine which function will execute the various commands stored in command queue 111-2 based on the characteristic values ​​and resource values ​​of multiple functions 112-1 to 112-n stored in resource manager 111-1. For example, scheduler 111-3 can determine, based on the characteristic values ​​and resource values ​​of multiple functions 112-1 to 112-n, which programming command should function 112-1 execute as the first command stored in command queue 111-2. See later. Figure 5 The detailed operation of scheduler 111-3 in determining the function of each command to be executed is described.

[0052] Figure 3This is a diagram illustrating a memory device 300 according to one embodiment of the present disclosure. Although indicated by another reference numeral for ease of illustration... Figure 3 The memory device 300, but it is understandable that the memory device 300 is related to... Figure 1 The same components as the memory device 120.

[0053] refer to Figure 3 The memory device 300 may include a memory cell array 310, a voltage generator 320, an address decoder 330, an input / output (I / O) circuit 340, and control logic 350.

[0054] The memory cell array 310 includes multiple memory blocks BLK1 to BLKi. The multiple memory blocks BLK1 to BLKi can be coupled to the address decoder 330 via row lines RL. The multiple memory blocks BLK1 to BLKi can be coupled to the input / output (I / O) circuitry 340 via column lines CL. In one embodiment, the row line RL may include word lines, source select lines, and drain select lines. In one embodiment, the column line CL may include bit lines.

[0055] Each of the memory blocks BLK1 to BLKi includes a plurality of memory cells. In one embodiment, the plurality of memory cells may be non-volatile memory cells. Among the plurality of memory cells, memory cells coupled to the same word line may be defined as a physical page. That is, the memory cell array 310 may include a plurality of physical pages. Each memory cell of the memory device 300 may be implemented as a single-level cell (SLC) capable of storing one data bit, a multi-level cell (MLC) capable of storing two data bits, a three-level cell (TLC) capable of storing three data bits, or a four-level cell (QLC) capable of storing four data bits.

[0056] In one embodiment, the voltage generator 320, address decoder 330, and I / O circuitry 340 can be designated as peripheral circuitry. This peripheral circuitry can drive the memory cell array 310 under the control of control logic 350. The peripheral circuitry can drive the memory cell array 310 to perform programming, reading, and erasing operations.

[0057] Voltage generator 320 can generate multiple operating voltages using the external power supply voltage provided to memory device 300. Voltage generator 320 can operate under the control of control logic 350.

[0058] In one embodiment, voltage generator 320 can generate an internal power supply voltage by adjusting an external power supply voltage. The internal power supply voltage generated by voltage generator 320 can be used as the operating voltage for memory device 300.

[0059] In one embodiment, voltage generator 320 can generate multiple operating voltages using an external power supply voltage or an internal power supply voltage. Voltage generator 320 can generate various voltages required by memory device 300. For example, voltage generator 320 can generate multiple erase voltages, multiple programming voltages, multiple pass voltages, multiple select read voltages, and multiple unselect read voltages.

[0060] The voltage generator 320 may include a plurality of pump capacitors for receiving an internal power supply voltage to generate a plurality of operating voltages having various voltage levels, and the plurality of operating voltages may be generated by selectively enabling the plurality of pump capacitors under the control of control logic 350.

[0061] The generated operating voltage can be supplied to the memory cell array 310 via the address decoder 330.

[0062] Address decoder 330 is coupled to memory cell array 310 via row lines RL. Address decoder 330 can operate under the control of control logic 350. Address decoder 330 can receive address ADDR from control logic 350. Address decoder 330 can decode the block address in the received address ADDR. Address decoder 330 can select at least one of memory blocks BLK1 to BLKi based on the decoded block address. Address decoder 330 can decode the row address in the received address ADDR. Address decoder 330 can select at least one word line of the selected memory block based on the decoded row address. In one embodiment, address decoder 330 can decode the column address in the received address ADDR. Address decoder 330 can couple I / O circuitry 340 to memory cell array 310 based on the decoded column address.

[0063] In one embodiment, address decoder 330 may include components such as row decoder, column decoder, and address buffer.

[0064] I / O circuitry 340 may include multiple page buffers. These page buffers can be coupled to memory cell array 310 via bit lines. During programming operations, data can be stored in selected memory cells based on data stored in the multiple page buffers.

[0065] During a read operation, data stored in the selected memory cell can be sensed via bit lines, and the sensed data can be stored in the page buffer.

[0066] Control logic 350 can control address decoder 330, voltage generator 320, and I / O circuit 340. Control logic 350 can operate in response to commands (CMD) transmitted from external devices. Control logic 350 can control peripheral circuits by generating control signals in response to commands (CMD) and addresses (ADDR).

[0067] Figure 4 This is a diagram illustrating the connection relationship between a function controller 112 and a memory device 120 according to an embodiment of the present disclosure.

[0068] refer to Figure 4 The multiple functions 112-1 to 112-n included in the function controller 112 can form different channels with the multiple memory blocks 120-1 to 120-n included in the memory device 120.

[0069] Multiple functions 112-1 to 112-n can form a one-to-one (1:1) correspondence with multiple memory blocks 120-1 to 120-n. That is, multiple functions 112-1 to 112-n can each control multiple memory blocks 120-1 to 120-n. For example, the first function 112-1 can form a first channel CH1 with the first memory block 120-1, the second function 112-2 can form a second channel CH2 with the second memory block 120-2, and the nth function 112-n can form an nth channel CHn with the nth memory block 120-n. Channels CH1 to CHn can refer to the interfaces or protocols required for communication between functions and memory blocks.

[0070] In one embodiment (not shown), multiple functions 112-1 to 112-n can form an n-to-one (n:1) correspondence with multiple memory blocks 120-1 to 120-n. That is, two or more of the multiple functions 112-1 to 112-n can control one of the multiple memory blocks 120-1 to 120-n.

[0071] Figure 5 This is a diagram illustrating the operation of a memory controller 110 according to an embodiment of the present disclosure.

[0072] refer to Figure 5 The scheduler 111-3 can base its work on information received from the resource manager 111-1 regarding commands and multiple functions (e.g., Figure 4 The function controller 112 uses information (e.g., characteristic values ​​and resource values) from multiple functions 112-1 to 112-n to control the function controller 112.

[0073] In one example, resource manager 111-1 can receive information about commands from command queue 111-2. This information may include details about the command currently to be output (or processed) among a plurality of commands stored sequentially in command queue 111-2. Whenever a command is executed, resource manager 111-1 can receive information about the corresponding command from command queue 111-2. In one example, resource manager 111-1 may receive information about commands from command queue 111-2 regardless of whether the commands have been executed.

[0074] Resource Manager 111-1 can store multiple functions (e.g., functions included in Function Controller 112) that correspond to the functions included in Function Controller 112. Figure 4 The characteristic and resource values ​​of multiple functions (112-1 to 112-n). In one example, multiple functions (e.g., Figure 4 The eigenvalues ​​of multiple functions (112-1 to 112-n) can be different from each other. Multiple functions (e.g., Figure 4 The resource values ​​of the multiple functions (112-1 to 112-n) can be updated as each command is executed.

[0075] Scheduler 111-3 can receive information about commands from resource manager 111-1 and information about multiple functions (e.g., Figure 4 Information on the characteristic values ​​and resource values ​​of multiple functions (112-1 to 112-n). Whenever a command is executed, the scheduler 111-3 can receive information about the command and information about the multiple functions (e.g., ...) from the resource manager 111-1. Figure 4 Information on the characteristic values ​​and resource values ​​of multiple functions (112-1 to 112-n). In one example, the scheduler 111-3 can receive information about commands from the resource manager 111-1 regardless of when the individual commands are executed, about the characteristics and resource values ​​corresponding to multiple functions (e.g., ...). Figure 4 Information on the characteristic values ​​and resource values ​​of multiple functions (112-1 to 112-n).

[0076] Scheduler 111-3 can be based on multiple functions (e.g., Figure 4 The resource values ​​of multiple functions (112-1 to 112-n) are prioritized for processing multiple functions (e.g., Figure 4 The command corresponding to the function with the lowest resource value among the multiple functions (112-1 to 112-n). For example, among multiple functions (e.g., Figure 4 If the third function 112-3 among the multiple functions 112-1 to 112-n has a resource value corresponding to the lowest value (e.g., 250), the command corresponding to the third function 112-3 (e.g., programming command) can be processed first.

[0077] In one example, when the resource values ​​corresponding to multiple functions 112-1 to 112-n are the same, the command corresponding to the function with the lowest characteristic value among the multiple functions 112-1 to 112-n can be processed first. In another example, when all multiple functions 112-1 to 112-n have a resource value of 0, the command corresponding to the function with the lowest characteristic value among the multiple functions 112-1 to 112-n can be processed first. In this way, the resources used by the multiple functions 112-1 to 112-n can be minimized.

[0078] Based on separate and multiple functions (e.g., Figure 4 The priority processing of multiple functions (112-1 to 112-n) is determined by the resource values ​​corresponding to those functions (e.g., Figure 4 In the event of a corresponding command among the multiple functions (112-1 to 112-n), the scheduler 111-3 can control the command queue 111-2 so that the command queue 111-2 outputs the corresponding command to the function controller 112. In one example, the command queue 111-2 can output a command to the function controller 112 under the control of the scheduler 111-3.

[0079] When a command corresponding to a function with the lowest resource value is processed first, resource manager 111-1 can update the resource value of the function by reflecting the characteristic value of the function with the lowest resource value in the resource value. In one example, if the function with the lowest resource value is the fifth function 112-5, and a command corresponding to the fifth function 112-5 is output to the memory device 120, resource manager 111-1 can update the resource values ​​corresponding to the plurality of functions 112-1 to 112-n respectively by reflecting the characteristic value of the fifth function 112-5 in the resource value of the fifth function 112-5.

[0080] Figure 6 The illustration shows an embodiment according to the present disclosure. Figure 5 A diagram illustrating the operation of the memory controller.

[0081] refer to Figure 6 The running function can be determined based on the processing commands corresponding to the resource values ​​of multiple functions 112-1 to 112-n, respectively. In the following description, we will use Table 610 related to the resource value of the first function, Table 620 related to the resource value of the second function, Table 630 related to the resource value of the third function, and Table 640 related to the running function. Although for ease of explanation... Figure 6The diagram only shows Table 610 related to the resource values ​​of the first function, Table 620 related to the resource values ​​of the second function, and Table 630 related to the resource values ​​of the third function, but this description can also be applied to the functions included in the multiple functions 112-1 to 112-n.

[0082] In one embodiment, when the resource values ​​of the first function, the second function, and the third function are all 0, the command corresponding to the function with the lowest characteristic value among the first to third functions can be processed first. For example, when the resource values ​​of the first function, the second function, and the third function are all 0, if the characteristic value x of the first function is 60, the characteristic value y of the second function is 100, and the characteristic value z of the third function is 150, the command corresponding to the first function can be processed first.

[0083] In one embodiment, when a command corresponding to the first function is processed first, the characteristic value x of the first function is reflected in the resource value of the first function, and therefore the resource value of the first function can be updated from 0 to x. The resource values ​​of the second and third functions can be maintained at 0.

[0084] In one embodiment, when the resource value of the first function is x, the resource value of the second function is 0, and the resource value of the third function is 0, the command corresponding to the function with the lower characteristic value between the second and third functions can be prioritized. For example, when the resource value of the first function is x, the resource value of the second function is 0, and the resource value of the third function is 0, if the characteristic value y of the second function is 100 and the characteristic value z of the third function is 150, the command corresponding to the second function can be prioritized.

[0085] In one embodiment, when the command corresponding to the second function is processed first, the characteristic value y of the second function is reflected in the resource value of the second function, and therefore the resource value of the second function can be updated from 0 to y. The resource values ​​of the first function and the third function can be maintained as x and 0, respectively.

[0086] In one embodiment, when the resource value of the first function is x, the resource value of the second function is y, and the resource value of the third function is 0, the command corresponding to the third function with the lowest resource value can be prioritized. In one example, when the resource value of the first function is 60, the resource value of the second function is 100, and the resource value of the third function is 0, the command corresponding to the third function can be prioritized.

[0087] In one embodiment, when the command corresponding to the third function is processed first, the characteristic value z of the third function is reflected in the resource value of the third function, and therefore the resource value of the third function can be updated from 0 to z. The resource values ​​of the first function and the second function can be maintained as x and y, respectively.

[0088] In one embodiment, when the resource value of the first function is x, the resource value of the second function is y, and the resource value of the third function is z, the command corresponding to the function with the lowest resource value among the first and third functions can be prioritized. In one example, when the resource value of the first function is 60, the resource value of the second function is 100, and the resource value of the third function is 150, the command corresponding to the first function with the lowest resource value among the first and third functions can be prioritized.

[0089] In one embodiment, when a command corresponding to the first function is processed first, the characteristic value x of the first function is reflected in the resource value of the first function, and therefore the resource value of the first function can be updated from x to 2x. The resource values ​​of the second and third functions can be maintained as y and z, respectively.

[0090] In one embodiment, when the resource value of the first function is 3x, the resource value of the second function is 2y, and the resource value of the third function is z, the command corresponding to the function with the lowest resource value among the first and third functions can be prioritized. In one example, when the resource value of the first function is 180, the resource value of the second function is 200, and the resource value of the third function is 150, the command corresponding to the third function with the lowest resource value among the first and third functions can be prioritized.

[0091] In one embodiment, when the command corresponding to the third function is processed first, the characteristic value z of the third function is reflected in the resource value of the third function, and therefore the resource value of the third function can be updated from z to 2z. The resource values ​​of the first and second functions can be maintained as 3x and 2y, respectively.

[0092] Figure 7 This is an operation flowchart of a memory controller 110 according to an embodiment of the present disclosure.

[0093] refer to Figure 7 The memory controller 110 can process commands based on function-related information (e.g., feature values ​​or resource values). Figure 7 The operation of the memory controller 110 shown in the figure can be referred to Figure 2 Let me describe it in detail.

[0094] In operation S701, the memory controller 110 can receive commands from the external host 101 corresponding to a plurality of functions 112-1 to 112-n. The commands corresponding to the plurality of functions 112-1 to 112-n may include programming commands, read commands, and erase commands.

[0095] In operation S703, the memory controller 110 can prioritize processing commands (e.g., programming commands) corresponding to the first function (e.g., 112-1) with the lowest resource value among the multiple functions 112-1 to 112-n, based on the resource values ​​corresponding to each of the multiple functions 112-1 to 112-n. In one example, when the resource values ​​corresponding to each of the multiple functions 112-1 to 112-n are the same, the command corresponding to the function with the lowest characteristic value among the multiple functions 112-1 to 112-n can be prioritized.

[0096] In operation S705, the memory controller 110 can update the resource value of the first function by reflecting the characteristic value of the first function (e.g., 112-1) whose commands are prioritized in the first function in the resource value of the first function (e.g., 112-1). In one example, the resource value of the first function may be a resource value in which the characteristic value of the first function is added to a previous resource value.

[0097] According to this disclosure, a storage device for reducing command latency, an electronic device including the storage device, and a method of operating the same are provided.

[0098] The present disclosure is not limited to the foregoing embodiments and drawings, and it will be apparent to those skilled in the art that various substitutions, modifications, and alterations can be made without departing from the spirit of the present disclosure and the claims. Furthermore, embodiments can be combined to form additional embodiments.

Claims

1. A memory controller, comprising: Multiple functions, each of which is configured to be identified from the perspective of an external host as one of a plurality of storage devices that are logically separate from each other; A resource manager is configured to store both a feature value and a resource value for each of the plurality of functions, the feature value and the resource value being associated with each of the plurality of functions; as well as A command processor is configured to receive commands from the external host that are directed to each of the plurality of functions, prioritize commands among the received commands that are directed to a first function among the plurality of functions by referring to the resource values ​​associated with each of the plurality of functions stored by the resource manager, and update the resource value associated with the first function by adding the feature value associated with the first function to the resource value associated with the first function in the resource manager. The feature values ​​are determined based on both the average amount of data processed by each function and its weight, whereby the weight is determined based on the type of command associated with each of the plurality of functions. The resource value corresponds to a value that is accumulated by summing the characteristic values ​​of each of the plurality of functions whenever a command associated with each of the plurality of functions is processed.

2. The memory controller according to claim 1, wherein the plurality of functions have different characteristic values.

3. The memory controller of claim 1, wherein the resource values ​​are initialized when the storage device is started.

4. The memory controller of claim 1, wherein the plurality of functional controls are included in different memory blocks among a plurality of memory blocks in the memory device.

5. The memory controller according to claim 1, wherein: The external host includes multiple hosts. The command processor includes a command queue, and Multiple commands received from the multiple hosts are stored in the command queue in the order in which the command processor receives the multiple commands.

6. The memory controller of claim 1, wherein the commands include programming commands, read commands, or erase commands.

7. The memory controller of claim 1, wherein the command processor uses a Protocol Information Unit (PIU) or a Protocol Data Unit (PDU) to perform communication with the external host.

8. The memory controller of claim 1, wherein the occupancy percentage of the plurality of functions is adjusted by adjusting the feature value.

9. A method of operating a memory controller, the memory controller including a plurality of functions, each of the plurality of functions being identified from the perspective of an external host as one of a plurality of logically separate storage devices, the method comprising: The operation of storing both feature values ​​and resource values ​​for each of the plurality of functions, wherein the feature values ​​and the resource values ​​are associated with each of the plurality of functions; The operation of receiving commands from the external host that are respectively directed to the plurality of functions; The operation of prioritizing the processing of commands pointing to the first function with the lowest resource value among the received commands is achieved by referring to the resource value associated with each of the plurality of functions. as well as The operation of updating the resource value associated with the first function by adding the feature value associated with the first function to the resource value associated with the first function. The feature values ​​are determined based on both the average amount of data processed by each function and its weight, whereby the weight is determined based on the type of command associated with each of the plurality of functions. The resource value corresponds to a value that is accumulated by summing the characteristic values ​​of each of the plurality of functions whenever a command associated with each of the plurality of functions is processed.

10. The method of claim 9, wherein the plurality of functions have different characteristic values.

11. The method of claim 9, wherein the resource value is initialized when the storage device is started.

12. The method of claim 9, wherein the plurality of function controls are included in different memory blocks among a plurality of memory blocks in the memory device.

13. The method of claim 9, wherein the command includes a programming command, a reading command, or an erasing command.

14. A storage device, comprising: A memory device, comprising multiple memory blocks; as well as The memory controller includes: Multiple functions, each of which is configured to be identified from the perspective of an external host as one of a plurality of storage devices that are logically separate from each other; A resource manager is configured to store both a feature value and a resource value for each of the plurality of functions, the feature value and the resource value being associated with each of the plurality of functions; and A command processor is configured to prioritize, among commands received from the external host and directed to each of the plurality of functions, a command pointing to a first function with the lowest resource value among the plurality of functions, by referring to the resource values ​​associated with each of the plurality of functions stored by the resource manager. The resource value associated with the first function is updated by adding the feature value associated with the first function to the resource value associated with the first function in the resource manager. The feature values ​​are determined based on both the average amount of data processed by each function and its weight, whereby the weight is determined based on the type of command associated with each of the plurality of functions. The resource value corresponds to a value that is accumulated by summing the characteristic values ​​of each of the plurality of functions whenever a command associated with each of the plurality of functions is processed.

15. The storage device of claim 14, wherein the plurality of functions include different characteristic values.

16. The storage device of claim 14, wherein the resource value is initialized when the storage device is started.

17. The storage device of claim 14, wherein the plurality of function controls are included in different memory blocks among the plurality of memory blocks in the storage device.

18. The storage device according to claim 14, wherein: The external host includes multiple hosts. The command processor includes a command queue, and Multiple commands received from the multiple hosts are stored in the command queue in the order in which the command processor receives the multiple commands.

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