A multi-level memory system

Abstract

The embodiment of the application provides a multi-level memory system, relates to the technical field of storage, and can configure the working state of the check circuit of the memory on demand and reduce power consumption. The multi-level memory system comprises a controller, a plurality of check circuits and a multi-level memory; the plurality of check circuits comprise a first check circuit and at least one second check circuit; the first check circuit is configured to check the data stored in the last level memory of the multi-level memory for errors; the second check circuit is configured to check the data stored in one or more memories, except the last level memory, of the multi-level memory for errors in the working state; and the controller is used for configuring the state of the second check circuit, including the working state and the non-working state, so that when the second check circuit is configured to be in the non-working state, the power consumption of the multi-level memory system as a whole can be reduced.

Description

Technical Field

[0001] This application relates to the field of memory technology, and more particularly to a multi-level memory system. Background Technology

[0002] Memory stores data by storing different polarization states such as charge and magnetism. However, because memory may be affected by electromagnetic or other factors in the space environment, the different polarization states of stored charge and magnetism may flip, which will cause the stored data to change. Therefore, it is necessary to verify the data stored in the memory to determine whether the stored data has changed (error).

[0003] There are various verification methods for memory, such as parity check and error correcting code (ECC) verification. Before storing data, a check code or check bit is generated based on the stored data. When verifying the data stored in the memory, it is determined whether the stored data matches the check code or check bit, thereby determining whether an error has occurred in the stored data.

[0004] For multi-level storage, regardless of whether the stored data is modified, a checksum needs to be generated every time data is written to the memory, and error checking and correction need to be performed every time data is read from the memory. This results in high power consumption of the check circuit in a multi-level storage system.

[0005] Another verification method is to generate a checksum only when writing data to the first-level memory, and perform error checking and correction when reading data from the last-level memory. For intermediate-level memory, only error checking is performed, without error correction. This can reduce power consumption to some extent. However, for unmodified data stored in different memories, the probability of errors is small. Performing error checking on every data read from intermediate-level memory still results in high power consumption. Summary of the Invention

[0006] The embodiments of this application provide a multi-level memory system that can configure the working state of the verification circuit according to preset conditions when verifying stored data, thereby reducing overall power consumption.

[0007] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0008] Embodiments of this application provide a multi-level memory system, which includes a controller, multiple verification circuits, and a multi-level memory. The multiple verification circuits include a first verification circuit and at least one second verification circuit. The first verification circuit is configured to perform error checking on data stored in the last-level memory of the multi-level memory. The second verification circuit is configured to, in an operating state, perform error checking on data stored in one or more memories of the multi-level memory, excluding the last-level memory. The controller is used to configure the state of the second verification circuit, which includes a non-operating state and an operating state. Since, in the multi-level storage process, if the data stored in the last-level memory is error-free, the data stored in the preceding-level memories is generally... Data errors will also be avoided. Thus, when verifying data stored in a multi-level memory system, for non-last-level memories, a second verification circuit is used to verify the data stored there. Simultaneously, the controller configures the state of the second verification circuit, setting it to either an active or inactive state based on preset conditions. For example, the second verification circuit is configured to be active when an error is detected in the data of the last-level memory, or when the memory is prone to errors due to its own inherent characteristics or environmental factors. In other cases, the second verification circuit is configured to be inactive, reducing redundant work of the verification circuit. When the second verification circuit is configured to be inactive, the overall power consumption of the system can be reduced.

[0009] In one possible implementation, the controller is configured to activate the second verification circuit when a preset condition is met, thereby enabling verification of the memory of each memory and checking whether the data stored in each memory has errors. The controller is also configured to deactivate the second verification circuit when the preset condition is not met, thereby reducing the verification power consumption of the multi-level memory system.

[0010] In one possible implementation, satisfying the preset conditions includes the first verification circuit detecting an error in the data stored in the final-level memory. Specifically, the controller is configured to activate the second verification circuit when the first verification circuit detects an error in the data stored in the final-level memory, and to deactivate the second verification circuit when the first verification circuit does not detect an error in the data stored in the final-level memory. Since it is impossible to determine which level of memory the error occurred in when the data stored in the final-level memory is erroneous, activating the second verification circuit to verify the data stored in the memory can determine which level of memory the error occurred in. Activating the second verification circuit to deactivate it when no data transmission error is detected in the final-level memory reduces the operating time of the second verification circuit and lowers power consumption.

[0011] In one possible implementation, satisfying preset conditions includes the memory degradation level parameter being greater than a threshold. When the memory degradation level parameter is greater than the threshold, the controller configures the second verification circuit to operate. The multi-level memory system includes a degradation detection circuit, which includes components for detecting the degree of memory degradation. The degradation detection circuit is configured to generate a memory degradation level parameter, which indicates the degree of memory degradation. The degradation detection circuit is connected to the controller, which is specifically configured to obtain the memory degradation level parameter. When the degradation level parameter is greater than the threshold, the probability of memory errors is high, and the controller configures the second verification circuit to operate to perform error checks on the data stored in the memory. When the degradation level parameter is less than or equal to the threshold, the controller configures the second verification circuit to operate in a non-operating state. In this way, when the memory has not degraded or the degree of degradation is minor, the second verification circuit operates in a non-operating state, which can reduce power consumption. When the degradation level parameter is greater than the threshold, the second verification circuit is configured to operate, which can promptly detect intermediate-level memory with errors.

[0012] In one possible implementation, the components include a first transistor, a second transistor, a first analog-to-digital converter (ADC), a second ADC, and a comparator circuit. The first terminal of the first transistor is connected to a power supply, and the second terminal of the first transistor is connected to the input terminal of the first ADC. The first terminal of the second transistor is connected to a power supply, and the second terminal of the second transistor is connected to the input terminal of the second ADC. The first transistor is in a conducting state, and the second transistor is in a cutoff state. The comparator circuit is connected to the output terminals of both the first and second ADCs, and is also connected to a controller. The comparator circuit calculates the difference between the signals output by the first and second ADCs to obtain a degradation parameter. Using the first and second transistors, optimal (i.e., not working) and worst-case (i.e., always working) operating conditions are simulated, respectively. The difference between the first and second transistors determines the potential degradation level of the memory. Since the first transistor is always in a conducting state, the degradation level of the memory transistors will not exceed that of the first transistor. Therefore, using the first and second transistors as a reference, the degradation level of the memory can be determined.

[0013] In one possible implementation, satisfying the preset conditions includes receiving a user's verification command. The controller is configured to configure the second verification circuit to operate when the user's verification command is received, and the controller is also configured to configure the second verification circuit to operate when no verification command is received.

[0014] In one possible implementation, the multi-level memory system includes registers configured to retrieve user verification instructions; the controller is specifically configured to periodically read the registers to retrieve the verification instructions.

[0015] In one possible implementation, satisfying the preset conditions includes any one of the memory's operating parameters reaching the corresponding health threshold. Specifically, the controller is configured to obtain the memory's operating parameters. When any one of the memory's operating parameters reaches the corresponding health threshold, the controller configures the second verification circuit to be in a working state. When none of the memory's operating parameters reach the corresponding health threshold, the controller configures the second verification circuit to be in a non-working state. For the memory, during its entire lifespan, only a small portion of the operating parameters reach the health threshold, while the majority of the time, all operating parameters fail to reach the corresponding health threshold. During this period, the second verification circuit is configured to be in a non-working state, which can reduce the overall power consumption.

[0016] In one possible implementation, the operating parameters include temperature, voltage, current, humidity, and pressure.

[0017] In one possible implementation, the first verification circuit includes an error checking circuit or an error checking and correction circuit; the second verification circuit includes an error checking circuit.

[0018] In one possible implementation, different memories store the same data, and multiple verification circuits are configured to perform error checks on the same data.

[0019] In one possible implementation, the verification circuit includes at least one of an error check code (ECC) verification circuit, a parity check circuit, and a cyclic redundancy check (CRC) verification circuit. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the structure of a storage unit provided in an embodiment of this application;

[0021] Figure 2 This is a schematic diagram of another storage unit provided in an embodiment of this application;

[0022] Figure 3 A schematic diagram illustrating the verification process of a multi-level memory provided in an embodiment of this application;

[0023] Figure 4 This is a schematic diagram of an error checking and correction circuit.

[0024] Figure 5 A schematic diagram illustrating the verification of another multi-level memory provided in an embodiment of this application;

[0025] Figure 6A schematic diagram of a multi-level memory system provided in an embodiment of this application;

[0026] Figure 7 This application provides a schematic diagram illustrating the connection between an operating parameter detection circuit and a controller.

[0027] Figure 8 A schematic diagram showing the connection between another operating parameter detection circuit and the controller provided in an embodiment of this application;

[0028] Figure 9 This is a schematic diagram showing the connection between the degradation detection circuit and the controller provided in an embodiment of this application;

[0029] Figure 10 A schematic diagram of a degradation detection circuit provided in an embodiment of this application;

[0030] Figure 11 This is a schematic diagram of another multi-level memory system provided in an embodiment of this application;

[0031] Figure 12 This is a schematic diagram illustrating the verification of another memory provided in an embodiment of this application. Detailed Implementation

[0032] Memory is a storage component used to store programs and various data information, and is an important part of a computer. Memory includes read-only memory (ROM) and random-access memory (RAM). ROM can only be read, not written; the data stored in ROM is generally pre-written and can only be read during operation, unlike RAM which can be quickly and easily rewritten. RAM, on the other hand, is a type of memory that can be read and written. Because the data stored in RAM is lost when the system is powered off, it is also called volatile memory. Common types of RAM include dynamic random-access memory (DRAM), static random-access memory (SRAM), ferroelectric random-access memory (FeRAM), and magnetic random-access memory (MRAM), among others.

[0033] SRAM is a simple semiconductor memory device and is the most common type of memory in most very large scale integration (VLSI) designs. SRAM stores data in a static form, and the data stored in SRAM will be retained indefinitely as long as power is not interrupted.

[0034] The smallest unit of memory is called a storage cell. Storage cells store data by storing different polarization states, such as electric charge or magnetism. Taking SRAM as an example, the common SRAM storage cell structure is a 6-transistor (T) structure. The 6T structure storage cell includes a pair of weakly cross-coupled inverters and a pair of access transistors for reading and writing the storage state.

[0035] In the embodiments of this application, the transistor can be a metal-oxide-semiconductor field-effect transistor (MOSFET). Transistors are classified into two types: N-type (negative) transistors and P-type (positive) transistors. A transistor includes a source, a drain, and a gate. The transistor's on / off state can be controlled by controlling the voltage level of the input gate. When the transistor is on, the source and drain conduct, generating a conduction current. The magnitude of the conduction current between the source and drain varies depending on the gate voltage level. When the transistor is off, the source and drain do not conduct, and no current is generated. In the embodiments of this application, the transistor's gate is also referred to as the control terminal, the source as the first terminal, and the drain as the second terminal; or, the gate is referred to as the control terminal, the drain as the first terminal, and the source as the second terminal. Furthermore, when the control terminal level is high, the N-type transistor is turned on, and both its first and second terminals are connected, generating a conduction current between them. When the control terminal level is low, the N-type transistor is turned off, and neither its first nor second terminal is connected, thus no current is generated. When the control terminal level is low, the P-type transistor is turned on, and both its first and second terminals are connected, generating a conduction current. When the control terminal level is high, the P-type transistor is turned off, and neither its first nor second terminal is connected, thus no current is generated. The transistors mentioned in the embodiments of this application can be either P-type or N-type transistors.

[0036] Figure 1A schematic diagram of a 6T SRAM memory cell is shown. The memory cell includes transistors T1 to T6. The first terminals of transistors T1 and T2 are connected to the power supply VDD. The second terminal of transistor T1 is connected to the first terminal of transistor T3. The second terminal of transistor T2 is connected to the first terminal of transistor T4. The second terminals of transistors T3 and T4 are grounded. The control terminals of transistors T5 and T6 are connected to the word line (WL). The first terminal of transistor T5 is connected to the first bit line (BL). The second terminal of transistor T5 is connected to the second terminal of transistor T1 and also to the control terminals of transistors T2 and T4. The first terminal of transistor T6 is connected to the second bit line BL!. The second terminal of transistor T6 is connected to the second terminal of transistor T2 and also to the control terminals of transistors T1 and T3. The voltage levels of the first bit line BL and the second bit line BL! are complementary. When the voltage level of the first bit line BL is high, the voltage level of the second bit line BL! is low; when the voltage level of the first bit line BL is high, the voltage level of the second bit line BL! is low. The voltage level is low.

[0037] Transistors T1 and T3 form an inverter, and transistors T2 and T4 form another inverter. These two inverters are cross-connected to form a latch circuit. Node P is the connection point between transistors T1 and T3, and node Q is the connection point between transistors T2 and T4. Data or information is stored using these two nodes. Transistors T5 and T6 are used for read / write control, controlled by the word line WL. Transistor T5 controls the connection or disconnection of bit line BL with node P, and transistor T6 controls the connection or disconnection of bit line BL1 with node Q. By properly configuring the voltage of word line WL and the voltages of bit lines BL1 and BL1, the 6T memory cell can perform three operations: reading data, writing data, and holding data.

[0038] Taking writing data as an example, writing data refers to writing data into a storage unit. Assuming the initial state of node P is "0" and the initial state of node Q is "1", the data to be written to node P is "1". First, the data to be written is "1", and bit lines BL and BL! are set to high and low levels respectively, the word line WL is turned on, and control transistors T5 and T6 are turned on. The high level of node Q will discharge to bit line BL! through transistor T6. When the voltage of node Q exceeds the inverter's flip voltage, according to the feedback of the coupled inverter, the voltage of node P is pulled up to "1", and the voltage of node Q also quickly drops to "0". In this way, node P achieves the transition from "0" to "1", and the data is successfully written. At this time, the word line WL can be turned off.

[0039] This operation maintains the stored data in the memory cell without power loss. In this state, the word line WL is set low, causing the corresponding access transistors T5 and T6 to be cut off. The circuit connections between nodes P and Q and the bit lines are broken. With normal memory power supply, the cross-coupled inverters form a bistable circuit, maintaining the node voltage constant. However, if any of these six transistors changes due to their own characteristics or environmental factors, the stored data will change.

[0040] DRAM memory cells are typically composed of transistors and capacitors. A cell containing two transistors and two capacitors is called a 2T2C; one containing two transistors and one capacitor is called a 2T1C; and one containing one transistor and one capacitor is called a 1T1C. Taking the 1T1C structure as an example... Figure 2 The diagram illustrates the structure of a DRAM memory cell, including a transistor T7 and a storage capacitor C. The first terminal of transistor T7 is connected to the bit line BL, and the second terminal of transistor T7 is connected to the first terminal of storage capacitor C. The control terminal of transistor T7 is connected to the word line WL. The second terminal of storage capacitor C is connected to the source line (SL), which can be connected to a specific voltage (e.g., ground). Storage capacitor C stores data; for example, a 1 is stored when the voltage at the first terminal of storage capacitor C is high and the voltage at the second terminal is low, and a 0 is stored when the voltage at the first terminal is low and the voltage at the second terminal is high. However, if the state of storage capacitor C or transistor T7 changes due to its own characteristics or environmental factors, the stored data will also change.

[0041] Besides SRAM and DRAM, other random access memories such as FeRAM and MRAM are also prone to data corruption. FeRAM stores data by utilizing the spontaneous polarization of ferroelectric materials and the ability to maintain this polarization state. MRAM stores data by utilizing the different magnetization states of magnetic tunnel junctions. These memories can be affected by electromagnetic or other factors in the space environment, causing the stored charge, magnetization, and other polarization states to flip, which can lead to changes in the stored data. Therefore, it is necessary to verify the data stored in the memory to determine whether the stored data has been altered (erroneous).

[0042] Common memory verification mechanisms include parity check, error correcting code (ECC) check, and cyclic redundancy check (CRC) check.

[0043] Parity check codes, which verify the number of "1"s in a stored binary code (usually 8 bits) by checking if the number is odd or even, are used to detect errors during data storage. It is one of the simpler check codes. As the name suggests, parity check includes two methods: odd parity and even parity. Odd parity uses an odd number of "1"s, and even parity uses an even number. Odd parity involves adding a parity bit to the original binary code, ensuring an odd number of "1"s. When reading the code, the number of "1"s is checked to determine if it is odd, thus confirming the correctness of the read code.

[0044] Similarly, even parity refers to adding a parity bit to the original binary code, so that there is an even number of "1"s in the binary code. When reading this code, the number of "1"s is checked to see if it is even, thereby determining the correctness of the code.

[0045] Parity checking can only detect an odd number of errors; it cannot detect an even number of errors. For example, using odd parity, assuming the correct binary code is 11000001, which has an odd number of 1s, if a 1-bit error occurs, for example, becoming 11000011, it becomes an even number of 1s, and the error can be detected. If a 2-bit error occurs, for example, becoming 11000010, it becomes an odd number of 1s, and the error cannot be detected. If a 3-bit error occurs, for example, becoming 11001010, it becomes an even number of 1s, and the error can be detected.

[0046] Parity checking checks the correctness of the current 8 bits of data by adding a data bit to the original data bits. However, as the number of data bits increases, the number of data bits used for parity checking also increases exponentially. That is, when the data bits are 16 bits, it needs to add 2 bits for checking, and when the data bits are 32 bits, it needs to add 4 bits. When the amount of data is very large, the probability of data errors is greater, and the limitations of parity checking become more pronounced.

[0047] Error correcting code (ECC) checks also store a check code in extra bits on the data bits, but the way the check bits are added differs from parity checks, leading to a difference in their main functions. The difference between ECC and parity checks is that if the data bits are 8 bits, 5 check bits are needed for error checking and correction. For every doubling of the data bits, the ECC adds only one check bit. That is, when the data bits are 16 bits, the ECC bits are 6 bits; when the data bits are 32 bits, the ECC bits are 7 bits; when the data bits are 64 bits, the ECC bits are 8 bits, and so on. The ECC bits increase by only one bit for every doubling of the data bits.

[0048] One function of ECC (Error Correction Control) is to check for errors. It generates a checksum from the data in the data area according to certain rules and stores the checksum in the redundancy space. When the system reads data from a data area, it reads the data in the data area and the checksum (denoted as A) in the redundancy space together. Then, it recalculates the data in the data area according to the rules used when generating the checksum information to generate a new checksum B. If B and A are the same, it means that there is no error in the data stored in the data area. If B and A are inconsistent, it means that the data in the data area has been flipped or is incorrect.

[0049] Another function of ECC is error correction. When a data bit flip is detected, the flipped bit in the data area can be corrected by using the check code stored in the redundancy area of ​​ECC. However, the error correction capability of ECC is also limited. Generally, it can perform single-bit error correction and double-bit error detection (SECDED).

[0050] Multilevel storage can resolve the conflict between speed, capacity, and cost in memory. For example, computer systems typically employ multilevel storage systems, assembling various memory devices with different capacities, read / write speeds, and costs into a hierarchical structure. This is achieved through the integration of management software and auxiliary hardware, allowing programs and data to be distributed hierarchically across these different memory locations. Currently, computer systems commonly use a three-level hierarchical structure for their storage systems, primarily consisting of cache, main memory, and auxiliary storage. A larger storage system, composed of various types of storage devices, is a multilevel hierarchical system. This system offers speeds comparable to the central processing unit (CPU), significant capacity, and lower cost. The cache addresses the speed issue, while the auxiliary storage addresses the capacity issue. Employing a multilevel hierarchical memory structure effectively resolves the conflict between speed, capacity, and price in memory.

[0051] In addition to the system-level application scenarios mentioned above, multi-level storage also has some micro-level applications. For example, the transfer of multi-level data within a chip requires temporary caching, which also necessitates the use of multi-level memory.

[0052] Whether it's a multi-level memory for system-level applications or a micro-level multi-level memory within a chip, the stored data needs to be verified. Figure 3 This paper illustrates a data verification method for multi-level memory. Taking ECC verification as an example, an ECC needs to be generated every time data is written to the memory, and the ECC needs to be re-verified every time data is read from the memory to check whether the stored data has been corrupted.

[0053] Combination Figure 3 , Figure 3 The illustrated multi-level memory includes memory M1, memory M2, memory M3, and memory M4. Memory M1, memory M2, memory M3, and memory M4 may store the same data or different data. Memory M1 to memory M4 are merely examples and do not represent that a multi-level memory only includes four memories; there can be more or fewer multi-level memories. For each memory, an error correcting code bits generator (ECCG) circuit and an error detection and correction circuit (ECCC) are respectively set.

[0054] For example, for the first-level memory, namely memory M1, when writing data, an error check code generation circuit is used to generate a check code, and then the data is stored. When reading data from memory M1, the error checking and correction circuit checks the read data for errors and corrects errors if they are detected.

[0055] For subsequent memory modules M2, M3, and M4, the above verification process is repeated to ensure the correctness of the data stored in each memory module.

[0056] See Figure 4 , Figure 4 A schematic diagram of an error checking and correction circuit is shown, including a syndrome generation circuit, a syndrome decoding circuit, a correction circuit, and an error detection circuit. The inputs of the syndrome generation circuit are k information bits (or data bits) and r parity bits, and its output is r syndrome bits. The output of the syndrome decoding circuit is k error patterns (or error matrices) representing each error. The correction circuit can generate correct data based on the error patterns. The output of the error detection circuit is an error signal representing the error type.

[0057] Error checking and correction are performed on each level of memory. This verification method can ensure the correctness of the data stored in each memory and improve the reliability of each memory. However, a check code needs to be generated every time data is written to memory, and error checking and correction are required every time data is read from memory, resulting in high power consumption.

[0058] In another scenario, if the data is not modified during the writing process to the multi-level memory and the same data is stored in the multi-level memory, then the verification method for the multi-level memory can be simplified. Error checking and correction are only performed when reading data from the last level of memory. For memory outside the last level of memory, only error checking is performed when reading data.

[0059] Figure 5 This illustrates another data verification method for multi-level memory, where a checksum is generated only when data is written to the first level of memory, and error checking and correction are performed when data is read from the last level of memory. For intermediate levels of memory, only error checking is performed, without error correction. (Combined with...) Figure 5 , Figure 5 The multi-level memory shown includes memory M1, memory M2, memory M3 and memory M4. Memory M1, memory M2, memory M3 and memory M4 store the same data. Among them, memory M1 is the first level memory in the multi-level memory, memory M4 is the last level memory in the multi-level memory, and memory M2 and memory M3 are intermediate level memories.

[0060] For the first-level memory, namely memory M1, an error correcting code bits generator (ECCG) is set up to generate a check code when writing data to memory M1. In this way, the data and the check code can be stored sequentially in memory M1 to memory M4, that is, memory M1 to memory M4 can store the same data and the same check code.

[0061] For the last-level memory, namely memory M4, an error checking and correction circuit (error correcting code detection and correction, ECCC) is set up to verify the correctness of the data when reading data from the last memory and when errors are detected, and to correct the erroneous data.

[0062] Figure 5The multi-level memory shown performs error checking and correction only when reading data from the last-level memory. For other memories, such as memories M1, M2, and M3, each has a corresponding error-correcting code detection (ECCD) circuit. This ECCD circuit checks the same data and checksums stored in memories M1, M2, and M3 for errors. This allows for the detection of errors in data stored in non-last-level memories such as M1, M2, and M3. Performing error checking and correction when reading data from the last-level memory ensures the correctness of the data read from the multi-level memory. If an error occurs, multiple error-checking circuits can be used to locate the memory location where the error occurred.

[0063] Figure 5 The multi-level memory shown is compared to Figure 3 The illustrated memory reduces the power consumption for generating checksums when writing data to intermediate memory and for error correction when reading data, but error checking is still required when reading data from each level of memory, resulting in relatively high power consumption.

[0064] To address the issue of high power consumption during verification in multi-level memories, embodiments of this application provide a multi-level memory system, referring to... Figure 6 The multi-level memory system includes a controller 11, a multi-level memory, and multiple verification circuits, including a first verification circuit 12 and at least one second verification circuit 13.

[0065] The first verification circuit 12 is configured to perform error checks on the data stored in the last level memory of the multi-level memory in the working state; the second verification circuit 13 is configured to perform error checks on the data stored in one or more memories of the multi-level memory other than the last level memory in the working state; the controller 11 is configured to configure the second verification circuit 13 to be in the working state or in the non-working state according to preset conditions. For example, the controller 11 is configured to configure the second verification circuit 13 to be in the working state when it is determined that the preset conditions are met; the controller 11 is also configured to configure the second verification circuit 13 to be in the non-working state when it is determined that the preset conditions are not met, so as to reduce the redundant operation of the verification circuit and reduce power consumption.

[0066] A multi-level memory system comprises multiple levels of memory, such as memory M1, memory M2, ..., memory Mn-1, memory Mn. Data stored in the previous (or next) level memory is transferred to the next (or next) level memory. Different memories store the same data, and multiple error checking circuits are configured to perform error checking on the same data stored in different memories. Figure 6The multi-level memory system also includes an error check code generation circuit 14. This circuit generates a check code based on the stored data when data is stored in the first-level memory of the multi-level memory system. Thus, the first-level memory and subsequent memory levels store the data and check code simultaneously. When reading data from each memory level, the check circuit performs error checks on the data based on the data and the check code. The first check circuit 12 checks the data in the last-level memory (e.g., ...). Figure 6 The second verification circuit 13 is used to perform error checking on the data stored in one or more non-last-level memories (e.g., memory Mn). Figure 6 Error checking is performed on the memory (M1 to Mn-1) in the memory. For example, each memory except the last memory can be provided with a second verification circuit 13 to perform error checking when reading the data stored in the memory. Alternatively, multiple memories except the last memory can be provided with a second verification circuit 13 to perform error checking when reading the data stored in these memories.

[0067] In a multi-level storage process, data is stored sequentially in the first-level memory (e.g., Figure 6 The memory M1 in the middle), the second level memory (e.g., Figure 6 The memory Mn in the middle is stored until it is stored in the last level memory (e.g., Figure 6 If the data in the memory (Mn) is not modified during the writing process, then the data stored in different memories in the multi-level memory is the same. The verification circuit (first verification circuit 12, second verification circuit 13) provided in the embodiments of this application is used to perform error checks on this part of the same or unmodified data.

[0068] Furthermore, since the data is stored sequentially in different memories, if the last-level memory does not detect an error in the stored data, it can be assumed that the preceding memory also has no error. In this case, there is no need to perform error checks on the memories other than the last-level memory. The controller 11 configures the state of the first verification circuit 12 to a non-operating state to reduce the verification power consumption of the multi-level memory system. However, on the other hand, it is also necessary to ensure the correctness of the data stored in the multi-level memories. Therefore, in the embodiments of this application, the controller 11 configures the state of the second verification circuit 13 according to preset conditions. When the preset conditions are met, the second verification circuit 13 is configured to operate to perform error checks on the data stored in the memory. When the preset conditions are not met, the second verification circuit 13 is configured to operate to reduce the power consumption of the multi-level memories.

[0069] For example, in one implementation of this application, satisfying the preset conditions includes: the first verification circuit 12 detects an error in the data stored in the final-level memory. Specifically, the controller 11 is configured to configure the second verification circuit 13 to operate when the first verification circuit 12 detects an error in the data stored in the final-level memory.

[0070] If the first verification circuit 12 detects an error in the data stored in the last-level memory, it may check the memory other than the last-level memory (e.g., ...). Figure 6 The error did not occur in any of the memory locations M1 to Mn-1, but rather in the memory stored at the last level (e.g., ...). Figure 6 An error may occur during storage of data in the final memory level (Mn); or the error may occur during storage in the first-level memory, causing the error to be retained when storing data in subsequent memory levels; or the error may occur in an intermediate memory level, which is then retained by subsequent memory levels. Therefore, when the first verification circuit 12 detects an error in the data stored in the final memory level, the second verification circuit 13 needs to be activated to locate the position of the error.

[0071] For example, controller 11 includes multiple input and output (IO) ports, such as combined with Figure 6 As shown, ports IO0 to IOn are defined. The first verification circuit 12 includes an error signal output terminal P1, which is connected to port IO0 of the controller 11. The first verification circuit 12 sends an error signal to the controller 11 via the error signal output terminal P1 when an error is detected in the data stored in the final-level memory. Each verification circuit (including the first verification circuit 12 and the second verification circuit 13) includes an enable terminal EN. The enable terminal of each verification circuit is connected to one of the IO ports of the controller 11. The controller 11 can configure the operating state of the verification circuit by outputting control signals through the IO ports. For example, when the enable terminal of the second verification circuit 13 is enabled, the second verification circuit 13 is configured to operate; when the enable terminal of the second verification circuit 13 is not enabled, the second verification circuit 13 is configured to be inactive. The enable signal can be a high-level signal or a low-level signal. Similarly, the first verification circuit 12 includes an enable terminal, which is connected to the I / O port of the controller 11 to receive the enable signal from the controller 11 and configure the operating state of the first verification circuit 12. When the enable terminal of the first verification circuit 12 is enabled, the first verification circuit 12 is configured to operate; when the enable terminal of the first verification circuit 12 is not enabled, the first verification circuit 12 is configured to be inactive. The enable signal can be a high-level signal or a low-level signal.

[0072] In the embodiments of this application, since the first verification circuit 12 is configured to perform error checking on the data of the last-level memory in the working state, in order to ensure that errors can be detected in the data stored in the multi-level memory system, the first verification circuit 12 is configured to be always in the working state to perform error checking on the data stored in the last-level memory in the multi-level memory system. The second verification circuit 13 is configured to perform error checking on the data stored in one or more memories in the multi-level memory system other than the last-level memory in the working state. Therefore, the controller 11 can configure the second verification circuit 13 to be in the working state when preset conditions are met, for example, when the first verification circuit 12 detects an error in the data stored in the last-level memory; and configure the second verification circuit 13 to be in the non-working state when the preset conditions are not met, in order to reduce overall power consumption.

[0073] It is understood that a memory consists of multiple storage cells, and the state of these cells may change due to environmental factors, leading to errors in the stored data. The probability of errors increases, especially when the memory's health is poor. The health of a memory can be measured using operating parameters such as temperature, voltage, and current. Under normal operating conditions, every operating parameter of the memory should be within a healthy or reasonable range. Taking temperature as an example, if the memory operates at high temperatures for a long time, it may lead to the loss of stored data. For example, if the memory can operate normally within the temperature range of -10℃ to 75℃, it is prone to errors when the temperature exceeds 75℃. Therefore, 75℃ can be regarded as the healthy temperature threshold. Similarly, when the operating voltage or operating current of the memory exceeds the rated voltage or rated current, it is prone to failure, leading to errors in the stored data. In addition to temperature, current, and voltage, the operating parameters of the memory's working environment, such as humidity and pressure, also have corresponding healthy thresholds. Excessive humidity or excessive pressure may lead to errors in the data stored in the memory. Different types of memory may have different healthy thresholds for their various operating parameters. When the operating parameters exceed the corresponding healthy thresholds, the probability of errors in the data stored in the memory is relatively high. It is necessary to configure the second verification circuit 13 to be in working state to perform error checks on the data stored in the memory.

[0074] For example, satisfying the preset conditions mentioned above includes any one of the operating parameters of the memory reaching the corresponding health threshold; the controller 11 is specifically configured to obtain the operating parameters of the memory, and when any one of the operating parameters of the memory reaches the corresponding health threshold, the controller 11 configures the second verification circuit 13 to operate. The memory here can be any level of memory in a multi-level memory system, and the operating parameters include, but are not limited to, temperature, voltage, current, humidity, and pressure, and may also include other operating parameters.

[0075] In some embodiments of this application, the multi-level memory system may be equipped with multiple operating parameter detection circuits with different functions to detect the operating parameters of the memory, such as voltage, current, temperature, humidity, and pressure. Figure 7 As shown, these detection circuits can be connected to controller 11 to send the detected operating parameters to controller 11; alternatively, the multi-level memory system may also include registers, such as... Figure 8 As shown, these detection circuits can also store the detected operating parameters in registers. The controller 11 can periodically access the registers to obtain the operating parameters in the memory. Furthermore, when any operating parameter reaches its corresponding health threshold, the controller 11 configures the second verification circuit 13 to operate.

[0076] Besides environmental factors, data stored in memory can also be corrupted due to inherent characteristics of the memory itself. For example, the probability of errors increases after memory ages (or degrades). The number of read / write cycles of memory is limited, or in other words, the lifespan of memory is finite. Frequent read / write operations accelerate memory degradation, which refers to the performance degradation of memory cells. For example, in SRAM, each cell contains six transistors. Degradation of transistor performance may result in a large current flowing even when the transistors are off, leading to changes in the stored data. Similarly, in MRAM, data is stored using magnetic tunnel junctions with different magnetization directions. Degradation of these junctions may cause the magnetization state to be lost, resulting in changes to the stored data. Therefore, when memory degrades, or the degradation is severe, the probability of errors increases. Even if the first verification circuit 12 does not detect errors in the data stored in the final memory stage, the second verification circuit 13 needs to be activated to perform error checks on the data stored in the memory.

[0077] For example, the aforementioned conditions for meeting preset conditions include the memory degradation level parameter being greater than a threshold. The multi-level memory system includes a degradation detection circuit configured to generate a memory degradation level parameter, which indicates the degree of memory degradation. Figure 9As shown, the degradation detection circuit is connected to the controller 11. The controller 11 is specifically configured to obtain the degradation degree parameter of the memory. When the degradation degree parameter is greater than the threshold, the controller 11 configures the second verification circuit 13 to work.

[0078] Taking SRAM as an example, its memory cell is composed of 6 transistors. Therefore, the degradation level parameter of the transistors can be used as the degradation level parameter of the memory. The degradation detection circuit can be used to detect the degradation level parameter of the transistors.

[0079] For example, see Figure 10 The degradation detection circuit includes a first transistor Q1, a second transistor Q2, a first analog-to-digital converter (ADC), a second ADC, and a comparator circuit. The first terminal of the first transistor Q1 and the first terminal of the second transistor Q2 are connected to a power supply. The second terminal of the first transistor Q1 is connected to the input terminal of the first ADC. The first ADC converts the voltage at the second terminal of the first transistor Q1 into a digital signal. The second terminal of the second transistor Q2 is connected to the input terminal of the second ADC, which also converts the voltage at the second terminal of the second transistor Q2 into a digital signal. The degradation detection circuit is used to detect the degradation degree parameter of the transistors. When a transistor experiences performance degradation, its output voltage changes. In this embodiment, the first transistor Q1 and the second transistor Q2 are used as reference transistors. One transistor is always in an active state and will degrade as the circuit's lifespan increases, while the other transistor is always in a non-active state and will not degrade as the circuit's lifespan increases. A signal is applied to the control terminal of the first transistor Q1 to keep it in the on state, and a signal is applied to the control terminal of the second transistor Q2 to keep it in the off state. Using the difference between the two output voltages as a degradation parameter can indicate the degree of transistor degradation.

[0080] The comparator circuit is connected to the output terminals of the first analog-to-digital converter circuit and the second analog-to-digital converter circuit. The comparator circuit is also connected to the controller 11. It calculates the difference between the digital signal output by the first analog-to-digital converter circuit and the digital signal output by the second analog-to-digital converter circuit, and sends the difference as a degradation degree parameter to the controller 11.

[0081] The controller 11 determines whether the degradation degree parameter meets the preset conditions. If the preset conditions are met, the controller 11 controls the second verification circuit 13 to work. For example, when the degradation degree parameter is greater than the threshold, the controller 11 configures the second verification circuit 13 to work.

[0082] In another implementation, the degradation detection circuit can also send the degradation level parameter to a register, which stores the degradation level parameter. The controller 11 periodically accesses the register to obtain the degradation level parameter.

[0083] The above embodiments use an SRAM degradation detection circuit as an example. The storage medium of SRAM is a transistor, so the degradation degree parameter can be generated using the degradation detection circuit. For other types of memory, the degradation detection circuit can be adjusted accordingly. For example, a sensor can be used to detect degradation, such as for capacitors, or for other storage media.

[0084] In addition to meeting the above-mentioned error checking, degradation level, and health status conditions, the multi-level memory system provided in the embodiments of this application can also initiate verification according to the user's verification instructions.

[0085] For example, the above-mentioned conditions for satisfying the preset conditions also include receiving a user's verification instruction. Specifically, the controller 11 is configured to configure the second verification circuit 13 to be in working state when it receives a user's verification instruction.

[0086] The aforementioned verification command can be a verification command sent by the user to the controller 11 through an input / output device, or it can be a verification command pre-configured in a register, for example, see [link to documentation]. Figure 11 The multi-level memory system includes registers configured to retrieve user verification instructions; the controller 11 is specifically configured to periodically read the registers to obtain verification instructions. These verification instructions may include the time to initiate verification, an identifier for the second verification circuit 13 that initiates verification, or other conditions for initiating verification, etc.

[0087] In some possible implementations, each memory other than the last-level memory is provided with a corresponding second verification circuit 13. The controller 11 can establish a correspondence between the I / O port, the identifier of the second verification circuit 13, and the memory. In this way, when the verification instruction includes the identifier of the second verification circuit 13 that starts the verification, the controller 11 can configure the working state of the matching second verification circuit 13 according to the identifier of the second verification circuit 13.

[0088] In addition, the verification instructions may also include health thresholds corresponding to different operating parameters, thresholds for degradation degree parameters, etc. That is to say, users can also configure the start conditions of the second verification circuit 13 through the verification instructions.

[0089] To reduce the verification power consumption of a multi-level memory system, the first verification circuit 12 can be an error checking circuit to check for errors in the data stored in the last-level memory. Alternatively, the first verification circuit 12 can also be an error checking and correction circuit, correcting errors in addition to checking them. The second verification circuit 13 is an error checking circuit that only detects errors without correcting them, and its operating state is configured according to preset conditions, thereby reducing the verification power consumption of the multi-level memory system.

[0090] In addition, the first verification circuit 12 and the second verification circuit 13 mentioned above can be ECC verification circuits, parity verification circuits or CRC verification circuits, or other verification circuits.

[0091] In the foregoing embodiments, the verification of a multi-level memory system is described using the example of data not being modified in multi-level storage. In some other possible implementations, if the data is modified in multi-level storage and the proportion of modified data is small, the modified data and the unmodified data can be verified separately. The unmodified data is configured with the working state of its corresponding verification circuit according to the several cases provided in the foregoing embodiments of this application, thereby reducing the overall power consumption of the system.

[0092] For example, such as Figure 12 As shown, Figure 12 A schematic diagram of an intermediate-level memory verification is shown. When data is stored in this memory, some data is modified. Therefore, when verifying data at this level of memory, the modified data and the unmodified data can be separated for error checking. The unmodified data is checked for errors using a second verification circuit 13. The controller 11 configures the operating state of the second verification circuit 13 according to preset conditions, thus reducing overall power consumption.

[0093] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A multi-level memory system, characterized in that, The multi-level memory system includes a controller, multiple verification circuits, and multiple levels of memory, wherein different memories store the same data, and the multiple verification circuits are configured to perform error checks on the same data. The plurality of verification circuits include a first verification circuit and at least one second verification circuit; The first verification circuit is configured to perform error checking on the data stored in the last level of the multi-level memory. The second verification circuit is configured to, in the operating state, perform error checks on the data stored in one or more memories in the multi-level memory, excluding the last-level memory. The controller is configured to keep the first verification circuit in a working state. The controller is also configured to configure the second verification circuit to a working state when a preset condition is met, and to configure the second verification circuit to a non-working state when the preset condition is not met.

2. The multi-level memory system according to claim 1, characterized in that, The condition of satisfying the preset condition includes the first verification circuit detecting an error in the data stored in the final stage memory; Specifically, the controller is configured to enable the second verification circuit to operate when the first verification circuit detects an error in the data stored in the final-level memory. Specifically, the controller is configured to disable the second verification circuit when the first verification circuit fails to detect an error in the data stored in the final-level memory.

3. The multi-level memory system according to claim 1, characterized in that, The preset conditions include the memory degradation process parameter being greater than a threshold. The multi-level memory system includes a degradation detection circuit, which includes components for detecting the degree of degradation of the memory. The degradation detection circuit is configured to generate a degradation parameter of the memory, which indicates the degree of degradation of the memory. The degradation detection circuit is connected to the controller, which is specifically configured to obtain a degradation degree parameter of the memory. When the degradation degree parameter is greater than a threshold, the controller configures the second verification circuit to be in a working state; when the degradation degree parameter is less than or equal to the threshold, the controller configures the second verification circuit to be in a non-working state.

4. The multi-level memory system according to claim 3, characterized in that, The components include a first transistor, a second transistor, a first analog-to-digital converter circuit, a second analog-to-digital converter circuit, and a comparator circuit; The first terminal of the first transistor is connected to a power supply, and the second terminal of the first transistor is connected to the input terminal of the first analog-to-digital converter circuit; the first terminal of the second transistor is connected to a power supply, and the second terminal of the second transistor is connected to the input terminal of the second analog-to-digital converter circuit; wherein the first transistor is in the on state, and the second transistor is in the off state; The comparison circuit is connected to the output terminals of the first analog-to-digital converter circuit and the second analog-to-digital converter circuit, and is also connected to the controller. The comparison circuit is used to calculate the difference between the signals output by the first analog-to-digital converter circuit and the signals output by the second analog-to-digital converter circuit to obtain the degradation degree parameter.

5. The multi-level memory system according to claim 1, characterized in that, The preset conditions include receiving a user's verification command. The controller is configured to configure the second verification circuit to be in a working state when the user's verification command is received; the controller is also configured to configure the second verification circuit to be in a non-working state when the verification command is not received.

6. The multi-level memory system according to claim 5, characterized in that, The multi-level memory system includes registers configured to acquire the user's verification instruction; The controller is specifically configured to periodically read the register to obtain the verification instruction.

7. The multi-level memory system according to claim 1, characterized in that, The preset conditions include any one of the memory's operating parameters reaching the health threshold corresponding to that operating parameter. The controller is specifically configured to obtain the operating parameters of the memory. When any one of the operating parameters of the memory reaches the health threshold corresponding to the operating parameter, the controller configures the second verification circuit to be in working state; when none of the operating parameters of the memory reach the corresponding health threshold, the controller configures the second verification circuit to be in non-working state.

8. The multi-level memory system according to claim 7, characterized in that, The operating parameters include temperature, voltage, current, humidity, and pressure.

9. The multi-level memory system according to any one of claims 1 to 7, characterized in that, The first verification circuit includes an error checking circuit or an error checking and correction circuit; the second verification circuit includes an error checking circuit.

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