On-chip inductor structure and method of making the same

Abstract

The application discloses an on-chip inductor structure and a manufacturing method thereof. The manufacturing method comprises the following steps: forming a first magnetic layer on the surface of a substrate; forming an inductor on the surface of the first magnetic layer, wherein the inductor comprises a wire circuit; forming a first photosensitive coating covering the inductor; performing first exposure on the first photosensitive coating, wherein the first exposure has a first window, and the width of the first window is greater than the width of the inductor; forming a second photosensitive coating on the surface of the first photosensitive coating; performing second exposure on the second photosensitive coating, wherein the second exposure has a second window, and the width of the second window is equal to the width of the wire circuit; removing the first photosensitive coating and the second photosensitive coating which are not exposed around the inductor, and performing solidification to form a patterned coating covering the inductor, wherein the sidewall of the patterned coating is in an arc shape which slowly descends and is provided with a buffer area, and the corner of the buffer area is in a concave angle; and forming a second magnetic layer on the surface of the patterned coating. The application improves the coverage and thickness uniformity of the second magnetic layer.

Description

Technical Field

[0001] This application relates to the semiconductor field, and more particularly to an on-chip inductor structure and its fabrication method. Background Technology

[0002] Inductors are key components in microelectronic circuits such as switching regulators, radio frequency (RF) circuits, and electromagnetic interference (EMI) mitigation circuits. As microelectronic devices continue to evolve towards higher integration and complexity, achieving high inductance within small-sized devices has become crucial. Therefore, inductors must be integrated on-die or on-package to achieve high-performance circuits; however, the performance of existing on-chip inductor structures still needs improvement. Summary of the Invention

[0003] Some embodiments of this application provide a method for fabricating an on-chip inductor structure, including:

[0004] Provide a base;

[0005] A first magnetic layer is formed on the surface of the substrate;

[0006] An inductor is formed on the surface of the first magnetic layer, and the inductor includes at least one wire line.

[0007] A first photosensitive coating covering the inductor is formed on the first magnetic layer, and the first photosensitive coating directly above the conductor line has a raised first bulge structure.

[0008] A first exposure is performed on the first photosensitive coating on the inductor, wherein the first exposure has a first window, the width of the first window being greater than the width of the inductor;

[0009] After the first exposure is performed, a second photosensitive coating is formed on the surface of the first photosensitive coating, and the second photosensitive coating directly above the wire line has a raised second bulge structure.

[0010] A second exposure is performed on the second photosensitive coating directly above the conductor line, the second exposure having a second window, the width of the second window being equal to the width of the conductor line;

[0011] The unexposed first and second photosensitive coatings around the inductor are removed, and the remaining exposed first and second photosensitive coatings are cured to form a patterned coating covering the inductor on the first magnetic layer. The patterned coating includes a cured first photosensitive coating and a cured second photosensitive coating on the surface of the cured first photosensitive coating. The patterned coating directly above the conductor has an upwardly bulging structure. The sidewalls of the cured second photosensitive coating and the cured first photosensitive coating around the inductor are in a gently descending arc shape, and a buffer zone is formed at the junction of the sidewall of the cured second photosensitive coating and the sidewall of the cured first photosensitive coating. The corner of the buffer zone is concave.

[0012] A second magnetic layer is formed on the patterned coating surface.

[0013] In some embodiments, the materials of the first photosensitive coating and the second photosensitive coating are negative photoresist.

[0014] In some embodiments, the negative photoresist is made of a photosensitive polyimide polymer, a polybenzoxazole polymer, or a benzocyclobutene polymer.

[0015] In some embodiments, the process of removing the unexposed first and second photosensitive coatings around the inductor includes a developing process; the process of curing the remaining exposed first and second photosensitive coatings includes a heat treatment.

[0016] In some embodiments, the surfaces of the first photosensitive coatings on both sides of the first bulge structure are lower than the top surface of the first bulge structure; the surfaces of the second photosensitive coatings on both sides of the second bulge structure are lower than the top surface of the second bulge structure.

[0017] In some embodiments, the width of the cured second photosensitive coating is smaller than the width of the cured first photosensitive coating.

[0018] In some embodiments, the inductor is a spiral inductor or a linear inductor. When the inductor is a spiral inductor, there is one conductor line that is spiral in shape. When the inductor is a linear inductor, there are at least two conductor lines that are parallel to each other.

[0019] In some embodiments, the method further includes: forming a first dielectric layer on the surface of the first magnetic layer before forming an inductor on the surface of the first magnetic layer; and forming a second dielectric layer on the surface of the patterned coating before forming a second magnetic layer on the surface of the patterned coating.

[0020] In some embodiments, the first magnetic layer and the second magnetic layer are both stacked structures with alternating layers of magnetic thin film layers and spacer layers.

[0021] Some embodiments of this application also provide an on-chip inductor structure, including:

[0022] Base;

[0023] A first magnetic layer located on the surface of the substrate;

[0024] An inductor located on the surface of the first magnetic layer, the inductor comprising at least one wire line;

[0025] A patterned coating is located on the first magnetic layer and covers the inductor. The patterned coating includes a cured first photosensitive coating and a cured second photosensitive coating on the surface of the cured first photosensitive coating. The patterned coating directly above the conductor has an upwardly bulging bulge structure. The sidewalls of the cured second photosensitive coating and the sidewalls of the cured first photosensitive coating around the inductor form a gently descending arc shape. A buffer zone is formed at the junction of the sidewalls of the cured second photosensitive coating and the sidewalls of the cured first photosensitive coating. The corner of the buffer zone is concave.

[0026] A second magnetic layer located on the patterned coating surface.

[0027] In some embodiments, the materials of the cured first photosensitive coating and the cured second photosensitive coating are negative photoresist.

[0028] In some embodiments, the negative photoresist is made of a photosensitive polyimide polymer, a polybenzoxazole polymer, or a benzocyclobutene polymer.

[0029] In some embodiments, the width of the cured second photosensitive coating is smaller than the width of the cured first photosensitive coating.

[0030] In some embodiments, the inductor is a spiral inductor or a linear inductor. When the inductor is a spiral inductor, there is one conductor line that is spiral in shape. When the inductor is a linear inductor, there are at least two conductor lines that are parallel to each other.

[0031] In some embodiments, the system further includes: a first dielectric layer located between the inductor and the first magnetic layer; and a second dielectric layer located between the second magnetic layer and the patterned coating.

[0032] In some embodiments, the first magnetic layer and the second magnetic layer are both stacked structures with alternating layers of magnetic thin film layers and spacer layers.

[0033] In some embodiments, the bulge structure includes a first bulge structure located in the cured first photosensitive coating and a second bulge structure located in the cured second photosensitive coating.

[0034] The on-chip inductor structure and its fabrication method in some of the foregoing embodiments of this application include the following steps: After forming a first magnetic layer on the surface of a substrate, an inductor is formed on the surface of the first magnetic layer. The inductor includes at least one conductive line. A first photosensitive coating covering the inductor is formed on the first magnetic layer, and the first photosensitive coating directly above the conductive line has a raised first bulge structure. The first photosensitive coating on the inductor undergoes a first exposure, during which a first window is provided, the width of which is greater than the width of the inductor. After the first exposure, a second photosensitive coating is formed on the surface of the first photosensitive coating, and the second photosensitive coating directly above the conductive line has a raised second bulge structure. The second photosensitive coating directly above the conductive line undergoes a second exposure, during which a second window is provided. The width of the second window is equal to the width of the conductor line; the unexposed first and second photosensitive coatings around the inductor are removed, and the remaining exposed first and second photosensitive coatings are cured to form a patterned coating covering the inductor on the first magnetic layer. The patterned coating includes a cured first photosensitive coating and a cured second photosensitive coating on the surface of the cured first photosensitive coating. The patterned coating directly above the conductor line has an upwardly bulging structure. The sidewalls of the cured second photosensitive coating and the cured first photosensitive coating around the inductor are in a slowly descending arc shape, and a buffer zone is formed at the junction of the sidewall of the cured second photosensitive coating and the sidewall of the cured first photosensitive coating. The corner of the buffer zone is concave. A second magnetic layer is formed on the surface of the patterned coating.Through the combination of the aforementioned specific steps, a patterned coating with a specific structure is formed (the patterned coating includes a cured first photosensitive coating and a cured second photosensitive coating on the surface of the cured first photosensitive coating; the patterned coating directly above the conductor has an upwardly bulging bulge structure; the sidewalls of the cured second photosensitive coating and the sidewalls of the cured first photosensitive coating around the inductor form a gently descending arc shape; and a buffer zone is formed at the junction of the sidewalls of the cured second photosensitive coating and the sidewalls of the cured first photosensitive coating, with concave corners). The upwardly bulging bulge structure in the patterned coating directly above the conductor reduces the steepness of the patterned coating surface above the conductor (preventing it from being too inclined or too vertical), and the inductor... The sidewalls of the cured second photosensitive coating and the cured first photosensitive coating form a gently descending arc, reducing the steepness of the patterned coating sidewalls (preventing them from being too inclined or too vertical). Furthermore, a buffer zone is formed at the junction of the sidewalls of the cured first photosensitive coating and the first photosensitive coating. The corners of this buffer zone are concave, further reducing the steepness of the patterned coating sidewalls (preventing them from being too inclined or too vertical). Therefore, when the second magnetic layer is formed on the patterned coating surface, the coverage and thickness uniformity of the second magnetic layer are improved. This prevents the thickness of the second magnetic layer formed on the patterned coating surface from being too thin at a certain location, causing that location to reach saturation magnetic flux density earlier than other locations, thus saturating the inductor and affecting its inductance. Attached Figure Description

[0035] Figures 1-14 This is a schematic diagram illustrating the fabrication process of the on-chip inductor structure in some embodiments of this application. Detailed Implementation

[0036] The specific embodiments of this application will be described in detail below with reference to the accompanying drawings. In describing the embodiments of this application in detail, for ease of explanation, the schematic diagrams may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of this application. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0037] This application first provides a method for fabricating an on-chip inductor structure, and the aforementioned fabrication method is described in detail below with reference to the accompanying drawings.

[0038] refer to Figure 1 Provides a base.

[0039] In some embodiments, the substrate includes a semiconductor substrate 22 and an interlayer dielectric layer 24 located on the surface of the semiconductor substrate 22.

[0040] In some specific embodiments, the semiconductor substrate 22 can be made of silicon (Si), germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC); it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or other materials, such as gallium arsenide or other group III-V compounds. The semiconductor substrate 22 can also be implanted with certain dopant ions to change electrical parameters according to design requirements. A shallow trench isolation structure (not shown in the figure) is also formed within the semiconductor substrate 22. The shallow trench isolation structure is used to isolate adjacent active regions. The material of the shallow trench isolation structure can be one or more of silicon oxide, silicon nitride, and silicon oxynitride. Semiconductor devices are formed in and / or on the active regions, including one or more of transistors, resistors, capacitors, and diodes.

[0041] In some embodiments, an interconnect structure 26 is further formed in (or in and on) the interlayer dielectric layer 24. In a specific embodiment, the interconnect structure 26 includes a metal wire, or includes a metal wire and a conductive plug connected to the metal wire.

[0042] In some specific embodiments, the interlayer dielectric layer 24 can be a single-layer or multi-layer stacked structure, and the corresponding interconnect structure 26 can also be a single-layer or multi-layer stacked structure, with each interconnect structure formed in and on the surface of the corresponding interlayer dielectric layer. The material of the interlayer dielectric layer 24 can be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxycarbide, silicon carbonitride, carbon, FSG (fluorine-doped silicon dioxide), BSG (boron-doped silicon dioxide), PSG (phosphorus-doped silicon dioxide), or BPSG (boron-phosphorus-doped silicon dioxide), or a low dielectric constant (K less than 2.5). The material of the interconnect structure 26 is one or more of Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, W, or WN.

[0043] In some embodiments, the substrate further includes: a passivation layer 26 formed on the surface of the interlayer dielectric layer 24; a first adhesive layer 28 formed on the surface of the passivation layer 26; and a bottom dielectric layer 30 formed on the surface of the first adhesive layer 28.

[0044] The passivation layer 26 can be made of one or more of silicon nitride, silicon carbide, silicon oxide, or silicon oxynitride.

[0045] The first adhesive layer 28 is used to improve the adhesion between layers. The first adhesive layer 28 can be a metal material or alloy such as titanium, copper, or tantalum, or a combination of other metals. The formation process of the first adhesive layer 28 includes physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), and other processes.

[0046] The bottom dielectric layer 30 is used for electrical isolation between the subsequently formed first magnetic layer and the substrate. The bottom dielectric layer 30 may be one or more of silicon nitride, silicon carbide, silicon oxide, or silicon oxynitride, and the formation process of the bottom dielectric layer 30 includes atomic layer deposition (ALD), chemical vapor deposition (CVD), or plasma-enhanced chemical vapor deposition (PECVD).

[0047] In one embodiment, reference Figure 2 The bottom dielectric layer 30 and the first adhesive layer 28 are partially etched away, and the remaining surface of the bottom dielectric layer 30 is subsequently used to form the first magnetic layer.

[0048] The etching removal of the underlying dielectric layer 30 and the first adhesive layer 28 can be achieved by ion beam etching (IBE), reactive ion etching (RIE), or reactive ion beam etching (RIBE).

[0049] refer to Figure 3 and Figure 4 A first magnetic layer 32 is formed on the surface of the substrate.

[0050] In some embodiments, the first magnetic layer 32 is formed on the surface of the underlying dielectric layer 30.

[0051] The first magnetic layer 32 and the subsequently formed second magnetic layer 50 (reference) Figure 14 The magnetic shell encapsulates the subsequently formed inductor 40 (reference). Figure 14 The first magnetic layer 32 and the second magnetic layer 50 form a continuous magnetic circuit or generate magnetic coupling, which affects the wire lines in the inductor 40 between the first magnetic layer 32 and the second magnetic layer 50, thereby increasing the inductance of the inductor.

[0052] In some embodiments, the formation process of the first magnetic layer 32 includes: forming the first magnetic layer 32 on the surfaces of the bottom dielectric layer 30 and the passivation layer 26 (see reference). Figure 3 The first magnetic layer 32 is patterned, and the first magnetic layer 32 outside the bottom dielectric layer 30 is removed, while the first magnetic layer 32 on the surface of the bottom dielectric layer 30 is retained.

[0053] The first magnetic layer 32 can be a single-layer structure or a multi-layer stacked structure composed of magnetic materials.

[0054] In some embodiments, when the first magnetic layer 32 is a multilayer stacked structure, it is a stacked structure of alternating magnetic thin film layers and spacer layers. The magnetic thin film layer is made of nanocrystalline magnetic alloy or amorphous magnetic alloy, such as CoZrTa, CoZrTaB, NiFe, CoP, FeBN, CoZrO, etc., and is formed by processes such as copper physical vapor deposition (PVD). The spacer layer is made of materials such as silicon oxide or cobalt oxide, and is formed by deposition processes such as physical vapor deposition (PVD) or oxidation processes such as plasma oxidation or thermal oxidation. The thickness of the spacer layer is typically 5-10% of the thickness of the magnetic thin film layer.

[0055] In other embodiments, the first magnetic layer 32 is a multilayer stacked structure, which is a stacked structure of alternating magnetic thin film layers of different magnetic materials. In a specific embodiment, the first magnetic layer 32 is a stacked structure of alternating first magnetic thin film layers and second magnetic thin film layers, which are made of different magnetic materials.

[0056] In some embodiments, reference Figure 5 A first dielectric layer 34 is formed on the surface of the first magnetic layer 32 (and the surface of the passivation layer 26).

[0057] The first dielectric layer 34 serves as electrical isolation between the subsequently formed inductor and the first magnetic layer 32, and also increases the height of the first magnetic layer 32 and the subsequently formed second magnetic layer 50 (see reference). Figure 14 The dielectric constant of the material between the first magnetic layer 32 and the first dielectric layer 34 has a flat surface.

[0058] In some embodiments, the first dielectric layer 34 may be a polymer, specifically polyimide (PI), polybenzoxazole (PBO), etc. In other embodiments, the first dielectric layer 34 may also be an inorganic dielectric material, specifically one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, and silicon carbonitride.

[0059] In some embodiments, reference Figure 6 It also includes forming a seed layer 36 on the surface of the first dielectric layer 34. The seed layer 36 serves as a seed layer and conductive layer for subsequent electroplating to form an inductor. The seed layer 36 is formed by processes such as physical vapor deposition (PVD) and chemical vapor deposition (CVD). The material of the seed layer 36 can be metals such as copper and titanium and their alloys, or a combination of multiple metals.

[0060] refer to Figure 7 and Figure 8An inductor 40 is formed on the surface of the first magnetic layer 32, and the inductor 40 includes at least one conductor line 41.

[0061] In this embodiment, the inductor 40 is formed on the surface of the first dielectric layer 34 on the surface of the first magnetic layer 32. In other embodiments, the inductor 40 may be formed directly on the surface of the first magnetic layer 32.

[0062] In some embodiments, the formation process of the inductor 40 includes: forming a mask layer 38 (see reference) on the seed layer 34. Figure 7 The mask layer 38 has an opening that exposes a portion of the surface of the seed layer 34. The shape and position of the opening define the shape and position of the formed inductor 40. The inductor 40 is formed by electroplating a conductive material into the opening. The inductor 40 includes at least one conductive line 41. The conductive material can be metals such as copper, titanium, nickel, and gold, or their alloys, or a combination of multiple metals. The mask layer and the seed layer on both sides of the conductive line are then removed (see reference). Figure 8 ).

[0063] The inductor 40 is a spiral inductor or a linear inductor. In some embodiments, when the inductor 40 is a spiral inductor, there is one spiral wire; in other embodiments, when the inductor 40 is a linear inductor, there are at least two linear wires 41, and at least two linear wires 41 are parallel to each other. Figure 8 The following description uses two examples, namely the conductor line 41 in the inductor 40, as an example.

[0064] refer to Figure 9 A first photosensitive coating 42 is formed on the first magnetic layer 32 to cover the inductor 40, and the first photosensitive coating 42 directly above the conductor line 41 has a raised first bulge structure 11.

[0065] The first photosensitive coating 42 is subsequently used to form the lower portion of the patterned coating.

[0066] In some embodiments, the material of the first photosensitive coating 42 is a negative photoresist. In specific embodiments, the negative photoresist is a photosensitive polyimide polymer (PI), a polybenzoxazole polymer (PBO), or a benzocyclobutene polymer (BCB). The first photosensitive coating 42 can then be patterned using exposure and development processes.

[0067] The process for forming the first photosensitive coating 42 includes spin coating, spray coating, physical vapor deposition (PVD) or chemical vapor deposition (CVD).

[0068] The first photosensitive coating 42 includes a first bulge structure 11 protruding directly above the conductor line 41. The apex of the first bulge structure 11 is arc-shaped. The surfaces of the first photosensitive coating 42 on both sides of the first bulge structure 11 are lower than the top surface of the first bulge structure 11. The first bulge structure 11 facilitates the formation of a second bulge structure 12 in the subsequently formed second photosensitive coating 44 (see reference). Figure 11 Therefore, when the first photosensitive coating 42 and the second photosensitive coating 44 are exposed (specific first exposure and second exposure are performed on the first photosensitive coating 42 and the second photosensitive coating 44 respectively), developed and cured to form a patterned coating (the patterned coating includes the cured first photosensitive coating and the cured second photosensitive coating located on the surface of the cured first photosensitive coating), a raised first bulge structure 11 is easily formed in the patterned coating directly above the conductor line 41, reducing the steepness of the patterned coating surface directly above the conductor line 41 (preventing it from being too tilted). (Or too vertical), the patterned coating sidewalls around the inductor 40 tend to form a gently descending arc, thereby reducing the steepness of the patterned coating sidewalls (not too inclined or too vertical), and a buffer zone is formed at the junction of the sidewalls of the cured first photosensitive coating and the sidewall of the cured first photosensitive coating. The corners of the buffer zone are concave, thus further reducing the steepness of the patterned coating sidewalls (not too inclined or too vertical), thereby enabling the subsequent formation of the second magnetic layer 50 on the patterned coating surface (refer to...). Figure 14 When the second magnetic layer 50 is formed on the patterned coating surface, the coverage and thickness uniformity of the second magnetic layer 50 are improved to prevent the thickness of the second magnetic layer 50 formed on the patterned coating surface from being too thin at a certain position, so that the position reaches the saturation magnetic flux density earlier than other positions, thereby causing the inductor 40 to saturate and affecting the inductance of the inductor 40.

[0069] refer to Figure 10 The first photosensitive coating 42 on the inductor 40 is subjected to a first exposure, and the first exposure has a first window 51, the width of the first window 51 being greater than the width of the inductor 40.

[0070] When performing the first exposure on the first photosensitive coating 42, a first photomask 54 is used. The first photomask includes a light-transmitting portion and an opaque portion. During the first exposure, the exposure light passes through the light-transmitting portion of the first photomask 54 and is projected into the first photosensitive coating 42 through corresponding optical components. The first window 51 during the first exposure is the size of the exposure light projected into the first photosensitive coating 42, or the first window 51 during the first exposure is the feature size of the light-transmitting portion of the first photomask 54 multiplied by the scaling factor of the optical components. The width of the inductor 40 is the vertical distance between the outer walls of the two outermost conductor lines 41 of the inductor.

[0071] The size of the first window 51 defines the size of the cross-linked hardening portion in the first photosensitive coating 42, that is, it defines the size of the lower portion of the subsequently formed patterned coating. The width of the first window 51 is greater than the width of the inductor 40, so that the subsequently formed patterned coating must at least cover the inductor 40.

[0072] refer to Figure 11 After the first exposure, a second photosensitive coating 44 is formed on the surface of the first photosensitive coating 42. The second photosensitive coating 44 directly above the conductor line 41 has a raised second bulge structure 12.

[0073] The second photosensitive coating 44 is subsequently used to form the upper part of the patterned coating.

[0074] In some embodiments, the material of the second photosensitive coating 44 is a negative photoresist. In specific embodiments, the negative photoresist is a photosensitive polyimide polymer (PI), a polybenzoxazole polymer (PBO), or a benzocyclobutene polymer (BCB). The second photosensitive coating 44 can then be patterned using exposure and development processes.

[0075] The process for forming the second photosensitive coating 44 includes spin coating, spray coating, physical vapor deposition (PVD) or chemical vapor deposition (CVD).

[0076] The formed second photosensitive coating 44 includes a second bulge structure 12 protruding directly above the conductor line 41. The apex of the second bulge structure 12 is arc-shaped. The surfaces of the second photosensitive coating 44 on both sides of the second bulge structure 12 are lower than the top surface of the second bulge structure 12. This allows for subsequent specific second exposures of the second photosensitive coating 44, and the development and curing of the first photosensitive coating 42 after a specific first exposure and the second photosensitive coating 44 after a specific first exposure to form a patterned coating (the patterned coating includes the cured first photosensitive coating and the cured second photosensitive coating on the surface of the cured first photosensitive coating). The patterned coating directly above the conductor line 41... The patterned coating easily forms raised bumps, reducing the steepness of the patterned coating surface directly above the conductor line 41 (preventing it from being too sloping or too vertical). Furthermore, the patterned coating sidewalls around the inductor 40 tend to form a gently sloping arc, further reducing the steepness of the patterned coating sidewalls (preventing them from being too sloping or too vertical). A buffer zone is formed at the junction of the sidewalls of the cured first photosensitive coating and the sidewall of the cured first photosensitive coating, with concave corners, further reducing the steepness of the patterned coating sidewalls (preventing them from being too sloping or too vertical). This facilitates the subsequent formation of the second magnetic layer 50 (see reference) on the patterned coating surface. Figure 14 When the second magnetic layer 50 is formed on the patterned coating surface, the coverage and thickness uniformity of the second magnetic layer 50 are improved to prevent the thickness of the second magnetic layer 50 formed on the patterned coating surface from being too thin at a certain position, so that the position reaches the saturation magnetic flux density earlier than other positions, thereby causing the inductor 40 to saturate and affecting the inductance of the inductor 40.

[0077] refer to Figure 12 A second exposure is performed on the second photosensitive coating 44 directly above the conductor line 41. The second exposure has a second window 52, ​​the width of which is equal to the width of the conductor line 41.

[0078] A second photomask 56 is used for the second exposure of the second photosensitive coating 44. The second photomask 56 includes multiple transparent portions and multiple opaque portions. During the second exposure, the exposure light passes through the transparent portions of the second photomask 56 and is projected into the second photosensitive coating 44 through corresponding optical components. The second window 52 during the second exposure is the size of the exposure light projected into the second photosensitive coating 44, or the second window 52 during the second exposure is the feature size of the transparent portion of the second photomask 56 multiplied by the scaling factor of the optical components. The width of the conductor line 41 is the vertical distance between the two opposite outer walls of the conductor line 41.

[0079] The size of the second window 52 defines the size of the cross-linked hardening portion in the second photosensitive coating 44, that is, it defines the size of the upper portion of the subsequently formed patterned coating. The width of the second window 52 is equal to or slightly larger than the width of the conductor line 41, thereby causing the second photosensitive coating 44 directly above and near the conductor line 41 to cross-link and harden, so that the subsequently formed patterned coating has a raised bulge structure, and the sidewalls of the patterned coating are slowly descending arcs with a buffer zone.

[0080] refer to Figure 13 The unexposed first and second photosensitive coatings around the inductor 40 are removed, and the remaining exposed first and second photosensitive coatings 42 and 44 are cured to form a patterned coating covering the inductor 40 on the first magnetic layer 32. The patterned coating includes the cured first photosensitive coating 42 and the cured second photosensitive coating 44 on the surface of the cured first photosensitive coating 42. The patterned coating directly above the conductor line 41 has an upwardly bulging bulge structure 13. The sidewalls of the cured second photosensitive coating 44 and the cured first photosensitive coating 42 around the inductor 40 are in a slowly descending arc shape, and a buffer zone 45 is formed at the junction of the sidewall of the cured second photosensitive coating 44 and the sidewall of the cured first photosensitive coating 42. The corner of the buffer zone 45 is concave.

[0081] The patterned coating directly above the conductor line 41 has an upwardly bulging structure 13, including a first bulge structure and a second bulge structure located on the surface of the first bulge structure. The first bulge structure is located in a first photosensitive coating 42 cured directly above the conductor line 41, and the second bulge structure is located in a second photosensitive coating 44 cured directly above the conductor line 41. The apex of the bulge structure 13 is arc-shaped.

[0082] The width of the cured second photosensitive coating 44 is smaller than the width of the cured first photosensitive coating 42. The sidewall of the cured second photosensitive coating 44 extends in a slowly descending arc to the buffer zone 45 at the junction with the sidewall of the cured first photosensitive coating 42. The sidewall of the cured first photosensitive coating 42 extends in a slowly descending arc from the buffer zone to the surface of the first magnetic layer 32.

[0083] refer to Figure 14 A second magnetic layer 50 is formed on the surface of the patterned coating 40.

[0084] In some embodiments, the second magnetic layer 50 is formed directly on the surface of the patterned coating 40. In other embodiments, a second adhesive layer 46 and a second dielectric layer 48 located on the surface of the patterned coating 40 are formed before the second magnetic layer 50 is formed.

[0085] In some embodiments, the method further includes forming a third dielectric layer 52 on the surface of the second magnetic layer 50.

[0086] The material and forming process of the second adhesive layer 46 are the same as those of the first adhesive layer 28. The materials and forming processes of the second dielectric layer 48 and the third dielectric layer 52 are the same as those of the bottom dielectric layer 30 and the first dielectric layer 34. The material and forming process of the second magnetic layer 50 are the same as those of the first magnetic layer 32.

[0087] The second magnetic layer 50 formed is blanket-like covering the first magnetic layer 32, and the length of the second magnetic layer 50 is greater than the length of the first magnetic layer 32.

[0088] In forming the second magnetic layer 50, this application achieves a patterned coating with a specific structure through the organic combination of the aforementioned specific steps. This patterned coating includes a cured first photosensitive coating 42 and a cured second photosensitive coating 44 on the surface of the cured first photosensitive coating 42. The patterned coating directly above the conductor line 41 has an upwardly bulging structure. The sidewalls of the cured second photosensitive coating 44 and the sidewalls of the cured first photosensitive coating 42 around the inductor 40 form a slowly descending arc shape. A buffer zone 45 is formed at the junction of the sidewall of the cured second photosensitive coating 44 and the sidewall of the cured first photosensitive coating 42, with concave corners. The patterned coating directly above the conductor line 41... The patterned coating has an upwardly bulging structure, reducing the steepness of the patterned coating surface directly above the conductor line 41 (not too inclined or too vertical). The sidewalls of the cured second photosensitive coating 44 and the cured first photosensitive coating 42 around the inductor 40 form a gently descending arc, further reducing the steepness of the patterned coating sidewalls (not too inclined or too vertical). Furthermore, a buffer zone is formed on the patterned coating sidewalls (at the junction of the sidewalls of the cured first photosensitive coating and the sidewall of the first photosensitive coating), with concave corners, further reducing the steepness of the patterned coating sidewalls (not too inclined or too vertical). Thus, a second magnetic layer 50 (see reference) is formed on the patterned coating surface. Figure 14When the second magnetic layer 50 is formed on the patterned coating surface, the coverage and thickness uniformity of the second magnetic layer 50 are improved to prevent the thickness of the second magnetic layer 50 formed on the patterned coating surface from being too thin at a certain position, so that the position reaches the saturation magnetic flux density earlier than other positions, thereby causing the inductor 38 to saturate and affecting the inductance of the inductor 38.

[0089] Some embodiments of this application also provide an on-chip inductor structure, in conjunction with reference to the reference. Figure 14 and Figure 13 ,include:

[0090] Base;

[0091] A first magnetic layer 32 located on the surface of the substrate;

[0092] An inductor 40 located on the surface of the first magnetic layer 32, the inductor 40 including at least one wire line 41;

[0093] A patterned coating is located on the first magnetic layer 32 and covers the inductor 40. The patterned coating includes a cured first photosensitive coating 42 and a cured second photosensitive coating 44 on the surface of the cured first photosensitive coating 42. The patterned coating directly above the conductor line 41 has an upwardly bulging bulge structure 13 (see reference). Figure 13 The sidewalls of the cured second photosensitive coating 44 and the sidewalls of the cured first photosensitive coating 42 around the inductor 40 form a slowly descending arc shape, and a buffer zone 45 is formed at the junction of the sidewalls of the cured second photosensitive coating 44 and the sidewalls of the cured first photosensitive coating 42, and the corners of the buffer zone 45 are concave.

[0094] A second magnetic layer 50 is located on the patterned coating surface.

[0095] In some embodiments, the materials of the cured first photosensitive coating 42 and the cured second photosensitive coating 44 are negative photoresist.

[0096] In some embodiments, the negative photoresist is made of a photosensitive polyimide polymer, a polybenzoxazole polymer, or a benzocyclobutene polymer.

[0097] In some embodiments, the width of the cured second photosensitive coating 44 is smaller than the width of the cured first photosensitive coating 42.

[0098] In some embodiments, the inductor 40 is a spiral inductor or a linear inductor. When the inductor is a spiral inductor, there is one conductor line that is spiral in shape. When the inductor is a linear inductor, there are at least two conductor lines that are parallel to each other.

[0099] In some embodiments, the invention further includes: a first dielectric layer 34 located between the inductor 40 and the first magnetic layer 32; and a second dielectric layer 48 located between the second magnetic layer 50 and the patterned coating.

[0100] In some embodiments, it further includes a (second) adhesive layer 46 located between the second dielectric layer 48 and the patterned coating.

[0101] In some embodiments, the first magnetic layer 32 and the second magnetic layer 50 are both stacked structures with alternating layers of magnetic thin film layers and spacer layers.

[0102] In some embodiments, the bulge structure 13 includes a first bulge structure located in the cured first photosensitive coating 42 and a second bulge structure located in the cured second photosensitive coating 44.

[0103] It should be noted that the terms "comprising" and "having," and their variations, used in this invention are intended to cover non-exclusive inclusion. The terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence, unless explicitly indicated by the context. It should be understood that such data can be used interchangeably where appropriate. Furthermore, embodiments and features within embodiments of this invention can be combined with each other unless otherwise specified. In addition, descriptions of well-known components and technologies have been omitted in the above description to avoid unnecessarily obscuring the concepts of this invention. In the various embodiments described above, each embodiment focuses on its differences from other embodiments; similar / identical parts between embodiments can be referred to (or understood) interchangeably.

[0104] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A method for fabricating an on-chip inductor structure, characterized in that, include: Provide a base; A first magnetic layer is formed on the surface of the substrate; An inductor is formed on the surface of the first magnetic layer, and the inductor includes at least one wire line. A first photosensitive coating covering the inductor is formed on the first magnetic layer, and the first photosensitive coating directly above the conductor line has a raised first bulge structure. A first exposure is performed on the first photosensitive coating on the inductor, wherein the first exposure has a first window, the width of the first window being greater than the width of the inductor; After the first exposure is performed, a second photosensitive coating is formed on the surface of the first photosensitive coating, and the second photosensitive coating directly above the wire line has a raised second bulge structure. A second exposure is performed on the second photosensitive coating directly above the conductor line, the second exposure having a second window, the width of the second window being equal to the width of the conductor line; The unexposed first and second photosensitive coatings around the inductor are removed, and the remaining exposed first and second photosensitive coatings are cured to form a patterned coating covering the inductor on the first magnetic layer. The patterned coating includes a cured first photosensitive coating and a cured second photosensitive coating on the surface of the cured first photosensitive coating. The patterned coating directly above the conductor has an upwardly bulging structure. The sidewalls of the cured second photosensitive coating and the cured first photosensitive coating around the inductor are in a gently descending arc shape, and a buffer zone is formed at the junction of the sidewall of the cured second photosensitive coating and the sidewall of the cured first photosensitive coating. The corner of the buffer zone is concave. A second magnetic layer is formed on the patterned coating surface.

2. The method for fabricating the on-chip inductor structure as described in claim 1, characterized in that, The materials of the first and second photosensitive coatings are negative photoresist.

3. The method for fabricating the on-chip inductor structure as described in claim 2, characterized in that, The negative photoresist is made of a photosensitive polyimide polymer, a polybenzoxazole polymer, or a benzocyclobutene polymer.

4. The method for fabricating the on-chip inductor structure as described in claim 1 or 2, characterized in that, The process for removing the unexposed first and second photosensitive coatings around the inductor includes a developing process; the process for curing the remaining exposed first and second photosensitive coatings includes a heat treatment.

5. The method for fabricating the on-chip inductor structure as described in claim 1, characterized in that, The surfaces of the first photosensitive coatings on both sides of the first bulge structure are lower than the top surface of the first bulge structure; the surfaces of the second photosensitive coatings on both sides of the second bulge structure are lower than the top surface of the second bulge structure.

6. The method for fabricating the on-chip inductor structure as described in claim 1 or 5, characterized in that, The width of the cured second photosensitive coating is smaller than the width of the cured first photosensitive coating.

7. The method for fabricating the on-chip inductor structure as described in claim 1, characterized in that, The inductor is a spiral inductor or a linear inductor. When the inductor is a spiral inductor, there is one conductor line that is spiral in shape. When the inductor is a linear inductor, there are at least two conductor lines that are parallel to each other.

8. The method for fabricating the on-chip inductor structure as described in claim 1, characterized in that, Also includes: Before forming an inductor on the surface of the first magnetic layer, a first dielectric layer is formed on the surface of the first magnetic layer; Before forming a second magnetic layer on the patterned coating surface, a second dielectric layer is formed on the patterned coating surface.

9. The method for fabricating the on-chip inductor structure as described in claim 1, characterized in that, Both the first magnetic layer and the second magnetic layer are stacked structures with alternating layers of magnetic thin film layers and spacer layers.

10. An on-chip inductor structure, characterized in that, include: Base; A first magnetic layer located on the surface of the substrate; An inductor located on the surface of the first magnetic layer, the inductor comprising at least one wire line; A patterned coating is located on the first magnetic layer and covers the inductor. The patterned coating includes a cured first photosensitive coating and a cured second photosensitive coating on the surface of the cured first photosensitive coating. The patterned coating directly above the conductor has an upwardly bulging bulge structure. The sidewalls of the cured second photosensitive coating and the sidewalls of the cured first photosensitive coating around the inductor form a gently descending arc shape. A buffer zone is formed at the junction of the sidewalls of the cured second photosensitive coating and the sidewalls of the cured first photosensitive coating. The corner of the buffer zone is concave. A second magnetic layer located on the patterned coating surface.

11. The on-chip inductor structure as described in claim 10, characterized in that, The materials of the cured first photosensitive coating and the cured second photosensitive coating are negative photoresist.

12. The on-chip inductor structure as described in claim 11, characterized in that, The negative photoresist is made of a photosensitive polyimide polymer, a polybenzoxazole polymer, or a benzocyclobutene polymer.

13. The on-chip inductor structure as described in claim 10, characterized in that, The width of the cured second photosensitive coating is smaller than the width of the cured first photosensitive coating.

14. The on-chip inductor structure as described in claim 10, characterized in that, The inductor is a spiral inductor or a linear inductor. When the inductor is a spiral inductor, there is one conductor line that is spiral in shape. When the inductor is a linear inductor, there are at least two conductor lines that are parallel to each other.

15. The on-chip inductor structure as described in claim 10, characterized in that, Also includes: A first dielectric layer located between the inductor and the first magnetic layer; A second dielectric layer located between the second magnetic layer and the patterned coating.

16. The on-chip inductor structure as described in claim 10, characterized in that, Both the first magnetic layer and the second magnetic layer are stacked structures with alternating layers of magnetic thin film layers and spacer layers.

17. The on-chip inductor structure as described in claim 10, characterized in that, The bulge structure includes a first bulge structure located in the cured first photosensitive coating and a second bulge structure located in the cured second photosensitive coating.

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