Germanium-silicon heterojunction transistors and methods of making the same

Abstract

The application provides a germanium-silicon heterojunction transistor and a preparation method thereof. The preparation method comprises the following steps: providing a substrate, and forming a sacrifice layer on the surface of the substrate and an isolation layer in a groove; forming a germanium-silicon layer in a second opening at the bottom of a first opening; forming a first dielectric layer; removing the sacrifice layer on the surface of the germanium-silicon layer, and forming a first polysilicon layer in a fourth opening between the first dielectric layer and the germanium-silicon layer; forming a second dielectric layer; forming a second polysilicon layer; forming a third dielectric layer; and forming a third polysilicon layer in a fifth opening between the third dielectric layer and the isolation layer and on a part of the surface of the isolation layer. The application discloses a preparation method for preparing an outer base region conductive layer in a segmented mode based on a sacrifice layer self-alignment process, so as to simplify the connection process of the base region germanium-silicon layer and the outer base region conductive layer and reduce the preparation difficulty.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, specifically to a germanium-silicon heterojunction transistor and its fabrication method. Background Technology

[0002] Silicon-germanium heterojunction transistors (SiGe HBTs) offer significant advantages in high-frequency characteristics compared to traditional Si-based bipolar transistors, making them highly sought after in high-speed radio frequency (RF) circuits. Compared to group III-VI RF devices, they offer advantages such as lower cost, better thermal conductivity, and superior substrate mechanical properties; furthermore, they are compatible with mature silicon integration and CMOS technologies, providing greater flexibility in production.

[0003] SiGe HBT devices fabricated using the traditional dual-layer polysilicon self-aligned process (DPSA) are among the highest-performing mass-produced products. However, the traditional DPSA process involves first growing an outer polysilicon base region and then forming a germanium-silicon layer. This results in the germanium-silicon layer being epitaxially grown from top to bottom on one side and from bottom to top on the other, leading to a large number of crystal defects in the final germanium-silicon layer. Consequently, the connection resistance between the outer and base regions in this structure is relatively high, thus limiting further performance improvements.

[0004] Furthermore, in the traditional double-layer polysilicon self-aligned (DPSA) process, the outer polysilicon layer is grown first, followed by the germanium-silicon layer. This inevitably leads to the outer polysilicon layer being affected by the thermal processes of subsequent steps, resulting in excessive impurity diffusion and increased device instability. In addition, the traditional DPSA process for manufacturing SiGe HBT devices is quite challenging and complex. Summary of the Invention

[0005] This application provides a germanium-silicon heterojunction transistor and its fabrication method. Based on the sacrificial layer self-aligned process (SLSA), it can effectively solve at least one of the problems in traditional DPSA structure SiGe HBT devices, such as large external base region connection resistance and high difficulty in SiGe epitaxial process.

[0006] The sacrificial layer self-aligned (SLSA) process proposed in this application ingeniously overcomes the shortcomings of the traditional DPSA structure, greatly reducing the difficulty of device manufacturing, decreasing the connection resistance of the outer base region, and further improving device performance.

[0007] On one hand, embodiments of this application provide a method for fabricating a germanium-silicon heterojunction transistor, comprising:

[0008] A substrate is provided, in which trenches are formed, an isolation layer is formed on the surface of the substrate and in the trenches, a sacrificial layer is formed on the isolation layer, and a first opening is formed in the sacrificial layer;

[0009] Remove the insulating layer on the substrate surface at the bottom of the first opening to form a second opening;

[0010] A germanium-silicon layer is formed, the germanium-silicon layer filling the second opening;

[0011] A first dielectric layer is formed, which covers the sacrificial layer and fills the first opening. At this time, a third opening is formed on the surface of the first dielectric layer located on the first opening.

[0012] Etch the first dielectric layer and the sacrificial layer on both sides of the germanium-silicon layer to the surface of the isolation layer;

[0013] Remove the remaining sacrificial layer from the surface of the germanium-silicon layer. At this time, a fourth opening is formed between the first dielectric layer and the germanium-silicon layer.

[0014] A first polysilicon layer is formed, and the first polysilicon layer fills the fourth opening;

[0015] A second dielectric layer is formed, which covers the side surface of the first polysilicon, the isolation layer, and the first dielectric layer;

[0016] Remove a portion of the second dielectric layer and a portion of the first dielectric layer vertically downward from the third opening location;

[0017] A second polysilicon layer is formed, which fills the third opening and covers the second dielectric layer above the germanium-silicon layer;

[0018] A third dielectric layer is formed, which covers the second polysilicon layer and a portion of the second dielectric layer;

[0019] The second dielectric layer on the surface of the isolation layer is removed, at which point a fifth opening is formed between the third dielectric layer and the isolation layer;

[0020] A third polysilicon layer is formed, the third polysilicon layer covering a portion of the isolation layer adjacent to the first polysilicon layer, and filling the fifth opening, wherein the third polysilicon layer and the first polysilicon layer constitute an outer base region conductive layer; and

[0021] Remove the third dielectric layer from the upper surface of the second polysilicon layer.

[0022] Optionally, in the method for fabricating the germanium-silicon heterojunction transistor, the germanium-silicon layer is formed from bottom to top by a selective epitaxial process.

[0023] Optionally, in the method for fabricating the germanium-silicon heterojunction transistor, the step of vertically removing a portion of the second dielectric layer and a portion of the first dielectric layer from the third opening location includes:

[0024] Using a dry etching process, a portion of the second dielectric layer is removed vertically downwards from the third opening location to the surface of the first dielectric layer; and

[0025] A portion of the first dielectric layer is removed from the surface of the germanium-silicon layer by etching vertically downwards from the third opening using a wet etching process.

[0026] Optionally, in the method for fabricating the germanium-silicon heterojunction transistor, the first polycrystalline silicon layer is formed from bottom to top by a selective growth process.

[0027] Optionally, in the method for fabricating the germanium-silicon heterojunction transistor, the third polycrystalline silicon layer is formed from the inside out using a selective growth process.

[0028] Optionally, in the method for fabricating the germanium-silicon heterojunction transistor, the materials of the isolation layer, the first dielectric layer, and the third dielectric layer are all silicon oxide.

[0029] Optionally, in the method for fabricating the germanium-silicon heterojunction transistor, both the sacrificial layer and the second dielectric layer are made of silicon nitride.

[0030] On the other hand, embodiments of this application also provide a germanium-silicon heterojunction transistor, comprising:

[0031] A substrate in which trenches are formed, an isolation layer is formed in the trenches, and a second opening is formed in the substrate between the isolation layers;

[0032] A germanium-silicon layer, wherein the germanium-silicon layer fills the second opening;

[0033] A first polysilicon layer, wherein a first opening is formed between the first polysilicon layers;

[0034] A first dielectric layer, the first dielectric layer covering the first polysilicon layer and filling the first opening;

[0035] A second dielectric layer covers the first dielectric layer, wherein a third opening is formed in both the first dielectric layer and the second dielectric layer;

[0036] A second polysilicon layer, the second polysilicon layer filling the third opening and covering a portion of the second dielectric layer;

[0037] A third dielectric layer, the third dielectric layer covering the sidewalls of the second polysilicon layer and the remainder of the second dielectric layer, wherein a fifth opening is formed between the third dielectric layer and the isolation layer; and

[0038] A third polysilicon layer covers a portion of the isolation layer adjacent to the first polysilicon layer and fills the fifth opening, wherein the third polysilicon layer and the first polysilicon layer constitute an outer base region conductive layer.

[0039] The technical solution of this application has at least the following advantages:

[0040] First, this application forms a sacrificial layer on the substrate surface and a germanium-silicon layer in the second opening between the sacrificial layers. Then, a first polysilicon layer and a third polysilicon layer are epitaxially prepared from bottom to top at the location of the sacrificial layer. This achieves segmented formation of the outer base region conductive layer based on the sacrificial layer self-aligned process (SLSA). This application uses the sacrificial layer self-aligned process (SLSA) to prepare the outer base region conductive layer in segments, which simplifies the connection process between the base region germanium-silicon layer and the outer base region conductive layer, reduces the fabrication difficulty, and improves the fabrication efficiency of the device.

[0041] Second, this application first forms a sacrificial layer on the isolation layer, then forms a germanium-silicon layer in the sacrificial layer through a bottom-up epitaxial process, then removes the sacrificial layer in segments, and first forms a first segment of the outer base region conductive layer (first polysilicon layer) from bottom to top at the location of the sacrificial layer, and finally forms a second segment of the outer base region conductive layer (third polysilicon layer) through epitaxy. This segmented formation of the outer base region conductive layer is completely different from the traditional process of first forming the outer base region polysilicon layer and then the germanium-silicon layer. The fabrication process of this application can obtain a germanium-silicon layer and an outer base region conductive layer (first polysilicon layer) with good crystal quality through a bottom-up epitaxial process, reducing crystal defects in the germanium-silicon layer and the outer base region conductive layer, reducing the connection resistance between the outer base region and the base region, and improving device performance. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0043] Figure 1 This is a flowchart of a method for fabricating a germanium-silicon heterojunction transistor according to an embodiment of the present invention;

[0044] Figures 2-17This is a schematic diagram of the semiconductor structure in each process step of the fabrication of germanium-silicon heterojunction transistors according to an embodiment of the present invention.

[0045] The reference numerals in the attached figures are explained as follows:

[0046] 10-Substrate, 20-Isolation layer, 30-Sacrificial layer, 40-Germanium-silicon layer, 50-First dielectric layer, 60-First polysilicon layer, 70-Second dielectric layer, 80-Second polysilicon layer, 90-Third dielectric layer, 61-Third polysilicon layer;

[0047] 201 - First opening, 202 - Second opening, 203 - Third opening, 204 - Fourth opening, 205 - Fifth opening. Detailed Implementation

[0048] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0049] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0050] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0051] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0052] This application provides a method for fabricating a germanium-silicon heterojunction transistor, referring to... Figure 1 , Figure 1 This is a flowchart of a method for fabricating a germanium-silicon heterojunction transistor according to an embodiment of the present invention. The method for fabricating the germanium-silicon heterojunction transistor includes:

[0053] Step S1: Provide a substrate in which trenches are formed, an isolation layer is formed on the substrate surface and in the trenches, a sacrificial layer is formed on the isolation layer, and a first opening is formed in the sacrificial layer;

[0054] Step S2: Remove the insulating layer on the substrate surface at the bottom of the first opening to form a second opening;

[0055] Step S3: Form a germanium-silicon layer, wherein the germanium-silicon layer fills the second opening;

[0056] Step S4: A first dielectric layer is formed, which covers the sacrificial layer and fills the first opening. At this time, a third opening is formed on the surface of the first dielectric layer located on the first opening.

[0057] Step S5: Etch the first dielectric layer and the sacrificial layer on both sides of the germanium-silicon layer to the surface of the isolation layer;

[0058] Step S6: Remove the remaining sacrificial layer on the surface of the germanium-silicon layer. At this time, a fourth opening is formed between the first dielectric layer and the germanium-silicon layer.

[0059] Step S7: Form a first polysilicon layer, wherein the first polysilicon layer fills the fourth opening;

[0060] Step S8: Form a second dielectric layer, the second dielectric layer covering the side of the first polysilicon, the isolation layer and the first dielectric layer;

[0061] Step S9: Remove a portion of the second dielectric layer and a portion of the first dielectric layer vertically downwards from the third opening position;

[0062] Step S10: Form a second polysilicon layer, the second polysilicon layer filling the third opening and covering the second dielectric layer above the germanium-silicon layer;

[0063] Step S11: Form a third dielectric layer, the third dielectric layer covering the second polysilicon layer and a portion of the second dielectric layer;

[0064] Step S12: Remove the second dielectric layer on the surface of the isolation layer. At this time, a fifth opening is formed between the third dielectric layer and the isolation layer.

[0065] Step S13: Form a third polysilicon layer, the third polysilicon layer covering a portion of the isolation layer adjacent to the first polysilicon layer, and filling the fifth opening, wherein the third polysilicon layer and the first polysilicon layer constitute an outer base region conductive layer; and

[0066] Step S14: Remove the third dielectric layer on the upper surface of the second polysilicon layer.

[0067] For details, please refer to Figures 2-17 , Figures 2-17 This is a schematic diagram of the semiconductor structure in each process step of the fabrication of a germanium-silicon heterojunction transistor according to an embodiment of the present invention. The fabrication method of the germanium-silicon heterojunction transistor provided in the embodiments of this application will be described in detail below.

[0068] First, perform step S1: as follows Figure 2 As shown, Figure 2 This is a schematic diagram of a semiconductor structure after the formation of the first opening according to an embodiment of the present invention. A substrate 10 is provided, a trench is formed in the substrate 10, an isolation layer 20 is formed on the surface of the substrate 10 and in the trench, a sacrificial layer 30 is formed on the isolation layer 20, and a first opening 201 is formed in the sacrificial layer 30.

[0069] In this embodiment, the substrate 10 is a silicon substrate; the isolation layer 20 is made of silicon dioxide, and the isolation layer filling the trench can be regarded as STI (shallow trench isolation structure).

[0070] Preferably, the sacrificial layer 30 is a silicon nitride layer.

[0071] Preferably, the thickness of the sacrificial layer 30 is

[0072] In this embodiment, the sacrificial layer 30 can be etched using a dry etching process. Furthermore, the first opening 201 is located between two adjacent shallow trench isolation structures.

[0073] Then, proceed to step S2: as follows Figure 3 As shown, Figure 3 This is a schematic diagram of the semiconductor structure after the formation of the second opening in an embodiment of the present invention. The isolation layer 20 on the surface of the substrate 10 at the bottom of the first opening 201 is removed to form the second opening 202.

[0074] Preferably, a wet etching process is used to remove the isolation layer 20 on the surface of the substrate 10 at the bottom of the first opening 201 to form the second opening 202.

[0075] Next, proceed to step S3: as follows Figure 4 As shown, Figure 4This is a schematic diagram of the semiconductor structure after the formation of the germanium-silicon layer according to an embodiment of the present invention. The germanium-silicon layer 40 is formed, and the germanium-silicon layer 40 fills the second opening 202.

[0076] Preferably, the germanium-silicon layer 40 is formed from bottom to top using a selective epitaxial process. Since only the substrate 10 in the semiconductor structure is a silicon substrate, the germanium-silicon layer 40 can be formed from bottom to top using a selective epitaxial process. Therefore, the crystal orientation of the resulting germanium-silicon layer 40 is all in one direction, thereby improving the crystal quality and thickness uniformity of the germanium-silicon layer 40.

[0077] Further, proceed to step S4: as follows Figure 5 As shown, Figure 5 This is a schematic diagram of the semiconductor structure after the formation of the first dielectric layer according to an embodiment of the present invention. The first dielectric layer 50 is formed, which covers the sacrificial layer 30 and fills the first opening 201. At this time, a third opening 203 is formed on the surface of the first dielectric layer 50 located on the first opening 201.

[0078] Preferably, the first dielectric layer 50 is made of silicon oxide.

[0079] Next, proceed to step S5: (e.g.) Figure 6 As shown, Figure 6 This is a schematic diagram of the semiconductor structure after etching the first dielectric layer and the sacrificial layer on both sides of the germanium-silicon layer according to an embodiment of the present invention. The first dielectric layer 50 and the sacrificial layer 50 on both sides of the germanium-silicon layer 40 are etched to the surface of the isolation layer 20.

[0080] Preferably, the first dielectric layer 50 and the sacrificial layer 50 on both sides of the germanium-silicon layer 40 can be etched by a dry etching process.

[0081] Further, proceed to step S6: as follows Figure 7 As shown, Figure 7 This is a schematic diagram of the semiconductor structure after removing the remaining sacrificial layer on the surface of the germanium-silicon layer according to an embodiment of the present invention. After removing the remaining sacrificial layer 30 on the surface of the germanium-silicon layer 40, a fourth opening 204 is formed between the first dielectric layer 50 and the germanium-silicon layer 40.

[0082] Preferably, a wet etching process is used to remove the remaining sacrificial layer 30 on the surface of the germanium-silicon layer 40.

[0083] Next, proceed to step S7: as follows Figure 8 As shown, Figure 8 This is a schematic diagram of the semiconductor structure after the formation of the first polysilicon layer according to an embodiment of the present invention. The first polysilicon layer 60 is formed and the first polysilicon layer 60 fills the fourth opening 204.

[0084] Preferably, the first polycrystalline silicon layer 60 is formed from bottom to top using a selective growth process.

[0085] It is worth noting that the first polysilicon layer 60 is the first segment in the outer base region conductive layer. Since only the germanium silicon layer 40 is located at the bottom of the fourth opening 204 in the semiconductor structure at this time, the first polysilicon layer 60 can be epitaxially formed from bottom to top through selective growth process. Therefore, the crystal orientation of the first polysilicon layer 60 is all in one direction, thereby improving the crystal quality and thickness uniformity of the first polysilicon layer 60.

[0086] Further, proceed to step S8: as follows Figure 9 As shown, Figure 9 This is a schematic diagram of the semiconductor structure after the formation of the second dielectric layer in an embodiment of the present invention. The second dielectric layer 70 is formed, and the second dielectric layer 70 covers the side of the first polysilicon 60, the isolation layer (shallow trench isolation structure) 20 and the first dielectric layer 50.

[0087] In this embodiment, the material of the second dielectric layer 70 is silicon nitride.

[0088] Next, proceed to step S9: (e.g.) Figure 10 As shown, Figure 10 This is a schematic diagram of the semiconductor structure after a portion of the second dielectric layer and a portion of the first dielectric layer are removed vertically downward from the third opening position according to an embodiment of the present invention. A portion of the second dielectric layer 70 and a portion of the first dielectric layer 50 are removed vertically downward from the third opening 203 position.

[0089] Preferably, the step of removing a portion of the second dielectric layer 70 and a portion of the first dielectric layer 50 vertically downward from the third opening 203 position may specifically include:

[0090] Step S9.1: Using a dry etching process, a portion of the second dielectric layer 70 is etched vertically downwards from the third opening 203 to remove the surface of the first dielectric layer 50; and

[0091] Step S9.2: Using a wet etching process, a portion of the first dielectric layer 70 to the surface of the germanium-silicon layer 40 is removed by vertically etching downwards from the third opening 203.

[0092] Further, proceed to step S10: as follows Figure 11 and Figure 12 As shown, Figure 11 This is a schematic diagram of the semiconductor structure after the formation of the second polysilicon layer according to an embodiment of the present invention. Figure 12This is a schematic diagram of the semiconductor structure after removing a portion of the second polysilicon layer on the second dielectric layer according to an embodiment of the present invention. A second polysilicon layer 80 is formed, which fills the third opening 203 and covers the second dielectric layer 70 above the germanium-silicon layer 40. The second polysilicon layer 80 subsequently serves as the emitter of the device.

[0093] Preferably, the step of forming the second polysilicon layer 80 may specifically include:

[0094] Step S10.1: As Figure 11 As shown, a second polysilicon layer 80 is formed, which fills the third opening 203 and covers all of the second dielectric layer 70.

[0095] Step S10.2: As Figure 12 As shown, a dry etching process is used to etch away the second polysilicon layer 80 on the surface of the second dielectric layer 70 above the shallow trench isolation structure. The remaining second polysilicon layer 80 fills the third opening 203 and covers the second dielectric layer 70 above the germanium-silicon layer 40.

[0096] Next, proceed to step S11: as follows Figure 13 and 14 As shown, Figure 13 This is a schematic diagram of the semiconductor structure after the formation of the third dielectric layer according to an embodiment of the present invention. Figure 14 This is a schematic diagram of the semiconductor structure after removing the third dielectric layer from the surface of the isolation layer according to an embodiment of the present invention, forming a third dielectric layer 90, which covers the second polysilicon layer 80 and a portion of the second dielectric layer 70. In this embodiment, the material of the third dielectric layer 90 is silicon oxide.

[0097] Specifically, the step of forming the third dielectric layer 90 may include:

[0098] Step S11.1: As Figure 13 As shown, a third dielectric layer 90 is formed using a CVD process, and the third dielectric layer 90 covers the second polysilicon layer 80 and the second dielectric layer 70.

[0099] Step S11.2: As Figure 14 As shown, the third dielectric layer 90 above the shallow trench isolation structure is removed by dry etching process, and the remaining third dielectric layer 90 covers the second polysilicon layer 80 and the second dielectric layer 70 on the side of the device bump structure.

[0100] Further, proceed to step S12: as follows Figure 15 As shown, Figure 15This is a schematic diagram of the semiconductor structure after removing the second dielectric layer on the surface of the isolation layer according to an embodiment of the present invention. After removing the second dielectric layer 70 on the surface of the isolation layer, a fifth opening 205 is formed between the third dielectric layer 90, the remaining second dielectric layer 70 and the isolation layer 20.

[0101] Next, proceed to step S13: as follows Figure 16 As shown, Figure 16 This is a schematic diagram of the semiconductor structure after the formation of the third polysilicon layer according to an embodiment of the present invention. A third polysilicon layer 61 is formed, which covers a portion of the isolation layer 20 near the first polysilicon layer 60 and fills the fifth opening 205. That is, the third polysilicon layer 61 extends to the surface of the isolation layer 20 outside the fifth opening 205. The third polysilicon layer 61 and the first polysilicon layer 60 constitute an outer base region conductive layer.

[0102] It is worth noting that the third polysilicon layer 61 is the second segment of the conductive layer in the outer base region. The third polysilicon layer 61 can be epitaxially formed from the inside out using a selective growth process. Since the first polysilicon layer 60 is located inside the fifth opening 205 in the semiconductor structure at this time, the third polysilicon layer 61 can be epitaxially formed from the inside out outside of the first polysilicon layer 60 using a selective growth process. Therefore, the crystal orientation of the obtained third polysilicon layer 61 is all in one direction, thereby improving the crystal quality and thickness uniformity of the third polysilicon layer 61. Here, "inside" is defined as the direction closer to the second polysilicon layer 80 (towards the device center), and "outside" is defined as the direction farther from the second polysilicon layer 80 (towards the device edge).

[0103] In this application, a sacrificial layer is first formed on the substrate surface, and a germanium-silicon layer is formed in the second opening between the sacrificial layers. Then, a first polysilicon layer is epitaxially prepared from bottom to top at the location of the sacrificial layer, and finally a third polysilicon layer is prepared. This achieves segmented formation of the outer base region conductive layer based on the sacrificial layer self-aligned process (SLSA). This application uses the sacrificial layer self-aligned process (SLSA) to prepare the outer base region conductive layer in segments, which simplifies the connection process between the base region germanium-silicon layer and the outer base region conductive layer, reduces the fabrication difficulty, and improves the device fabrication efficiency.

[0104] Furthermore, this application first forms a sacrificial layer on the isolation layer, then forms a germanium-silicon layer in the sacrificial layer through a bottom-up epitaxial process, then removes the sacrificial layer in segments, and firstly epitaxially forms a first segment of the outer base region conductive layer (first polysilicon layer) at the location of the sacrificial layer from bottom to top, and finally epitaxially forms a second segment of the outer base region conductive layer (third polysilicon layer), thus forming the outer base region conductive layer in segments. The fabrication process of this application is completely different from the traditional process of first forming the outer base region polysilicon layer and then forming the germanium-silicon layer. The fabrication process of this application can obtain a germanium-silicon layer and an outer base region conductive layer (first polysilicon layer) with good crystal quality through a bottom-up epitaxial process, reducing crystal defects in the germanium-silicon layer and the outer base region conductive layer, reducing the connection resistance between the outer base region and the base region, and improving device performance.

[0105] Finally, perform step S14: as follows Figure 17 As shown, Figure 17 This is a schematic diagram of the semiconductor structure after removing the third dielectric layer from the upper surface of the second polysilicon layer 80 according to an embodiment of the present invention. The third dielectric layer 90 on the upper surface of the second polysilicon layer 80 has been removed. The remaining third dielectric layer 90 covers the side surface of the second polysilicon layer 80 and the exposed side surface of the final second dielectric layer 70.

[0106] Based on the same inventive concept, and referring to Figure 17 This application also provides a germanium-silicon heterojunction transistor, comprising:

[0107] A substrate 10, in which trenches are formed, an isolation layer 20 is formed in the trenches, and a second opening 202 is formed in the substrate 10 between the isolation layers 20;

[0108] A germanium-silicon layer 40, wherein the germanium-silicon layer 40 fills the second opening 202;

[0109] A first polysilicon layer 60, wherein a first opening 201 is formed between the first polysilicon layers 60;

[0110] A first dielectric layer 50, the first dielectric layer 60 covers the first polysilicon layer 50 and fills the first opening 201;

[0111] A second dielectric layer 70 covers the first dielectric layer 50, wherein a third opening 203 is formed in both the first dielectric layer 50 and the second dielectric layer 70;

[0112] The second polysilicon layer 80 fills the third opening 203 and covers a portion of the second dielectric layer 70.

[0113] A third dielectric layer 90 covers the sides of the second polysilicon layer 80 and the remaining second dielectric layer 70, wherein a fifth opening 205 is formed between the third dielectric layer 90 and the isolation layer 20; and

[0114] A third polysilicon layer 61 covers a portion of the isolation layer 20 near the first polysilicon layer 60 and fills the fifth opening 205, wherein the third polysilicon layer 61 and the first polysilicon layer 60 constitute an outer base region conductive layer.

[0115] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A method for fabricating a germanium-silicon heterojunction transistor, characterized in that, include: A substrate is provided, in which trenches are formed, an isolation layer is formed on the surface of the substrate and in the trenches, a sacrificial layer is formed on the isolation layer, and a first opening is formed in the sacrificial layer; Remove the insulating layer on the substrate surface at the bottom of the first opening to form a second opening; A germanium-silicon layer is formed, the germanium-silicon layer filling the second opening; A first dielectric layer is formed, which covers the sacrificial layer and fills the first opening. At this time, a third opening is formed on the surface of the first dielectric layer located on the first opening. Etch the first dielectric layer and the sacrificial layer on both sides of the germanium-silicon layer to the surface of the isolation layer; Remove the remaining sacrificial layer from the surface of the germanium-silicon layer. At this time, a fourth opening is formed between the first dielectric layer and the germanium-silicon layer. A first polysilicon layer is formed, and the first polysilicon layer fills the fourth opening; A second dielectric layer is formed, which covers the side surface of the first polysilicon, the isolation layer, and the first dielectric layer; Remove a portion of the second dielectric layer and a portion of the first dielectric layer vertically downward from the third opening location; A second polysilicon layer is formed, which fills the third opening and covers the second dielectric layer above the germanium-silicon layer; A third dielectric layer is formed, which covers the second polysilicon layer and a portion of the second dielectric layer; The second dielectric layer on the surface of the isolation layer is removed, at which point a fifth opening is formed between the third dielectric layer and the isolation layer; A third polysilicon layer is formed, the third polysilicon layer covering a portion of the isolation layer adjacent to the first polysilicon layer, and filling the fifth opening, wherein the third polysilicon layer and the first polysilicon layer constitute an outer base region conductive layer; and Remove the third dielectric layer from the upper surface of the second polysilicon layer.

2. The method for fabricating a germanium-silicon heterojunction transistor according to claim 1, characterized in that, The germanium-silicon layer is formed from bottom to top using a selective epitaxial process.

3. The method for fabricating a germanium-silicon heterojunction transistor according to claim 1, characterized in that, The step of removing a portion of the second dielectric layer and a portion of the first dielectric layer vertically downward from the third opening location includes: Using a dry etching process, a portion of the second dielectric layer is removed vertically downwards from the third opening location to the surface of the first dielectric layer; and A portion of the first dielectric layer is removed from the surface of the germanium-silicon layer by etching vertically downwards from the third opening using a wet etching process.

4. The method for fabricating a germanium-silicon heterojunction transistor according to claim 1, characterized in that, The first polycrystalline silicon layer is formed from bottom to top using a selective growth process.

5. The method for fabricating a germanium-silicon heterojunction transistor according to claim 1, characterized in that, The third polycrystalline silicon layer is formed from the inside out using a selective growth process.

6. The method for fabricating a germanium-silicon heterojunction transistor according to claim 1, characterized in that, The isolation layer, the first dielectric layer, and the third dielectric layer are all made of silicon oxide.

7. The method for fabricating a germanium-silicon heterojunction transistor according to claim 1, characterized in that, Both the sacrificial layer and the second dielectric layer are made of silicon nitride.

8. A germanium-silicon heterojunction transistor, characterized in that, include: A substrate in which trenches are formed, an isolation layer is formed in the trenches, and a second opening is formed in the substrate between the isolation layers; A germanium-silicon layer, wherein the germanium-silicon layer fills the second opening; A first polysilicon layer, wherein a first opening is formed between the first polysilicon layers; A first dielectric layer, the first dielectric layer covering the first polysilicon layer and filling the first opening; A second dielectric layer covers the first dielectric layer, wherein a third opening is formed in both the first dielectric layer and the second dielectric layer; A second polysilicon layer, the second polysilicon layer filling the third opening and covering a portion of the second dielectric layer; A third dielectric layer, the third dielectric layer covering the sidewalls of the second polysilicon layer and the remainder of the second dielectric layer, wherein a fifth opening is formed between the third dielectric layer and the isolation layer; and A third polysilicon layer covers a portion of the isolation layer adjacent to the first polysilicon layer and fills the fifth opening, wherein the third polysilicon layer and the first polysilicon layer constitute an outer base region conductive layer.

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