Method for manufacturing a semiconductor device

Abstract

A method of fabricating a semiconductor device includes forming a gate structure on a III-V compound semiconductor layer. A gate silicide layer and a source / drain silicide layer are formed by an annealing fabrication process. The gate silicide layer is formed on the gate structure, the source / drain silicide layer is formed on the III-V compound semiconductor layer, and a material composition of the gate silicide layer is different from a material composition of the source / drain silicide layer.

Description

Technical Field

[0001] This invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device comprising a III-V compound semiconductor layer. Background Technology

[0002] III-V compound semiconductors, due to their semiconductor properties, can be used to form many types of integrated circuit devices, such as high-power field-effect transistors (FETs), high-frequency transistors, or high electron mobility transistors (HEMTs). In HEMTs, two semiconductor materials with different band gaps are combined at a junction to form a heterojunction, providing a channel for charge carriers. In recent years, gallium nitride (GaN) series materials have become suitable for high-power and high-frequency products due to their wide band gap and high saturation velocity. GaN series HEMTs generate a two-dimensional electron gas (2DEG) through the piezoelectric effect of the material itself, which has high electron velocity and density, thus increasing switching speed. Furthermore, III-V compound semiconductor transistors have many different structural designs to meet different product requirements, which complicates the corresponding fabrication processes and negatively impacts production yield and / or production costs. Summary of the Invention

[0003] This invention provides a method for fabricating a semiconductor device, which utilizes an annealing process to simultaneously form gate silicide layers and source / drain silicide layers with different material compositions, thereby achieving a simplified fabrication process.

[0004] An embodiment of the present invention provides a method for fabricating a semiconductor device, comprising the following steps: forming a gate structure on a III-V compound semiconductor layer; forming a gate silicide layer and a source / drain silicide layer by an annealing process. The gate silicide layer is formed on the gate structure, the source / drain silicide layer is formed on the III-V compound semiconductor layer, and the material composition of the gate silicide layer is different from the material composition of the source / drain silicide layer. Attached Figure Description

[0005] Figures 1 to 8 This is a schematic diagram of a method for fabricating a semiconductor device according to an embodiment of the present invention, wherein...

[0006] Figure 2 for Figure 1 A diagram illustrating the subsequent situation;

[0007] Figure 3 for Figure 2A diagram illustrating the subsequent situation;

[0008] Figure 4 for Figure 3 A diagram illustrating the subsequent situation;

[0009] Figure 5 for Figure 4 A diagram illustrating the subsequent situation;

[0010] Figure 6 for Figure 5 A diagram illustrating the subsequent situation;

[0011] Figure 7 for Figure 6 A diagram illustrating the subsequent situation;

[0012] Figure 8 for Figure 7 A diagram illustrating the subsequent situation.

[0013] Explanation of main component symbols

[0014] 10 base

[0015] 10B Bottom Surface

[0016] 10T upper surface

[0017] 12 III-V compound semiconductor layers

[0018] 14 III-V compound barrier layer

[0019] 20 Gate material layer

[0020] 20G gate structure

[0021] 32 First metal layer

[0022] 32P Metal Pattern

[0023] 34 First silicon layer

[0024] 34P Silicon Pattern

[0025] 36 Gate silicide layer

[0026] 40 passivation layer

[0027] 52 Second silicon layer

[0028] 54 Second metal layer

[0029] 56 Source / Drain Silice Layer

[0030] 56A First source / drain silicide layer

[0031] 56B Second source / drain silicide layer

[0032] 60 dielectric layers

[0033] 80 Patterned mask layers

[0034] 91 Patterning process

[0035] 91S Etching Steps

[0036] 92 Annealing process

[0037] 101 Semiconductor Device

[0038] CT1 contact structure

[0039] CT2 contact structure

[0040] CT3 contact structure

[0041] D1 Vertical direction

[0042] D2 Horizontal direction

[0043] OP opening Detailed Implementation

[0044] The following detailed description of the invention discloses sufficient detail to enable those skilled in the art to practice it. The embodiments described below should be considered illustrative rather than restrictive. It will be apparent to those skilled in the art that various changes and modifications in form and detail can be made without departing from the spirit and scope of the invention.

[0045] Before further describing the various embodiments, the following explanation will focus on the specific terms used throughout the text.

[0046] The meanings of the terms “on,” “above,” and “on top of” should be interpreted in the broadest sense, such that “on” means not only “directly on” something but also includes something with other intervening features or layers in between, and that “above” or “on top of” means not only “above” or “on top of” something but can also include something “above” or “on top of” without other intervening features or layers in between (i.e., directly on something).

[0047] The ordinal numbers used in the specification and claims, such as "first" and "second", are used to modify the elements of the claims. Unless otherwise specified, they do not imply or represent any prior ordinal number of the claimed element, nor do they represent the order of one claimed element with another, or the order of manufacturing methods. The use of these ordinal numbers is only to enable a claim element with a certain name to be clearly distinguished from another claim element with the same name.

[0048] The term "etching" is generally used herein to describe a fabrication process for patterning material such that at least a portion of the material is left after etching. When a material is "etched," at least a portion of the material is retained after etching. Conversely, when a material is "removed," essentially all of the material can be removed during the process. However, in some embodiments, "removal" can be considered a broad term to include etching.

[0049] The terms “forming” or “setting” are used below to describe the behavior of applying a layer of material to a substrate. These terms are intended to describe any feasible layer forming technique, including but not limited to thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, etc.

[0050] Please see Figures 1 to 8 . Figures 1 to 8 The illustration is a schematic diagram of a method for fabricating a semiconductor device according to an embodiment of the present invention, wherein... Figure 2 It is illustrated Figure 1 A diagram illustrating the subsequent situation. Figure 3 It is illustrated Figure 2 A diagram illustrating the subsequent situation. Figure 4 It is illustrated Figure 3 A diagram illustrating the subsequent situation. Figure 5 It is illustrated Figure 4 A diagram illustrating the subsequent situation. Figure 6 It is illustrated Figure 5 A diagram illustrating the subsequent situation. Figure 7 It is illustrated Figure 6 The following is a diagram illustrating the situation, and Figure 8 It is illustrated Figure 7 A diagram illustrating the subsequent situation. (See example.) Figure 8 As shown, the method for fabricating the semiconductor device 101 in this embodiment may include the following steps: A gate structure 20G is formed on a III-V compound semiconductor layer 12. Then, a gate silicide layer 36 and a source / drain silicide layer 56 are formed by an annealing process. The gate silicide layer 36 is formed on the gate structure 20G, and the source / drain silicide layer 56 is formed on the III-V compound semiconductor layer 12, and the material composition of the gate silicide layer 36 is different from that of the source / drain silicide layer 56. By forming the gate silicide layer 36 and the source / drain silicide layer 56 with different material compositions in the same annealing process, the number of annealing processes can be reduced and / or the negative impact of the annealing process on the semiconductor device can be reduced, thus achieving the effect of simplifying the fabrication process and / or improving the electrical performance of the semiconductor device.

[0051] To further explain, the method for fabricating the semiconductor device of the present invention may include, but is not limited to, the following steps. For example... Figure 1As shown, a III-V compound semiconductor layer 12, a III-V compound barrier layer 14, a gate material layer 20, a first metal layer 32, and a first silicon layer 34 can be sequentially formed on a substrate 10. In other words, the gate material layer 20 can be considered as being formed on the III-V compound semiconductor layer 12 in a vertical direction D1, the first metal layer 32 can be considered as being formed on the gate material layer 20 in a vertical direction D1, and the first silicon layer 34 can be considered as being formed on the first metal layer 32 in a vertical direction D1. The substrate 10 may include a silicon substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, a sapphire substrate, or a substrate formed of other suitable materials. In some embodiments, a buffer layer (not shown) may be formed on the substrate 10 before forming the III-V compound semiconductor layer 12. The buffer layer may include, for example, gallium nitride, aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), or other suitable buffer materials, but is not limited thereto. In other words, the buffer layer may be located between the substrate 10 and the III-V compound semiconductor layer 12 in the vertical direction D1.

[0052] In some embodiments, the III-V compound semiconductor layer 12 may include gallium nitride, indium gallium nitride (InGaN), or other suitable III-V compound semiconductor materials, and the III-V compound barrier layer 14 may include aluminum gallium nitride, aluminum indium nitride, aluminum gallium indium nitride, aluminum nitride (AlN), or other suitable III-V compound materials. In some embodiments, the gate material layer 20 may include a p-type doped III-V compound material, such as p-type doped aluminum gallium nitride, p-type doped gallium nitride, or other suitable p-type doped III-V compound materials, but is not limited thereto. Furthermore, the p-type dopant in the p-type doped III-V compound material may include cyclopentadienyl magnesium (Cp2Mg), magnesium, beryllium (Be), zinc (Zn), combinations of the above materials, or other suitable p-type dopant. Furthermore, the first metal layer 32 and the first silicon layer 34 can be used to form the aforementioned gate silicide layer. Therefore, the material of the first metal layer 32 can be adjusted according to the material composition of the gate silicide layer to be formed. For example, the first metal layer 32 may include nickel, cobalt, platinum, or other suitable metal materials, while the first silicon layer 34 may be a pure silicon layer, such as a monocrystalline silicon layer, a polycrystalline silicon layer, an amorphous silicon layer, or other silicon layers with different structures, but is not limited thereto.

[0053] In some embodiments, the vertical direction D1 can be considered as the thickness direction of the substrate 10. The substrate 10 may have an upper surface 10T and a bottom surface 10B opposite each other in the vertical direction D1. The III-V compound semiconductor layer 12, the III-V compound barrier layer 14, the gate material layer 20, the first metal layer 32, and the first silicon layer 34 may be formed on one side of the upper surface 10T. Horizontal directions that are substantially orthogonal to the vertical direction D1 (e.g., horizontal direction D2 and other directions orthogonal to the vertical direction D1) may be substantially parallel to the upper surface 10T and / or the bottom surface 10B of the substrate 10, but are not limited thereto. In this document, the distance in the vertical direction D1 between a relatively high position and / or between a component and the bottom surface 10B of the substrate 10 may be greater than the distance in the vertical direction D1 between a relatively low position and / or between a component and the bottom surface 10B of the substrate 10. The lower part or bottom of each component may be closer to the bottom surface 10B of the substrate 10 in the vertical direction D1 than the upper part or top of the component. Another component above a component may be considered to be relatively far from the bottom surface 10B of the substrate 10 in the vertical direction D1, while another component below a component may be considered to be relatively close to the bottom surface 10B of the substrate 10 in the vertical direction D1.

[0054] like Figures 1 to 3 As shown, after the first silicon layer 34 is formed, a patterning process 91 can be performed on the first silicon layer 34, the first metal layer 32, and the gate material layer 20 to form a silicon pattern 34P, a metal pattern 32P, and a gate structure 20G, respectively. In some embodiments, after the first silicon layer 34 is formed, a patterning mask layer 80 can be formed on the first silicon layer 34, and the patterning process 91 can be performed using the patterning mask layer 80, but this is not a limitation. Furthermore, the patterning process 91 may include one or more etching steps to etch the first silicon layer 34, the first metal layer 32, and the gate material layer 20, respectively, thereby forming the silicon pattern 34P, the metal pattern 32P, and the gate structure 20G. For example, after the first silicon layer 34 is patterned by the patterning process 91 to become the silicon pattern 34P, an etching step 91S can be performed using the silicon pattern 34P and / or the remaining patterning mask layer 80 as an etching mask to pattern the first metal layer 32 or the first metal layer 32 and the gate material layer 20. In some embodiments, the patterned mask layer 80 may be removed before the etching step 91S or etched during the etching step 91S and no longer located on the silicon pattern 34P. Therefore, the etching step 91S can be considered as an etching step using the silicon pattern 34P as an etching mask, but is not limited thereto. In other words, the patterning fabrication process 91 includes an etching step 91S using the silicon pattern 34P as an etching mask, and the first metal layer 32 may be etched by the etching step 91S to become the metal pattern 32P.

[0055] It is worth noting that the method used in this invention to form the gate structure 20G, the metal pattern 32P, and the silicon pattern 34P may include, but is not limited to, the steps described above. In other words, other suitable methods can be used to form, such as... Figure 3 The diagram illustrates the gate structure 20G, metal pattern 32P, and silicon pattern 34P. Furthermore, when the first silicon layer 34, the first metal layer 32, and the gate material layer 20 are patterned by the patterning fabrication process 91 to become the silicon pattern 34P, the metal pattern 32P, and the gate structure 20G, respectively, the shape and / or area of ​​the projected patterns of the silicon pattern 34P, the metal pattern 32P, and the gate structure 20G in the vertical direction D1 may be substantially the same as each other, but are not limited thereto. Moreover, the material composition of the silicon pattern 34P, the metal pattern 32P, and the gate structure 20G may be the same as the material composition of the first silicon layer 34, the first metal layer 32, and the gate material layer 20, respectively. The metal pattern 32P can be considered to be formed on the gate structure 20G, and the silicon pattern 34P can be considered to be formed on the metal pattern 32P. After forming the gate structure 20G, the metal pattern 32P, and the silicon pattern 34P, a passivation layer 40 may be formed to cover the gate structure 20G, the metal pattern 32P, the silicon pattern 34P, the III-V compound barrier layer 14, and the III-V compound semiconductor layer 12. The passivation layer 40 may include silicon oxide, silicon nitride, tetraethoxysilane (TEOS), or other suitable insulating materials.

[0056] like Figures 4 to 6As shown, after the passivation layer 40 is formed, an annealing process 92 can be performed. The passivation layer 40 can cover the gate structure 20G, metal pattern 32P, silicon pattern 34P, III-V compound barrier layer 14, and III-V compound semiconductor layer 12 during the annealing process 92. The metal pattern 32P and silicon pattern 34P can be transformed into a gate silicide layer 36 through the annealing process 92. In some embodiments, the annealing process 92 may include rapid thermal processing (RTP) or other suitable thermal processing methods. In some embodiments, the gate silicide layer 36 may include nickel silicide, cobalt silicide, platinum silicide, or other suitable conductive silicide materials. Furthermore, the methods used to form the gate silicide layer 36 in this invention may include, but are not limited to, the methods described above for forming the metal pattern 32P and silicon pattern 34P. In other words, in some embodiments, the gate silicide layer 36 may also be formed using other material layers through the annealing process 92, depending on design requirements. Furthermore, in some embodiments, prior to the annealing process 92, an opening OP can be formed through a passivation layer 40 on the III-V compound semiconductor layer 12. After the opening OP is formed, a second silicon layer 52 can be formed, and a second metal layer 54 can be formed on the second silicon layer 52. At least a portion of the second silicon layer 52 can be formed in the opening OP, and the second silicon layer 52 and the second metal layer 54 can be transformed into source / drain silicide layers 56 by the annealing process 92.

[0057] In some embodiments, the material of the second metal layer 54 may be adjusted according to the material composition of the source / drain silicide layer 56 to be formed. For example, the source / drain silicide layer 56 may include titanium silicide, tantalum silicide, titanium aluminum silicide, or other suitable conductive silicide materials, and the second metal layer 54 may therefore include titanium, tantalum, titanium aluminum alloy, or other suitable metal materials, while the second silicon layer 52 may be a pure silicon layer, such as a monocrystalline silicon layer, a polycrystalline silicon layer, an amorphous silicon layer, or other structured silicon layer, but is not limited thereto. In other words, since the material composition of the gate silicide layer 36 is different from the material composition of the source / drain silicide layer 56, the material composition of the metal pattern 32P (that is, the material composition of the first metal layer 32) is also different from the material composition of the second metal layer 54. In some embodiments, the second silicon layer 52 may be conformally formed on the passivation layer 40 and conformally formed in the opening OP, while the second metal layer 54 may be conformally formed on the second silicon layer 52, but is not limited thereto. Furthermore, the second silicon layer 52 may also be formed on the passivation layer 40 located above the gate structure 20G. Therefore, after the annealing process, the source / drain silicide layer 56 may also be formed on the passivation layer 40 located above the gate structure 20G, but this is not a limitation.

[0058] In some embodiments, the fabrication process temperature for transforming the metal pattern 32P and silicon pattern 34P into the gate silicide layer 36 may be substantially equal to or lower than the fabrication process temperature for transforming the second silicon layer 52 and the second metal layer 54 into the source / drain silicide layer 56, thereby allowing the annealing process 92 to be used to simultaneously form the gate silicide layer 36 and the source / drain silicide layer 56. For example, the fabrication process temperature of the annealing process 92 may be between 550 degrees Celsius and 650 degrees Celsius, but is not limited thereto. Furthermore, the methods used in this invention to form the source / drain silicide layer 56 may include, but are not limited to, the methods described above for forming the second silicon layer 52 and the second metal layer 54. In other words, in some embodiments, the source / drain silicide layer 56 may also be formed using other material layers through the annealing process 92, depending on design requirements.

[0059] like Figures 5 to 7 As shown, after the annealing process 92, the source / drain silicide layer 56 and other portions of the source / drain silicide layer 56 formed on the passivation layer 40 above the gate structure 20G can be removed to form a first source / drain silicide layer 56A and a second source / drain silicide layer 56B. In some embodiments, openings OP can be formed on two opposite sides of the gate structure 20G in the horizontal direction D2, and the first source / drain silicide layer 56A and the second source / drain silicide layer 56B can be at least partially disposed in the corresponding openings OP. Therefore, the first source / drain silicide layer 56A and the second source / drain silicide layer 56B can be disposed on two opposite sides of the gate structure 20G in the horizontal direction D2, but this is not a limitation. In some embodiments, the aperture OP may also penetrate the III-V compound barrier layer 14, so the source / drain silicide layer 56 (e.g., the first source / drain silicide layer 56A and the second source / drain silicide layer 56B) can directly contact the III-V compound semiconductor layer 12, but this is not a limitation. In some embodiments, the aperture OP may only penetrate the passivation layer 40 and not the III-V compound barrier layer 14, so a portion of the III-V compound barrier layer 14 may be located between the source / drain silicide layer 56 and the III-V compound semiconductor layer 12 in the vertical direction D1.

[0060] like Figure 8As shown, after the first source / drain silicide layer 56A and the second source / drain silicide layer 56B are formed, a dielectric layer 60 can be formed to cover the passivation layer 40, the first source / drain silicide layer 56A, and the second source / drain silicide layer 56B. Contact structures CT1, CT2, and CT3 can be formed corresponding to the gate silicide layer 36, the first source / drain silicide layer 56A, and the second source / drain silicide layer 56B, respectively. Contact structure CT1 can penetrate the dielectric layer 60 and the passivation layer 40 on the gate silicide layer 36 in the vertical direction D1 to form an electrical connection with the gate silicide layer 36. Contact structure CT2 can penetrate the dielectric layer 60 on the first source / drain silicide layer 56A in the vertical direction D1 to form an electrical connection with the first source / drain silicide layer 56A. The contact structure CT3 can penetrate the dielectric layer 60 located on the second source / drain silicide layer 56B in the vertical direction D1 to form an electrical connection with the second source / drain silicide layer 56B. In some embodiments, the dielectric layer 60 may include a single layer or multiple layers of dielectric material, such as oxide dielectric material or other suitable dielectric material, and each contact structure may include a barrier layer (not shown) and a metal layer (not shown) disposed on the barrier layer, but is not limited thereto. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride or other suitable barrier materials, and the metal layer may include tungsten, copper, aluminum, titanium-aluminum alloy or other suitable metal materials.

[0061] Using the above manufacturing method, a product can be formed as follows: Figure 8The semiconductor device 101 shown may include the substrate 10, the III-V compound semiconductor layer 12, the III-V compound barrier layer 14, the gate structure 20G, the gate silicide layer 36, the passivation layer 40, the first source / drain silicide layer 56A, the second source / drain silicide layer 56B, the dielectric layer 60, the contact structure CT1, the contact structure CT2, and the contact structure CT3. In some embodiments, the contact structure CT1 may be considered as the gate electrode, the contact structure CT2 may be considered as the source electrode, and the contact structure CT3 may be considered as the drain electrode, but this is not a limitation. Conversely, the gate silicide layer 36 may be considered as the contact pad of the gate electrode, the first source / drain silicide layer 56A may be considered as the contact pad of the source electrode, and the second source / drain silicide layer 56B may be considered as the contact pad of the drain electrode. The gate silicide layer 36 can be used to form a Schottky contact, while the source / drain silicide layer 56 can be used to form an ohmic contact. Therefore, the material composition of the gate silicide layer 36 is different from that of the source / drain silicide layer 56. The work function of the source / drain silicide layer 56 can be relatively low to meet the requirements of the ohmic contact. Therefore, the work function of the gate silicide layer 36 can be higher than that of the source / drain silicide layer 56, but this is not a limitation.

[0062] In summary, in the semiconductor device fabrication method of the present invention, gate silicide layers and source / drain silicide layers with different material compositions can be formed simultaneously using an annealing process. This reduces the number of annealing processes and / or the negative impact of annealing on the semiconductor device, thus achieving the effects of simplifying the fabrication process and / or improving the electrical performance of the semiconductor device.

[0063] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, comprising: A gate structure is formed on a III-V compound semiconductor layer; as well as A gate silicide layer and a source / drain silicide layer are formed by an annealing process, wherein the gate silicide layer is formed on the gate structure, the source / drain silicide layer is formed on the III-V compound semiconductor layer, and the material composition of the gate silicide layer is different from that of the source / drain silicide layer. The metal material layer and the silicon material layer are converted into silicides in the same annealing process to form the gate silicide layer and the source / drain silicide layer; The method for forming the gate silicide layer includes: A metal pattern is formed on the gate structure; A silicon pattern is formed on the metal pattern; and A passivation layer is formed covering the gate structure, the metal pattern, the silicon pattern, and the III-V compound semiconductor layer, wherein, The annealing process is performed after the passivation layer is formed, and the metal pattern and the silicon pattern are transformed into the gate silicide layer through the annealing process.

2. The method for fabricating a semiconductor device as claimed in claim 1, wherein the work function of the gate silicide layer is higher than the work function of the source / drain silicide layer.

3. The method for fabricating a semiconductor device as claimed in claim 1, wherein the gate silicide layer comprises nickel silicide, cobalt silicide, or platinum silicide.

4. The method for fabricating a semiconductor device as claimed in claim 1, wherein the source / drain silicide layer comprises titanium silicide, tantalum silicide, or aluminum titanium silicide.

5. The method of fabricating a semiconductor device as claimed in claim 1, wherein the passivation layer covers the gate structure, the metal pattern, the silicon pattern, and the III-V compound semiconductor layer in the annealing process.

6. The method of fabricating a semiconductor device as claimed in claim 1, wherein the method of forming the gate structure, the metal pattern, and the silicon pattern comprises: A gate material layer is formed on the III-V compound semiconductor layer; A first metal layer is formed on the gate material layer; A first silicon layer is formed on the first metal layer; as well as The first silicon layer, the first metal layer, and the gate material layer are patterned.

7. The method for fabricating a semiconductor device as claimed in claim 6, wherein the first silicon layer, the first metal layer, and the gate material layer are patterned by the patterning fabrication process to become the silicon pattern, the metal pattern, and the gate structure, respectively.

8. The method for fabricating a semiconductor device as claimed in claim 6, wherein the patterning process includes an etching step using the silicon pattern as an etching mask, and the first metal layer is etched by the etching step to form the metal pattern.

9. The method of fabricating a semiconductor device as claimed in claim 1, wherein the method of forming the source / drain silicide layer comprises: An opening is formed that penetrates the passivation layer on the III-V compound semiconductor layer; A second silicon layer is formed, wherein at least a portion of the second silicon layer is formed in the opening; as well as A second metal layer is formed on the second silicon layer, wherein the second silicon layer and the second metal layer are transformed into the source / drain silicide layer by the annealing process.

10. The method of fabricating a semiconductor device as claimed in claim 9, wherein the second silicon layer is further formed on the passivation layer located above the gate structure.

11. The method of fabricating a semiconductor device as claimed in claim 9, wherein the source / drain silicide layer is further formed on the passivation layer located above the gate structure, and the source / drain silicide layer formed on the passivation layer located above the gate structure is removed after the annealing fabrication process.

12. The method of fabricating a semiconductor device as claimed in claim 9, wherein the material composition of the metal pattern is different from the material composition of the second metal layer.

13. The method of fabricating a semiconductor device as claimed in claim 9, wherein the second silicon layer is conformally formed on the passivation layer and conformally formed in the opening.

14. The method of fabricating a semiconductor device as claimed in claim 9, wherein the second metal layer is conformally formed on the second silicon layer.

15. The method of fabricating a semiconductor device as claimed in claim 1, wherein the gate structure comprises a P-type doped III-V compound material.

16. The method for manufacturing a semiconductor device as claimed in claim 1, wherein the manufacturing process temperature of the annealing process is between 550 degrees Celsius and 650 degrees Celsius.

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