Semiconductor fabrication method and semiconductor structure

Abstract

This invention provides a semiconductor fabrication method and semiconductor structure. The method includes: forming a first dielectric layer on the surface of a P-type gallium nitride (GaN); etching the first dielectric layer to form a gate pattern; forming a second dielectric layer; performing maskless etching on the second dielectric layer to leave second dielectric layer residues on both sides of the gate pattern; forming a source and a drain on a passivation layer on the surface of the region containing aluminum gallium nitride (GaN), with the source and drain connected to GaN through contact holes; etching the gate pattern and forming gate metal filling holes until the P-type GaN is exposed; forming gate metal within the gate metal filling holes to form the gate; forming a third dielectric layer; and forming a back-end metal interconnect on the third dielectric layer. This method addresses the defect in the prior art where byproduct contaminants are easily adsorbed at the interface of the GaN epitaxial layer, thereby improving the reliability of GaN semiconductor devices.

Description

Technical Field

[0001] This invention relates to the field of semiconductor process technology, and in particular to a semiconductor fabrication method and semiconductor structure. Background Technology

[0002] Gallium nitride (GaN) is a III-V compound semiconductor composed of gallium and nitrogen atoms. Unlike traditional semiconductor materials such as silicon and germanium, gallium nitride semiconductors have advantages such as high electron mobility and high thermal conductivity, and therefore have wide applications in chemistry, electronics, optics and other fields.

[0003] A typical gallium nitride (GaN) semiconductor device, from bottom to top, consists of: a gallium nitride epitaxial layer, a source / drain electrode, a gate electrode, a passivation layer, and a field plate metal layer. The gallium nitride epitaxial layer, from bottom to top, includes: a silicon (Si) substrate, a gallium nitride (GaN) layer, an aluminum gallium nitride (AlGaN) layer, and a p-type gallium nitride (P-GaN) layer.

[0004] Current gate fabrication processes for gallium nitride (GaN) semiconductor devices primarily involve the following steps: 1. Deposition of the gate metal and dielectric layer; 2. Photolithography to define the gate metal pattern; 3. Dry etching of the gate metal and P-type GaN; 4. Wet etching to form the gate structure. However, the acid-base reaction process used in wet etching easily introduces byproduct contaminants that adsorb onto the aluminum gallium nitride (AlGaN), P-type GaN, or gate surface at the GaN epitaxial layer interface. Furthermore, wet etching can damage the metal gate, affecting the reliability of GaN semiconductor devices. Summary of the Invention

[0005] This invention provides a gate fabrication method to address the defect in the prior art where byproduct contaminants are easily adsorbed at the interface of gallium nitride epitaxial layers, thereby improving the reliability of gallium nitride semiconductor devices.

[0006] This invention provides a semiconductor fabrication method, comprising:

[0007] A first dielectric layer is formed on the surface of a P-type gallium nitride, and the first dielectric layer is etched to form a gate pattern;

[0008] A second dielectric layer is formed, and the second dielectric layer is etched without a mask to leave a second dielectric layer residue on both sides of the gate pattern. The P-type gallium nitride in the area not covered by the second dielectric layer is etched away to expose aluminum gallium nitride.

[0009] A passivation layer is formed, and a source and a drain are formed on the passivation layer on the surface of the region where aluminum gallium nitride is located. The source and the drain are connected to aluminum gallium nitride through contact holes.

[0010] The gate pattern is etched and a gate metal filling hole is formed until the P-type gallium nitride is exposed. Gate metal is formed in the gate metal filling hole to form the gate.

[0011] A third dielectric layer is formed, and the back metal interconnects of the source, drain and gate are formed on the third dielectric layer respectively.

[0012] According to a semiconductor fabrication method provided by the present invention, the step of forming a first dielectric layer on the surface of a P-type gallium nitride and etching the first dielectric layer to form a gate pattern includes:

[0013] A gallium nitride passivation layer is formed on the surface of a p-type gallium nitride;

[0014] A first dielectric layer is formed on the gallium nitride passivation layer by plasma-enhanced chemical vapor deposition.

[0015] The gate region is defined in the first dielectric layer by photolithography, and the area not covered by photoresist is etched by dry etching to form the gate pattern.

[0016] Clean the byproducts generated during gate etching.

[0017] According to a semiconductor fabrication method provided by the present invention, the step of forming a second dielectric layer, performing maskless etching on the second dielectric layer to form second dielectric layer residues on both sides of the gate pattern, and etching away P-type gallium nitride in areas not covered by the second dielectric layer to expose aluminum gallium nitride, includes:

[0018] The second dielectric layer was formed by plasma-enhanced chemical vapor deposition.

[0019] The second dielectric layer is etched without a mask to leave a second dielectric layer residue on both sides of the gate pattern.

[0020] The remaining second dielectric layer is used as a hard mask layer for P-type gallium nitride, and the P-type gallium nitride in the area not covered by the second dielectric layer is etched away.

[0021] According to a semiconductor fabrication method provided by the present invention, the width of the residual second dielectric layer is 60-70 nm.

[0022] According to a semiconductor fabrication method provided by the present invention, the step of forming a passivation layer and forming a source and a drain on the passivation layer on the surface of the region containing aluminum gallium nitride, wherein the source and drain are connected to aluminum gallium nitride through contact holes, comprising:

[0023] A strain layer is formed, and a passivation layer is formed in the strain layer;

[0024] Source contact holes and drain contact holes are formed in the source and drain regions of the passivation layer on the surface of the aluminum gallium nitride region, respectively.

[0025] Form a metal layer;

[0026] The metal layer is etched by photolithography to retain the stacked metal of the source and drain regions to form the source and drain. The source and drain are connected to aluminum gallium nitride through source contact holes and drain contact holes, respectively.

[0027] The source and drain electrodes are subjected to high-temperature annealing.

[0028] According to a semiconductor fabrication method provided by the present invention, the passivation layer has a thickness of 350-400 angstroms, and the metal layer is a stacked metal layer, which includes a bottom titanium metal, an interlayer aluminum metal, and a top titanium metal connected in sequence.

[0029] According to a semiconductor fabrication method provided by the present invention, the step of etching the gate pattern and forming a gate metal filling hole until P-type gallium nitride is exposed, and forming gate metal within the gate metal filling hole to form a gate, includes:

[0030] The gate pattern is etched using a photolithography process to expose the first dielectric layer within the gate pattern;

[0031] The first dielectric layer within the gate pattern is longitudinally etched using a wet etching solution to form gate metal filling holes until the P-type gallium nitride is exposed.

[0032] A gate metal layer is formed by magnetron sputtering, and the gate metal layer is etched by photolithography to form a gate in the gate pattern region.

[0033] According to a semiconductor fabrication method provided by the present invention, the step of forming a gate metal layer by magnetron sputtering and etching the gate metal layer by photolithography to form a gate in the gate pattern region includes:

[0034] A gate metal layer is formed by magnetron sputtering, and the gate metal layer is etched by photolithography to form a gate in the gate pattern region. A field plate structure is defined according to the gate to modulate the electric field strength from the drain to the gate.

[0035] According to a semiconductor fabrication method provided by the present invention, the material of the first dielectric layer is silicon oxide, the thickness of the first dielectric layer is 1000-1500 angstroms, the material of the second dielectric layer is silicon nitride, the thickness of the second dielectric layer is 800-1200 angstroms, and the material of the third dielectric layer is silicon oxide.

[0036] The present invention also provides a semiconductor structure comprising: aluminum gallium nitride, a gate step, a strain layer, a passivation layer, a gate, a source, and a drain;

[0037] The gate step includes: a P-type gallium nitride and a second dielectric layer, wherein the second dielectric layer is formed on the surface of the P-type gallium nitride and the P-type gallium nitride is formed at the gate position on the surface of aluminum gallium nitride.

[0038] The strain layer is formed on the surface of the second dielectric layer, the passivation layer is formed on the surface of the strain layer, the source and drain are formed on the surface of the passivation layer and are respectively connected to aluminum gallium nitride through contact holes. The passivation layer exposes P-type gallium nitride by etching to form a gate metal filling hole. Gate metal is formed in the gate metal filling hole to form a gate.

[0039] The third dielectric layer is formed on the gate metal surface, and the back metal interconnects of the source, drain and gate are formed on the third dielectric layer respectively.

[0040] This invention provides a semiconductor fabrication method that defines the gate pattern using a first dielectric layer to avoid introducing metal contamination sources. A second dielectric layer is then introduced to form residual second dielectric layers on both sides of the gate pattern, creating a step region between the gate pattern and P-type gallium nitride (GaN) to protect the GaN surface and prevent interface contamination during wet etching. After fabricating the source and drain electrodes, the gate pattern is etched using the wet etching selectivity of the different materials in the first and second dielectric layers to form gate metal filling holes until the P-type GaN is exposed. This achieves gate self-alignment, avoiding the introduction of byproduct contamination sources on the aluminum gallium nitride (AlGaN), P-type GaN, or gate surface. Gate metal is formed within the gate metal filling holes to form the gate. Simultaneously, the gate metal fabrication sequence is shifted to after epitaxial layer passivation, avoiding the contamination effect of metal ions on the epitaxial layer interface. This invention solves the defect in existing technologies where byproduct contamination sources easily adsorb at the GaN epitaxial layer interface, thereby improving the reliability of GaN semiconductor devices. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0042] Figure 1 This is a schematic flowchart of the semiconductor fabrication method provided by the present invention;

[0043] Figure 2 This is one of the process schematic diagrams of the semiconductor fabrication method provided by the present invention;

[0044] Figure 3 This is the second schematic diagram of the semiconductor fabrication method provided by the present invention;

[0045] Figure 4 This is the third schematic diagram of the semiconductor fabrication method provided by the present invention;

[0046] Figure 5 This is the fourth schematic diagram of the semiconductor fabrication method provided by the present invention.

[0047] Reference numerals: 1. First dielectric layer; 2. Second dielectric layer; 3. Third dielectric layer; 4. Gate; 5. Source; 6. Drain; 7. P-type gallium nitride; 8. Aluminum gallium nitride; 9. Gallium nitride; 10. Substrate; 11. Gallium nitride passivation layer; 12. Passivation layer; 13. Strain layer; 14. Gate metal. Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0049] The following is combined Figures 1-5 The semiconductor fabrication method of the present invention is described.

[0050] like Figure 1 As shown, the first embodiment of the present invention provides a semiconductor fabrication method, specifically including the following steps:

[0051] Step S1: Form a first dielectric layer 1 on the surface of P-type gallium nitride 7, and etch the first dielectric layer 1 to form a gate pattern.

[0052] First, a first dielectric layer 1 is formed on the surface of the P-type gallium nitride 7 epitaxial layer of gallium nitride 9. The first dielectric layer 1 is etched to form a gate pattern in order to avoid the introduction of metal contamination sources and to define the area for subsequent gate 4 processing.

[0053] Step S2: Form a second dielectric layer 2, perform maskless etching on the second dielectric layer 2 to leave the second dielectric layer 2 residue on both sides of the gate pattern, and etch away the P-type gallium nitride 7 in the area not covered by the second dielectric layer 2 to expose aluminum gallium nitride 8.

[0054] Then, a second dielectric layer 2 is formed, and the second dielectric layer 2 is etched without a mask to form a residue of the second dielectric layer 2 on both sides of the gate pattern. The P-type gallium nitride 7 in the area not covered by the second dielectric layer 2 is etched away to expose aluminum gallium nitride 8. The etching solution has different etching rates for the first dielectric layer 1 and the second dielectric layer 2 to form a step region with the gate pattern and the P-type gallium nitride 7 to protect the surface of the P-type gallium nitride 7 and avoid interface contamination introduced by the wet etching process. At this time, the gate pattern forms a composite gate 4 structure consisting of the dielectric layer and the P-type gallium nitride 7.

[0055] Step S3: Form a passivation layer 12, and form a source 5 and a drain 6 on the passivation layer 12 on the surface of the region where the aluminum gallium nitride 8 is located. The source 5 and the drain 6 are connected to the aluminum gallium nitride 8 through contact holes.

[0056] At this time, a passivation layer 12 is formed, and a source electrode 5 and a drain electrode 6 are formed on the passivation layer 12 on the surface of the region where the aluminum gallium nitride 8 is located, so as to prepare the source electrode 5 and the drain electrode 6, and the source electrode 5 and the drain electrode 6 are connected to the aluminum gallium nitride 8 through contact holes.

[0057] Step S4: Etch the gate pattern and form gate metal 14 filling holes until P-type gallium nitride 7 is exposed, and form gate metal 14 in the gate metal 14 filling holes to form gate 4.

[0058] After the source 5 and drain 6 are fabricated, the gate pattern is etched and the gate metal 14 filling hole is formed by using the wet etching selectivity of the different materials of the first dielectric layer 1 and the second dielectric layer 2 until the P-type gallium nitride 7 is exposed, so as to achieve the self-alignment of the gate 4 and avoid the introduction of by-product contamination sources on the surface of aluminum gallium nitride 8, P-type gallium nitride 7 or gate 4. The gate metal 14 is formed in the gate metal 14 filling hole to form the gate 4.

[0059] Step S5: Form a third dielectric layer 3, and form the rear metal interconnects of the source 5, drain 6 and gate 4 on the third dielectric layer 3 respectively.

[0060] Finally, a third dielectric layer 3 is formed, and source 5, drain 6 and gate 4 metal interconnects are formed on the third dielectric layer 3, respectively, to obtain the finished gallium nitride 9 semiconductor device.

[0061] This invention provides a semiconductor fabrication method that defines a gate pattern using a first dielectric layer 1 to avoid introducing metal contamination sources. A second dielectric layer 2 is then introduced, forming residues of the second dielectric layer 2 on both sides of the gate pattern, creating a step region between the gate pattern and the P-type gallium nitride (GaN) 7. This protects the surface of the P-type GaN 7 and prevents interface contamination during wet etching. After fabricating the source 5 and drain 6, the gate pattern is etched using the wet etching selectivity of the different materials in the first dielectric layer 1 and the second dielectric layer 2, forming gate metal 14 filling holes until the P-type GaN 7 is exposed. This achieves gate 4 self-alignment, avoiding the introduction of byproduct contamination sources on the surface of aluminum gallium nitride (AlGaN), P-type GaN 7, or gate 4. Gate metal 14 is formed within the gate metal 14 filling holes to form the gate 4. Simultaneously, the fabrication sequence of the gate metal 14 is shifted to after epitaxial layer passivation, avoiding the contamination effect of metal ions on the epitaxial layer interface. This invention solves the defect in the prior art where by-product contaminants are easily adsorbed at the interface of gallium nitride 9 epitaxial layer, thereby improving the reliability of gallium nitride 9 semiconductor devices.

[0062] In this embodiment, forming a first dielectric layer 1 on the surface of P-type gallium nitride 7 and etching the first dielectric layer 1 to form a gate pattern includes:

[0063] A gallium nitride passivation layer 11 is formed on the surface of p-type gallium nitride 7;

[0064] The first dielectric layer 1 is formed on the gallium nitride passivation layer 11 by plasma-enhanced chemical vapor deposition.

[0065] The gate region is defined in the first dielectric layer 1 by photolithography, and the non-photoresist-covered area is etched by dry etching to form the gate pattern.

[0066] Clean the byproducts generated during the etching of gate 4.

[0067] like Figure 2 As shown, Figure 2 (a) The gallium nitride 9 epitaxial layer to be processed includes, from bottom to top: substrate 10, gallium nitride 9, aluminum gallium nitride 8, and p-type gallium nitride 7. First, a gallium nitride passivation layer 11 is formed on the surface of the p-type gallium nitride 7. Then, a first dielectric layer 1 is formed on the gallium nitride passivation layer 11 using plasma-enhanced chemical vapor deposition. The result is as follows. Figure 2As shown in (b). The first dielectric layer 1 is made of silicon oxide with a thickness of 1000–1500 angstroms. The gate region is defined on the first dielectric layer 1 using a photolithography process with a photomask. The photoresist thickness is 10 k angstroms, and the exposure energy is 350–400 MJ / cm². The gate linewidth 4 can be modulated by the exposure energy, with a final target linewidth of 0.3 μm. Then, dry etching is used to etch the non-photoresist-covered areas to form the gate pattern. Organic byproducts are generated during this process. These byproducts are cleaned using a sulfuric acid mixture and water to remove surface impurities. The result is shown in [image / description]. Figure 2 As shown in (c). The above steps can avoid the problem of introducing metal contamination sources and define the area for subsequent gate 4 processing.

[0068] In this embodiment, the formation of the second dielectric layer 2 involves maskless etching of the second dielectric layer 2 to leave residues of the second dielectric layer 2 on both sides of the gate pattern, and etching away the P-type gallium nitride 7 in areas not covered by the second dielectric layer 2 to expose the aluminum gallium nitride 8.

[0069] The second dielectric layer 2 was formed by plasma-enhanced chemical vapor deposition.

[0070] The second dielectric layer 2 is etched without a mask to leave the second dielectric layer 2 residue on both sides of the gate pattern;

[0071] The remaining second dielectric layer 2 is used as a hard mask layer for P-type gallium nitride 7, and the P-type gallium nitride 7 in areas not covered by the second dielectric layer 2 is etched away.

[0072] like Figure 3 As shown in (a), a second dielectric layer 2 is formed by plasma-enhanced chemical vapor deposition. This second dielectric layer 2 uses a different material than the first dielectric layer 1, allowing for wet removal of the gate oxide in subsequent processes through different wet etching selectivity ratios, thereby filling the metal material to form the final gate 4 structure. In this embodiment, the material of the second dielectric layer 2 is silicon nitride, with a physical thickness ranging from 800 to 1200 angstroms. After the second dielectric layer 2 is deposited, it is directly etched using a maskless etching method. This results in residues of the second dielectric layer 2 forming on both sides of the gate pattern, creating a step region between the gate pattern and the P-type gallium nitride 7. This protects the surface of the P-type gallium nitride 7 and prevents interface contamination introduced during the wet etching process. The remaining second dielectric layer 2 is used as a hard mask layer for etching P-type gallium nitride 7. The P-type gallium nitride 7 areas not covered by the second dielectric layer 2 are etched away, thus forming a composite gate 4 structure consisting of an oxide dielectric layer and P-type gallium nitride 7. (After etching to form the residual structure, a portion of the second dielectric layer 2 will remain on top of the first dielectric layer 1; this portion will be etched away in subsequent processes and is not shown in the figure.) The result is as follows: Figure 3 As shown in (b).

[0073] In this embodiment, the width of the remaining second dielectric layer 2 is 60-70 nm.

[0074] The width of the remaining second dielectric layer 2 is controlled to be 60-70 nm, which is the overall width of the step formed by the gate oxide and P-type gallium nitride. This facilitates the etching of the P-type gallium nitride 7 as a hard mask layer, removing the P-type gallium nitride 7 in areas not covered by the second dielectric layer 2, thereby forming a composite gate 4 structure consisting of an oxide dielectric layer and P-type gallium nitride 7.

[0075] In this embodiment, the formation of a passivation layer 12, and the formation of a source 5 and a drain 6 on the passivation layer 12 on the surface of the region where the aluminum gallium nitride 8 is located, wherein the source 5 and the drain 6 are connected to the aluminum gallium nitride 8 through contact holes, includes:

[0076] A strain layer 13 is formed, and a passivation layer 12 is formed in the strain layer 13;

[0077] Source 5 contact holes and drain 6 contact holes are formed in the source 5 region and drain 6 region of the passivation layer 12 on the surface of the region where aluminum gallium nitride 8 is located, respectively.

[0078] Form a metal layer;

[0079] The metal layer is etched by photolithography to retain the stacked metal in the source 5 region and the drain 6 region to form the source 5 and the drain 6. The source 5 and the drain 6 are connected to the aluminum gallium nitride 8 through the source 5 contact hole and the drain 6 contact hole, respectively.

[0080] The source electrode 5 and the drain electrode 6 are subjected to high-temperature annealing.

[0081] like Figure 3 As shown in (c), a strain layer 13 is formed, followed by passivation to form a passivation layer 12. Source 5 contact holes and drain 6 contact holes are formed using photolithography, dry etching, and magnetron sputtering deposition processes, followed by the formation of a metal layer. The metal layer is then photolithographically and etched, retaining the stacked metal layers in the source 5 and drain 6 regions to form source 5 and drain 6. The photolithography process includes resist coating, exposure, and development, resulting in the final source 5 and drain 6. Source 5 and drain 6 are directly connected to aluminum gallium nitride 8 through source 5 contact holes and drain 6 contact holes, respectively. Finally, source 5 and drain 6 undergo high-temperature annealing to form alloy ohmic contacts, reducing resistance and repairing etching damage. The annealing temperature is 830–850°C, and the results are as follows. Figure 4 As shown in (a).

[0082] In this embodiment, the passivation layer 12 has a thickness of 350-400 angstroms, and the metal layer is a stacked metal layer, which includes a bottom titanium metal, an interlayer aluminum metal, and a top titanium metal connected in sequence.

[0083] The thickness of the passivation layer 12 is controlled to be 350–400 angstroms to adjust the overall profitability of the device. The metal layer is a stacked metal layer, comprising a bottom titanium layer, a sandwich aluminum layer, and a top titanium layer connected in sequence. The bottom titanium layer has a thickness of 180 angstroms, the sandwich aluminum layer has a thickness of 1400 angstroms, and the top titanium layer has a thickness of 200 angstroms. This stacked metal layer structure is used to adjust the overall stress distribution of the device while reducing contact resistance.

[0084] In this embodiment, etching the gate pattern and forming gate metal 14 filling holes until the P-type gallium nitride 7 is exposed, and forming gate metal 14 within the gate metal 14 filling holes to form gate 4, includes:

[0085] The gate pattern is etched using a photolithography process to expose the first dielectric layer 1 within the gate pattern;

[0086] The first dielectric layer 1 within the gate pattern is longitudinally etched using a wet etching solution to form gate metal 14 filling holes until the P-type gallium nitride 7 is exposed.

[0087] A gate metal layer 14 is formed by magnetron sputtering, and the gate metal layer 14 is etched by photolithography to form a gate 4 in the gate pattern region.

[0088] like Figure 4 As shown in (b), the gate region is etched using photolithography and dry etching to expose the first dielectric layer 1, i.e., the gate oxide, within the gate pattern. A wet etching solution is used to longitudinally etch the first dielectric layer 1 within the gate pattern and form gate metal 14 filling holes until P-type gallium nitride 7 is exposed, achieving gate 4 self-alignment and avoiding the introduction of byproduct contaminants on the surfaces of aluminum gallium nitride 8, P-type gallium nitride 7, or gate 4. In this embodiment, a diluted hydrofluoric acid solution is used for wet etching of the gate oxide for 30 seconds. Because the etching rate of hydrofluoric acid on the first dielectric layer 1 (silicon oxide) and the second dielectric layer 2 (silicon nitride) is different, silicon oxide is preferentially etched to form gate metal 14 filling holes, which are used to fill the gate metal 14 layer. This gate metal 14 layer is made of titanium metal composite material and deposited with a thickness of 1000 angstroms using magnetron sputtering at a power of 7 kW. The gate metal 14 layer is etched using photolithography to form the gate 4 in the gate pattern region, as shown in the figure. Figure 4As shown in (c). Due to the high surface activity of the epitaxial layer interface, it is easy to adsorb impurities. In this embodiment, the preparation order of the gate metal 14 is transferred to the epitaxial layer passivation, which avoids the contamination effect of metal ions on the epitaxial layer interface and effectively avoids the impact of defects on device reliability.

[0089] In this embodiment, the step of forming a gate metal layer 14 by magnetron sputtering and etching the gate metal layer 14 by photolithography to form a gate 4 in the gate pattern region includes:

[0090] A gate metal layer 14 is formed by magnetron sputtering, and the gate metal layer 14 is etched by photolithography to form a gate 4 in the gate pattern region. A field plate structure is defined according to the gate 4 to modulate the electric field strength from the drain 6 to the gate 4.

[0091] like Figure 5 As shown in (b), after the gate metal 14 is deposited, the metal gate region is defined by photolithography. At the same time, the field plate structure (FP1 to FP3 in the figure) can be defined to modulate the electric field intensity from the drain 6 to the gate 4, so as to save photomasks and process flow and improve process efficiency.

[0092] In this embodiment, the material of the first dielectric layer 1 is silicon oxide, and the thickness of the first dielectric layer 1 is 1000-1500 angstroms; the material of the second dielectric layer 2 is silicon nitride, and the thickness of the second dielectric layer 2 is 800-1200 angstroms; and the material of the third dielectric layer 3 is silicon oxide.

[0093] The etching solution has high selectivity for etching oxides and nitrides. During the post-gate process, gate 4 is self-aligned, avoiding the introduction of by-product contaminants on the surface of aluminum gallium nitride 8, p-type gallium nitride 7, or gate 4.

[0094] The first dielectric layer 1 is made of silicon oxide with a thickness controlled at 1000–1500 angstroms. The second dielectric layer 2 is made of silicon nitride with a thickness controlled at 800–1200 angstroms. A 20:1 diluted hydrofluoric acid solution is used as the etching solution at room temperature. This solution has an etching selectivity ratio of 20:1 for silicon oxide and silicon nitride, meaning the etching rate for silicon oxide is approximately 200 angstroms / min and the etching rate for silicon nitride is approximately 10 angstroms / min. The etching selectivity ratio is controllable due to different hydrofluoric acid concentrations and the control of the film quality of the two materials. The third dielectric layer 3 is made of silicon oxide, which possesses excellent insulating properties and chemical stability. Figure 5 As shown in (a), a third dielectric layer 3 is formed by plasma-enhanced chemical vapor deposition. Metal vias 5 (source), 6 (drain), and 4 (gate) are then formed on the third dielectric layer 3, and metal structures are deposited to form subsequent metal interconnects, resulting in a finished gallium nitride (GaN) 9 semiconductor device. The results are as follows: Figure 5As shown in (b).

[0095] A second embodiment of the present invention also provides a semiconductor structure, including: aluminum gallium nitride 8, a gate step, a strain layer 13, a passivation layer 12, a gate 4, a source 5, and a drain 6;

[0096] The gate step includes: a P-type gallium nitride 7 and a second dielectric layer 2, the second dielectric layer 2 being formed on the surface of the P-type gallium nitride 7, and the P-type gallium nitride 7 being formed on the gate position of the surface of aluminum gallium nitride 8;

[0097] The strain layer 13 is formed on the surface of the second dielectric layer 2, the passivation layer 12 is formed on the surface of the strain layer 13, the source 5 and the drain 6 are formed on the surface of the passivation layer 12 and are respectively connected to the aluminum gallium nitride 8 through contact holes. The passivation layer 12 exposes the P-type gallium nitride 7 by etching to form a gate metal filling hole. A gate metal 14 is formed in the gate metal filling hole to form a gate 4.

[0098] The third dielectric layer 3 is formed on the surface of the gate metal 14, and the rear metal interconnects of the source 5, drain 6 and gate 4 are formed on the third dielectric layer 3 respectively.

[0099] like Figure 5 As shown in (b), the gate pattern and the stepped region of P-type gallium nitride 7 prepared through the above steps can protect the surface of P-type gallium nitride 7 and avoid interface contamination introduced by the wet etching process. The etching solution has different etching rates for the first dielectric layer 1 and the second dielectric layer 2. The remaining second dielectric layer 2 serves as a hard mask layer for etching P-type gallium nitride 7, etching away the P-type gallium nitride 7 in areas not covered by the second dielectric layer 2. This results in a stepped region of the composite gate 4 structure, combining the oxide dielectric layer and P-type gallium nitride 7, thus protecting the surface of P-type gallium nitride 7. Compared to traditional processes that define the metal gate pattern using a mask, resulting in a single morphology and the ability to only control the lateral linewidth of the metal gate, the metal gate structure prepared in this invention can form a stepped gate structure under different wet etching selectivities through the preceding layer structure. Furthermore, the step width and height can be modulated through process parameter optimization to match optimal device performance. The stepped gate structure prepared in this invention can be used to modulate the electric field distribution from the drain to the gate, thereby improving device performance.

[0100] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor fabrication method, characterized in that, include: A first dielectric layer is formed on the surface of a P-type gallium nitride, and the first dielectric layer is etched to form a gate pattern; A second dielectric layer is formed, and the second dielectric layer is etched without a mask to leave a second dielectric layer residue on both sides of the gate pattern. The P-type gallium nitride in the area not covered by the second dielectric layer is etched away to expose aluminum gallium nitride. A passivation layer is formed, and a source and a drain are formed on the passivation layer on the surface of the region where aluminum gallium nitride is located. The source and the drain are connected to aluminum gallium nitride through contact holes. The gate pattern is etched and a gate metal filling hole is formed until the P-type gallium nitride is exposed. Gate metal is formed in the gate metal filling hole to form the gate. A third dielectric layer is formed, and the back metal interconnects of the source, drain and gate are formed on the third dielectric layer respectively.

2. The semiconductor fabrication method according to claim 1, characterized in that, The step of forming a first dielectric layer on the surface of a P-type gallium nitride and etching the first dielectric layer to form a gate pattern includes: A gallium nitride passivation layer is formed on the surface of a p-type gallium nitride; A first dielectric layer is formed on the gallium nitride passivation layer by plasma-enhanced chemical vapor deposition. The gate region is defined in the first dielectric layer by photolithography, and the area not covered by photoresist is etched by dry etching to form the gate pattern. Clean the byproducts generated during gate etching.

3. The semiconductor fabrication method according to claim 1, characterized in that, The process of forming a second dielectric layer, performing maskless etching on the second dielectric layer to leave second dielectric layer residues on both sides of the gate pattern, and etching away the P-type gallium nitride in areas not covered by the second dielectric layer to expose aluminum gallium nitride includes: The second dielectric layer was formed by plasma-enhanced chemical vapor deposition. The second dielectric layer is etched without a mask to leave a second dielectric layer residue on both sides of the gate pattern. The remaining second dielectric layer is used as a hard mask layer for P-type gallium nitride, and the P-type gallium nitride in the area not covered by the second dielectric layer is etched away.

4. The semiconductor fabrication method according to claim 3, characterized in that, The width of the second dielectric layer remaining is 60~70nm.

5. The semiconductor fabrication method according to claim 1, characterized in that, The process involves forming a passivation layer and forming a source and drain electrode on the passivation layer on the surface of the region containing aluminum gallium nitride (AlGaN). The source and drain electrode are connected to AlGaN via contact holes. A strain layer is formed, and a passivation layer is formed on the strain layer; Source contact holes and drain contact holes are formed in the source and drain regions of the passivation layer on the surface of the aluminum gallium nitride region, respectively. Form a metal layer; The metal layer is etched by photolithography to retain the stacked metal of the source and drain regions to form the source and drain. The source and drain are connected to aluminum gallium nitride through source contact holes and drain contact holes, respectively. The source and drain electrodes are subjected to high-temperature annealing.

6. The semiconductor fabrication method according to claim 5, characterized in that, The passivation layer has a thickness of 350-400 angstroms, and the metal layer is a stacked metal layer, which includes a bottom titanium metal, an interlayer aluminum metal, and a top titanium metal connected in sequence.

7. The semiconductor fabrication method according to claim 1, characterized in that, The etching of the gate pattern and the formation of gate metal filling vias until the P-type gallium nitride is exposed, and the formation of gate metal within the gate metal filling vias to form the gate, includes: The gate pattern is etched using a photolithography process to expose the first dielectric layer within the gate pattern; The first dielectric layer within the gate pattern is longitudinally etched using a wet etching solution to form gate metal filling holes until the P-type gallium nitride is exposed. A gate metal layer is formed by magnetron sputtering, and the gate metal layer is etched by photolithography to form a gate in the gate pattern region.

8. The semiconductor fabrication method according to claim 7, characterized in that, The process of forming a gate metal layer by magnetron sputtering and etching the gate metal layer by photolithography to form a gate in the gate pattern region includes: A gate metal layer is formed by magnetron sputtering, and the gate metal layer is etched by photolithography to form a gate in the gate pattern region. A field plate structure is defined according to the gate to modulate the electric field strength from the drain to the gate.

9. The semiconductor fabrication method according to any one of claims 1 to 8, characterized in that, The first dielectric layer is made of silicon oxide and has a thickness of 1000-1500 angstroms. The second dielectric layer is made of silicon nitride and has a thickness of 800-1200 angstroms. The third dielectric layer is made of silicon oxide.

10. A semiconductor structure, characterized in that, The semiconductor fabrication method described in claim 1 yields a product comprising: aluminum gallium nitride, a gate step, a strained layer, a passivation layer, a gate, a source, and a drain. The gate step includes: a P-type gallium nitride and a second dielectric layer, wherein the second dielectric layer is formed on the surface of the P-type gallium nitride and the P-type gallium nitride is formed at the gate position on the surface of aluminum gallium nitride. The strain layer is formed on the surface of the second dielectric layer, the passivation layer is formed on the surface of the strain layer, the source and drain are formed on the surface of the passivation layer and are respectively connected to aluminum gallium nitride through contact holes. The passivation layer exposes P-type gallium nitride by etching to form a gate metal filling hole. Gate metal is formed in the gate metal filling hole to form a gate. The third dielectric layer is formed on the gate metal surface, and the back metal interconnects of the source, drain and gate are formed on the third dielectric layer respectively.

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