Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method of forming the same, the method comprising: forming an interconnection opening through a first dielectric layer and a second dielectric layer on top of a source-drain doped region, and along a direction perpendicular to a gate structure, an opening width of the interconnection opening in the second dielectric layer is greater than an opening width of the interconnection opening in the first dielectric layer; forming a first sidewall, a sacrificial sidewall and a second sidewall sequentially stacked on sidewalls of the interconnection opening; filling a source-drain interconnection layer in the interconnection opening, the source-drain interconnection layer being in contact with the source-drain doped region and covering sidewalls of the second sidewall; removing the sacrificial sidewall to form an air sidewall between the first sidewall and the second sidewall; forming a third dielectric layer on the second dielectric layer and the source-drain interconnection layer to seal a top of the air sidewall; forming a source-drain plug in the third dielectric layer on top of the source-drain interconnection layer and in contact with the source-drain interconnection layer. Embodiments of the present application reduce the risk of the top of the air sidewall being opened and increase the process window for forming the source-drain plug.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] To meet the interconnect requirements of reduced critical dimensions, current interconnect structures are used to connect different metal layers or between metal layers and a substrate. These interconnect structures include interconnect lines and contact holes formed within contact openings. The contact holes connect to semiconductor devices, and the interconnect lines connect the contact holes to form a circuit.

[0003] Transistor structures typically include a gate plug that contacts the gate structure to provide electrical connection between the gate structure and external circuitry, and a source-drain interconnect structure that contacts the source-drain doped regions to provide electrical connection between the source-drain doped regions and external circuitry. To reduce the coupling capacitance between the gate structure and the source-drain interconnect structure, one current approach is to form an air gap spacer between them. Air has a lower dielectric constant than commonly used dielectric materials in semiconductor processes (e.g., low-k or ultra-low-k dielectric materials), which significantly reduces the coupling capacitance between the gate structure and the source-drain interconnect structure.

[0004] However, the current process window for forming air sidewalls is relatively small. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which reduces the risk of the top of the air sidewall being opened and increases the process window for forming source and drain plugs.

[0006] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure, comprising: a substrate; a gate structure discretely disposed on the substrate; source / drain doped regions located within the substrate on both sides of the gate structure; a first dielectric layer located on the side of the gate structure and covering the source / drain doped regions; a second dielectric layer located on top of the first dielectric layer and the gate structure; a source / drain interconnect layer penetrating the first and second dielectric layers on top of the source / drain doped regions and contacting the source / drain doped regions, and extending in a direction perpendicular to the gate structure, wherein the width of the source / drain interconnect layer in the second dielectric layer is greater than the width of the source / drain interconnect layer in the first dielectric layer; a sidewall structure layer located between the sidewall of the gate structure and the sidewall of the source / drain interconnect layer, the sidewall structure layer including a first sidewall on the sidewall of the gate structure, a second sidewall on the sidewall of the source / drain interconnect layer, and an air sidewall located between the first and second sidewalls; a third dielectric layer located on the second dielectric layer and the source / drain interconnect layer and sealing the top of the air sidewall; and a source / drain plug located in the third dielectric layer on top of the source / drain interconnect layer and contacting the source / drain interconnect layer.

[0007] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, wherein discrete gate structures are formed on the substrate, source / drain doped regions are formed in the substrate on both sides of the gate structures, and a first dielectric layer covering the source / drain doped regions is formed on the side of the gate structures; forming a second dielectric layer on top of the first dielectric layer and the gate structures; forming an interconnection opening penetrating the first and second dielectric layers on top of the source / drain doped regions, wherein the opening width of the interconnection opening in the second dielectric layer is greater than the opening width of the interconnection opening in the first dielectric layer along a direction perpendicular to the extension of the gate structures; forming a first sidewall, a sacrificial sidewall, and a second sidewall stacked sequentially on the sidewall of the interconnection opening; filling the interconnection opening with a source / drain interconnection layer, the source / drain interconnection layer contacting the source / drain doped regions and covering the sidewall of the second sidewall; removing the sacrificial sidewall, forming an air sidewall between the first and second sidewalls; forming a third dielectric layer on the second dielectric layer and the source / drain interconnection layer, sealing the top of the air sidewall; and forming a source / drain plug in the third dielectric layer on top of the source / drain interconnection layer, contacting the source / drain interconnection layer.

[0008] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0009] The semiconductor structure provided in this invention has a wider source-drain interconnect layer in the second dielectric layer than in the first dielectric layer, extending perpendicularly to the gate structure. The portion of the source-drain interconnect layer in the second dielectric layer is wider than the portion in the first dielectric layer, thus increasing the exposed top width of the source-drain interconnect layer. Consequently, the area of ​​the source-drain interconnect layer used to receive the source-drain plug is larger. Even if there is overlay misalignment during the process of forming the source-drain plug, the probability of the etching process causing mis-etching of the top of the second sidewall and the top of the air sidewall is low. This reduces the risk of the top of the air sidewall being opened, ensuring the effectiveness of the air sidewall in reducing the parasitic capacitance between the source-drain interconnect layer and the gate structure. Furthermore, it increases the process window for forming the source-drain plug and improves the performance of the semiconductor structure.

[0010] In the semiconductor structure formation method provided by this embodiment of the invention, a second dielectric layer is formed on top of a first dielectric layer and a gate structure. In the step of forming an interconnect opening penetrating the top of the first and second dielectric layers through the source / drain doped regions, the opening width of the interconnect opening in the second dielectric layer is greater than the opening width of the interconnect opening in the first dielectric layer along a direction perpendicular to the extension of the gate structure. Correspondingly, after filling the interconnect opening with the source / drain interconnect layer, the width of the portion of the source / drain interconnect layer located in the second dielectric layer is larger than the portion located in the first dielectric layer, thereby increasing the risk of surface cracking. In the step of forming a source / drain plug in the third dielectric layer on top of the exposed source / drain interconnect layer, the area of ​​the source / drain interconnect layer for receiving the source / drain plug is relatively large. Even if there is an overlay offset in the step of forming the source / drain plug, the probability of the etching process for forming the source / drain plug causing mis-etching to the top of the second sidewall and the top of the air sidewall is low. This reduces the risk of the top of the air sidewall being opened, ensures the effectiveness of the air sidewall in reducing the parasitic capacitance between the source / drain interconnect layer and the gate structure, and increases the process window for forming the source / drain plug, thereby improving the performance of the semiconductor structure. Attached Figure Description

[0011] Figures 1 to 3 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0012] Figure 4 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0013] Figure 5 This is a schematic diagram of another embodiment of the semiconductor structure of the present invention;

[0014] Figures 6 to 18 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure of the present invention;

[0015] Figures 19 to 22 This is a schematic diagram of the structure corresponding to each step in another embodiment of the method for forming the semiconductor structure of the present invention. Detailed Implementation

[0016] As is known from the background art, forming air sidewalls currently tends to result in a smaller process window for forming source / drain plugs. This paper analyzes, in conjunction with a semiconductor structure formation method, the reasons why forming air sidewalls leads to a smaller process window for forming source / drain plugs.

[0017] Figures 1 to 3 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0018] refer to Figure 1The system provides a substrate (not shown), a gate structure 1 located on the substrate, source / drain doped regions 2 located in the substrate on both sides of the gate structure 1, and a bottom dielectric layer (not shown) covering the side of the gate structure 1 and the source / drain doped regions 2. A source / drain interconnect layer 4 in contact with the source / drain doped regions 2 is formed in the bottom dielectric layer. There is a gap between the sidewall of the source / drain interconnect layer 4 and the sidewall of the gate structure 1. A first sidewall 5 is formed on the sidewall of the source / drain interconnect layer 4, and a second sidewall 6 is formed on the sidewall of the gate structure 1. An air sidewall 7 is formed between the first sidewall 5 and the second sidewall 6.

[0019] refer to Figure 2 A top dielectric layer 3 is formed on the bottom dielectric layer and the gate structure 1 to seal the top of the air sidewall 7.

[0020] refer to Figure 3 A source / drain plug 8 is formed, penetrating the top dielectric layer 3 of the source / drain interconnect layer 4 and contacting the source / drain interconnect layer 4. The steps of forming the source / drain plug 8 include: forming a source / drain contact hole (not shown) penetrating the top dielectric layer 3 of the source / drain interconnect layer 4 to expose the source / drain interconnect layer 4; and filling the source / drain contact hole with conductive material to form the source / drain plug 8.

[0021] Continue to refer to Figure 3 A gate plug 9 is formed by penetrating the top dielectric layer 3 through the top of the gate structure 1 and contacting the gate structure 1. The steps of forming the gate plug 9 include: forming a gate contact hole (not shown) through the top dielectric layer 3 through the top of the gate structure 1 to expose the gate structure 1; and filling the gate contact hole with a conductive material to form the gate plug 9.

[0022] In the semiconductor field, the width of the source-drain interconnect layer 4 is usually smaller than that of the gate structure 1, and the width of the source-drain plug 8 is usually larger than that of the gate plug 8. Therefore, the process tolerance for overlay offset is small in the step of forming the source-drain contact hole. When overlay offset exists, it is easy to cause mis-etching on the top of the first sidewall 5 on the sidewall of the source-drain interconnect layer 4 and the top dielectric layer 3 on the top of the air sidewall 7, which will cause the top of the air sidewall 7 to be opened, resulting in a smaller process window for forming the gate contact hole.

[0023] Correspondingly, during the process of filling the source and drain contact holes with conductive material, the conductive material is easily filled into the air sidewall 7, which reduces the effectiveness of the air sidewall 7 in reducing parasitic capacitance, and may even lead to a decrease in device performance or device failure.

[0024] To mitigate the problem of the air sidewall top being opened due to overlay misalignment during the formation of source-drain contact holes, one approach is to reduce the size of the bottom of the source-drain contact holes, but this increases the extension resistance and reduces the electrical performance of the device; another approach is to increase the width of the first sidewall located on the sidewall of the source-drain interconnect layer, but this compresses the space of the air sidewall.

[0025] Furthermore, addressing the issue of air sidewall top opening caused by overlay misalignment requires high consistency in the critical dimensions of the source / drain interconnect layer, gate plug, and source / drain plug in both local and global regions. Additionally, during mass production, other process variations exacerbate overlay misalignment, resulting in a smaller process window for forming air sidewalls and source / drain plugs.

[0026] Therefore, how to increase the process window for forming the source-drain plug while forming the air sidewall has become an urgent problem to be solved.

[0027] To address the technical problem, this invention provides a semiconductor structure in which the width of the source-drain interconnect layer in the second dielectric layer, extending perpendicularly to the gate structure, is greater than the width of the source-drain interconnect layer in the first dielectric layer. The width of the portion of the source-drain interconnect layer located in the second dielectric layer is also greater than the portion located in the first dielectric layer. This increases the exposed top width of the source-drain interconnect layer, resulting in a larger area for receiving the source-drain plug. Even if there is overlay misalignment during the process of forming the source-drain plug, the probability of the etching process causing mis-etching of the top of the second sidewall and the top of the air sidewall is low. This reduces the risk of the top of the air sidewall being opened, ensuring the effectiveness of the air sidewall in reducing the parasitic capacitance between the source-drain interconnect layer and the gate structure. Furthermore, it increases the process window for forming the source-drain plug and improves the performance of the semiconductor structure.

[0028] To make the above-mentioned objects, features, and advantages of the embodiments of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. (Reference) Figure 4 The diagram shows a schematic representation of an embodiment of the semiconductor structure of the present invention.

[0029] like Figure 4 As shown, in this embodiment, the semiconductor structure includes: a substrate (not shown); a gate structure 110, discretely disposed on the substrate; source / drain doped regions 120, located within the substrate on both sides of the gate structure 110; and a first dielectric layer 130 (refer to reference). Figure 11A first dielectric layer 130 is located on the side of the gate structure 110 and covers the source / drain doped region 120; a second dielectric layer 160 is located on top of the first dielectric layer 130 and the gate structure 110; a source / drain interconnect layer 240 penetrates the first dielectric layer 130 and the second dielectric layer 160 on top of the source / drain doped region 120 and contacts the source / drain doped region 120, and along a direction perpendicular to the gate structure 110, the width of the source / drain interconnect layer 240 in the second dielectric layer 160 is greater than the width of the source / drain interconnect layer 240 in the first dielectric layer 130; a sidewall structure layer 230, Located between the sidewall of the gate structure 110 and the sidewall of the source-drain interconnect layer 240, the sidewall structure layer 230 includes a first sidewall 31 on the sidewall of the gate structure 110, a second sidewall 32 on the sidewall of the source-drain interconnect layer 240, and an air sidewall 35 between the first sidewall 31 and the second sidewall 32; a third dielectric layer 250 is located on the second dielectric layer 160 and the source-drain interconnect layer 240 and seals the top of the air sidewall 35; and a source-drain plug 210 is located in the third dielectric layer 250 on top of the source-drain interconnect layer 240 and is in contact with the source-drain interconnect layer 240.

[0030] The substrate is used to provide a process platform for the formation of semiconductor structures.

[0031] In this embodiment, the substrate is a three-dimensional substrate, which includes a substrate, protrusions disposed on the substrate, and a channel structure layer located on the protrusions. In other embodiments, the substrate may also be a planar substrate.

[0032] In this embodiment, the substrate is a silicon substrate. In other embodiments, the substrate material can also be other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate. The substrate can also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates. The substrate material can be a material suitable for process requirements or easy to integrate.

[0033] The protrusions provide support for the channel structure layer. In this embodiment, the protrusions are made of silicon. In other embodiments, the protrusions may also be made of other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide. In this embodiment, the protrusions and the substrate are an integral structure.

[0034] The channel structure layer is used to provide a conductive channel for the field-effect transistor. In this embodiment, the material of the channel structure layer is the same as the substrate material, which is silicon. In other embodiments, the material of the channel structure layer can also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium, or other semiconductor materials suitable for forming a channel structure layer.

[0035] In this embodiment, taking the substrate used to form a FinFET as an example, the channel structure layer is a fin. The fin is used to provide the conductive channel of the FinFET. In this embodiment, the fin and the protrusion are an integral structure.

[0036] In other embodiments, when forming a nanosheet or forksheet gate transistor, a channel structure layer is suspended over the protrusions, and the channel structure layer includes one or more channel layers spaced apart and suspended. The channel layer provides a conductive channel for the nanosheet or forksheet gate transistor.

[0037] In this embodiment, the semiconductor structure further includes an isolation layer (not shown), located on the substrate and surrounding the protrusion, exposing the channel structure layer.

[0038] The isolation layer is used to isolate adjacent protrusions and also to isolate the substrate from the gate structure 110. In this embodiment, the material of the isolation layer includes one or more of silicon oxide, silicon oxynitride, and silicon nitride.

[0039] The gate structure 110 is used to control the turning on and off of the conductive channel of the field-effect transistor. In this embodiment, the gate structure 110 is located on the isolation layer and spans the channel structure layer.

[0040] Specifically, in this embodiment, the gate structure 110 is located on the isolation layer, and the gate structure 110 spans the fin and covers part of the top and part of the sidewall of the fin.

[0041] In other embodiments, when the channel structure layer includes one or more spaced-apart channel layers, the gate structure is located on the isolation layer and surrounds the channel layer.

[0042] In this embodiment, the gate structure 110 is a metal gate structure, which is formed by forming a high k last metal gate last process after forming a high k last gate dielectric layer.

[0043] In this embodiment, the gate structure 110 includes a gate dielectric layer (not shown), a work function layer (not shown) located on the gate dielectric layer, and a gate electrode layer (not shown) located on the work function layer.

[0044] The gate dielectric layer is used to achieve electrical isolation between the work function layer and the electrode material layer and the channel structure layer.

[0045] In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer. The material of the high-k gate dielectric layer is a high-k dielectric material; wherein, a high-k dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer is HfO2. In other embodiments, the material of the high-k gate dielectric layer may also be selected from ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.

[0046] In other embodiments, the gate dielectric layer may further include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer. The gate oxide layer is made of one or both of silicon oxide and silicon oxynitride. In still other embodiments, the gate dielectric layer may consist only of a gate oxide layer.

[0047] The work function layer is used to adjust the work function of the metal gate structure, thereby regulating the threshold voltage of the transistor. When forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the work function layer includes one or more of titanium aluminide, tantalum carbide, aluminum, or titanium carbide. When forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the work function layer includes one or more of titanium nitride, tantalum nitride, titanium carbide, silicon tantalum nitride, silicon titanium nitride, and tantalum carbide.

[0048] The electrode material layer serves as an electrode, used to draw out the electrical properties of the metal gate structure, thereby achieving electrical connection between the metal gate structure and external circuitry. In this embodiment, the electrode material layer is made of W. In other embodiments, the electrode material layer may also be made of Al, Cu, Ag, Au, Pt, Ni, or Ti, etc.

[0049] In a specific embodiment, a gate sidewall (not shown) may also be formed on the sidewall of the gate structure 110. The gate sidewall is used to protect the sidewall of the gate structure 110 and to define the formation location of the source and drain doped regions 120.

[0050] The gate sidewall can be a single layer or a multilayer structure. As an example, the gate sidewall material includes one or more of silicon oxide, low-k dielectric materials, and ultra-low-k dielectric materials.

[0051] During device operation, the source / drain doped regions 120 are used to provide carrier sources. In this embodiment, the source / drain doped regions 120 are located on both sides of the gate structure 110 and the gate sidewalls. Specifically, the source / drain doped regions 120 are located in the fins on both sides of the gate structure 110.

[0052] In this embodiment, the source / drain doped region 120 includes a stress layer doped with ions. The source / drain doped region 120 is also used to provide stress to the channel, thereby improving the carrier mobility of the channel.

[0053] Specifically, when forming an NMOS transistor, the source and drain doped regions 120 are made of a stress layer doped with N-type ions. The stress layer is made of Si or SiC. The stress layer provides tensile stress to the channel region of the NMOS transistor, which helps to improve the carrier mobility of the NMOS transistor. The N-type ions are P ions, As ions, or Sb ions.

[0054] When forming a PMOS transistor, the source and drain doped regions 120 are made of a stress layer doped with P-type ions. The stress layer is made of Si or SiGe. The stress layer provides compressive stress to the channel region of the PMOS transistor, which helps to improve the carrier mobility of the PMOS transistor. The P-type ions are B ions, Ga ions, or In ions.

[0055] In this embodiment, the semiconductor structure further includes: a first barrier layer 140 located between the sidewall of the gate structure 110 and the first dielectric layer 130; and a second barrier layer 150 located between the top of the gate structure 110 and the second dielectric layer 160.

[0056] The first barrier layer 140 located on the sidewall of the gate structure 110 is used to define the etching stop position along the extension direction perpendicular to the gate structure 110 during the step of forming the interconnect opening, thereby defining the position and opening size of the interconnect opening in the first dielectric layer 130, and also reducing the probability of the process of forming the interconnect opening causing damage to the sidewall of the gate structure 110.

[0057] It should be noted that, in this embodiment, the first barrier layer 140 is also located between the source / drain doped region 120 and the first dielectric layer 130, and between the source / drain doped region 120 and the sidewall structure layer 230.

[0058] During the formation of the semiconductor structure, interconnect openings are formed before the source / drain interconnect layer 240. These openings provide space for the formation of the source / drain interconnect layer 240 and the sidewall structure layer 230. Specifically,

[0059] The first barrier layer 140 located on the source / drain doped region 120 can temporarily define the etching stop position during the interconnect opening formation step, thereby reducing the probability of damage to the source / drain doped region 120 caused by the interconnect opening formation process. Furthermore, the first barrier layer 140 located on the source / drain doped region 120 can also define the etching stop position during the sidewall structure layer 230 formation step, and protect the source / drain doped region 120, and prevent the air sidewall 55 from exposing the source / drain doped region 120, thereby reducing the probability of damage to the source / drain doped region 120.

[0060] In this embodiment, the first barrier layer 140 is a contact etch stop layer (CESL), so that an existing contact etch stop layer can be used as the first barrier layer 140, which is beneficial to improving process compatibility and process integration.

[0061] Specifically, in this embodiment, the first barrier layer 140 is formed on the source / drain doped region 120 and on the sidewall of the gate structure 120 exposed by the source / drain doped region 120.

[0062] In this embodiment, the first barrier layer 140 is selected from materials that have etching selectivity with the material of the first dielectric layer 130. In this embodiment, the material of the first barrier layer 140 includes one or more of the following: silicon oxycarbonate, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon carbonitride, silicon germanium oxide, boron nitride, and boron carbonitride.

[0063] The second barrier layer 150 is used to protect the top of the gate structure 110 during the step of forming the interconnect opening, thereby reducing the probability of damage to the gate structure 110 caused by the process of forming the interconnect opening; and, during the step of forming the gate plug that contacts the top of the gate structure 110, the second barrier layer 150 located on the top of the gate structure 110 can temporarily define the etch stop position, thereby improving the bottom depth consistency of the gate plug.

[0064] The second barrier layer 150 is selected from materials that have etching selectivity with the material of the first dielectric layer 130. In this embodiment, the material of the second barrier layer 150 includes one or more of the following: silicon oxycarbonate, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon carbonitride, silicon germanium oxide, boron nitride, and boron carbonitride.

[0065] The first dielectric layer 130 is used to isolate adjacent gate structures 110, and the first dielectric layer 130 is also used to isolate adjacent source-drain interconnect layers 240.

[0066] The material of the first dielectric layer 130 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of the first dielectric layer 130 is silicon oxide.

[0067] In this embodiment, the top of the gate structure 110 is flush with the top of the first dielectric layer 130; the second barrier layer 150 is also located between the second dielectric layer 160 and the first dielectric layer 130 on the side of the source / drain plug 210. Correspondingly, the source / drain interconnect layer 240 also penetrates the second barrier layer 150 above the source / drain doped region 120.

[0068] The second barrier layer 150 is also located on the first dielectric layer 130, so the second dielectric layer 160 is located on the second barrier layer 150. In the step of forming interconnect openings, the second dielectric layer 160 located above the source / drain doped region 120 can be etched first with the top surface of the second barrier layer 150 as the stop position, which is beneficial to obtain a larger opening size for the interconnect openings located in the second dielectric layer 160.

[0069] In other embodiments, the top of the gate structure is lower than the top of the first dielectric layer, and the top of the gate structure and the first barrier layer form a trench; the second barrier layer fills the trench. The second barrier layer is located only at the top of the gate structure, so the second dielectric layer is located on the second barrier layer and the first dielectric layer. In the step of forming the interconnect opening, it is not necessary to etch the second barrier layer located above the source / drain doped regions. After removing the second dielectric layer located above the source / drain doped regions, the first dielectric layer can then be etched. During the etching of the first dielectric layer above the source / drain doped regions, the first barrier layer located on the sidewall of the gate structure can be used as a stop layer along the direction perpendicular to the extension of the gate structure, thereby achieving self-alignment of the etching.

[0070] The second dielectric layer 160 is used to achieve isolation between adjacent source-drain interconnect layers 240, and also to achieve isolation between the source-drain interconnect layer 240 and the gate plug, as well as isolation between adjacent gate plugs.

[0071] The second dielectric layer 160 is made of an insulating material, and the second dielectric layer 160 is selected from materials that have high etching selectivity between the first barrier layer 140 and the second barrier layer 150. The material of the second dielectric layer 160 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of the second dielectric layer 160 is silicon oxide.

[0072] In this embodiment, a second barrier layer 150 is also formed on the top of the gate structure 110, and a second dielectric layer 160 is formed on the first dielectric layer 130 and the second barrier layer 150. Specifically, in this embodiment, the second dielectric layer 160 covers the second barrier layer 150.

[0073] The source-drain interconnect layer 240 is in contact with the source-drain doped region 120 and is used to realize the electrical connection between the source-drain doped region 120 and the external circuit. Specifically, the source-drain interconnect layer 240 is used to realize the electrical connection between the source-drain doped region 120 and the source-drain plug 210.

[0074] In this embodiment, the source-drain interconnect layer 240 also extends through the first barrier layer 140 located on top of the source-drain doped region 120.

[0075] Along the direction perpendicular to the gate structure 110, the width of the source-drain interconnect layer 240 located in the second dielectric layer 160 is greater than the width of the source-drain interconnect layer 240 located in the first dielectric layer 160. Correspondingly, the width of the portion of the source-drain interconnect layer 240 located in the second dielectric layer 160 is larger than the portion of the source-drain interconnect layer 240 located in the first dielectric layer 130. This increases the exposed top width of the source-drain interconnect layer 240, thereby increasing the top area of ​​the source-drain interconnect layer 240 for receiving the source-drain plug 210, which is beneficial for increasing the process window for forming the source-drain plug 210.

[0076] As an example, the source-drain interconnect layer 240 is made of copper. Copper has low resistivity, which helps improve the back-end RC delay, increases chip processing speed, and also reduces the resistance of the source-drain interconnect layer 240, thereby reducing power consumption. In other embodiments, the source-drain interconnect layer can also be made of conductive materials such as tungsten or cobalt.

[0077] In this embodiment, along the direction perpendicular to the gate structure 110, the sidewall of the top interconnect layer 22 protrudes beyond the sidewall of the bottom interconnect layer 21. Thus, on the projection plane parallel to the substrate, the top interconnect layer 22 not only covers the area of ​​the bottom interconnect layer 21 but also extends outward. The portion of the top interconnect layer 22 protruding beyond the bottom interconnect layer 21 can increase the tolerance space for overlay offset in forming the source / drain plug 210, thereby increasing the process window for forming the source / drain plug 210 and increasing the distance between the air sidewall 35 and the source / drain plug 210. This correspondingly reduces the risk that the process of forming the source / drain plug 210 will open the top of the air sidewall 35.

[0078] It should be noted that the difference between the width of the top interconnect layer 22 and the width of the bottom interconnect layer 21 along the extension direction perpendicular to the gate structure 110 should not be too small or too large. If the difference between the width of the top interconnect layer 22 and the width of the bottom interconnect layer 21 is too small, the effect of increasing the top width of the exposed source-drain interconnect layer 240 will be insignificant. If the difference between the width of the top interconnect layer 22 and the width of the bottom interconnect layer 21 is too large, the width of the top interconnect layer 22 will be too large, which will in turn lead to the width of the remaining second dielectric layer 160 on top of the gate structure 110 being too small along the extension direction perpendicular to the gate structure 110. This will increase the difficulty of forming a gate plug penetrating the second dielectric layer 160 on top of the gate structure 110. Therefore, in this embodiment, the width of the top interconnect layer 22 is 2 nanometers to 6 nanometers larger than the width of the bottom interconnect layer 21 along the extension direction perpendicular to the gate structure 110.

[0079] The sidewall structure layer 230 is used to achieve isolation between the source-drain interconnect layer 240 and the gate structure 110.

[0080] In this embodiment, the sidewall structure layer 230 is also located between the source-drain interconnect layer 240 and the second dielectric layer 160, that is, the air sidewall 35 is also located between the source-drain interconnect layer 240 and the second dielectric layer 160, so the air sidewall 35 can also reduce the parasitic capacitance between the source-drain interconnect layer 240 and the gate plug 220.

[0081] In this embodiment, the sidewall structure layer 230 is located between the sidewall of the first barrier layer 140 and the source-drain interconnect layer 240, between the sidewall of the second barrier layer 150 and the source-drain interconnect layer 240, and between the second dielectric layer 160 and the source-drain interconnect layer 240, and the sidewall structure layer 230 is in contact with the sidewall of the first barrier layer 140.

[0082] During the formation of the semiconductor structure, an interconnection opening is first formed through the first dielectric layer 130 and the second dielectric layer 160 on the top of the source / drain doped region 120. Then, a first sidewall 31, a sacrificial sidewall, and a second sidewall 32 are formed in sequence on the sidewall of the interconnection opening. The source / drain interconnection layer 240 is then filled into the interconnection opening. The sidewall structure layer 230 is in contact with the sidewall of the first barrier layer 140. That is, along the extension direction perpendicular to the gate structure 110, the position and size of the interconnection opening (i.e., the bottom opening) in the first dielectric layer 130 are defined by the first barrier layer 140. The first barrier layer 140 on the sidewall of the gate structure 110 can serve as an etch stop layer for forming the bottom opening, thereby achieving self-alignment of the etching process. This reduces the process difficulty and improves the control accuracy of the cross-sectional morphology and size of the bottom opening. It also helps to increase the volume of the bottom interconnection layer 41.

[0083] The first sidewall 31 and the second sidewall 32 are used to achieve isolation between the gate structure 110 and the source-drain interconnect layer 240, and also to form an air sidewall 35.

[0084] The first sidewall 31 and the second sidewall 32 are selected from materials that have etching selectivity with respect to the material of the second dielectric layer 160. As an example, the material of the first sidewall 31 includes one or more of silicon oxide, low-k dielectric materials, and ultra-low-k dielectric materials. As an example, the material of the second sidewall 32 includes one or more of silicon oxide, low-k dielectric materials, and ultra-low-k dielectric materials.

[0085] In this embodiment, the materials of the first sidewall 31 and the second sidewall 32 are the same, which is beneficial for improving process compatibility. In this embodiment, the materials of the first sidewall 31 and the second sidewall 32 are low-k dielectric materials, which is beneficial for further reducing the parasitic capacitance between the gate structure 110 and the source-drain interconnect layer.

[0086] Air has a lower dielectric constant than commonly used dielectric materials in semiconductor processes (e.g., low-k dielectric materials or ultra-low-k dielectric materials), thereby significantly reducing the coupling capacitance between the gate structure 110 and the source-drain interconnect layer 240 by providing air sidewalls 35 in the sidewall structure layer 230.

[0087] The third dielectric layer 250 is used to seal the air sidewall 21. The third dielectric layer 250 is also used to achieve isolation between the source and drain plugs 210, between the gate plugs, and between the source and drain plugs 210 and the gate plug.

[0088] The third dielectric layer 250 can be a single layer or a multilayer structure. The material of the third dielectric layer 250 includes one or more of the following: silicon oxide, carbon-containing silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon carbonitride, germanium silicon oxide, boron nitride, and boron carbonitride.

[0089] As an example, the third dielectric layer 250 includes: an etch stop layer 51 located on the second dielectric layer 160 and covering the source / drain interconnect layer 240 and the sidewall structure layer 230, the etch stop layer 51 sealing the top of the air sidewall 35; and a dielectric material layer 52 located on the etch stop layer 51.

[0090] The etch stop layer 51 can temporarily define the etch stop position during the process of forming the source drain plug 210, thereby improving the bottom depth consistency of the source drain plug 210 and reducing the probability of damage to the source drain interconnect layer 240.

[0091] The etch stop layer 51 is selected from materials that exhibit etch selectivity with respect to the materials of the second dielectric layer 160 and the dielectric material layer 52. As an example, the material of the etch stop layer 51 includes one or more of silicon oxycarbonate, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon carbonitride, germanium silicon oxide, boron nitride, and boron carbonitride. Specifically, the material of the etch stop layer 51 is silicon nitride.

[0092] In this embodiment, the dielectric material layer 52 is made of silicon oxide.

[0093] The source-drain plug 210 is used to realize the electrical connection between the source-drain interconnect layer 240 and the external circuit.

[0094] Specifically, in this embodiment, the source / drain plug 210 is in contact with the top interconnect layer 42.

[0095] In this embodiment, the portion of the source-drain interconnect layer 240 located in the second dielectric layer 160 is wider than the portion of the source-drain interconnect layer 240 located in the first dielectric layer 130. This increases the exposed top width of the source-drain interconnect layer 240, resulting in a larger area of ​​the source-drain interconnect layer 240 for receiving the source-drain plug 210. Even if there is an overlay offset during the process of forming the source-drain plug 210, the probability of the etching process of forming the source-drain plug 210 causing mis-etching to the top of the second sidewall 32 and the top of the air sidewall 35 is also low. This reduces the risk of the top of the air sidewall 35 being opened, ensuring the effectiveness of the air sidewall 35 in reducing the parasitic capacitance between the source-drain interconnect layer 240 and the gate structure 110. Furthermore, it increases the process window for forming the source-drain plug 210 and improves the performance of the semiconductor structure.

[0096] Specifically, the width of the top interconnect layer 42 is larger, thereby increasing the distance between the second sidewall 32 and the air sidewall 35 located on the sidewall of the top interconnect layer 42 and the source / drain plug 210, thereby reducing the probability of the source / drain plug 210 forming step causing mis-etching on the top of the second sidewall 32 and the air sidewall 35.

[0097] The source / drain plug 210 is made of a conductive material. In this embodiment, the source / drain plug 210 is made of tungsten. In other embodiments, the source / drain plug may also be made of conductive materials such as copper or cobalt.

[0098] In this embodiment, the semiconductor structure further includes a gate plug 220 that penetrates the second dielectric layer 160 and the third dielectric layer 250 on the top of the gate structure 110 and is in contact with the gate structure 110.

[0099] The gate plug 220 is used to realize the electrical connection between the gate structure 110 and the external circuit.

[0100] The gate plug 220 is made of a conductive material. In this embodiment, the gate plug 220 is made of tungsten. In other embodiments, the gate plug may also be made of conductive materials such as copper or cobalt.

[0101] Figure 5 A schematic diagram of another embodiment of the semiconductor structure of the present invention is shown. The similarities between this embodiment and the foregoing embodiments will not be repeated here. The differences between this embodiment and the foregoing embodiments are as follows:

[0102] In this embodiment, the air sidewall 435 is higher than the top portion of the gate structure 310 as a top air sidewall (not shown); the sidewall structure layer 430 also includes a third sidewall 433, located on the sidewalls of the first sidewall 431 and the second sidewall 432 exposed by the top air sidewall.

[0103] By including a third sidewall 433 in the sidewall structure layer 430, the width of the top portion of the sidewall structure layer 430 is greater, and the size of the top portion of the air sidewall 435 is smaller. This further increases the distance between the top of the air sidewall 435 and the source / drain plug 410, thereby further reducing the risk of the process steps for forming the source / drain plug 410 opening the top of the air sidewall 435 and increasing the process window for forming the source / drain plug 410.

[0104] Furthermore, the bottom of the third sidewall 433 is higher than the top of the gate structure 310, thereby ensuring that the air sidewall 435 located between the bottom interconnect layer 441 and the gate structure 310 has sufficient width, and correspondingly ensuring the effectiveness of the air sidewall 435 in reducing the parasitic capacitance between the bottom interconnect layer 441 and the gate structure 310.

[0105] The material of the third sidewall 433 is an insulating material. In this embodiment, the material of the third sidewall 433 includes one or more of silicon oxide, low-k dielectric materials, and ultra-low-k dielectric materials. In this embodiment, the third sidewall 433, the second sidewall 432, and the first sidewall 431 are made of the same material, thereby improving process compatibility.

[0106] It should be noted that, along the extension direction perpendicular to the gate structure 310, the distance between the sidewalls of the first sidewall 431 and the second sidewall 432 is the first width, and the thickness of the third sidewall 433 is the second width. The proportion of the second width to the first width should not be too small or too large. If the proportion is too small, the effect of the third sidewall 433 in reducing the size of the air sidewall 435 near the top will be insignificant, and the formation difficulty of the third sidewall 433 will be increased. If the proportion is too large, the area of ​​the top of the remaining sacrificial sidewall exposed at the bottom of the third sidewall 433 will be too small during the formation of the semiconductor structure, or even the third sidewalls 433 will come into contact, which will increase the difficulty of removing the remaining sacrificial sidewall to form the air sidewall 435. Therefore, in this embodiment, the second width is greater than or equal to 10% of the first width and less than 50% of the first width.

[0107] Accordingly, the present invention also provides a method for forming a semiconductor structure. Figures 6 to 18 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0108] The method for forming the semiconductor structure of this embodiment will be described in detail below with reference to the accompanying drawings.

[0109] refer to Figures 6 to 7A substrate (not shown) is provided, on which discrete gate structures 110 are formed. Active and drain doped regions 120 are formed in the substrate on both sides of the gate structure 110, and a first dielectric layer 130 covering the active and drain doped regions 120 is formed on the side of the gate structure 110.

[0110] The substrate provides a process platform for subsequent process steps. In this embodiment, the substrate is a three-dimensional substrate, including a substrate, protrusions discrete on the substrate, and a channel structure layer located on the protrusions. In other embodiments, the substrate may also be a planar substrate.

[0111] In this embodiment, the substrate is a silicon substrate. In other embodiments, the substrate material can also be other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate. The substrate can also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates. The substrate material can be a material suitable for process requirements or easy to integrate.

[0112] The protrusions provide support for the channel structure layer. In this embodiment, the protrusions are made of silicon. In other embodiments, the protrusions may also be made of other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide. In this embodiment, the protrusions and the substrate are an integral structure.

[0113] The channel structure layer is used to provide a conductive channel for the field-effect transistor. In this embodiment, the material of the channel structure layer is the same as the substrate material, which is silicon. In other embodiments, the material of the channel structure layer can also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium, or other semiconductor materials suitable for forming a channel structure layer.

[0114] In this embodiment, taking the substrate used to form a FinFET as an example, the channel structure layer is a fin. The fin is used to provide the conductive channel of the FinFET. In this embodiment, the fin and the protrusion are an integral structure.

[0115] In other embodiments, when forming a fully enclosed gate transistor or a fork-type gate transistor, a channel structure layer is suspended over the protrusion, and the channel structure layer includes one or more channel layers spaced apart and suspended. The channel layer is used to provide a conductive channel for the fully enclosed gate transistor or the fork-type gate transistor.

[0116] In this embodiment, an isolation layer (not shown) is also formed on the substrate, surrounding the protrusions and exposing the channel structure layer. The isolation layer is used to isolate adjacent protrusions and also to isolate the substrate from the gate structure 110. In this embodiment, the material of the isolation layer includes one or more of silicon oxide, silicon oxynitride, and silicon nitride.

[0117] The gate structure 110 is used to control the turning on and off of the conductive channel of the field-effect transistor. In this embodiment, the gate structure 110 is located on the isolation layer and spans the channel structure layer.

[0118] Specifically, in this embodiment, the gate structure 110 is located on the isolation layer, and the gate structure 110 spans the fin and covers a portion of the top and a portion of the sidewalls of the fin. In other embodiments, when the channel structure layer includes one or more spaced-apart channel layers, the gate structure is located on the isolation layer and surrounds the channel layers.

[0119] In this embodiment, the gate structure 110 is a metal gate structure, which is formed by forming a high k last metal gate last process after forming a high k last gate dielectric layer.

[0120] In this embodiment, the gate structure 110 includes a gate dielectric layer (not shown), a work function layer (not shown) located on the gate dielectric layer, and a gate electrode layer (not shown) located on the work function layer.

[0121] The gate dielectric layer is used to achieve electrical isolation between the work function layer and the electrode material layer and the channel structure layer.

[0122] In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer. The material of the high-k gate dielectric layer is a high-k dielectric material; wherein, a high-k dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer is HfO2. In other embodiments, the material of the high-k gate dielectric layer may also be selected from ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.

[0123] In other embodiments, the gate dielectric layer may further include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer. The gate oxide layer is made of one or both of silicon oxide and silicon oxynitride. In still other embodiments, the gate dielectric layer may consist only of a gate oxide layer.

[0124] The work function layer is used to adjust the work function of the metal gate structure, thereby regulating the threshold voltage of the transistor. When forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the work function layer includes one or more of titanium aluminide, tantalum carbide, aluminum, or titanium carbide. When forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the work function layer includes one or more of titanium nitride, tantalum nitride, titanium carbide, silicon tantalum nitride, silicon titanium nitride, and tantalum carbide.

[0125] The electrode material layer serves as an electrode, used to draw out the electrical properties of the metal gate structure, thereby achieving electrical connection between the metal gate structure and external circuitry. In this embodiment, the electrode material layer is made of W. In other embodiments, the electrode material layer may also be made of Al, Cu, Ag, Au, Pt, Ni, or Ti, etc.

[0126] In a specific embodiment, a gate sidewall (not shown) may also be formed on the sidewall of the gate structure 110. The gate sidewall is used to protect the sidewall of the gate structure 110 and to define the formation location of the source and drain doped regions 120.

[0127] The gate sidewall can be a single layer or a multilayer structure. As an example, the gate sidewall material includes one or more of silicon oxide, low-k dielectric materials, and ultra-low-k dielectric materials.

[0128] During device operation, the source / drain doped regions 120 are used to provide carrier sources. In this embodiment, the source / drain doped regions 120 are located on both sides of the gate structure 110 and the gate sidewalls. Specifically, the source / drain doped regions 120 are located in the fins on both sides of the gate structure 110.

[0129] In this embodiment, the source / drain doped region 120 includes a stress layer doped with ions. The source / drain doped region 120 is also used to provide stress to the channel, thereby improving the carrier mobility of the channel.

[0130] Specifically, when forming an NMOS transistor, the source and drain doped regions 120 are made of a stress layer doped with N-type ions. The stress layer is made of Si or SiC. The stress layer provides tensile stress to the channel region of the NMOS transistor, which helps to improve the carrier mobility of the NMOS transistor. The N-type ions are P ions, As ions, or Sb ions.

[0131] When forming a PMOS transistor, the source and drain doped regions 120 are made of a stress layer doped with P-type ions. The stress layer is made of Si or SiGe. The stress layer provides compressive stress to the channel region of the PMOS transistor, which helps to improve the carrier mobility of the PMOS transistor. The P-type ions are B ions, Ga ions, or In ions.

[0132] In this embodiment, a first barrier layer 140 and a second barrier layer 150 are respectively formed on the sidewall and top of the gate structure 110. The first dielectric layer 130 covers the sidewall of the first barrier layer 140.

[0133] The first barrier layer 140 located on the sidewall of the gate structure 110 is used to define the etching stop position along the extension direction perpendicular to the gate structure 110 in the subsequent step of forming interconnect openings, thereby defining the position and opening size of the interconnect openings located in the first dielectric layer 130, and also reducing the probability of the process of forming interconnect openings damaging the sidewall of the gate structure 110.

[0134] It should be noted that, in the step of providing the substrate, a first barrier layer 140 is also formed between the source / drain doped region 120 and the first dielectric layer 130. Thus, in the subsequent step of forming interconnect openings, the first barrier layer 140 located on the source / drain doped region 120 can temporarily define the etching stop position, reducing the probability of damage to the source / drain doped region 120 during the interconnect opening formation process. Furthermore, when a first sidewall, a sacrificial sidewall, and a second sidewall are subsequently formed sequentially on the sidewalls of the interconnect opening, the first barrier layer 140, located at the bottom of the interconnect opening, can also define the etching stop position during the steps of forming the first sidewall, sacrificial sidewall, and second sidewall, thereby reducing the probability of damage to the source / drain doped region 120. In addition, in the subsequent step of removing the sacrificial sidewall to form an air sidewall, the first barrier layer 140 is located at the bottom of the air sidewall, thereby preventing the source / drain doped region from being exposed, further reducing the probability of damage to the source / drain doped region 120 during the sacrificial sidewall removal process.

[0135] In this embodiment, the first barrier layer 140 is a contact etch stop layer (CESL), which allows existing contact etch stop layers to be used as the first barrier layer 140 without requiring additional process steps to form it, thus improving process compatibility and process integration. Specifically, in this embodiment, the first barrier layer 140 is formed on the source / drain doped regions 120 and on the sidewalls of the exposed gate structure 120 of the source / drain doped regions 120.

[0136] In this embodiment, the first barrier layer 140 is selected from materials that have etching selectivity with the material of the first dielectric layer 130. In this embodiment, the material of the first barrier layer 140 includes one or more of the following: silicon oxycarbonate, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon carbonitride, silicon germanium oxide, boron nitride, and boron carbonitride.

[0137] The second barrier layer 150 serves to protect the top of the gate structure 110 during the subsequent step of forming interconnect openings, thereby reducing the probability of damage to the gate structure 110 caused by the interconnect opening process; and, during the subsequent step of forming a gate plug that contacts the top of the gate structure 110, the second barrier layer 150 located on the top of the gate structure 110 can temporarily define the etch stop position, thereby improving the bottom depth consistency of the gate plug.

[0138] The second barrier layer 150 is selected from materials that have etching selectivity with the material of the first dielectric layer 130. In this embodiment, the material of the second barrier layer 150 includes one or more of the following: silicon oxycarbonate, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon carbonitride, silicon germanium oxide, boron nitride, and boron carbonitride.

[0139] The first dielectric layer 130 is used to isolate adjacent gate structures 110. After the source-drain interconnect layer is subsequently formed, the first dielectric layer 130 is also used to isolate adjacent source-drain interconnect layers.

[0140] The material of the first dielectric layer 130 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of the first dielectric layer 130 is silicon oxide.

[0141] The steps for providing the substrate in this embodiment will be described in detail below with reference to the accompanying drawings.

[0142] like Figure 6 As shown, a substrate is provided, a gate structure 110 discrete on the substrate, source and drain doped regions 120 located in the substrate on both sides of the gate structure 110, a first barrier layer 140 located on the sidewall of the gate structure 110, and a first dielectric layer 130 located on the side of the gate structure 110 and the first barrier layer 140 and covering the source and drain doped regions 120.

[0143] Specifically, a substrate is provided; a separate dummy gate structure (not shown) is formed on the substrate; source / drain doped regions 120 are formed in the substrate on both sides of the dummy gate structure; a first barrier layer 140 is formed on the sidewalls of the dummy gate structure and on the source / drain doped regions 120; and a first dielectric layer 130 is filled in the area enclosed by the first barrier layer 140.

[0144] like Figure 7 As shown, a second barrier layer 150 is formed on the top of the gate structure 110, and the second barrier layer 150 is also formed on the first dielectric layer 130. In this embodiment, the top surface of the gate structure 110 is flush with the top surface of the first dielectric layer 130.

[0145] In this embodiment, the second barrier layer 150 is also formed on the first dielectric layer 130, so that the second dielectric layer is subsequently formed on the second barrier layer 150. In the subsequent step of forming interconnect openings, the second dielectric layer above the source / drain doped region 120 can be etched first with the top surface of the second barrier layer 150 as the stop position, which is beneficial to obtain a larger opening size for the interconnect openings in the second dielectric layer.

[0146] It should be noted that the above steps for providing a substrate are only an example, and the steps for providing a substrate are not limited to this.

[0147] For example, in other embodiments, the step of providing the substrate includes: Figure 8 As shown, a substrate is provided, a gate structure 110a discretely disposed on the substrate, source / drain doped regions 120a located in the substrate on both sides of the gate structure 110a, a first barrier layer 140a located on the sidewall of the gate structure 110a, and a first dielectric layer 130a located on the sides of the gate structure 110a and the first barrier layer 140a and covering the source / drain doped regions 120a; as Figure 9 As shown, a portion of the gate structure 110a is removed, leaving the top of the remaining gate structure 110a forming a trench 145a with the first barrier layer 140a; as Figure 10 As shown, a second barrier layer 150a is formed within the trench 145a.

[0148] The second barrier layer 150a is formed only on the top of the gate structure 110a, so that the subsequent second dielectric layer is formed on the second barrier layer 150a and the first dielectric layer 130a. In the step of forming the interconnect opening, it is not necessary to etch the second barrier layer 150a located above the source / drain doped region 120a. After removing the second dielectric layer located above the source / drain doped region 120a, the first dielectric layer 130a can be etched. During the etching of the first dielectric layer 130a above the source / drain doped region 120a, the first barrier layer 140a located on the sidewall of the gate structure 110a can be used as a stop layer along the extension direction perpendicular to the gate structure, thereby achieving self-alignment of the etching.

[0149] refer to Figure 11 A second dielectric layer 160 is formed on top of the first dielectric layer 130 and the gate structure 110. Subsequently, a source-drain interconnect layer is formed in the first dielectric layer 130 and the second dielectric layer 160 on top of the source-drain doped region 120. The second dielectric layer 160 is used to achieve isolation between adjacent source-drain interconnect layers, as well as isolation between the source-drain interconnect layers and the gate plug, and isolation between adjacent gate plugs.

[0150] The second dielectric layer 160 is made of an insulating material, and the second dielectric layer 160 is selected from materials that have high etching selectivity between the first barrier layer 140 and the second barrier layer 150. The material of the second dielectric layer 160 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of the second dielectric layer 160 is silicon oxide.

[0151] In this embodiment, a second barrier layer 150 is also formed on the top of the gate structure 110, and a second dielectric layer 160 is formed on the first dielectric layer 130 and the second barrier layer 150. Specifically, in this embodiment, the second dielectric layer 160 covers the second barrier layer 150.

[0152] refer to Figure 12 An interconnect opening 200 is formed, penetrating the top of the first dielectric layer 130 and the second dielectric layer 160 on the source / drain doped region 120. Along a direction perpendicular to the gate structure 110, the opening width of the interconnect opening 200 in the second dielectric layer 160 is greater than the opening width of the interconnect opening 200 in the first dielectric layer 160. The interconnect opening 200 provides space for forming the source / drain interconnect layer and the sidewall structure layer.

[0153] Along the direction perpendicular to the gate structure 110, the opening width of the interconnect opening 200 in the second dielectric layer 160 is greater than the opening width of the interconnect opening 200 in the first dielectric layer 160. Correspondingly, after the source-drain interconnect layer is subsequently filled in the interconnect opening 200, the width of the portion of the source-drain interconnect layer located in the second dielectric layer 160 is larger than that of the portion of the source-drain interconnect layer located in the first dielectric layer 130, thereby increasing the top width of the exposed source-drain interconnect layer and thus increasing the top area of ​​the source-drain interconnect layer for receiving the source-drain plug.

[0154] In this embodiment, the interconnect opening 200 includes a top opening 21 in the second dielectric layer 160 and a bottom opening 22 in the first dielectric layer 130 below the top opening 21. Along the extension direction perpendicular to the gate structure 110, the opening size of the top opening 21 is larger than the opening size of the bottom opening 22.

[0155] In this embodiment, along the direction perpendicular to the gate structure 110, the sidewall of the top opening 21 is located on the side of the same sidewall of the bottom opening 22 away from the source / drain doped region 120. Thus, on the projection plane parallel to the substrate, the top opening 21 covers the bottom opening 22 and expands outward relative to the bottom opening 22. After the source / drain interconnect layer located in the interconnect opening 200 is subsequently formed, the source / drain interconnect layer located in the top opening 21 serves as the top interconnect layer, and the source / drain interconnect layer located in the bottom opening 22 serves as the bottom interconnect layer. Thus, on the projection plane parallel to the substrate, the top interconnect layer not only covers the area of ​​the bottom interconnect layer but also extends outward. In the subsequent step of forming the source / drain plug that contacts the source / drain interconnect layer, the source / drain plug contacts the top interconnect layer, and the portion of the top interconnect layer protruding from the bottom interconnect layer can increase the tolerance space for overlay offset in forming the source / drain plug, thereby increasing the process window for forming the source / drain plug and increasing the distance between the air sidewall and the top interconnect layer, thereby reducing the risk that the process of forming the source / drain plug will open the top of the air sidewall.

[0156] Specifically, in this embodiment, in the step of forming the interconnect opening 200, the interconnect opening 200 exposes the sidewall of the first barrier layer 140 located on the sidewall of the gate structure 110, thereby increasing the opening size of the interconnect opening 200 along the extension direction perpendicular to the gate structure 110, which is beneficial to increase the volume of the source-drain interconnect layer subsequently formed in the interconnect opening 200 and correspondingly reduce the resistance of the source-drain interconnect layer; and, since the interconnect opening 200 exposes the sidewall of the first barrier layer 140, the position and size of the bottom opening 22 are defined by the first barrier layer 140 along the extension direction perpendicular to the gate structure 110, and the first barrier layer 140 located on the sidewall of the gate structure 110 can serve as an etch stop layer for forming the bottom opening 22, thereby achieving self-alignment of the etching process, correspondingly reducing the process difficulty and improving the control accuracy of the cross-sectional morphology and size of the bottom opening 22.

[0157] In this embodiment, during the step of forming the interconnect opening 200, the bottom of the interconnect opening 200 exposes the first barrier layer 140 located on the source / drain doped region 120.

[0158] It should be noted that the difference between the opening size d1 of the top opening 21 and the opening size d2 of the bottom opening 22 along the extension direction perpendicular to the gate structure 110 should not be too small or too large. If the difference between the opening sizes is too small, the effect of increasing the opening size of the interconnect opening 200 near the top will be insignificant, and consequently, the effect of increasing the top width of the exposed source-drain interconnect layer after the subsequent formation of the source-drain interconnect layer will be insignificant. If the difference between the opening sizes is too large, the opening size d1 of the top opening 21 will be too large, and consequently, the width of the remaining second dielectric layer 160 on the top of the gate structure 110 along the extension direction perpendicular to the gate structure 110 will be too small, which will increase the process difficulty of forming a gate plug that penetrates the second dielectric layer 160 and contacts the top of the gate structure 110. Therefore, in this embodiment, in the step of forming the interconnect opening 200, along the extension direction perpendicular to the gate structure 110, the opening size d1 of the top opening 21 is 2 nanometers to 6 nanometers larger than the opening size d2 of the bottom opening 22.

[0159] In this embodiment, the step of forming the interconnect opening 200 includes: forming a patterned layer (not shown) on the second dielectric layer, wherein a patterned opening (not shown) is formed in the patterned layer above the source / drain doped region 120, and the boundary of the patterned opening is located on the side of the first barrier layer 140 away from the source / drain doped region 120; using the patterned layer as a mask, etching the second dielectric layer 160 below the patterned opening to form a top opening 21; using the first barrier layer 140 as a stop layer along the extension direction perpendicular to the gate structure 110, etching the first dielectric layer 130 below the top opening 21 to form a bottom opening 22, wherein the bottom opening 22 is connected to the top opening 21 to form the interconnect opening 200; and removing the patterned layer.

[0160] The patterned layer is used as an etching mask to form the interconnect openings 200. As an example, the material of the patterned layer includes photoresist.

[0161] The boundary of the patterned opening is located on the side of the first barrier layer 140 sidewall away from the source / drain doped region 120, so that the size of the patterned opening is larger than the distance between the adjacent first barrier layer 140 sidewalls. As a result, in the step of etching the second dielectric layer 160 below the patterned opening using the patterned layer as a mask to form the top opening 21, the size of the formed top opening 21 is larger.

[0162] In this embodiment, using the patterned layer as a mask, an anisotropic etching process is employed to etch the second dielectric layer 160 below the patterned opening, forming the top opening 21. The anisotropic etching process improves pattern transfer accuracy, thereby enhancing the dimensional accuracy, cross-sectional topography quality, and sidewall steepness of the top opening 21. As an example, the anisotropic etching process is an anisotropic dry etching process.

[0163] In this embodiment, the first barrier layer 140 is used as a stop layer along the extension direction perpendicular to the gate structure 110. The first dielectric layer 130 below the top opening 21 is etched to form the bottom opening 22, thereby achieving self-alignment of the etching, which reduces the difficulty of forming the bottom opening 22 and improves the dimensional accuracy of the bottom opening 22. The position and opening size of the bottom opening 22 are defined by the first barrier layer 140 located on the sidewall of the gate structure 110, which correspondingly improves the cross-sectional morphology quality and sidewall steepness of the bottom opening 22, and can also increase the spatial size of the bottom opening 22.

[0164] In this embodiment, an anisotropic etching process is used to etch the first dielectric layer 130 below the top opening 21.

[0165] It should be noted that in this embodiment, the second barrier layer 150 is also formed on the first dielectric layer 130. Therefore, before etching the first dielectric layer 130 below the top opening 21, the second barrier layer 150 located on the first dielectric layer 130 is also etched.

[0166] In other embodiments, for example, when the second barrier layer 150a is formed only on top of the gate structure 110a (e.g.) Figure 10 As shown, after forming the top opening, the first dielectric layer 130a below the top opening can be etched, which helps to simplify the process flow.

[0167] refer to Figure 13 A first sidewall 31, a sacrificial sidewall 34, and a second sidewall 32 are formed sequentially on the sidewall of the interconnect opening 200. The first sidewall 31 and the second sidewall 32 are used to achieve isolation between the gate structure 110 and the source-drain interconnect layer.

[0168] The first sidewall 31 and the second sidewall 32 are selected from materials that have etching selectivity with respect to the material of the second dielectric layer 160. As an example, the material of the first sidewall 31 includes one or more of silicon oxide, low-k dielectric materials, and ultra-low-k dielectric materials. As an example, the material of the second sidewall 32 includes one or more of silicon oxide, low-k dielectric materials, and ultra-low-k dielectric materials.

[0169] In this embodiment, the materials of the first sidewall 31 and the second sidewall 32 are the same, which is beneficial for improving process compatibility. In this embodiment, the materials of the first sidewall 31 and the second sidewall 32 are low-k dielectric materials, which is beneficial for further reducing the parasitic capacitance between the gate structure 110 and the source-drain interconnect layer.

[0170] The sacrificial sidewall 34 is used to occupy space for the formation of the air sidewall.

[0171] The sacrificial sidewall 34 is made of a material that is easy to remove and has etching selectivity with the materials of the first sidewall 31, the second sidewall 32, and the second dielectric layer 160, thereby reducing the difficulty of subsequent removal of the sacrificial sidewall 34 and reducing the probability of damage to the first sidewall 31, the second sidewall 32, and the second dielectric layer 160 during the removal of the sacrificial sidewall 34.

[0172] In this embodiment, the material of the sacrificial sidewall 34 includes one or more of amorphous silicon, silicon oxycarbide, silicon oxide, silicon nitride, silicon carbide, boron nitride, aluminum oxide, aluminum nitride, and silicon oxynitride.

[0173] In this embodiment, the bottom of the interconnect opening 200 exposes the first barrier layer 140 located on the source / drain doped region 120. Therefore, in the step of forming the first sidewall 31, the sacrificial sidewall 34, and the second sidewall 32, the first sidewall 31, the sacrificial sidewall 34, and the second sidewall 32 are formed on the first barrier layer 140, which helps to reduce the probability of damage to the source / drain doped region 120 during the process of forming the first sidewall 31, the sacrificial sidewall 34, and the second sidewall 32.

[0174] Specifically, in this embodiment, in the bottom opening 21, a first sidewall 31 is formed on a first barrier layer 140 located on the sidewall of the gate structure 110.

[0175] In this embodiment, a first sidewall 31, a sacrificial sidewall 34, and a second sidewall 32 are sequentially formed on the sidewall of the interconnection opening 200.

[0176] Specifically, the step of forming the first sidewall 31 includes: forming a first sidewall material layer (not shown) on the sidewall and bottom of the interconnect opening 200 and on the top of the second dielectric layer 160; using an anisotropic etching process to remove the first sidewall material layer located on the bottom of the interconnect opening 200 and the top of the second dielectric layer 160, and the remaining first sidewall material layer located on the sidewall of the interconnect opening 200 is used as the first sidewall 31.

[0177] Specifically, the steps of forming the sacrificial sidewall 34 include: forming a second sidewall material layer (not shown) on the sidewall of the first sidewall 31, the bottom of the interconnect opening 200, and the top of the second dielectric layer 160; using an anisotropic etching process to remove the second sidewall material layer located at the bottom of the interconnect opening 200 and the top of the second dielectric layer 160, and the remaining second sidewall material layer located on the sidewall of the first sidewall 31 is used as the sacrificial sidewall 34.

[0178] Specifically, the steps of forming the second sidewall 32 include: forming a third sidewall material layer (not shown) on the sidewall of the sacrificial sidewall 34, the bottom of the interconnect opening 200, and the top of the second dielectric layer 160; using an anisotropic etching process to remove the third sidewall material layer located at the bottom of the interconnect opening 200 and the top of the second dielectric layer 160, and the remaining third sidewall material layer located on the sidewall of the sacrificial sidewall 34 is used as the second sidewall 32.

[0179] The process for forming the first, second, and third sidewall material layers includes atomic layer deposition (ALD). ALD can improve the deposition uniformity of the film layers, which is beneficial for improving the thickness uniformity of the first, second, and third sidewall material layers, and also helps to precisely control the thickness of the first, second, and third sidewall material layers.

[0180] In the steps of removing the first sidewall material layer located at the bottom of the interconnect opening 200 and the top of the second dielectric layer 160, removing the second sidewall material layer located at the bottom of the interconnect opening 200 and the top of the second dielectric layer 160, and removing the third sidewall material layer located at the bottom of the interconnect opening 200 and the top of the second dielectric layer 160, the first barrier layer 140 located at the bottom of the interconnect opening 200 can define the etching stop position, thereby improving the etching uniformity and reducing the probability of damage to the source / drain doped region 120.

[0181] In this embodiment, the anisotropic etching process is an anisotropic dry etching process.

[0182] It should be noted that, in this embodiment, since the source / drain doped region 120 at the bottom of the interconnect opening 200 also has a first barrier layer 140, therefore, referring to Figure 14 The method for forming a semiconductor structure further includes: after forming the first sidewall 31, the sacrificial sidewall 34, and the second sidewall 32, and before forming the source-drain interconnect layer, removing the first barrier layer 140 exposed by the first sidewall 31, the sacrificial sidewall 34, and the second sidewall 32, thereby exposing the source-drain doped region 120 to the interconnect opening 200 so that the subsequent source-drain interconnect layer can contact the source-drain doped region 120.

[0183] As an example, an isotropic etching process is used to remove the first barrier layer 140 exposed on the first sidewall 31, the sacrificial sidewall 34, and the second sidewall 32.

[0184] refer to Figure 15 The source-drain interconnect layer 240 is filled in the interconnect opening 200. The source-drain interconnect layer 240 is in contact with the source-drain doped region 120 and covers the sidewall of the second sidewall 32.

[0185] The source-drain interconnect layer 240 is in contact with the source-drain doped region 120 and is used to realize the electrical connection between the source-drain doped region 120 and the external circuit. Specifically, the source-drain interconnect layer 240 is used to realize the electrical connection between the source-drain doped region 120 and the subsequent source-drain plug.

[0186] Along the direction perpendicular to the gate structure 110, the opening width of the interconnect opening 200 in the second dielectric layer 160 is greater than the opening width of the interconnect opening 200 in the first dielectric layer 160. Correspondingly, the width of the portion of the source-drain interconnect layer 240 located in the second dielectric layer 160 is larger than the portion of the source-drain interconnect layer 240 located in the first dielectric layer 130. This increases the exposed top width of the source-drain interconnect layer 240, thereby increasing the top area of ​​the source-drain interconnect layer 240 for receiving the source-drain plug, which is beneficial for increasing the process window for forming the source-drain plug.

[0187] In this embodiment, the portion of the source-drain interconnect layer 240 located in the top opening 21 serves as the top interconnect layer 42, and the portion of the source-drain interconnect layer 240 located in the bottom opening 22 serves as the bottom interconnect layer 41. Along the extension direction perpendicular to the gate structure 110, the width of the top interconnect layer 42 is greater than the width of the bottom interconnect layer 41.

[0188] As an example, the source-drain interconnect layer 240 is made of copper. Copper has low resistivity, which helps improve the back-end RC delay, increases chip processing speed, and also reduces the resistance of the source-drain interconnect layer 240, thereby reducing power consumption. In other embodiments, the source-drain interconnect layer can also be made of conductive materials such as tungsten or cobalt.

[0189] In this embodiment, the step of forming the source-drain interconnect layer 240 includes: filling the interconnect opening 200 with a conductive material layer (not shown), the conductive material layer also being formed on top of the second dielectric layer 160; removing the conductive material layer located on top of the second dielectric layer 160, the remaining conductive material layer being used as the source-drain interconnect layer 240.

[0190] In this embodiment, one or more of the following processes are used to form a conductive material layer: chemical vapor deposition, physical vapor deposition, and electrochemical plating.

[0191] In this embodiment, a planarization process (e.g., chemical mechanical planarization) is used to remove the conductive material layer located on top of the second dielectric layer 160.

[0192] refer to Figure 16 Remove the sacrificial sidewall 34 to form an air sidewall 35 between the first sidewall 31 and the second sidewall 32.

[0193] Air has a lower dielectric constant than commonly used dielectric materials in semiconductor processes (e.g., low-k dielectric materials or ultra-low-k dielectric materials), thereby significantly reducing the coupling capacitance between the gate structure 110 and the source-drain interconnect layer 240 by forming air sidewalls 35.

[0194] In this embodiment, an isotropic etching process is used to remove the sacrificial sidewall 34. The isotropic etching process has the characteristics of isotropic etching and strong interstitial etching ability, which is beneficial to remove the sacrificial sidewall 34 cleanly and reduce the probability of sacrificial sidewall 34 residue.

[0195] Specifically, the isotropic etching process includes one or both of dry and wet etching processes. As an example, a dry etching process is used to remove the sacrificial sidewall 34. The etching gas used in the dry etching process includes NF3 and HF. The dry etching process forms a highly active plasma by dissociating NF3 and HF gases. The plasma etches the sacrificial sidewall 34, which is beneficial for removing the sacrificial sidewall 34 cleanly and can achieve a high etching selectivity.

[0196] In this embodiment, since the first sidewall 31, the sacrificial sidewall 34 and the second sidewall 32 are formed on the first barrier layer 140 located on the top of the source / drain doped region 120, the first barrier layer 140 can protect the source / drain doped region 120, thereby preventing the source / drain doped region 120 from being exposed to the process environment of removing the sacrificial sidewall 34, and thus reducing the probability of damage to the source / drain doped region 120.

[0197] In this embodiment, after the air sidewall 35 is formed, the first sidewall 31, the air sidewall 35, and the second sidewall 32 are used to form the sidewall structure layer 230.

[0198] refer to Figure 17 A third dielectric layer 250 is formed on the second dielectric layer 160 and the source-drain interconnect layer 240 to seal the top of the air sidewall 21. The third dielectric layer 250 is used to seal the air sidewall 21 and, after the subsequent formation of the source-drain plugs and the gate plugs, to achieve isolation between the source-drain plugs, between the gate plugs, and between the source-drain plugs and the gate plugs.

[0199] The third dielectric layer 250 can be a single layer or a multilayer structure. The material of the third dielectric layer 250 includes one or more of the following: silicon oxide, carbon-containing silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon carbonitride, germanium silicon oxide, boron nitride, and boron carbonitride.

[0200] As an example, the third dielectric layer 250 is a stacked structure, and the steps of forming the third dielectric layer 250 include: forming an etch stop layer 51 on the second dielectric layer 160 that covers the source-drain interconnect layer 240, the first sidewall 31, and the second sidewall 32, the etch stop layer 51 sealing the top of the air sidewall 35; and forming a dielectric material layer 52 on the etch stop layer 51.

[0201] The etch stop layer 51 can temporarily define the location of the etch stop in the subsequent source / drain plug formation step, thereby improving the bottom depth consistency of the source / drain plug and reducing the probability of damage to the source / drain interconnect layer 240.

[0202] The etch stop layer 51 is selected from materials that exhibit etch selectivity with respect to the materials of the second dielectric layer 160 and the dielectric material layer 52. As an example, the material of the etch stop layer 51 includes one or more of silicon oxycarbonate, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon carbonitride, germanium silicon oxide, boron nitride, and boron carbonitride. Specifically, the material of the etch stop layer 51 is silicon nitride.

[0203] In this embodiment, the dielectric material layer 52 is made of silicon oxide.

[0204] refer to Figure 18 A source / drain plug 210 is formed in the third dielectric layer 250 on top of the source / drain interconnect layer 240, which contacts the source / drain interconnect layer 240. In this embodiment, the source / drain plug 210 contacts the top interconnect layer 42.

[0205] The source-drain plug 210 is used to realize the electrical connection between the source-drain interconnect layer 240 and the external circuit.

[0206] In this embodiment, the portion of the source-drain interconnect layer 240 located in the second dielectric layer 160 is wider than the portion of the source-drain interconnect layer 240 located in the first dielectric layer 130. This increases the exposed top width of the source-drain interconnect layer 240, resulting in a larger area of ​​the source-drain interconnect layer 240 for receiving the source-drain plug 210. Even if there is an overlay offset during the process of forming the source-drain plug 210, the probability of the etching process of forming the source-drain plug 210 causing mis-etching to the top of the second sidewall 32 and the top of the air sidewall 35 is also low. This reduces the risk of the top of the air sidewall 35 being opened, ensuring the effectiveness of the air sidewall 35 in reducing the parasitic capacitance between the source-drain interconnect layer 240 and the gate structure 110. Furthermore, it increases the process window for forming the source-drain plug 210 and improves the performance of the semiconductor structure.

[0207] Specifically, in this embodiment, since the width of the top interconnect layer 42 is relatively large, the distance between the second sidewall 32 and the air sidewall 35 located on the sidewall of the top interconnect layer 42 and the source / drain plug 210 is increased, thereby reducing the probability of accidental etching of the top of the second sidewall 32 and the air sidewall 35 during the step of forming the source / drain plug 210.

[0208] The source / drain plug 210 is made of a conductive material. In this embodiment, the source / drain plug 210 is made of tungsten. In other embodiments, the source / drain plug may also be made of conductive materials such as copper or cobalt.

[0209] In this embodiment, the step of forming the source / drain plug 210 includes: forming a source / drain contact hole (not shown) penetrating the third dielectric layer 250 at the top of the source / drain interconnect layer 240, with the source / drain interconnect layer 240 exposed at the bottom of the source / drain contact hole; and filling the source / drain plug 210 into the source / drain contact hole.

[0210] The source / drain contact hole is used to provide space for forming the source / drain plug 210.

[0211] In this embodiment, an etching process is used to form source / drain contact holes. Because this embodiment increases the width of the top interconnect layer 42, the exposed top width of the source / drain interconnect layer 240 is increased. The area of ​​the source / drain interconnect layer 240 used to receive the source / drain plug 210 is larger. Even if there is an overlay misalignment in the etching process for forming the source / drain contact holes, the probability of the etching process causing accidental etching of the top of the second sidewall 32 and the top of the air sidewall 35 is low. This reduces the risk of the top of the air sidewall 35 being opened and increases the process window for forming the source / drain contact holes.

[0212] In this process, an anisotropic etching process is used to form the source / drain contact holes. During the formation of the source / drain contact holes, the anisotropic etching process has a low probability of causing accidental etching on the top of the second sidewall 32 and the air sidewall 35.

[0213] In this embodiment, the step of filling the source drain plug 210 in the source drain contact hole includes: filling the source drain contact hole with a source drain plug material layer (not shown), the source drain plug material layer is also formed on the third dielectric layer 250; using a planarization process, the source drain plug material layer located on the third dielectric layer 250 is removed, and the remaining plug material layer located in the source drain contact hole is used as a source drain plug.

[0214] In this embodiment, one or more of the following processes are used: chemical vapor deposition, physical vapor deposition, and electrochemical plating, to form the source / drain plug material layer.

[0215] In this embodiment, a chemical mechanical planarization process is used to remove the source / drain plug material layer located on the third dielectric layer 250.

[0216] It should be noted that, in this embodiment, the method for forming the semiconductor structure further includes: after forming the third dielectric layer 250, forming a gate plug 220 that penetrates the second dielectric layer 160 and the third dielectric layer 250 on the top of the gate structure 110, and the gate plug 220 is in contact with the gate structure 110.

[0217] The gate plug 220 is used to realize the electrical connection between the gate structure 110 and the external circuit.

[0218] In this embodiment, the sidewall structure layer 230 is also located between the source-drain interconnect layer 240 and the second dielectric layer 160, that is, the air sidewall 35 is also located between the source-drain interconnect layer 240 and the second dielectric layer 160, so the air sidewall 35 can also reduce the parasitic capacitance between the source-drain interconnect layer 240 and the gate plug 220.

[0219] The gate plug 220 is made of a conductive material. In this embodiment, the gate plug 220 is made of tungsten. In other embodiments, the gate plug may also be made of conductive materials such as copper or cobalt.

[0220] In this embodiment, the step of forming the gate plug 220 includes: forming a gate contact hole (not shown) penetrating the third dielectric layer 250 at the top of the gate structure 110, with the bottom of the gate contact hole exposing the gate structure 110; and filling the source / drain contact hole with the gate plug 220.

[0221] For a detailed description of the step of forming the gate plug 220, please refer to the foregoing description of the step of forming the source-drain plug, which will not be repeated here.

[0222] Figures 19 to 22 This is a schematic diagram of the structure corresponding to each step in another embodiment of the method for forming a semiconductor structure of the present invention. The similarities between this embodiment and the previous embodiments will not be repeated here. The differences between this embodiment and the previous embodiments are:

[0223] refer to Figure 19 After forming the source-drain interconnect layer 440 and before removing the sacrificial sidewall 434, the method of forming the semiconductor structure further includes: removing a portion of the height of the sacrificial sidewall 434, such that the top of the remaining sacrificial sidewall 434 forms a gap 436 with the first sidewall 431 and the second sidewall 432, and the bottom of the gap 436 is higher than the top surface of the gate structure 110.

[0224] The sacrificial sidewall 434 with a portion of its height is removed to form a gap 436, so that a third sidewall can be formed on the sidewall of the gap 436, thereby reducing the width of the air sidewall near the top.

[0225] The bottom of the gap 436 is higher than the top surface of the gate structure 310, thereby avoiding the subsequent formation of a third sidewall from affecting the size of the air sidewall between the gate structure 310 and the source-drain interconnect layer 440. This ensures that the air sidewall between the gate structure 310 and the source-drain interconnect layer 440 has sufficient volume, thus ensuring the effectiveness of the air sidewall in reducing the parasitic capacitance between the gate structure 310 and the source-drain interconnect layer 440.

[0226] In this embodiment, an isotropic etching process is used to remove a portion of the sacrificial sidewalls 434.

[0227] refer to Figure 20 A third sidewall 433 is formed on the sidewall of the gap 436, and the third sidewall 433 exposes part of the top surface of the remaining sacrificial sidewall 434.

[0228] The third sidewall 433 is used together with the air sidewall, the first sidewall 431, and the second sidewall 432 to form a sidewall structure layer. The third sidewall 433 is also used to reduce the size of the air sidewall near the top and increase the width of the sidewall structure layer located on the sidewall of the top interconnect layer 442, thereby further reducing the probability of etching open the top of the air sidewall during the subsequent formation of the source / drain plug.

[0229] In this embodiment, the third sidewall 433 exposes part of the top surface of the remaining sacrificial sidewall 434 so that the remaining sacrificial sidewall 434 can be removed subsequently.

[0230] The material of the third sidewall 433 is an insulating material. In this embodiment, the material of the third sidewall 433 includes one or more of silicon oxide, low-k dielectric materials, and ultra-low-k dielectric materials. In this embodiment, the third sidewall 433, the second sidewall 432, and the first sidewall 431 are made of the same material, thereby improving process compatibility.

[0231] Along the extension direction perpendicular to the gate structure 410, the width of the gap 436 is a first width. In the step of forming the third sidewall 433, along the extension direction perpendicular to the gate structure 410, the thickness of the third sidewall 433 is a second width. The proportion of the second width to the first width should not be too small or too large. If the proportion is too small, the effect of the third sidewall 433 in reducing the size of the gap 436 will be insignificant, and the thickness of the third sidewall 433 will be too small, which will increase the difficulty of forming the third sidewall 433. If the proportion is too large, the area of ​​the top of the remaining sacrificial sidewall 434 exposed by the gap 436 will be too small, or even the third sidewall 433 located on the sidewall of the gap 436 will come into contact, thus filling the gap 436 completely, which will increase the difficulty of removing the remaining sacrificial sidewall 434 in the future. Therefore, in this embodiment, the second width is greater than or equal to 10% of the first width and less than 50% of the first width.

[0232] In this embodiment, the step of forming the third sidewall 433 includes: forming a fourth sidewall material layer (not shown) on the sidewall and bottom of the gap 436 and on top of the second dielectric layer 360 and the source-drain interconnect layer 440; removing the fourth sidewall material layer located on the bottom surface of the gap 436 and on top of the second dielectric layer 360 and the source-drain interconnect layer 440, and using the remaining fourth sidewall material layer on the sidewall of the gap 436 as the third sidewall 433.

[0233] In this embodiment, atomic layer deposition (ALD) is used to form the fourth sidewall material layer. ALD is advantageous for forming thinner films with high step coverage and improves the thickness uniformity of the fourth sidewall material layer.

[0234] In this embodiment, an anisotropic dry etching process is used to remove the fourth sidewall material layer located on the bottom surface of the gap 436 and on top of the second dielectric layer 360 and the source-drain interconnect layer 440.

[0235] refer to Figure 21 The sacrificial sidewall 434 is removed, and an air sidewall 435 is formed between the first sidewall 431 and the second sidewall 432. The air sidewall 435, together with the first sidewall 431, the second sidewall 432 and the third sidewall 433, constitutes the sidewall structural layer 430.

[0236] In this embodiment, an isotropic etching process is used to remove the sacrificial sidewall 434. Specifically, the isotropic etching process includes one or both of dry etching and wet etching processes. As an example, a dry etching process is used to remove the sacrificial sidewall 434. The etching gas used in the dry etching process includes NF3 and HF. The dry etching process forms a highly active plasma by dissociating NF3 and HF gases, which can penetrate into the gap 436 to etch the sacrificial sidewall 434, thus facilitating the complete removal of the remaining sacrificial sidewall 434.

[0237] refer to Figure 22 A third dielectric layer 450 is formed on the second dielectric layer 360 and the source-drain interconnect layer 440 to seal the top of the air sidewall 435; a source-drain plug 410 is formed in the third dielectric layer 450 on top of the source-drain interconnect layer 440 to contact the source-drain interconnect layer 440.

[0238] In this embodiment, since the sidewall structure layer 430 also includes a third sidewall 433, the width of the sidewall structure layer 430 near the top is larger, and the size of the air sidewall 435 near the top is smaller, thereby increasing the distance between the top of the air sidewall 435 and the source / drain plug 410, thereby further reducing the risk of the top of the air sidewall 435 being opened when the source / drain plug 410 is formed and increasing the process window for forming the source / drain plug 410.

[0239] Furthermore, the bottom of the third sidewall 433 is higher than the top of the gate structure 310, thereby ensuring that the air sidewall 435 located between the bottom interconnect layer 441 and the gate structure 310 has sufficient width, and correspondingly ensuring the effectiveness of the air sidewall 435 in reducing the parasitic capacitance between the bottom interconnect layer 441 and the gate structure 310.

[0240] For a detailed description of the formation of the third dielectric layer 450 and the source / drain plug 410, please refer to the corresponding descriptions in the foregoing embodiments. This embodiment will not repeat them here.

[0241] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Base; The gate structure is discretely disposed on the substrate; The source and drain doped regions are located within the substrate on both sides of the gate structure; A first dielectric layer is located on the side of the gate structure and covers the source and drain doped regions; The second dielectric layer is located on top of the first dielectric layer and the gate structure; The source-drain interconnect layer extends through the first and second dielectric layers on top of the source-drain doped region and is in contact with the source-drain doped region. The width of the source-drain interconnect layer in the second dielectric layer is greater than the width of the source-drain interconnect layer in the first dielectric layer in a direction perpendicular to the gate structure. A sidewall structure layer is located between the sidewall of the gate structure and the sidewall of the source-drain interconnect layer. The sidewall structure layer includes a first sidewall located on the sidewall of the gate structure, a second sidewall located on the sidewall of the source-drain interconnect layer, and an air sidewall located between the first sidewall and the second sidewall. A third dielectric layer is located on top of the second dielectric layer and the source-drain interconnect layer and seals the top of the air sidewall; The source / drain plug is located in the third dielectric layer on top of the source / drain interconnect layer and is in contact with the source / drain interconnect layer.

2. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes a gate plug that penetrates the second and third dielectric layers on the top of the gate structure and is in contact with the gate structure.

3. The semiconductor structure as described in claim 1 or 2, characterized in that, The sidewall structure layer is also located between the source / drain interconnect layer and the second dielectric layer.

4. The semiconductor structure as described in claim 3, characterized in that, The air sidewall is higher than the top portion of the gate structure as a top air sidewall; the sidewall structure layer further includes a third sidewall located on the sidewall of the first and second sidewalls exposed by the top air sidewall.

5. The semiconductor structure as described in claim 4, characterized in that, Along the extension direction perpendicular to the gate structure, in the sidewall structure layer, the distance between the first sidewall and the second sidewall is a first width, the thickness of the third sidewall is a second width, and the second width is greater than or equal to 10% of the first width and less than 50% of the first width.

6. The semiconductor structure as described in claim 1, characterized in that, The source-drain interconnect layer includes a top interconnect layer located in the second dielectric layer and a bottom interconnect layer located in the first dielectric layer, and the sidewall of the top interconnect layer protrudes from the sidewall of the bottom interconnect layer along a direction perpendicular to the gate structure.

7. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes: a first barrier layer located between the sidewall of the gate structure and the first dielectric layer; The second barrier layer is located between the top of the gate structure and the second dielectric layer; The sidewall structure layer is located between the sidewall of the first barrier layer and the source / drain interconnect layer, between the sidewall of the second barrier layer and the source / drain interconnect layer, and between the second dielectric layer and the source / drain interconnect layer, and the sidewall structure layer is in contact with the sidewall of the first barrier layer.

8. The semiconductor structure as described in claim 7, characterized in that, The top of the gate structure is flush with the top of the first dielectric layer; the second barrier layer is also located between the second dielectric layer and the first dielectric layer on the source / drain plug side; Alternatively, the top of the gate structure is lower than the top of the first dielectric layer, and the top of the gate structure forms a trench with the first barrier layer; The second barrier layer fills the trench.

9. The semiconductor structure as described in claim 7, characterized in that, The first barrier layer is also located between the source / drain doped region and the first dielectric layer, and between the source / drain doped region and the sidewall structure layer; The source-drain interconnect layer also extends through the first barrier layer located on top of the source-drain doped region.

10. The semiconductor structure as claimed in claim 7, characterized in that, The material of the first barrier layer includes one or more of the following: silicon oxycarbonate, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon carbonitride, silicon germanium oxide, boron nitride, and boron carbonitride; The material of the second barrier layer includes one or more of silicon oxycarbonate, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon carbonitride, silicon germanium oxide, boron nitride, and boron carbonitride.

11. The semiconductor structure as claimed in claim 1, characterized in that, The third dielectric layer includes: an etch stop layer located on the second dielectric layer and covering the source / drain interconnect layer and the sidewall structure layer, the etch stop layer sealing the top of the air sidewall; and a dielectric material layer located on the etch stop layer.

12. The semiconductor structure according to any one of claims 1, 2, 6 to 11, characterized in that, The source-drain interconnect layer includes a top interconnect layer located in the second dielectric layer and a bottom interconnect layer located in the first dielectric layer. Along the extension direction perpendicular to the gate structure, the width of the top interconnect layer is 2 nanometers to 6 nanometers larger than the width of the bottom interconnect layer.

13. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided on which discrete gate structures are formed, and source / drain doped regions are formed in the substrate on both sides of the gate structures. A first dielectric layer covering the source / drain doped regions is formed on the side of the gate structures. A second dielectric layer is formed on top of the first dielectric layer and the gate structure; An interconnection opening is formed through the top of the first dielectric layer and the second dielectric layer, and the opening width of the interconnection opening in the second dielectric layer is greater than the opening width of the interconnection opening in the first dielectric layer in a direction perpendicular to the gate structure. A first sidewall, a sacrificial sidewall, and a second sidewall are formed in sequence on the sidewall of the interconnection opening; A source-drain interconnect layer is filled in the interconnect opening, the source-drain interconnect layer is in contact with the source-drain doped region and covers the sidewall of the second sidewall; Remove the sacrificial sidewall to form an air sidewall between the first sidewall and the second sidewall; A third dielectric layer is formed on the second dielectric layer and the source-drain interconnect layer to seal the top of the air sidewall; A source / drain plug is formed in the third dielectric layer on top of the source / drain interconnect layer, which is in contact with the source / drain interconnect layer.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, The method for forming the semiconductor structure further includes: after forming the third dielectric layer, forming a gate plug that penetrates the second dielectric layer and the third dielectric layer on the top of the gate structure, wherein the gate plug is in contact with the gate structure.

15. The method for forming a semiconductor structure as described in claim 13, characterized in that, In the step of forming the interconnect opening, the interconnect opening includes a top opening in the second dielectric layer and a bottom opening in the first dielectric layer below the top opening. Along a direction perpendicular to the extension of the gate structure, the sidewall of the top opening is located on the side of the same sidewall of the bottom opening away from the source / drain doped region.

16. The method for forming a semiconductor structure as described in claim 13, 14, or 15, characterized in that, In the step of providing the substrate, a first barrier layer and a second barrier layer are respectively formed on the sidewalls and top of the gate structure; The second dielectric layer is formed on the first dielectric layer and the second barrier layer; In the step of forming the interconnect opening, the interconnect opening exposes the sidewall of the first barrier layer located on the sidewall of the gate structure.

17. The method for forming a semiconductor structure as described in claim 16, characterized in that, The step of providing a substrate includes: providing a substrate, a gate structure discretely disposed on the substrate, source / drain doped regions located within the substrate on both sides of the gate structure, a first barrier layer located on the sidewall of the gate structure, and a first dielectric layer located on the sides of the gate structure and the first barrier layer and covering the source / drain doped regions; forming a second barrier layer on top of the gate structure, the second barrier layer also being formed on the first dielectric layer; or... The step of providing the substrate includes: providing a substrate, a gate structure discrete on the substrate, source and drain doped regions located in the substrate on both sides of the gate structure, a first barrier layer located on the sidewall of the gate structure, and a first dielectric layer located on the side of the gate structure and the first barrier layer and covering the source and drain doped regions; removing a portion of the thickness of the gate structure so that the top of the remaining gate structure and the first barrier layer form a trench; and forming a second barrier layer in the trench.

18. The method for forming a semiconductor structure as described in claim 16, characterized in that, In the step of providing the substrate, the first barrier layer is also formed between the source / drain doped regions and the first dielectric layer; In the step of forming the interconnect opening, the bottom of the interconnect opening exposes the first barrier layer located on the source / drain doped region; In the step of forming the first sidewall, the sacrificial sidewall, and the second sidewall, the first sidewall, the sacrificial sidewall, and the second sidewall are formed on the first barrier layer; The method for forming the semiconductor structure further includes: after forming the first sidewall, the sacrificial sidewall, and the second sidewall, and before forming the source-drain interconnect layer, removing the first barrier layer exposed by the first sidewall, the sacrificial sidewall, and the second sidewall, thereby exposing the source-drain doped region.

19. The method for forming a semiconductor structure as described in claim 16, characterized in that, The step of forming the interconnect opening includes: forming a patterned layer on the second dielectric layer, wherein a patterned opening is formed in the patterned layer above the source / drain doped region, and the boundary of the patterned opening is located on the side of the first barrier layer sidewall away from the source / drain doped region on the same side. Using the patterned layer as a mask, the second dielectric layer below the patterned opening is etched to form a top opening; Using the first barrier layer as a stop layer along the extension direction perpendicular to the gate structure, the first dielectric layer below the top opening is etched to form a bottom opening, which is connected to the top opening to form the interconnect opening; Remove the graphics layer.

20. The method for forming a semiconductor structure as described in claim 13, characterized in that, After forming the source-drain interconnect layer and before removing the sacrificial sidewall, the method of forming the semiconductor structure further includes: removing a portion of the height of the sacrificial sidewall, such that the top of the remaining sacrificial sidewall forms a gap with the first sidewall and the second sidewall, the bottom of the gap being higher than the top surface of the gate structure; A third sidewall is formed on the sidewall of the gap, and the third sidewall exposes part of the top surface of the remaining sacrificial sidewall.

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