Semiconductor structure and method of forming the same
By thinning the sidewalls of the isolation region and removing the gate electrode of the isolation region, the distance between adjacent gate structures is increased, solving the problem of excessive contact resistance in semiconductor devices and achieving lower contact resistance and higher electrical performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SEMICON MFG INT (SHANGHAI) CORP
- Filing Date
- 2022-05-18
- Publication Date
- 2026-06-19
AI Technical Summary
In the prior art, the contact resistance of semiconductor devices is too high, especially in the contact trenches of PMOS and NMOS regions, which leads to a decrease in electrical performance.
By thinning the sidewalls of the isolation region, increasing the distance between adjacent gate structures, and removing the gate electrode of the isolation region to form an isolation opening, an isolation structure is formed, reducing contact resistance.
It effectively reduces contact resistance, simplifies process steps, avoids photolithography alignment problems, and improves device performance.
Smart Images
Figure CN117133718B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Technology
[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are evolving towards higher component density and higher integration. Transistors, as the most basic semiconductor devices, are currently widely used. Therefore, as the component density and integration of semiconductor devices increase, the gate size of planar transistors is becoming shorter and shorter. Traditional planar transistors have a weaker ability to control channel current, resulting in short-channel effects, leakage current, and ultimately affecting the electrical performance of semiconductor devices.
[0003] As the distance between semiconductor contact nodes decreases, the critical dimension (CD) of the source and drain contact points in the semiconductor structure also continues to decrease, posing a significant challenge to the control of contact resistance.
[0004] Implanting contact trenches to reduce contact resistance is a well-known method for lowering device contact resistance and improving performance. In this method, the PMOS and NMOS regions require two masks for protection, while the unmasked regions are implanted.
[0005] However, in the existing methods, the injected contact trenches still have the problem of excessive resistance. Summary of the Invention
[0006] The problem addressed by this invention is to provide a semiconductor structure and a method for forming the same, in order to reduce contact resistance.
[0007] To address the above problems, the present invention provides a method for forming a semiconductor structure, comprising:
[0008] A substrate is formed, the substrate being divided into a first region, a second region, and an isolation region located between and adjacent to both regions. The substrate includes a gate structure extending from the first region through the isolation region to the second region. The gate structure includes a gate electrode and a sidewall located on the sidewall of the gate electrode. The sidewall of the isolation region is thinned to increase the distance between adjacent gate structures within the isolation region. The gate electrode of the isolation region is removed to form an isolation opening. An isolation structure is formed within the isolation opening.
[0009] Optionally, the method further includes: after forming the substrate and before thinning the sidewalls of the isolation region, forming an etching mask on the substrate, the etching mask having an etching opening, the bottom of the etching opening exposing the substrate of the isolation region; in the step of thinning the sidewalls of the isolation region, thinning the sidewalls of the isolation region through the etching opening; and in the step of removing the gate electrode of the isolation region to form the isolation opening, removing the gate electrode of the isolation region through the etching opening to form the isolation opening.
[0010] Optionally, in the step of forming the substrate, the substrate further includes: an interlayer dielectric layer, the interlayer dielectric layer filling between adjacent gate structures; the step of thinning the sidewalls of the isolation region includes: removing the interlayer dielectric layer between adjacent gate structures of the isolation region to expose the sidewalls; and removing a portion of the thickness of the sidewalls along the direction pointing to the gate structure.
[0011] Optionally, in the step of removing a portion of the thickness of the sidewall, less than 50% of the sidewall thickness is removed.
[0012] Optionally, the step of removing the gate electrode of the isolation region to form the isolation opening includes: after removing a portion of the thickness of the sidewall, filling the space between adjacent gate structures with dielectric material to form a recovery dielectric layer; and after forming the recovery dielectric layer, etching away the gate electrode of the isolation region to form the isolation opening.
[0013] Optionally, the step of filling the space between adjacent gate structures with dielectric material to form a recovery dielectric layer includes: filling the space between adjacent gate structures with dielectric material, the dielectric material further covering the sidewalls of the etched opening; and at least removing the dielectric material from the sidewalls of the etched opening.
[0014] Optionally, it further includes: after forming an isolation structure within the isolation opening, forming a contact trench, the contact trench being located within the substrate on both sides of the gate structure, the contact trench extending from the first region through the isolation region to the second region.
[0015] Optionally, in the step of forming the contact trench, the interlayer dielectric layer between adjacent gate structures in the first region and the second region and the recovery dielectric layer between adjacent gate structures in the isolation region are removed.
[0016] Optionally, the width of the contact groove in the isolation zone is not less than the width of the contact groove in the first zone or the second zone.
[0017] Optionally, in the step of forming the isolation structure within the isolation opening, the material of the isolation structure is the same as the material of the sidewall.
[0018] Optionally, in the step of forming an isolation structure within the isolation opening, the material of the isolation structure and the material of the sidewall are both silicon nitride.
[0019] Optionally, after forming the contact trench, the method further includes: performing a first ion implantation on the substrate of the first region; and performing a second ion implantation on the substrate of the second region.
[0020] Optionally, before performing the first ion implantation step on the substrate of the first region, a first implantation mask is formed on the substrate of the isolation region and the substrate of the second region; before performing the second ion implantation step on the substrate of the second region, a second implantation mask is formed on the substrate of the isolation region and the substrate of the first region.
[0021] Optionally, the bottom of the contact trench has an interface layer; after the steps of performing a first ion implantation on the substrate of the first region and a second ion implantation on the substrate of the second region, the interface layer is removed.
[0022] Accordingly, the present invention provides a semiconductor structure comprising:
[0023] The substrate is divided into a first region, a second region, and an isolation region located between and adjacent to both regions. Both the substrate of the first region and the substrate of the second region include: a gate structure comprising a gate electrode and a sidewall located on the sidewall of the gate electrode; an interlayer dielectric layer filling the space between adjacent gate structures; and an isolation structure located within the isolation region between the gate structures of the first region and the second region. The sidewall of the isolation structure has a sidewall, the thickness of which is less than the thickness of the sidewall on the gate electrode sidewall of the first region or the second region.
[0024] Optionally, it also includes: a contact trench located in the substrate on both sides of the gate structure, the contact trench extending from the first region through the isolation region to the second region.
[0025] Optionally, the sidewalls of the contact groove are exposed above the sidewall.
[0026] Optionally, the width of the contact groove in the isolation zone is not less than the width of the contact groove in the first zone or the second zone.
[0027] Optionally, the substrate in the first region is implanted with a first ion; the substrate in the second region is implanted with a second ion.
[0028] Compared with the prior art, the technical solution of the present invention has the following advantages:
[0029] In this invention, the sidewalls of the isolation region are thinned to increase the distance between adjacent gate structures within the isolation region; and the gate electrode of the isolation region is removed to form an isolation opening. By thinning the sidewalls of the isolation region, the distance between adjacent gate structures within the isolation region is increased, thereby ensuring the width of the subsequent isolation trench within the isolation region and reducing contact resistance.
[0030] In an optional embodiment of the present invention, after the substrate is formed but before thinning the sidewalls of the isolation region, an etching mask is formed on the substrate. The etching mask has etching openings, the bottom of which exposes the substrate of the isolation region. The thinning process and removal of the gate electrode are then performed through these etching openings. This thinning process can be performed using etching openings that cut off the gate structure by removing the gate electrode, without increasing the number of process steps, eliminating the need to consider photolithography alignment issues, and reducing the process complexity. Attached Figure Description
[0031] Figures 1 to 3 This is a cross-sectional structural diagram illustrating the various steps in a semiconductor structure formation method.
[0032] Figures 4 to 20 This is a cross-sectional structural schematic diagram of each step in an embodiment of the semiconductor structure formation method of the present invention;
[0033] Figure 21 This is a cross-sectional structural schematic diagram of each step in another embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation
[0034] As the background technology shows, the contact trenches created by injection in the existing technology still suffer from excessive resistance. This paper analyzes the reasons for this excessive resistance problem using a semiconductor structure formation method as an example:
[0035] refer to Figures 1 to 3 The diagram shows a cross-sectional view of each step in a method for forming a semiconductor structure.
[0036] refer to Figure 1 A substrate is provided, the substrate comprising: a first region 10p and a second region 10n, the substrate of the first region 10p being used to form an N-type device, and the substrate of the second region 10n being used to form a P-type device; each region of the substrate comprises: a substrate 11; and source / drain doped regions 12 located on the substrate 11.
[0037] Continue to refer to Figure 1 A contact trench 21 is formed in the substrate, the contact trench 21 extending from the first region 10p to the second region 10n; the bottom of the contact trench 21 exposes the interface layer 16 on the surface of the source / drain doped region 12.
[0038] like Figure 1 As shown, the process of performing a first ion implantation on the source / drain doped region 12 of the first region 10p to reduce the contact resistance includes: forming a first mask 31 in the contact trench 21 in the second region 10n; and performing a first ion implantation on the source / drain doped region 12 of the first region 10p using the first mask 31 as a mask.
[0039] refer to Figure 2 The process of performing a second ion implantation on the source / drain doped region 12 of the second region 10n to reduce contact resistance includes: forming a second mask 41 in the contact trench 21 in the first region 10p; and performing a second ion implantation on the source / drain doped region 12 of the second region 10n using the second mask 41 as a mask.
[0040] To prevent ion implantation from affecting other regions, during the first and second ion implantation processes, both the first mask 31 and the second mask 41 cover the boundary between the first region 10p and the second region 10n (e.g., ...). Figure 3 (The area shown in the dashed box 51); therefore, after the first ion implantation and the second ion implantation, the ion implantation situation at the junction is different from that of the substrates of the first region 10p and the second region 10n.
[0041] On the other hand, such as Figure 3 As shown, where, Figure 3 yes Figure 1 A top view of the structure is shown; the substrate also includes: a gate structure 13, the gate structure 13 including: a gate electrode 14; a sidewall 15, the sidewall 15 being located on the sidewall of the gate electrode 14. The gate structure 13 extends from the first region 10p to the second region 10n; the contact trench 21 is located between adjacent gate structures 13.
[0042] Because the ion implantation conditions at the junction of the first region 10p and the second region 10n are different from those of the substrates of the first region 10p and the second region 10n, the etching efficiency of the sidewalls 15 in different regions is different when the interface layer 16 at the bottom of the contact trench 21 is subsequently stripped. This results in a smaller size of the contact trench 21 between the first region 10p and the second region 10n after the interface layer 16 is removed. Consequently, the contact resistance of the interconnect structure within the contact trench 21 increases, affecting the device performance.
[0043] To solve the aforementioned technical problem, the present invention provides a method for forming a semiconductor structure, comprising:
[0044] A substrate is formed, the substrate including a first region, a second region, and an isolation region. Along a plane parallel to the surface of the substrate, the isolation region is located between the first and second regions, adjacent to both the first and second regions. The substrate includes a gate structure extending from the first region through the isolation region to the second region, the gate structure including a gate electrode and a sidewall located on the sidewall of the gate electrode. The sidewall of the isolation region is thinned to increase the distance between adjacent gate structures within the isolation region. The gate electrode of the isolation region is removed to form an isolation opening. An isolation structure is formed within the isolation opening.
[0045] The present invention thins the sidewalls of the isolation region to increase the distance between adjacent gate structures within the isolation region; and removes the gate electrode of the isolation region to form an isolation opening. By thinning the sidewalls of the isolation region, the distance between adjacent gate structures within the isolation region is increased, thereby ensuring the width of the subsequent isolation trench within the isolation region and reducing contact resistance.
[0046] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0047] refer to Figures 4 to 20 The diagram shows a schematic representation of the various steps in an embodiment of the semiconductor structure formation method of the present invention.
[0048] refer to Figure 4 and Figure 5 ,in Figure 5 yes Figure 4 The schematic diagram shown is a cross-sectional view along line A1A2 in the top view. A substrate is formed, which is divided into a first region 100p, a second region 100n, and an isolation region 100is located between and adjacent to the two regions. The substrate includes a gate structure 110, which extends from the first region 100p through the isolation region 100is to the second region 100n. The gate structure 110 includes a gate electrode 111 and a sidewall 112 located on the sidewall of the gate electrode 111.
[0049] The substrate is used to provide a process basis for subsequent process steps.
[0050] The substrate of the first region 100p and the substrate of the second region 100n are used to form different transistors. In some embodiments of the present invention, the substrate of the first region 100p is used to form a PMOS device, and the substrate of the second region 100n is used to form an NMOS device.
[0051] The substrate of the isolation region 100is is located between the substrate of the first region 100p and the substrate of the second region 100n, so as to achieve electrical isolation between the first region 100p and the second region 100n. The isolation region 100is is adjacent to both the first region 100p and the second region 100n, that is, the isolation region 100is is adjacent to and in contact with the first region 100p, and the isolation region 100is is adjacent to and in contact with the second region 100n.
[0052] The substrate of each region includes a gate structure 110 extending from the first region 100p through the isolation region 100is to the second region 100n. The gate structure 110 includes a gate electrode 111 and a sidewall 112 located on the sidewall of the gate electrode 111.
[0053] Since the gate structure 110 extends from the first region 100p through the isolation region 100is to the second region 100n, the gate electrode 111 of the gate structure 110 needs to be cut in the isolation region 100is to achieve electrical insulation between the gate structure 110 of the first region 100p and the gate structure 110 of the second region 100n.
[0054] In some embodiments of the present invention, the gate structure 110 is a metal gate structure, that is, the gate electrode 111 of the gate structure 110 is made of metal. In other embodiments of the present invention, the gate structure 110 may also be a polysilicon gate structure, that is, the gate electrode 111 of the gate structure 110 is made of polysilicon.
[0055] In some embodiments of the present invention, the sidewall 112 is made of silicon nitride. In other embodiments of the present invention, the sidewall 112 may also be made of other dielectric materials such as silicon oxide or silicon oxynitride.
[0056] In some embodiments of the present invention, the substrate further includes an interlayer dielectric layer 103 in the step of forming the substrate, the interlayer dielectric layer 103 being filled between adjacent gate structures 110. The interlayer dielectric layer 103 is suitable for ensuring electrical insulation between adjacent gate structures 110. Specifically, the material of the interlayer dielectric layer 103 is silicon oxide. In other embodiments of the present invention, the interlayer dielectric layer 103 may also be a low-k dielectric material or an ultra-low-k dielectric material.
[0057] In some embodiments of the present invention, during the step of forming the substrate, the substrate further includes a substrate 101; the gate structure 110 is located on the substrate 101, and the substrate 101 between adjacent gate structures 110 of the first region 100p and the second region 100n has source and drain regions (not shown in the figure); the interlayer dielectric layer 103 fills the substrate 101 between adjacent gate structures 110. An interface layer is also provided between the substrate 101 between adjacent gate structures 110 and the interlayer dielectric layer 103 to protect the source and drain regions during the semiconductor process.
[0058] refer to Figures 6 to 8 The sidewalls 112 of the isolation region 100is are thinned to increase the distance between adjacent gate structures 110 within the isolation region 100is. Figure 6 and Figure 7 The cross-sectional structural diagram shown is consistent with Figure 5 Corresponding to the schematic diagram of the cross-sectional structure shown, Figure 8 yes Figure 7 The cross-sectional structural schematic diagram shown is a top view of the structure along direction B; and Figure 8 The top view structural diagram shown is consistent with Figure 4 The top view of the structure shown corresponds to the schematic diagram.
[0059] It should be noted that, in some embodiments of the present invention, after the substrate is formed and before the sidewall 112 of the isolation region 100is is thinned, an etching mask 113 is formed on the substrate. The etching mask 113 has an etching opening 114, and the bottom of the etching opening 114 exposes the substrate of the isolation region 100is.
[0060] It should also be noted that the top view structural diagram (i.e.) Figure 4 The material film layers above the etching mask 113 are omitted for clear display.
[0061] The etching mask 113 is used to protect the substrate of the first region 100p and the substrate of the second region 100n during the process of thinning the sidewalls 112 and cutting off the gate electrode 111; the etching opening 114 is a window for thinning the sidewalls 112 and cutting off the gate electrode 111.
[0062] Specifically, the step of forming the etching mask 113 on the substrate includes: forming a hard mask layer on the substrate; forming a patterning layer (such as...) on the hard mask layer. Figure 5 (as shown); the pattern layer is patterned to form a pattern opening within the pattern layer, the position of which corresponds to the position of the isolation region 100is; using the pattern layer as a mask, the hard mask layer is etched to form an etching opening 114 within the hard mask layer, the bottom of which exposes the substrate of the isolation region 100is.
[0063] The hard mask layer can be made of dielectric materials such as silicon nitride or silicon oxynitride, and the pattern layer can be made of photoresist. Therefore, the pattern layer can be patterned by exposure and development to form a pattern opening. The hard mask layer at the bottom of the pattern opening is removed by at least one of dry etching and wet etching to expose the substrate of the isolation area 100is, forming an etch opening 114.
[0064] After forming the etching mask 113, the sidewalls 112 of the isolation region 100is are thinned to increase the distance between adjacent gate structures 110 in the isolation region 100is, that is, to increase the distance between the opposite surfaces of adjacent gate structures 110 in the isolation region 100is.
[0065] In some embodiments of the present invention, an etching mask 113 with etching openings 114 is also formed on the substrate; therefore, in the thinning process of the sidewall 112 of the isolation region 100is, the sidewall 112 of the isolation region 100is is thinned through the etching openings 114.
[0066] Furthermore, in some embodiments of the present invention, an interlayer dielectric layer 103 is filled between adjacent gate structures 110; therefore, the step of thinning the sidewall 112 of the isolation region 100is includes: Figure 6 As shown, the interlayer dielectric layer 103 between adjacent gate structures 110 of the isolation region 100is is removed, exposing the sidewall 112; as Figure 7 and Figure 8 As shown, a portion of the thickness of the sidewall 112 is removed along the direction pointing to the gate structure 110.
[0067] Specifically, the inter-side dielectric layer between adjacent gate structures 110 of the isolation region 100is is removed to expose the surface of the sidewall 112, that is, to expose the opposing surfaces of the adjacent gate structures 110; a portion of the thickness of the sidewall 112 is etched away, thereby increasing the distance between adjacent gate structures 110.
[0068] In some embodiments of the present invention, a portion of the thickness of the sidewall 112 can be removed by dry or wet etching to increase the distance between adjacent gate structures 110. Specifically, the dry etching process parameters are as follows: reaction gas: CF4 or other gas combinations with a low C / F ratio; reaction temperature: 50–100 degrees Celsius; dissociation energy: 500W–1000W; bias voltage: 0V; reaction pressure: 5mTorr–10mTorr; and the sidewall etching rate using these parameters is 0.2nm / s–0.5nm / s.
[0069] like Figure 8As shown, in some embodiments of the present invention, in the step of removing a portion of the thickness of the sidewall 112, the removal is within 50% of the thickness of the sidewall 112. That is, after the thinning process, the difference between the remaining thickness of the sidewall 112 in the isolation region 100is and the thickness of the sidewall 112 in the first region 100p and the sidewall 112 in the second region 100n is within 4nm. The thickness of the sidewall 112 in the first region 100p and the sidewall 112 in the second region 100n is approximately 9nm. If the thickness of the sidewall 112 removed is too small, the distance between adjacent gate structures 110 will be insufficient, making it difficult to guarantee the width of the subsequently formed isolation trench, which is not conducive to reducing contact resistance. If the thickness of the sidewall 112 removed is too large, it will increase the possibility of damage to the gate electrode 111, increasing process risk.
[0070] refer to Figures 9 to 13 The gate electrode 111 of the isolation region 100is is removed to form an isolation opening 130. Wherein, Figure 9 , Figure 11 and Figure 13 The cross-sectional structural diagram shown is consistent with Figure 7 This corresponds to the schematic diagram of the cross-sectional structure shown; Figure 10 and Figure 12 yes Figure 8 The cross-sectional view of the structure along line D1D2 in the top view shown.
[0071] The function of removing the gate electrode 111 of the isolation region 100is to form the isolation opening 130 is to cut off the gate electrode 111 to achieve electrical insulation between the gate structure 110 of the first region 100p and the gate structure 110 of the second region 100n.
[0072] In some embodiments of the present invention, an etching mask 113 with etching openings 114 is further formed on the substrate; therefore, in the step of removing the gate electrode 111 of the isolation region 100is to form the isolation opening 130, the gate electrode 111 of the isolation region 100is is removed through the etching openings 114 to form the isolation opening 130. Thinning and cutting off the gate electrode 111 through the same etching opening 114 can increase the distance between adjacent gate structures 110 of the isolation region 100is without adding photolithography steps, avoiding photolithography alignment problems and simplifying the process.
[0073] In some embodiments of the present invention, before removing the gate electrode 111 of the isolation region 100is to form the isolation opening 130, the sidewall 112 is thinned, which can effectively reduce the difficulty of the thinning process and is conducive to ensuring and improving the yield.
[0074] Therefore, in some embodiments of the present invention, the step of removing the gate electrode 111 of the isolation region 100is to form the isolation opening 130 includes: after removing a portion of the thickness of the sidewall 112, as follows: Figures 9 to 12 As shown, dielectric material is filled between adjacent gate structures 110 to form a recovery dielectric layer 120; as Figure 13 As shown, after the recovery dielectric layer 120 is formed, the gate electrode 111 of the isolation region 100is is etched away to form the isolation opening 130.
[0075] Specifically, the step of filling the space between adjacent gate structures 110 with dielectric material to form a recovery dielectric layer 120 includes: as follows Figure 9 and Figure 10 As shown, dielectric material is filled between adjacent gate structures 110, and the dielectric material also covers the sidewalls of the etched opening 114; as Figure 11 and Figure 12 As shown, at least the dielectric material on the sidewall of the etched opening 114 is removed.
[0076] During the filling process of the dielectric material, the dielectric material will also cover the sidewall of the etched opening 114, thereby reducing the size of the etched opening 114 and affecting the removal of the gate electrode 111; therefore, the dielectric material on the sidewall of the etched opening 114 is removed to restore the size of the etched opening 114 and reduce the difficulty of removing the gate electrode 111.
[0077] In some embodiments of the present invention, the material of the recovery dielectric layer 120 is the same as the material of the interlayer dielectric layer 103. Specifically, the material of the recovery dielectric layer 120 is silicon oxide. In other embodiments of the present invention, the material of the recovery dielectric layer 120 may also be a low-k dielectric material or an ultra-low-k dielectric material.
[0078] Specifically, dielectric material can be filled between the thinned gate structures 110 by atomic layer deposition; dielectric material on the sidewalls of the etched openings 114 can be removed by at least one of dry etching and wet etching.
[0079] refer to Figures 14 to 16 An isolation structure 140 is formed within the isolation opening 130. Figure 14 and Figure 15 The cross-sectional structural diagram shown is consistent with Figure 13 This corresponds to the schematic diagram of the cross-sectional structure shown; Figure 16 The top view of the structure shown is Figure 15 The schematic diagram of the cross-sectional structure shown is a top view along direction C.
[0080] The isolation structure 140 is used to achieve electrical insulation between the gate structure 110 of the first region 100p and the gate structure 110 of the second region 100n.
[0081] In some embodiments of the present invention, in the step of forming the isolation structure 140 within the isolation opening 130, the material of the isolation structure 140 is the same as the material of the sidewall 112. Specifically, in the step of forming the isolation structure 140 within the isolation opening 130, the material of the isolation structure 140 and the material of the sidewall 112 are both silicon nitride.
[0082] Using the same material as the sidewall 112, such as silicon nitride, as the isolation structure 140 can effectively ensure the insulation performance and mechanical strength of the isolation structure 140, which is beneficial to ensuring the stability of the device.
[0083] Specifically, the step of forming the isolation structure 140 within the isolation opening 130 includes: as follows Figure 14 As shown, an isolation material is filled into the isolation opening 130, and the isolation material completely fills the isolation opening 130 and the etched opening 114; as Figure 15 and Figure 16 As shown, the isolation material inside the etching mask 113 and the etching opening 114 is removed.
[0084] The isolation material can be filled by atomic layer deposition; then, the isolation material in the etching mask 113 and the etching opening 114 can be removed by chemical mechanical polishing (CMP) or etching.
[0085] refer to Figure 17 The forming method further includes: after forming an isolation structure 140 within the isolation opening 130, forming a contact trench 150, the contact trench 150 being located within the substrate on both sides of the gate structure 110, the contact trench 150 extending from the first region 100p through the isolation region 100is to the second region 100n. Figure 17 The top view structural diagram shown is consistent with Figure 16 The top view of the structure shown corresponds to the schematic diagram.
[0086] The contact trench 150 is used to form an interconnect structure to realize the electrical connection between the source / drain region in the substrate and the external circuit.
[0087] like Figure 17In some embodiments of the present invention, in the step of forming the contact trench 150, the interlayer dielectric layer 103 between adjacent gate structures 110 in the first region 100p and the second region 100n and the recovery dielectric layer 120 between adjacent gate structures 110 in the isolation region 100is are removed to form the contact trench 150 between adjacent gate structures 110.
[0088] Because the semiconductor structure has a high device density, small device size, small spacing between source and drain regions, and small distance between gate structures 110 in the source and drain regions, the interconnect structure formed by the contact trench 150 can effectively reduce contact resistance and reduce process difficulty. Moreover, by directly removing the interlayer dielectric layer 103 and the recovery dielectric layer 120, that is, the contact trench 150 is surrounded by the gate structure 110 and the sidewall of the contact trench 150 is the sidewall 112 of the gate structure 110, the process difficulty of forming the small-sized contact trench 150 can be effectively reduced.
[0089] Furthermore, since the sidewalls 112 in the isolation region 100is are thinned, the spacing between adjacent gate structures 110 in the isolation region 100is is greater than the distance between adjacent gate structures 110 in the first region 100p and the second region 100n. Therefore, in some embodiments of the present invention, the width of the contact trench 150 in the isolation region 100is is not less than the width of the contact trench 150 in the first region 100p or the second region 100n, that is, the width of the contact trench 150 in the isolation region 100is is greater than or equal to the width of the contact trench 150 in the first region 100p or the second region 100n.
[0090] To further reduce contact resistance, in some embodiments of the present invention, after forming the contact trench 150, the forming method further includes: as follows: Figure 18 As shown, the first ion implantation was performed on the substrate in the first region of 100p; as Figure 19 As shown, a second ion implantation was performed on the substrate in the second region of 100n. Wherein, Figure 18 and Figure 19 The top view structural diagram shown is consistent with Figure 16 The top view of the structure shown corresponds to the schematic diagram.
[0091] The ion implantation is suitable for further reducing the contact resistance of the source / drain region within the substrate.
[0092] Since the first region 100p and the second region 100n are used to form different semiconductor devices, such as PMOS devices and NMOS devices respectively, in some embodiments of the present invention, a first implantation mask is formed on the substrate of the isolation region 100is and the second region 100n before the first ion implantation step on the substrate of the first region 100p; in some embodiments of the present invention, a second implantation mask is formed on the substrate of the isolation region 100is and the first region 100p before the second ion implantation step on the substrate of the second region 100n.
[0093] The first implantation mask is used to protect the substrate of the second region 100n during the first ion implantation process; the second implantation mask is used to protect the substrate of the first region 100p during the second ion implantation process. Furthermore, to ensure complete coverage of the protected areas by the implantation mask, the first implantation mask covers not only the substrate of the second region 100n but also the substrate of the isolation region 100is; the second implantation mask covers not only the substrate of the first region 100p but also the substrate of the isolation region 100is.
[0094] Both the first implantation mask and the second implantation mask can be made of photoresist; at least one of the steps of forming the first implantation mask and the second implantation mask includes: spin-coating a photoresist layer on the substrate; and exposing and developing the photoresist.
[0095] Specifically, the process parameters for the first ion implantation include: implanted ions Al, Ga, In, or Ge; implantation energy <= 60 keV; and implantation dose 10. 14 ~10 16 / cm 2 The process parameters for the second ion implantation include: implanted ions N, P, or As; implantation energy <= 60 keV; and implantation dose 10. 14 ~10 16 / cm 2 .
[0096] In addition, such as Figure 20 As shown, in some embodiments of the present invention, the bottom of the contact trench 150 has an interface layer; after the steps of performing a first ion implantation on the substrate of the first region 100p and a second ion implantation on the substrate of the second region 100n, the interface layer is removed. Figure 20 The top view structural diagram shown is consistent with Figure 19 The top view of the structure shown corresponds to the schematic diagram.
[0097] The interface layer is removed to expose the source and drain regions within the substrate on both sides of the gate structure 110, thereby providing a basis for the formation of subsequent interconnect structures and the electrical connection between the interconnect structures and the source and drain regions.
[0098] In some embodiments of the present invention, the interface layer is made of silicon oxide. In other embodiments of the present invention, the interface layer may also be made of other materials such as silicon nitride or silicon oxynitride. Specifically, the interface layer can be removed by peeling.
[0099] During the removal of the interface layer, the sidewalls of the contact trench 150, i.e., the sidewalls 112 of the gate structure 110, are also etched. Therefore, the width of the contact trench 150 increases before and after the interface layer is removed. Moreover, since the substrates of the first region 100p and the second region 100n have undergone the first ion implantation and the second ion implantation, respectively, the widths of the contact trench 150 of the first region 100p and the contact trench 150 of the second region 100n increase to the same extent before and after the interface layer is removed.
[0100] The sidewall 112 of the isolation region 100is is thinned. Although the width of the contact groove 150 of the isolation region 100is has not been ion implanted, the width of the contact groove 150 of the isolation region 100is is relatively large. Therefore, in some embodiments of the present invention, after removing the interface layer, the width of the contact groove 150 in the isolation region 100is is not less than the width of the contact groove 150 in the first region 100p or the second region 100n.
[0101] Specifically, such as Figure 20 As shown, in some embodiments of the present invention, after removing the interface layer, the width of the contact groove 150 in the isolation region 100is is still greater than the width of the contact groove 150 in the first region 100p or the second region 100n; or as... Figure 21 As shown, in some embodiments of the present invention, after removing the interface layer, the width of the contact groove 250 in the isolation region 200is is equal to the width of the contact groove 250 in the first region 200p or the second region 200n.
[0102] Accordingly, the present invention also provides a semiconductor structure.
[0103] refer to Figure 15 and Figure 16 ,in Figure 15 A cross-sectional schematic diagram of an embodiment of the semiconductor structure of the present invention is shown. Figure 16 A top view schematic diagram of an embodiment of the semiconductor structure of the present invention is shown.
[0104] The semiconductor structure includes: a substrate, the substrate being divided into a first region 100p, a second region 100n, and an isolation region 100is located between and adjacent to both regions; both the substrate of the first region 100p and the substrate of the second region 100n include: a gate structure 110, the gate structure 110 including a gate electrode 111 and a sidewall 112 located on the sidewall of the gate electrode 111; an interlayer dielectric layer 103, the interlayer dielectric layer 103 filling between adjacent gate structures 110; and an isolation structure 140, the isolation structure 140 being located within the isolation region 100is between the gate structure 110 of the first region 100p and the gate structure 110 of the second region 100n, the sidewall of the isolation structure 140 having a sidewall 112, the thickness of the sidewall 112 of the isolation structure 140 being less than the thickness of the sidewall 112 on the sidewall of the gate electrode 111 of the first region 100p or the second region 100n.
[0105] The substrate is used to provide a process basis for subsequent process steps.
[0106] The substrate of the first region 100p and the substrate of the second region 100n are used to form different transistors. In some embodiments of the present invention, the substrate of the first region 100p is used to form a PMOS device, and the substrate of the second region 100n is used to form an NMOS device.
[0107] The substrate of the isolation region 100is is used to achieve electrical isolation between the first region 100p and the second region 100n. The isolation region 100is is adjacent to both the first region 100p and the second region 100n, that is, the isolation region 100is is adjacent to and in contact with the first region 100p, and the isolation region 100is is adjacent to and in contact with the second region 100n.
[0108] The substrate of each region includes a gate structure 110, which is located in the first region 100p and the second region 100n, respectively. The gate structure 110 includes a gate electrode 111 and a sidewall 112 located on the sidewall of the gate electrode 111.
[0109] The gate electrode 111 of the gate structure 110 is cut off in the isolation region 100is to achieve electrical insulation between the gate structure 110 of the first region 100p and the gate structure 110 of the second region 100n; therefore, the gate structure 110 of the first region 100p and the gate structure 110 of the second region 100n are located on their respective extension lines.
[0110] In some embodiments of the present invention, the gate structure 110 is a metal gate structure, that is, the gate electrode 111 of the gate structure 110 is made of metal. In other embodiments of the present invention, the gate structure 110 may also be a polysilicon gate structure, that is, the gate electrode 111 of the gate structure 110 is made of polysilicon.
[0111] In some embodiments of the present invention, the sidewall 112 is made of silicon nitride. In other embodiments of the present invention, the sidewall 112 may also be made of other dielectric materials such as silicon oxide or silicon oxynitride.
[0112] The interlayer dielectric layer 103 is suitable for ensuring electrical insulation between adjacent gate structures 110. Specifically, the material of the interlayer dielectric layer 103 is silicon oxide. In other embodiments of the present invention, the interlayer dielectric layer 103 may also be a low-k dielectric material or an ultra-low-k dielectric material.
[0113] In some embodiments of the present invention, during the step of forming the substrate, the substrate further includes a substrate; the gate structure 110 is located on the substrate, and the substrate between adjacent gate structures 110 of the first region 100p and the second region 100n has source and drain regions (not shown in the figure); the interlayer dielectric layer 103 fills the substrate between adjacent gate structures 110.
[0114] The isolation structure 140 is used to achieve electrical insulation between the gate structure 110 of the first region 100p and the gate structure 110 of the second region 100n.
[0115] In some embodiments of the present invention, the material of the isolation structure 140 is the same as the material of the sidewall 112. Specifically, the material of the isolation structure 140 and the material of the sidewall 112 are both silicon nitride. Setting the isolation structure 140 to be made of the same material as the sidewall 112, such as silicon nitride, can effectively ensure the insulation performance of the isolation structure 140, effectively ensure the mechanical strength of the isolation structure 140, and help ensure the stability of the device.
[0116] In some embodiments of the present invention, one side of the isolation structure 140 is in contact with the gate structure 110 of the first region 100p, and the other side is in contact with the gate structure 110 of the second region 100n, that is, along the direction from the first region 100p to the second region 100n, the isolation structure 140 penetrates the isolation region 100is.
[0117] The isolation structure 140 has a sidewall 112 on its sidewall.
[0118] In some embodiments of the present invention, one end of the sidewall 112 on the sidewall of the isolation structure 140 is in contact with the sidewall 112 on the sidewall of the gate electrode 111 of the first region 100p, and the other end is in contact with the sidewall 112 on the sidewall of the gate electrode 111 of the second region 100n.
[0119] Specifically, one end of the sidewall 112 on the side wall of the isolation structure 140 is integral with the sidewall 112 on the side wall of the gate electrode 111 of the first region 100p; the other end is integral with the sidewall 112 on the side wall of the gate electrode 111 of the second region 100n.
[0120] The thickness of the sidewall 112 on the sidewall of the isolation structure 140 is less than that of the sidewall 112 on the sidewall of the gate structure 110 in the first region 100p or the second region 100n. Because the sidewall 112 on the sidewall of the isolation structure 140 is thinner, the distance between adjacent sidewalls 112 on the sidewall of the isolation structure 140 is larger within the isolation region 100is.
[0121] refer to Figure 20 The diagram shows a top view of another embodiment of the semiconductor structure of the present invention.
[0122] As with the foregoing embodiments, the present invention will not be repeated here. The difference from the foregoing embodiments is that, in some embodiments of the present invention, the semiconductor structure further includes: a contact trench 150, the contact trench 150 being located within the substrate on both sides of the gate structure 110, the contact trench 150 extending from the first region through the isolation region 100is to the second region.
[0123] The contact trench 150 is used to form an interconnect structure to realize the electrical connection between the source / drain region in the substrate and the external circuit.
[0124] In some embodiments of the present invention, the sidewalls of the contact trench 150 expose the sidewalls 112. Because the semiconductor structure has a high device density, small device size, small spacing between source and drain regions, and a small distance between the gate structures 110 in the source and drain regions, forming an interconnect structure through the contact trench 150 can effectively reduce contact resistance and lower the process difficulty. Furthermore, directly removing the interlayer dielectric layer 103 and the recovery dielectric layer 120, i.e., the contact trench 150 being surrounded by the gate structures 110, and the sidewalls of the contact trench 150 being the sidewalls 112 of the gate structures 110, can effectively reduce the process difficulty of forming the small-sized contact trench 150.
[0125] Furthermore, since the sidewalls 112 in the isolation region 100is are thinned, the spacing between adjacent gate structures 110 in the isolation region 100is is greater than the distance between adjacent gate structures 110 in the first region and the second region. Therefore, in some embodiments of the present invention, the width of the contact trench 150 in the isolation region 100is is not less than the width of the contact trench 150 in the first region or the second region, that is, the width of the contact trench 150 in the isolation region 100is is greater than or equal to the width of the contact trench 150 in the first region or the second region.
[0126] To further reduce contact resistance, in some embodiments of the present invention, the substrate in the first region is implanted with a first ion; and the substrate in the second region is implanted with a second ion. The delivered ion implantation is suitable for further reducing the contact resistance of the source / drain regions within the substrate.
[0127] Since the first region and the second region are used to form different semiconductor devices, such as PMOS devices and NMOS devices respectively, only the substrate of the first region is implanted with the first ion, only the substrate of the second region is implanted with the second ion, and the substrate of the isolation region 100is is not implanted with ions.
[0128] It should be noted that, in some embodiments of the present invention, the bottom of the contact trench 150 exposes the source and drain regions in preparation for subsequent contact with the interconnect structure.
[0129] In summary, in the technical solution of the present invention, the sidewall 112 of the isolation region 100is is thinned to increase the distance between adjacent gate structures 110 within the isolation region 100is; and the gate electrode 111 of the isolation region 100is is removed to form an isolation opening 130. By thinning the sidewall 112 of the isolation region 100is, the distance between adjacent gate structures 110 within the isolation region 100is is increased, thereby ensuring the width of the subsequent isolation trench within the isolation region 100is to reduce contact resistance. In an optional embodiment of the present invention, after forming the substrate and before thinning the sidewall 112 of the isolation region 100is, an etching mask 113 is formed on the substrate, the etching mask 113 having an etching opening 114, the bottom of the etching opening 114 exposing the substrate of the isolation region 100is; the thinning process and the removal of the gate electrode 111 are performed through the etching opening 114. The thinning process can be performed by removing the gate electrode 111 to cut off the etching opening 114 of the gate structure 110, without increasing the number of process steps, eliminating the need to consider photolithography alignment issues, and reducing process difficulty. Although the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A method of forming a semiconductor structure, characterized by, include: A substrate is formed, the substrate being divided into a first region, a second region, and an isolation region located between and adjacent to both regions, the substrate including a gate structure extending from the first region through the isolation region to the second region, the gate structure including a gate electrode and a sidewall located on the sidewall of the gate electrode; The sidewalls of the isolation region are thinned to increase the distance between adjacent gate structures within the isolation region; Remove the gate electrode of the isolation region to form an isolation opening; An isolation structure is formed within the isolation opening.
2. The formation method of claim 1, wherein, Also includes: After the substrate is formed, before the sidewalls of the isolation area are thinned, an etching mask is formed on the substrate. The etching mask has an etching opening, and the bottom of the etching opening exposes the substrate of the isolation area. In the process of thinning the sidewall of the isolation zone, the sidewall of the isolation zone is thinned through the etched opening; In the step of removing the gate electrode of the isolation region to form an isolation opening, the gate electrode of the isolation region is removed through the etching opening to form an isolation opening.
3. The formation method of claim 2, wherein, In the step of forming the substrate, the substrate further includes: an interlayer dielectric layer, which fills the space between adjacent gate structures; The step of thinning the sidewall of the isolation region includes: removing the interlayer dielectric layer between adjacent gate structures of the isolation region to expose the sidewall; and removing a portion of the thickness of the sidewall along the direction pointing towards the gate structure.
4. The formation method of claim 3, wherein, In the step of removing a portion of the thickness of the sidewall, less than 50% of the sidewall thickness is removed.
5. The formation method of claim 3, wherein, The step of removing the gate electrode of the isolation region to form the isolation opening includes: after removing a portion of the thickness of the sidewall, filling the space between adjacent gate structures with dielectric material to form a recovery dielectric layer; after forming the recovery dielectric layer, etching away the gate electrode of the isolation region to form the isolation opening.
6. The formation method of claim 5, wherein, The step of filling the space between adjacent gate structures with dielectric material to form a recovery dielectric layer includes: filling the space between adjacent gate structures with dielectric material, the dielectric material further covering the sidewalls of the etched opening; and at least removing the dielectric material from the sidewalls of the etched opening.
7. The formation process of claim 1 wherein, Also includes: After an isolation structure is formed within the isolation opening, a contact trench is formed. The contact trench is located within the substrate on both sides of the gate structure and extends from the first region through the isolation region to the second region.
8. The formation method of claim 7 wherein, In the step of forming the contact trench, the interlayer dielectric layer between adjacent gate structures in the first region and the second region and the recovery dielectric layer between adjacent gate structures in the isolation region are removed.
9. The formation method of claim 7 wherein, The width of the contact groove in the isolation zone is not less than the width of the contact groove in the first zone or the second zone.
10. The formation process of claim 1 wherein, In the step of forming the isolation structure within the isolation opening, the material of the isolation structure is the same as the material of the sidewall.
11. The forming method of claim 1 or 10, wherein In the step of forming an isolation structure within the isolation opening, the material of the isolation structure and the material of the sidewall are both silicon nitride.
12. The formation process of claim 7 wherein, After the contact trenches are formed, the process also includes: The first ion implantation was performed on the substrate of the first region; A second ion implantation was performed on the substrate in the second region.
13. The forming method as described in claim 12, characterized in that, Before performing the first ion implantation on the substrate of the first region, a first implantation mask is formed on the substrates of the isolation region and the second region; Before performing the second ion implantation on the substrate of the second region, a second implantation mask is formed on the substrate of the isolation region and the first region.
14. The forming method as described in claim 12, characterized in that, The bottom of the contact trench has an interface layer; After performing the first ion implantation step on the substrate in the first region and the second ion implantation step on the substrate in the second region, the interface layer is removed.
15. A semiconductor structure, characterized in that, include: The substrate is divided into a first region, a second region, and an isolation region located between and adjacent to both regions. The substrate in the first region and the substrate in the second region both include a gate structure, which includes a gate electrode and a sidewall located on the sidewall of the gate electrode. An interlayer dielectric layer, wherein the interlayer dielectric layer is filled between adjacent gate structures; An isolation structure is located in an isolation region between the gate structure of the first region and the gate structure of the second region. The sidewall of the isolation structure has a sidewall, the thickness of which is less than the thickness of the sidewall on the gate electrode sidewall of the first region or the second region.
16. The semiconductor structure as claimed in claim 15, characterized in that, Also includes: The contact trench is located in the substrate on both sides of the gate structure and extends from the first region through the isolation region to the second region.
17. The semiconductor structure as claimed in claim 16, characterized in that, The sidewall of the contact groove is exposed above the sidewall.
18. The semiconductor structure as claimed in claim 16, characterized in that, The width of the contact groove in the isolation zone is not less than the width of the contact groove in the first zone or the second zone.
19. The semiconductor structure as described in claim 15, characterized in that, The substrate in the first region is implanted with a first ion; the substrate in the second region is implanted with a second ion.