Display panel, manufacturing method thereof and display device
By setting an overlapping structure of the first and second planarization layers in the display panel and adjusting the dielectric constant, the problem of reduced transparent area was solved, resulting in better transparency and display effects.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- TIANMA ADVANCED DISPLAY TECH INST (XIAMEN) CO LTD
- Filing Date
- 2022-12-01
- Publication Date
- 2026-08-04
AI Technical Summary
In existing transparent display panels, the boundary of the film layer causes a reduction in the area of the transparent region.
By setting a first planarization layer and a second planarization layer in the display panel, making them overlap on the inner surface of the sub-display area, and making the dielectric constant of the first planarization layer greater than that of the second planarization layer, with the second planarization layer located on the light-emitting side, the parasitic capacitance is reduced and the area of the transparent area is increased.
The transparent area of the transparent display panel was increased, improving the transparency effect and reducing the parasitic capacitance between the metal layers, thus ensuring a good display effect.
Smart Images
Figure CN117133751B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of display technology, and more specifically, to a display panel, a method for manufacturing the same, and a display device. Background Technology
[0002] In the prior art, when a transparent display panel includes a transparent area, the transparent area can be formed by etching a portion of the non-transparent display panel. When etching a portion of the film layer in the display panel, such as... Figure 1 As shown, there is a boundary 01 / 02 between two adjacent film layers. The presence of boundary 01 / 02 will reduce the area of the transparent area. Therefore, there is an urgent need to provide a film layer setting method for display panels to avoid the problem of small transparent area in display panels. Summary of the Invention
[0003] In view of this, the present invention provides a display panel and a method for manufacturing the same, as well as a display device, to improve the problem of the small area of the transparent area in the display panel.
[0004] In a first aspect, this application provides a display panel, comprising:
[0005] Substrate;
[0006] A first planarization layer is located on one side of the substrate;
[0007] The second planarization layer is located on the side of the first planarization layer away from the substrate, and the first planarization layer and the second planarization layer are in contact;
[0008] The display panel includes a display area, which includes a light-transmitting area and a sub-display area. The sub-display area and the light-transmitting area are alternately arranged. The first planarization layer and the second planarization layer are both located in the sub-display area.
[0009] In at least one of the sub-display areas, the first planarization layer includes a first surface near the side of the second planarization layer, and the second planarization layer includes a second surface near the side of the first planarization layer, wherein the first surface and the second surface overlap in a direction perpendicular to the plane of the substrate.
[0010] The dielectric constant of the first planarization layer is greater than that of the second planarization layer.
[0011] Secondly, this application provides a display device, the display device including the display panel.
[0012] Thirdly, this application provides a method for manufacturing a display panel, the method being used in the aforementioned display panel;
[0013] The manufacturing method includes:
[0014] The first planarization layer and the second planarization layer, located in the light-transmitting area, are etched in the same process.
[0015] Compared with the prior art, the display panel, its manufacturing method, and display device provided by the present invention achieve at least the following beneficial effects:
[0016] This application provides a display panel and its manufacturing method and display device. In a sub-display area of the display panel that is connected to the transparent area, the surfaces of the first planarization layer and the second planarization layer overlap, so that there is no obvious boundary area between the surfaces of the first planarization layer and the second planarization layer, thereby maximizing the area of the transparent area in the display panel and improving the transparency effect of the transparent display panel. Furthermore, the first planarization layer and the second planarization layer can be provided simultaneously, with the first planarization layer having a dielectric constant greater than that of the second planarization layer. The second planarization layer is located on the side of the first planarization layer facing the light-emitting surface of the display panel, so that the second planarization layer presents a more porous and loose low dielectric effect, thereby reducing the parasitic capacitance between the metal layers disposed on the upper and lower sides of the second planarization layer, thereby ensuring a good display effect of the display panel.
[0017] Of course, any product implementing this invention does not necessarily need to achieve all of the technical effects described above at the same time.
[0018] Other features and advantages of the invention will become clear from the following detailed description of exemplary embodiments of the invention with reference to the accompanying drawings. Attached Figure Description
[0019] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments of the invention and, together with their description, serve to explain the principles of the invention.
[0020] Figure 1 The image shown is a cross-sectional schematic diagram of a transparent display panel in the prior art;
[0021] Figure 2 The image shown is a schematic diagram of a display panel provided in an embodiment of this application;
[0022] Figure 3 The image shown is provided in an embodiment of this application. Figure 2 A cross-sectional view of AA';
[0023] Figure 4 The image shown is provided in an embodiment of this application. Figure 2 Another cross-sectional schematic diagram of AA';
[0024] Figure 5 The image shown is provided in an embodiment of this application. Figure 2 Another cross-sectional schematic diagram of AA';
[0025] Figure 6 The image shown is provided in an embodiment of this application. Figure 2 Another cross-sectional schematic diagram of AA';
[0026] Figure 7 The image shown is provided in an embodiment of this application. Figure 2 Another cross-sectional schematic diagram of AA';
[0027] Figure 8 The image shown is provided in an embodiment of this application. Figure 2 Another cross-sectional schematic diagram of AA';
[0028] Figure 9 The image shown is provided in an embodiment of this application. Figure 2 Another cross-sectional schematic diagram of AA';
[0029] Figure 10 The diagram shown is a schematic representation of a display device provided in an embodiment of this application. Detailed Implementation
[0030] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values of the components and steps set forth in these embodiments do not limit the scope of the invention.
[0031] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the invention or its application or use.
[0032] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.
[0033] In all the examples shown and discussed herein, any specific values should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.
[0034] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.
[0035] In the prior art, please refer to Figure 1 When a transparent display panel includes a transparent area 03, the transparent area 03 can be formed by etching a portion of the display panel in the non-transparent area 03. During the etching of a portion of the film layer in the display panel, such as... Figure 1As shown, there is a boundary 01 / 02 between two adjacent film layers, and the presence of the boundary 01 / 02 will reduce the area of the transparent region 03. The film layers of the display panel may include, for example, a glass substrate (Glass), a buffer layer (Buffer), an insulating layer (GI), a dielectric insulating layer (IMD), an interlayer insulating layer (ILD), a passivation layer (PV), a first planarization layer (PLN1), and a second planarization layer (PLN2). It may also include a capacitor formed by a lower electrode (M1) and an upper electrode (MC). A micro-LED light-emitting element may be disposed on the side of the second planarization layer (PLN) away from the glass substrate. Therefore, there is an urgent need to provide a film layer arrangement method for display panels to avoid the problem of a small transparent area in the display panel.
[0036] In view of this, the present invention provides a display panel and a method for manufacturing the same, as well as a display device, to improve the problem of the small area of the transparent area in the display panel.
[0037] Figure 1 The image shown is a cross-sectional schematic diagram of a display panel in the prior art. Figure 2 The image shown is a schematic diagram of a display panel provided in an embodiment of this application. Figure 3 The image shown is provided in an embodiment of this application. Figure 2 Please refer to a schematic diagram of a cross-section of AA'. Figures 1-3 This application provides a display panel 100, including:
[0038] Substrate 30;
[0039] The first planarization layer 31 is located on one side of the substrate 30;
[0040] The second planarization layer 32 is located on the side of the first planarization layer 31 away from the substrate 30, and the first planarization layer 31 and the second planarization layer 32 are in contact.
[0041] The display panel 100 includes a display area 10, which includes a light-transmitting area 11 and a sub-display area 12. The sub-display area 12 and the light-transmitting area 11 are alternately arranged. The first planarization layer 31 and the second planarization layer 32 are both located in the sub-display area 12.
[0042] In at least one sub-display area 12, the first planarization layer 31 includes a first surface 311 near the side of the second planarization layer 32, and the second planarization layer 32 includes a second surface 322 near the side of the first planarization layer 31. The first surface 311 and the second surface 322 overlap in a direction perpendicular to the plane of the substrate 30.
[0043] The dielectric constant of the first planarization layer 31 is greater than that of the second planarization layer 32.
[0044] Specifically, this application provides a display panel 100, which includes a display area 10. The display area 10 may specifically include a light-transmitting area 11 and a sub-display area 12. The sub-display area 12 is used to house light-emitting elements to achieve the normal display effect of the display panel 100. The light-transmitting area 11 does not have a non-transparent film structure and is used to allow natural light to pass through, thereby realizing the function of a transparent display panel 100. It should be noted that this application does not impose specific limitations on the number, area, or shape of the sub-display areas 12 and light-transmitting areas 11 in the display panel 100. Users can make adaptive adjustments to the number, area, and shape according to actual needs.
[0045] The display panel 100 provided in this application includes a substrate 30, a first planarization layer 31, and a second planarization layer 32 stacked sequentially. Specifically, the first planarization layer 31 is disposed between the substrate 30 and the second planarization layer 32. This application does not specifically limit whether other film structures are included between the first planarization layer 31 and the substrate 30, or the type and number of such other film structures. Users can configure the film layers between the substrate 30 and the first planarization layer 31 according to actual needs. Since the display panel 100 includes a light-transmitting area 11, which does not have any non-transparent film layers or devices, the first planarization layer 31 and the second planarization layer 32 disposed on one side of the substrate 30 will only be located in the sub-display area 12, while the light-transmitting area 11 does not include the first planarization layer 31 and the second planarization layer 32. This application provides a configuration of the first planarization layer 31 and the second planarization layer 32 in the sub-display area 12, wherein, along a direction perpendicular to the plane of the substrate 30, the first surface 311 of the first planarization layer 31 near the second planarization layer 32 and the second surface 322 of the second planarization layer 32 near the first planarization layer 31 are overlapped. Specifically, the first surface 311 and the second surface 322 can be configured to completely overlap. With this configuration, on the side near the light-transmitting area 11, the side surfaces of the first planarization layer 31 and the second planarization layer 32 are smoothly connected, and there is no step structure between the first planarization layer 31 and the second planarization layer 32. This effectively reduces the number of steps in the direction parallel to the plane of the substrate 30. Figure 1 The area of the boundary 01 shown in the figure increases the area of the light-transmitting area 11 to a certain extent compared with the prior art, which is conducive to improving the overall light transmittance of the display panel 100 and making the light transmission effect of the transparent display panel 100 better.
[0046] Based on the fact that the first surface 311 of the first planarization layer 31 near the second planarization layer 32 and the second surface 322 of the second planarization layer 32 near the first planarization layer 31 completely overlap, it is further possible to choose to set the first planarization layer 31 and the second planarization layer 32 to have different dielectric constants. For example, the dielectric constant of the first planarization layer 31 can be set to be greater than that of the second planarization layer 32. That is, the dielectric constant of the first planarization layer 31, which is closer to the substrate 30, is set to be larger. This makes the second planarization layer 32 present a more porous and loose low dielectric effect compared to the first planarization layer 31. This can reduce the parasitic capacitance between the metal layers set on the upper and lower sides of the second planarization layer 32, avoid the influence of parasitic capacitance on the electrical signal received by the light-emitting element, and thus help ensure the good display effect of the display panel 100.
[0047] It should be added that this application does not specifically limit the area of the surface of the first planarization layer 31 away from the second planarization layer 32, nor the area of the surface of the second planarization layer 32 away from the first planarization layer 31. Users can adjust the size of these two surfaces according to their actual needs.
[0048] Please refer to Figure 2 and Figure 3 Optionally, the density of the first planarization layer 31 is greater than the density of the second planarization layer 32.
[0049] Specifically, by differentiating the density of the first planarization layer 31 and the second planarization layer 32, the dielectric constants of the first planarization layer 31 and the second planarization layer 32 can be different. Therefore, this application also provides an optional setting method in which the density of the first planarization layer 31 is greater than that of the second planarization layer 32, which can make the first planarization layer 31 have a larger dielectric constant than the second planarization layer 32. This results in the second planarization layer 32 exhibiting a more porous and loose low dielectric effect compared to the first planarization layer 31, thereby reducing the parasitic capacitance between the metal layers set on the upper and lower sides of the second planarization layer 32 and avoiding the influence of parasitic capacitance on the electrical signals received by the light-emitting element, thus helping to ensure the good display effect of the display panel 100.
[0050] Please continue to refer to Figure 2 and Figure 3 Optionally, along the direction perpendicular to the plane of the substrate 30, the thickness of the first planarization layer 31 is H1, and the thickness of the second planarization layer 32 is H2; H1 > H2.
[0051] Specifically, this application also provides an optional setting method in which the thicknesses of the first planarization layer 31 and the second planarization layer 32 are set differently along the direction perpendicular to the plane where the substrate 30 is located, and the thickness H1 of the first planarization layer 31 can be set to be greater than the thickness H2 of the second planarization layer 32.
[0052] After the first planarization layer 31 is fabricated, a metal trace layer needs to be set on the surface of the first planarization layer 31 away from the substrate 30. In order to ensure the setting effect of the metal trace layer, the surface of the first planarization layer 31 away from the substrate 30 needs to have sufficient flatness. Making the thickness of the first planarization layer 31 larger can make the self-leveling effect of the first planarization layer 31 better, thereby making the surface of the first planarization layer 31 away from the substrate 30 flatter. This ensures that the metal trace layer on the side of the first planarization layer 31 away from the substrate 30 is made into a more uniform film, so as to avoid adverse effects on the photolithography accuracy of the metal trace layer. This is beneficial to improving the setting yield of each film layer and component in the display panel 100, thereby improving the display effect of the display panel 100.
[0053] Figure 4 The image shown is provided in an embodiment of this application. Figure 2 Please refer to another cross-sectional diagram of AA'. Figure 2 and Figure 4 Optionally, it also includes:
[0054] The first inorganic layer 33 located in the sub-display area 12 is disposed on the side of the first planarization layer 31 near the substrate 30, and the first planarization layer 31 and the first inorganic layer 33 are in contact.
[0055] The first planarization layer 31 includes a third surface 313 on the side away from the second planarization layer 32, and the first inorganic layer 33 includes a fifth surface 335 on the side close to the first planarization layer 31. The third surface 313 and the fifth surface 335 overlap in a direction perpendicular to the plane of the substrate 30.
[0056] Specifically, this application also provides an optional configuration method in which a first inorganic layer 33 is provided on the side of the first planarization layer 31 facing the substrate 30, and the first inorganic layer 33 can be configured to be in contact with the first planarization layer 31; in order to ensure the light transmission effect of the light-transmitting area 11 of the display panel 100, the first inorganic layer 33 can be optionally located in the sub-display area 12, rather than in the light-transmitting area 11. Furthermore, based on the condition that the first surface 311 of the first planarization layer 31, which is closer to the second planarization layer 32, completely overlaps with the second surface 322 of the second planarization layer 32, which is closer to the first planarization layer 31, a third surface 313 of the first planarization layer 31, which is farther from the second planarization layer 32, can be further configured to overlap with the fifth surface 335 of the first inorganic layer 33, which is closer to the first planarization layer 31, along a direction perpendicular to the plane of the substrate 30. Specifically, the third surface 313 and the fifth surface 335 can completely overlap. With this configuration, the side surfaces of the first planarization layer 31 and the first inorganic layer 33 are smoothly connected on the side near the light-transmitting area 11, and there is no step structure between the first planarization layer 31 and the first inorganic layer 33. This is equivalent to reducing the number of steps in the direction parallel to the plane of the substrate 30. Figure 1 The areas of boundary 01 and boundary 02 shown in the figure increase the area of the light-transmitting area 11 to a certain extent compared with the prior art, which is conducive to improving the overall light transmittance of the display panel 100 and making the light transmission effect of the transparent display panel 100 better.
[0057] Please refer to Figures 2-4 Optionally, the first planarization layer 31 is made of a first material component, and the second planarization layer 32 is made of a second material component;
[0058] The viscosity of the first material component is less than the viscosity of the second material component.
[0059] Specifically, this application also provides an optional configuration in which the first planarization layer 31 and the second planarization layer 32 are made of different material compositions. Specifically, the first material composition with relatively low viscosity can be used to make the first planarization layer 31, and the second material composition with relatively high viscosity can be used to make the second planarization layer 32, so that the material composition for making the first planarization layer 31 has a lower viscosity than the material composition for making the second planarization layer 32.
[0060] This application uses a first material component with lower viscosity to fabricate the first planarization layer 31, which improves the self-leveling effect of the first planarization layer 31. This results in a flatter surface on the side of the first planarization layer 31 away from the substrate 30, ensuring a more uniform film formation of the metal wiring layer on that side. This avoids adverse effects on the photolithography accuracy of the metal wiring layer, improves the yield of each film layer and component in the display panel 100, and ultimately enhances the display effect of the display panel 100. Furthermore, the better self-leveling effect of the first planarization layer 31 leads to better filling of film layers with height differences and better contact with irregular etched surfaces.
[0061] It should also be noted that viscosity is mainly determined by the solid content of the material components. The higher the solid content, the higher the viscosity. Therefore, the viscosity of the material components can be adjusted by adjusting the solid content and additives. The viscosity of the material components used in the first planarization layer 31 and the second planarization layer 32 mentioned in this application refers to the viscosity of the material components during manufacturing. When the first planarization layer 31 and the second planarization layer 32 are manufactured and cured, they are inorganic materials and do not have fluidity.
[0062] Figure 5 The image shown is provided in an embodiment of this application. Figure 2 Another cross-sectional diagram of AA'. Figure 6 The image shown is provided in an embodiment of this application. Figure 2 Another cross-sectional diagram of AA'. Figure 7 The image shown is provided in an embodiment of this application. Figure 2 Please refer to another cross-sectional diagram of AA'. Figures 2-7 Optionally, the first planarization layer 31 includes a third surface 313 on the side away from the second planarization layer 32, and the second planarization layer 32 includes a fourth surface 324 on the side away from the first planarization layer 31.
[0063] Along a direction perpendicular to the plane of the substrate 30, the first surface 311 and the third surface 313 completely overlap, or the first surface 311 is located within the region of the third surface 313; and / or,
[0064] Along a direction perpendicular to the plane of the substrate 30, the fourth surface 324 completely overlaps with the second surface 322, or the fourth surface 324 is located within the area of the second surface 322.
[0065] Specifically, such as Figure 5As shown, this application also provides an optional configuration where, along a direction perpendicular to the plane of the substrate 30, the third surface 313 of the first planarization layer 31 on the side away from the second planarization layer 32 and the first surface 311 of the first planarization layer 31 on the side near the second planarization layer 32 are completely overlapped. In other words, the upper and lower surfaces of the first planarization layer 31 located in any sub-display area 12 can be configured to be completely equal in size and completely overlapped. Alternatively, along a direction perpendicular to the plane of the substrate 30, the fourth surface 324 of the second planarization layer 32 on the side away from the first planarization layer 31 and the second surface 322 of the second planarization layer 32 on the side near the first planarization layer 31 are completely overlapped. In other words, the upper and lower surfaces of the second planarization layer 32 located in any sub-display area 12 can be configured to be completely equal in size and completely overlapped. Specifically, as follows... Figure 5 As shown in the cross-sectional view of a sub-display area 12, the first planarization layer 31 and the second planarization layer 32 have the same length along the direction of the plane where the substrate 30 is located, that is, they appear as two rectangles with the same long side.
[0066] In addition, such as Figure 6 As shown, when the upper and lower surfaces of the first planarization layer 31 located in any sub-display area 12 are completely equal in size and completely overlap, it is also possible to further configure the fourth surface 324 of the second planarization layer 32, which is away from the first planarization layer 31, to be located within the second surface 322 of the second planarization layer 32, which is close to the first planarization layer 31, along a direction perpendicular to the plane of the substrate 30. In other words, the surface of the second planarization layer 32 that is away from the first planarization layer 31 can be configured to be relatively smaller. Specifically, as shown... Figure 6 As shown in the cross-sectional view of a sub-display area 12, the first planarization layer 31 is rectangular, while the second planarization layer 32 is trapezoidal.
[0067] like Figure 7 As shown, this application also provides an optional configuration where, along a direction perpendicular to the plane of the substrate 30, the first surface 311 of the first planarization layer 31, near the second planarization layer 32, is located within the third surface 313 of the first planarization layer 31, away from the second planarization layer 32. In this case, it is optional to further configure, along a direction perpendicular to the plane of the substrate 30, the fourth surface 324 of the second planarization layer 32, away from the first planarization layer 31, and the second surface 322 of the second planarization layer 32, near the first planarization layer 31, are completely overlapped. That is, it is optional to configure the upper and lower surfaces of the second planarization layer 32 located in any sub-display area 12 to be completely equal in size and completely overlapped. Specifically, as shown... Figure 7As shown in the cross-sectional view of a sub-display area 12, the first planarization layer 31 can be set to be trapezoidal, while the second planarization layer 32 can be set to be rectangular.
[0068] In addition, please refer to Figure 3 and Figure 4 When the upper and lower surfaces of the first planarization layer 31 located in any sub-display area 12 are configured such that the size of the first surface 311 is smaller than the size of the third surface 313, it is also possible to further configure the fourth surface 324 of the second planarization layer 32, which is away from the first planarization layer 31, to be located within the second surface 322 of the second planarization layer 32, which is close to the first planarization layer 31, along a direction perpendicular to the plane of the substrate 30. In other words, the surface of the second planarization layer 32 that is away from the first planarization layer 31 can be configured to be relatively smaller. Specifically, for example... Figure 4 As shown in the cross-sectional view of a sub-display area 12, the first planarization layer 31 is presented as a trapezoid, and the second planarization layer 32 is also presented as a trapezoid. At the same time, the cross-sectional views of the first planarization layer 31 and the second planarization layer 32 can simultaneously present a large trapezoidal shape.
[0069] It should be noted that the four selectable settings of the first planarization layer 31 and the second planarization layer 32 provided above can be chosen by the user according to their needs, and this application does not impose any specific limitations on them; in addition, it is okay if there is a small step area between the first planarization layer 31 and the second planarization layer 32, as long as the area of the light-transmitting area 11 can be increased compared with the prior art.
[0070] Figure 8 The image shown is provided in an embodiment of this application. Figure 2 Please refer to another cross-sectional diagram of AA'. Figure 2 and Figure 8 Optionally, it also includes:
[0071] The buffer layer 34 located in the sub-display area 12 is disposed on the side of the substrate 30 facing the first planarization layer 31 and is in contact with the substrate 30;
[0072] The buffer layer 34 includes a sixth surface 346 facing the side of the substrate 30;
[0073] The second planarization layer 32 includes a fourth surface 324 on the side away from the first planarization layer 31. Along the direction perpendicular to the plane where the substrate 30 is located, the fourth surface 324 is located in the region where the sixth surface 346 is located.
[0074] Along a direction parallel to the plane of substrate 30, there is a first spacing D between the edge of the fourth surface 324 and the edge of the sixth surface 346, where 0 < D ≤ 9 μm.
[0075] Specifically, this application also provides an optional configuration in which the display panel 100 further includes a buffer layer 34. In order to ensure that the light-transmitting area 11 of the display panel 100 has good light transmittance, the buffer layer 34 can be optionally located in the sub-display area 12. Specifically, the buffer layer 34 can be optionally located on the side of the substrate 30 facing the first planarization layer 31 and is in contact with the substrate 30. At this time, along the direction perpendicular to the plane where the substrate 30 is located, the fourth surface 324 of the second planarization layer 32 on the side away from the first planarization layer 31 can be optionally located in the sixth surface 346 of the buffer layer 34 on the side close to the substrate 30; that is, along the direction parallel to the plane where the substrate 30 is located, there is a distance difference between the edge of the fourth surface 324 and the edge of the sixth surface 346, and the value of this distance difference (first pitch) can be less than or equal to 9 μm. This configuration, compared to existing technologies, can reduce the first pitch by at least 3μm, thereby increasing the area of the light-transmitting area 11 in the display panel 100 by about 12%, resulting in better light transmission of the transparent display panel 100.
[0076] Please continue to refer to Figure 2 and Figure 8 Optionally, along a direction parallel to the plane of the substrate 30 and pointing towards the sub-display area 12 along the light-transmitting area 11, the sub-display area 12 includes a first plane 41, and the first plane 41 and the plane of the substrate 30 include a first included angle α, 30°≤α≤90°, towards the sub-display area 12.
[0077] Specifically, this application provides an optional setting method in which, along the direction parallel to the plane where the substrate 30 is located, the light-transmitting area 11 points to the side of the sub-display area 12. The buffer layer 34 in the sub-display area 12, which is at least in contact with the substrate 30, includes a first plane 41. The first plane 41 and the plane where the substrate 30 is located include a first included angle α facing the side of the sub-display area 12. The value range of the first included angle α can be set to be greater than or equal to 30° and less than or equal to 90°.
[0078] Thus, by setting a larger first angle α between the first plane 41 of the sub-display area 12 pointing towards the sub-display area 12 along the light-transmitting area 11 and the plane where the substrate 30 is located, the tilt of the first plane 41 relative to the direction perpendicular to the plane where the substrate 30 is located can be smaller, so that the area of the light-transmitting area 11 can be relatively larger. Compared with the prior art, this increases the area of the light-transmitting area 11 to a certain extent, which is beneficial to improving the overall light transmittance of the display panel 100 and making the light transmission effect of the transparent display panel 100 better.
[0079] Specifically, the first spacing D between the edge of the fourth surface 324 and the edge of the sixth surface 346 can be set to a value range of 0 μm (∠α=90°)<D≤9 μm (∠α=30°). Further, the first spacing D can be set to a value range of 1 μm<X<8.7 μm.
[0080] Please refer to Figure 2 and Figure 8 Optionally, both the first material component and the second material component include siloxane.
[0081] Specifically, the first planarization layer 31 and the second planarization layer 32 can have different dielectric constants, which can be achieved by adding different organic solvents to the original materials. This application provides an optional configuration in which the materials used to fabricate the first planarization layer 31 and the second planarization layer 32 both include siloxanes; specifically, the materials used to fabricate the first planarization layer 31 and the second planarization layer 32 are both SOG (Silicon-on-Glass), and siloxanes are the main component of SOG.
[0082] In addition, SOG has a good barrier effect, which can further prevent external water and oxygen from entering the interior of the display panel 100.
[0083] Please continue to refer to Figure 2 and Figure 8 Optionally, the second material component includes a pore-forming agent.
[0084] Specifically, this application provides an optional configuration method in which, based on SOG as the material for fabricating the second planarization layer 32, a pore-forming agent can be further added to the second material component for fabricating the second planarization layer 32. The pore-forming agent can be, for example, an organic fine powder, so that the second planarization layer 32 presents a loose film, thereby achieving a lower dielectric effect in which the second planarization layer 32 is more porous and loose than the first planarization layer 31. This can reduce the parasitic capacitance between the metal layers disposed on the upper and lower sides of the second planarization layer 32, avoid the influence of parasitic capacitance on the electrical signals received by the light-emitting element, and thus help ensure the good display effect of the display panel 100.
[0085] Please continue to refer to Figure 2 and Figure 8 Optionally, the dielectric constant of the first planarization layer 31 is K1, and the dielectric constant of the second planarization layer 32 is K2; 3.4F / m≤K1≤3.6F / m, 2.9F / m≤K2≤3.1F / m.
[0086] Specifically, this application provides an optional setting method in which the dielectric constant K1 of the first planarization layer 31 can be set to a range of 3.4F / m-3.6F / m, and the dielectric constant K2 of the second planarization layer 32 can be set to a range of 2.9F / m-3.1F / m, so that the second planarization layer 32 has a relatively small dielectric constant. This results in the second planarization layer 32 exhibiting a more porous and loose low dielectric effect compared to the first planarization layer 31, thereby reducing the parasitic capacitance between the metal layers set on the upper and lower sides of the second planarization layer 32 and avoiding the influence of parasitic capacitance on the electrical signals received by the light-emitting element, thus helping to ensure a good display effect of the display panel 100.
[0087] Please continue to refer to Figure 2 and Figure 8 Optionally, 2μm≤H1≤3μm, 1.35μm≤H2≤1.65μm.
[0088] Specifically, this application also provides an optional setting method in which the thickness H1 of the first planarization layer 31 is set to be between 2μm and 3μm along the direction perpendicular to the plane where the substrate 30 is located, and the thickness H2 of the second planarization layer 32 is set to be between 1.35μm and 1.65μm.
[0089] After the first planarization layer 31 is fabricated, a metal trace layer needs to be set on the surface of the first planarization layer 31 away from the substrate 30. In order to ensure the setting effect of the metal trace layer, the surface of the first planarization layer 31 away from the substrate 30 needs to have sufficient flatness. Making the thickness H1 of the first planarization layer 31 larger can make the self-leveling effect of the first planarization layer 31 better, thereby making the surface of the first planarization layer 31 away from the substrate 30 flatter. This ensures that the metal trace layer on the side of the first planarization layer 31 away from the substrate 30 is made into a more uniform film, so as to avoid adverse effects on the photolithography accuracy of the metal trace layer, improve the setting yield of each film layer and component in the display panel 100, and thus improve the display effect of the display panel 100. Furthermore, if the thickness H1 of the first planarization layer 31 is set to be greater than 3 μm, the thickness of the first planarization layer 31 will be too large, which will increase the difficulty of etching away part of the first planarization layer 31 to achieve the light-transmitting area 11 without the first planarization layer 31. If the thickness H1 of the first planarization layer 31 is set to be less than 2 μm, the flatness of the first planarization layer 31 may not be good enough, which is not conducive to the fabrication of the metal trace layer on the side of the first planarization layer 31 away from the substrate 30. Therefore, in this application, the thickness H1 of the first planarization layer 31 is set to be between 2 μm and 3 μm, which can ensure the flatness of the first planarization layer 31 and avoid increasing the difficulty of the etching process. Furthermore, since the film layer difference on the side of the first planarization layer 31 away from the second planarization layer 32 is relatively large, a thicker film layer is required for planarization. Therefore, it is suitable to make the thickness of the first planarization layer 31 slightly thicker. A thicker first planarization layer 31 can eliminate and reduce the film layer height difference caused by the patterning process of the bottom film layer, prevent short circuits between the subsequent metal film layer and the previous metal layer, and prevent the risk of residual subsequent metal film layers. It can also reduce the difficulty of subsequent photolithography processes. Among them, a high film layer height difference makes the alignment and patterning of photolithography more difficult.
[0090] Furthermore, since metal layers are also disposed on the upper and lower sides of the second planarization layer 32, if the thickness H2 of the second planarization layer 32 is small, there will be a relatively large parasitic capacitance between the metal layers on the upper and lower sides of the second planarization layer 32, which will affect the optical parameters of the display panel 100 and have an adverse effect on the display effect of the display panel 100. If the thickness of the second planarization layer 32 is too thick, it will increase the difficulty of etching part of the second planarization layer 32 to achieve the light-transmitting area 11 without the second planarization layer 32. Therefore, the thickness H2 of the second planarization layer 32 in this application is set in the range of 1.35μm-1.65μm, which can avoid increasing the difficulty of the etching process and also ensure that there is no large parasitic capacitance between the metal layers disposed on the upper and lower sides that affects the display effect.
[0091] Figure 9 The image shown is provided in an embodiment of this application. Figure 2 Please refer to another cross-sectional diagram of AA'. Figure 2 and Figure 9 Optionally, it also includes:
[0092] The isolation layer 38 located in the sub-display area 12 is disposed on the side of the second planarization layer 32 away from the first planarization layer 31;
[0093] The materials used to make the isolation layer 38 include siloxane.
[0094] Specifically, this application also provides an optional configuration where the display panel 100 further includes an isolation layer 38. To ensure good light transmission in the light-transmitting area 11, the isolation layer 38 can be optionally located only in the sub-display area 12. Alternatively, the isolation layer 38 can be optionally located on the side of the second planarization layer 32 away from the first planarization layer 31. The isolation layer 38 can be made using siloxane. The material used to make the isolation layer 38 can be the aforementioned SOG (Silicon-on-Glass) structure, with siloxane being the main component of SOG.
[0095] In the prior art, the isolation layer 38 is formed by PECVD (Plasma Enhanced Chemical Vapor Deposition) using SiO / SiN film, which poses a risk of contaminating the PECVD chamber. In this application, the isolation layer 38 is formed by coating with SOG material, which eliminates the risk of contaminating the vacuum chamber (PECVD) and can reduce the manufacturing cost of the display panel 100 to a certain extent.
[0096] Figure 10 The diagram shown is a schematic representation of a display device provided in an embodiment of this application. Please refer to the provided text for further details. Figures 2-9 Reference Figure 10 Based on the same inventive concept, this application also provides a display device 200, which includes a display panel 100, and the display panel 100 is any of the display panels 100 provided in this application.
[0097] It should be noted that the embodiments of the display device 300 provided in this application can refer to the embodiments of the display panel 100 described above, and will not be repeated here. The display device 200 provided in this application can be any product and component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, vehicle display screen, or navigation device.
[0098] Please refer to Figures 2-10Based on the same inventive concept, this application also provides a method for manufacturing a display panel, which is used for the aforementioned display panel 100, wherein the display surface 100 is any of the display panel 100 provided in this application. The manufacturing method includes:
[0099] The first planarization layer 31 and the second planarization layer 32 located in the light-transmitting area 11 are etched in the same process.
[0100] Specifically, this application provides a method for manufacturing a display panel 100. This method includes at least the following steps: after the first planarization layer 31 and the second planarization layer 32 are manufactured and cured, the first planarization layer 31 and the second planarization layer 32 located in the light-transmitting area 11 of the display panel 100 need to be removed. This can be achieved by etching the portion of the first planarization layer 31 and the second planarization layer 32 in the same process, without first etching the second planarization layer 32 and then etching the first planarization layer 31, or without first etching the first planarization layer 31 and then etching the second planarization layer 32. This helps to reduce the complexity of manufacturing the display panel 100 and also helps to avoid the formation of obvious step areas on the side portions between the first planarization layer 31 and the second planarization layer 32. This helps to increase the area of the light-transmitting area 11 to a certain extent, improves the overall light transmittance of the display panel 100, and makes the light transmission effect of the transparent display panel 100 better.
[0101] One alternative fabrication method involves, after the first planarization layer 31 is fabricated and cured, the first SOG layer (first planarization layer 31) is dry-etched away through the contact holes of the electrical connections, while the SOG is retained in the light-transmitting area. After the second SOG layer (second planarization layer 32) is cured and the SOG is removed through the contact holes, a one-step etching process is used to remove all inorganic film layers (at least the first planarization layer 31 and the second planarization layer 32) in the light-transmitting area. Alternatively, the first planarization layer 31, the second planarization layer 32, and the first inorganic layer 33 can be etched in the same process as needed. This application does not impose specific limitations on this, and users can select the number and type of film layers etched together in the same process according to their needs.
[0102] As can be seen from the above embodiments, the display panel, its manufacturing method, and the display device provided by the present invention achieve at least the following beneficial effects:
[0103] This application provides a display panel and its manufacturing method and display device. In a sub-display area of the display panel that is connected to the transparent area, the surfaces of the first planarization layer and the second planarization layer overlap, so that there is no obvious boundary area between the surfaces of the first planarization layer and the second planarization layer, thereby maximizing the area of the transparent area in the display panel and improving the transparency effect of the transparent display panel. Furthermore, the first planarization layer and the second planarization layer can be provided simultaneously, with the first planarization layer having a dielectric constant greater than that of the second planarization layer. The second planarization layer is located on the side of the first planarization layer facing the light-emitting surface of the display panel, so that the second planarization layer presents a more porous and loose low dielectric effect, thereby reducing the parasitic capacitance between the metal layers disposed on the upper and lower sides of the second planarization layer, thereby ensuring a good display effect of the display panel.
[0104] While specific embodiments of the invention have been described in detail by way of examples, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should understand that modifications can be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims
1. A display panel, characterized in that, include: Substrate; A first planarization layer is located on one side of the substrate; The second planarization layer is located on the side of the first planarization layer away from the substrate, and the first planarization layer and the second planarization layer are in contact; The display panel includes a display area, which includes a light-transmitting area and a sub-display area. The sub-display area and the light-transmitting area are alternately arranged. The first planarization layer and the second planarization layer are both located in the sub-display area. In at least one of the sub-display areas, the first planarization layer includes a first surface near the side of the second planarization layer, and the second planarization layer includes a second surface near the side of the first planarization layer, wherein the first surface and the second surface overlap in a direction perpendicular to the plane of the substrate. The dielectric constant of the first planarization layer is greater than that of the second planarization layer.
2. The display panel according to claim 1, characterized in that, The density of the first planarization layer is greater than that of the second planarization layer.
3. The display panel according to claim 1, characterized in that, Along a direction perpendicular to the plane of the substrate, the thickness of the first planarization layer is H1, and the thickness of the second planarization layer is H2; H1 > H2.
4. The display panel according to claim 1, characterized in that, Also includes: The first inorganic layer located in the sub-display area is disposed on the side of the first planarization layer near the substrate, and the first planarization layer and the first inorganic layer are in contact; The first planarization layer includes a third surface on the side away from the second planarization layer, and the first inorganic layer includes a fifth surface on the side close to the first planarization layer. The third surface and the fifth surface overlap in a direction perpendicular to the plane of the substrate.
5. The display panel according to claim 1, characterized in that, The first planarization layer is made of a first material component, and the second planarization layer is made of a second material component; The viscosity of the first material component is less than the viscosity of the second material component.
6. The display panel according to claim 1, characterized in that, The first planarization layer includes a third surface on the side away from the second planarization layer, and the second planarization layer includes a fourth surface on the side away from the first planarization layer; Along a direction perpendicular to the plane of the substrate, the first surface completely overlaps with the third surface, or the first surface is located within the region of the third surface; And / or, Along a direction perpendicular to the plane of the substrate, the fourth surface completely overlaps with the second surface, or the fourth surface is located within the region of the second surface.
7. The display panel according to claim 1, characterized in that, Also includes: A buffer layer located in the sub-display area is disposed on the side of the substrate facing the first planarization layer and is in contact with the substrate; The buffer layer includes a sixth surface facing the substrate side; The second planarization layer includes a fourth surface on the side away from the first planarization layer, and the fourth surface is located in the region of the sixth surface along a direction perpendicular to the plane of the substrate. Along a direction parallel to the plane of the substrate, the edge of the fourth surface and the edge of the sixth surface include a first spacing D, 0 < D ≤ 9 μm.
8. The display panel according to claim 1, characterized in that, Along a direction parallel to the plane of the substrate, and pointing towards the sub-display area from the light-transmitting area, the sub-display area includes a first plane, and the first plane and the plane of the substrate include a first included angle α, 30°≤α≤90°, towards the sub-display area.
9. The display panel according to claim 5, characterized in that, Both the first material component and the second material component include siloxane.
10. The display panel according to claim 5, characterized in that, The second material component includes a pore-forming agent.
11. The display panel according to claim 1, characterized in that, The dielectric constant of the first planarization layer is K1, and the dielectric constant of the second planarization layer is K2; 3.4F / m≤K1≤3.6F / m, 2.9F / m≤K2≤3.1F / m.
12. The display panel according to claim 3, characterized in that, 2μm≤H1≤3μm, 1.35μm≤H2≤1.65μm.
13. The display panel according to claim 1, characterized in that, Also includes: An isolation layer located in the sub-display area is disposed on the side of the second planarization layer away from the first planarization layer; The material used to manufacture the isolation layer includes siloxane.
14. A display device, characterized in that, Includes the display panel as described in any one of claims 1-13.
15. A method for manufacturing a display panel, characterized in that, For use in a display panel as described in any one of claims 1-13; The manufacturing method includes: The first planarization layer and the second planarization layer, located in the light-transmitting area, are etched in the same process.