Semiconductor test structure and test method

Abstract

The application provides a semiconductor test structure and a test method. The semiconductor test structure comprises: a first pattern sequence, the first pattern sequence comprises a plurality of first patterns extending along a first direction and arranged along a second direction, and the gap between two adjacent first patterns gradually increases along the first direction; a second pattern sequence is arranged adjacent to the first pattern sequence along the first direction, the second pattern sequence comprises a plurality of second patterns extending along the first direction and arranged along the second direction, and the width of the second pattern gradually increases along the first direction; wherein the second direction is perpendicular to the first direction. The above technical scheme sets different density pattern sequences to monitor the etching deviation caused by the etching load in the etching process of different pattern densities, reduces the etching error of different density chip layouts, and improves the etching quality.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and more particularly to a semiconductor testing structure and testing method. Background Technology

[0002] In semiconductor etching processes, etching load effects can lead to etching deviations. Due to varying etching pattern densities, areas with higher etching pattern density are more prone to deviations, significantly impacting wafer etching quality. Current technologies only perform optical correction (OPC) on the etched areas based on process integration requirements, which is cumbersome and time-consuming.

[0003] As advanced process technologies advance to higher nodes, the challenge lies in reducing etching errors and improving etching quality to protect the scope of customer chip layout designs. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to reduce the etching error of chip layouts with different densities, improve the etching quality, and provide a semiconductor test structure and test method.

[0005] To address the aforementioned problems, the present invention provides a semiconductor testing structure, comprising: a first pattern sequence, the first pattern sequence including a plurality of first patterns extending along a first direction and arranged along a second direction, wherein the gap between adjacent first patterns gradually increases along the first direction; and a second pattern sequence, disposed adjacent to the first pattern sequence along the first direction, the second pattern sequence including a plurality of second patterns extending along the first direction and arranged along the second direction, wherein the width of the second patterns gradually increases along the first direction; wherein the second direction is perpendicular to the first direction.

[0006] In some embodiments, the second graphic sequence and the first graphic sequence are arranged adjacent to and complementary along the first direction, and the width of the gap between two adjacent first graphics is substantially the same as the width of the second graphic at the complementary position.

[0007] In some embodiments, every five of the first graphics and five of the second graphics arranged in a complementary manner constitute a test unit.

[0008] In some embodiments, within each test unit, the width of the gap between two adjacent first patterns is the same, and the width of all second patterns is the same.

[0009] In some embodiments, all the first patterns in the first pattern sequence have the same width, the width of the second patterns in the second pattern sequence ranges from 220nm to 1200nm, and the width difference between the second patterns of two adjacent test units is 100nm.

[0010] To address the aforementioned problems, the present invention also provides a semiconductor testing method using the semiconductor testing structure described herein. The method includes the following steps: providing an initial semiconductor structure; forming a mask layer on the surface of the initial semiconductor structure using the semiconductor testing structure as a template, and recording a first offset value; etching the initial semiconductor structure to form an etching pattern; comparing the etching pattern with the semiconductor testing structure to obtain a second offset value; and compensating the etching pattern if the difference between the first offset value and the second offset value is greater than or equal to a preset threshold.

[0011] In some embodiments, the etching pattern includes a forward etching pattern and a reverse etching pattern. Both the forward etching pattern and the reverse etching pattern include a plurality of trench patterns extending along the first direction and arranged along the second direction. The forward etching pattern and the reverse etching pattern are arranged adjacent to each other along the first direction. The forward etching pattern includes a plurality of first trench patterns extending along the first direction and arranged along the second direction. The reverse etching pattern includes a plurality of second trench patterns extending along the first direction and arranged along the second direction. The second offset value includes a second forward offset value and a second reverse offset value.

[0012] In some embodiments, the etched pattern is a bright field pattern, and the step of comparing the etched pattern with the semiconductor test structure to obtain a second offset value further includes the following steps: comparing the forward etched pattern with a first pattern sequence of the semiconductor test structure to obtain the edge difference between each first trench pattern and the corresponding first pattern, denoted as a second forward offset value; comparing the reverse etched pattern with a second pattern sequence of the semiconductor test structure to obtain the edge difference between each second trench pattern and the corresponding second pattern, denoted as a second reverse offset value; and summing the second forward offset value and the second reverse offset value to obtain the second offset value.

[0013] In some embodiments, the etching pattern is a dark field pattern, and the step of comparing the etching pattern with the semiconductor test structure to obtain a second offset value further includes the following steps: comparing the forward etching pattern with the second pattern sequence of the semiconductor test structure to obtain the edge difference between each first trench pattern and the second pattern, denoted as a second forward offset value; comparing the reverse etching pattern with the first pattern sequence of the semiconductor test structure to obtain the edge difference between each second trench pattern and the first pattern, denoted as a second reverse offset value; and summing the second forward offset value and the second reverse offset value to obtain the second offset value.

[0014] In some embodiments, the preset threshold is less than or equal to 10 nm.

[0015] In some embodiments, the step of compensating the etched pattern further includes: using a selective bias algorithm table to correct the optical proximity effect of the etched pattern.

[0016] The above technical solution, by setting pattern sequences of different densities, monitors the etching offset caused by the etching load in etching processes with different pattern densities, thereby reducing etching errors in chip layouts of different densities and improving etching quality. The semiconductor testing structure can also be used to replace critical dimension bars (CD bars) for measuring critical dimensions (CD) and to replace metal optical critical dimension bars (Metal OCDs) for measuring thickness. This structure significantly improves functionality, saves time, and provides more accurate and wider-range monitoring of etching offset.

[0017] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and apparatus should be considered part of the specification. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the specific embodiments of the present invention, the accompanying drawings used in the description of the specific embodiments will be briefly introduced below. Obviously, the drawings described below are only some specific embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0019] Figure 1 This is a schematic diagram of an embodiment of the semiconductor testing structure described in this invention.

[0020] Figure 2 This is a schematic diagram of another embodiment of the semiconductor test structure described in this invention.

[0021] Figure 3 This is a flowchart illustrating the steps of an embodiment of the semiconductor testing method described in this invention.

[0022] Figures 4A-4E This is a process flow diagram of one embodiment of the semiconductor testing method described in this invention.

[0023] Figures 5A to 5C This is a process flow diagram of another embodiment of the semiconductor testing method of the present invention, which compares the etched pattern with the semiconductor test structure to obtain a second offset value. Detailed Implementation

[0024] The technical solutions in the embodiments of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] Please see Figure 1 This is a schematic diagram of an embodiment of the semiconductor testing structure described in this invention. Figure 1 As shown, the semiconductor testing structure includes a first pattern sequence 11 and a second pattern sequence 12. The first pattern sequence 11 includes a plurality of first patterns 110 extending along a first direction D1 and arranged along a second direction D2, with the gap S1 between adjacent first patterns 110 gradually increasing along the first direction D1. The second pattern sequence 12 is arranged adjacent to the first pattern sequence 11 along the first direction D1, and includes a plurality of second patterns 120 extending along the first direction D1 and arranged along the second direction D2, with the width W2 of the second patterns 120 gradually increasing along the first direction D1. The second direction D2 is perpendicular to the first direction D1.

[0026] The above technical solution, by setting pattern sequences of different densities, monitors the etching offset caused by the etching load in etching processes with different pattern densities, thereby reducing etching errors in chip layouts of different densities and improving etching quality. The semiconductor testing structure can also be used to replace critical dimension bars (CD bars) for measuring critical dimensions (CD) and to replace metal optical critical dimension bars (Metal OCDs) for measuring thickness. This structure significantly improves functionality, saves time, and provides more accurate and wider-range monitoring of etching offset.

[0027] Figure 1The illustrated embodiment is a semiconductor test structure suitable for bright field patterns, where the bright field pattern can be a metal film layer, such as a copper metal film layer. The first pattern sequence 11 corresponds to the forward distribution structure of the metal line pattern of the bright field pattern, and the second pattern sequence 12 corresponds to the reverse distribution structure of the metal line pattern of the bright field pattern.

[0028] In some embodiments, the second graphic sequence 12 and the first graphic sequence 11 are arranged adjacent to and complementary along the first direction D1, and the width of the gap S1 between two adjacent first graphics 110 is substantially the same as the width W1 of the second graphic 120 at the complementary position.

[0029] In some embodiments, every five first patterns 110 and five complementary second patterns 120 constitute a test unit 13.

[0030] In some embodiments, within each test unit 13, the width W1 of the gap S1 between two adjacent first patterns 110 is the same, and the width W2 of all second patterns 120 is the same.

[0031] In some embodiments, the width W1 of all the first patterns 120 in the first pattern sequence 11 is the same, the width W2 of the second patterns 120 in the second pattern sequence 12 ranges from 220nm to 1200nm, and the width difference between the second patterns 120 of two adjacent test units 13 is 100nm. As shown in the figure, in this embodiment, the minimum value of the width W1 of the first pattern 120 and the minimum value of the width W2 of the second pattern 120 are the same. In this embodiment, at the 90nm film thickness node, the minimum value of the width W2 of the second pattern 120 is 220nm, the maximum value is 1200nm, and the width W2 of the second patterns 120 of the test units 13 arranged along the second direction D2 is 220nm, 320nm, 420nm, 520nm, 620nm, 720nm, 820nm, 920nm, 1000nm, 1100nm, and 1200nm respectively. In other embodiments, the width difference of the second pattern 120 of the two adjacent test units 13 can be adjusted according to different processes, such as 200nm, 300nm, etc.

[0032] Please see Figure 2 This is a schematic diagram of another embodiment of the semiconductor test structure described in this invention. Figure 2 The illustrated embodiments and Figure 1 The difference between the embodiments shown is that, Figure 2The illustrated embodiment is a semiconductor test structure suitable for dark field patterns. The dark field pattern can be an active region, a polysilicon layer, or a metal film layer (such as an aluminum metal film layer). The first pattern sequence 11 corresponds to the reverse distribution structure of the metal line pattern of the dark field pattern, and the second pattern sequence 12 corresponds to the forward distribution structure of the metal line pattern of the dark field pattern.

[0033] Based on the same inventive concept, the present invention also provides a semiconductor testing method.

[0034] like Figure 3 as well as Figures 4A-4E As shown, where, Figure 3 This is a flowchart illustrating the steps of an embodiment of the semiconductor testing method described in this invention. Figures 4A-4E This is a process flow diagram of one embodiment of the semiconductor testing method described in this invention. Figure 3 As shown, the semiconductor testing method employs the present invention. Figure 1 The semiconductor test structure shown includes the following steps: Step S31, providing an initial semiconductor structure; Step S32, forming a mask layer on the surface of the initial semiconductor structure using the semiconductor test structure as a template, and recording a first offset value; Step S33, etching the initial semiconductor structure to form an etching pattern; Step S34, comparing the etching pattern with the semiconductor test structure to obtain a second offset value; Step S35, if the difference between the first offset value and the second offset value is greater than or equal to a preset threshold, compensating for the etching pattern.

[0035] Please refer to Figure 4A And in step S31, an initial semiconductor structure 40 is provided. In some embodiments, the initial semiconductor structure 40 can be a bright field pattern, such as a copper metal film layer. In other embodiments, the initial semiconductor structure 40 can also be a dark field pattern, such as an active region, a polysilicon layer, an aluminum metal film layer, etc.

[0036] Please refer to Figure 4B And in step S32, a mask layer 41 is formed on the surface of the initial semiconductor structure 40 using the semiconductor test structure as a template, and a first offset value is recorded. The first offset value is the offset value between the mask layer 41 and the semiconductor test structure when the mask layer 41 is formed. In some embodiments, the mask layer 41 is a photoresist layer.

[0037] Please refer to Figure 4CAnd in step S33, the initial semiconductor structure 40 is etched to form an etching pattern 42. In some embodiments, the initial semiconductor structure 40 is etched using a mask layer 41 as a mask to form the etching pattern 42. In some embodiments, the etching pattern 42 includes a forward etching pattern 421 and a reverse etching pattern 422, and the forward etching pattern 421 and the reverse etching pattern 422 are disposed adjacent to each other along the first direction D1. The forward etching pattern 421 includes a plurality of first trench patterns 4211 extending along the first direction D1 and arranged along the second direction D2; the reverse etching pattern 422 includes a plurality of second trench patterns 4221 extending along the first direction D1 and arranged along the second direction D2.

[0038] Please refer to Figures 4D to 4E And in step S34, the etched pattern 42 is compared with the semiconductor test structure to obtain a second offset value P2. The second offset value P2 includes a second forward offset value P21 and a second reverse offset value P22. In this embodiment, the etched pattern 42 is a bright field pattern, and the step of comparing the etched pattern 42 with the semiconductor test structure to obtain the second offset value P2 further includes the following steps:

[0039] like Figure 4D As shown, the forward etched pattern 421 is compared with the first pattern sequence 11 of the semiconductor test structure to obtain the edge difference between each first trench pattern 4211 and the corresponding first pattern 110, which is denoted as the second forward offset value P21.

[0040] like Figure 4E As shown, the reverse etching pattern 422 is compared with the second pattern sequence 12 of the semiconductor test structure to obtain the edge difference between each second trench pattern 4221 and the corresponding second pattern 120, which is denoted as the second reverse offset value P22.

[0041] The second offset value P2 is obtained by summing the second positive offset value P21 and the second negative offset value P22.

[0042] After completing the above steps, the second offset value P2 described in step S34 can be obtained.

[0043] Please see Figures 5A to 5C This is a process flow diagram of another embodiment of the semiconductor testing method of the present invention, which compares the etched pattern with the semiconductor test structure to obtain a second offset value. For example... Figure 5AAs shown, in this embodiment, the etching pattern 52 is a dark field pattern. The etching pattern 52 includes a forward etching pattern 521 and a reverse etching pattern 522, and the forward etching pattern 521 and the reverse etching pattern 522 are arranged adjacent to each other along the first direction D1. The forward etching pattern 521 includes a plurality of first trench patterns 5211 extending along the first direction D1 and arranged along the second direction D2; the reverse etching pattern 522 includes a plurality of second trench patterns 5221 extending along the first direction D1 and arranged along the second direction D2. The semiconductor test structure adopts the present invention. Figure 2 The step of comparing the etched pattern 52 with the semiconductor test structure to obtain the second offset value P2 further includes the following steps:

[0044] like Figure 5B As shown, the forward etched pattern 521 is compared with the second pattern sequence 12 of the semiconductor test structure to obtain the edge difference between each first trench pattern 5211 and the second pattern 120, which is denoted as the second forward offset value P23.

[0045] like Figure 5C As shown, the reverse etching pattern 522 is compared with the first pattern sequence 11 of the semiconductor test structure to obtain the edge difference between each second trench pattern 5221 and the first pattern 110, which is denoted as the second reverse offset value P24.

[0046] The second offset value P2 is obtained by summing the second positive offset value P23 and the second negative offset value P24.

[0047] After completing the above steps, the second offset value P2 described in step S34 can be obtained.

[0048] Please refer to step S35. If the difference between the first offset value and the second offset value P2 is greater than or equal to a preset threshold, the etched pattern 42 is compensated. In some embodiments, the preset threshold is less than or equal to 10 nm. In this embodiment, the preset threshold is 10 nm. In other embodiments, the preset threshold may also be 1 nm, 3 nm, 5 nm, etc.

[0049] In some embodiments, the step of compensating the etched pattern 42 further includes: applying an optical proximity correction (OPC) to the etched pattern 42 using a selective bias algorithm table (SSA Table). By compensating for etched patterns 42 whose etch offset exceeds a certain threshold, the pattern is corrected, thereby reducing the etch error of chip layouts with different densities and improving the etch quality.

[0050] The above technical solution sets up pattern sequences of different densities to form a semiconductor test structure, compares the etched pattern with the semiconductor test structure and records the offset value, so as to monitor the semiconductor process of etched patterns of different densities. When the offset value is greater than a preset threshold, the etched pattern is compensated to correct the etched pattern, thereby reducing the etching error of chip layouts of different densities and improving the etching quality.

[0051] It should be noted that references to "an embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. In addition, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments is within the knowledge of those skilled in the art.

[0052] Generally, terms can be understood at least partially from their usage in context. For example, the term "one or more," as used herein, depends at least partially on the context and can be used to describe any feature, structure, or characteristic in a singular sense, or in a plural sense, to describe a combination of features, structures, or characteristics. Similarly, terms such as "a," "a," or "the" can also be understood, at least partially on the context, to express either a singular or plural usage. Furthermore, the term "based on" can be understood not necessarily to express an exclusive set of factors, but rather, alternatively, also at least partially on the context, to allow for the presence of other factors that are not necessarily explicitly described. It should also be noted in this specification that "connection / coupling" refers not only to a direct coupling of one component to another, but also to an indirect coupling of one component to another via an intermediate component.

[0053] It should be noted that the terms "comprising" and "having," and their variations, used in this invention document are intended to cover non-exclusive inclusion. The terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence, unless explicitly indicated by the context. It should be understood that such data used interchangeably where appropriate. Furthermore, embodiments and features within embodiments of this invention can be combined with each other unless otherwise specified. In addition, descriptions of well-known components and technologies have been omitted in the above description to avoid unnecessarily obscuring the concepts of this invention. In the various embodiments described above, each embodiment focuses on its differences from other embodiments; similar or identical parts between embodiments can be referred to interchangeably.

[0054] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A semiconductor testing structure, characterized in that, include: The first graphic sequence includes multiple first graphics extending along a first direction and arranged along a second direction, and the gap between two adjacent first graphics gradually increases along the first direction. The second graphic sequence is arranged adjacent to the first graphic sequence along the first direction. The second graphic sequence includes multiple second graphics extending along the first direction and arranged along the second direction, and the width of the second graphics gradually increases along the first direction. The second direction is perpendicular to the first direction. The second graphic sequence and the first graphic sequence are arranged adjacent to and complementary along the first direction. The width of the gap between two adjacent first graphics is basically the same as the width of the second graphic at the complementary position.

2. The semiconductor test structure according to claim 1, characterized in that, Every five of the first graphics and five of the second graphics in a complementary arrangement constitute a test unit.

3. The semiconductor test structure according to claim 2, characterized in that, Within each test unit, the gaps between two adjacent first patterns are of the same width, and all second patterns are of the same width.

4. The semiconductor test structure according to claim 2, characterized in that, All the first patterns in the first pattern sequence have the same width; the width of the second patterns in the second pattern sequence ranges from 220nm to 1200nm, and the width difference between the second patterns of two adjacent test units is 100nm.

5. A semiconductor testing method, characterized in that, The method, employing the semiconductor test structure according to any one of claims 1 to 4, comprises the following steps: Provide an initial semiconductor structure; Using the semiconductor test structure as a template, a mask layer is formed on the surface of the initial semiconductor structure, and a first offset value is recorded. The first offset value is the offset value between the mask layer and the semiconductor test structure when the mask layer is formed. The initial semiconductor structure is etched to form an etching pattern; The etched pattern is compared with the semiconductor test structure to obtain a second offset value; If the difference between the first offset value and the second offset value is greater than or equal to a preset threshold, the etching pattern is compensated.

6. The semiconductor testing method according to claim 5, characterized in that, The etching pattern includes a forward etching pattern and a reverse etching pattern, and the forward etching pattern and the reverse etching pattern are arranged adjacent to each other along the first direction. The forward etching pattern includes a plurality of first trench patterns that extend along the first direction and are arranged along the second direction. The reverse etching pattern includes a plurality of second groove patterns that extend along the first direction and are arranged along the second direction. The second offset value includes a second positive offset value and a second negative offset value.

7. The semiconductor testing method according to claim 6, characterized in that, The etching pattern is a bright field pattern, and the step of comparing the etching pattern with the semiconductor test structure to obtain the second offset value further includes the following steps: The forward etching pattern is compared with the first pattern sequence of the semiconductor test structure to obtain the edge difference between each first trench pattern and the corresponding first pattern, which is recorded as the second forward offset value. The reverse etching pattern is compared with the second pattern sequence of the semiconductor test structure to obtain the edge difference between each second trench pattern and the corresponding second pattern, which is recorded as the second reverse offset value. The second offset value is obtained by summing the second positive offset value and the second negative offset value.

8. The semiconductor testing method according to claim 6, characterized in that, The etching pattern is a dark field pattern, and the step of comparing the etching pattern with the semiconductor test structure to obtain the second offset value further includes the following steps: The forward etching pattern is compared with the second pattern sequence of the semiconductor test structure to obtain the edge difference between each first trench pattern and the second pattern, which is recorded as the second forward offset value. The reverse etching pattern is compared with the first pattern sequence of the semiconductor test structure to obtain the edge difference between each second trench pattern and the first pattern, which is recorded as the second reverse offset value. The second offset value is obtained by summing the second positive offset value and the second negative offset value.

9. The semiconductor testing method according to claim 5, characterized in that, The preset threshold is less than or equal to 10nm.

10. The semiconductor testing method according to claim 5, characterized in that, The step of compensating the etched pattern further includes: using a selective bias algorithm table to correct the optical proximity effect of the etched pattern.

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