Electrostatic discharge protection structure, forming method and working method thereof

Abstract

The application discloses an electrostatic discharge protection structure, a forming method and a working method thereof. The structure comprises a substrate, a first well region in the substrate, the first well region having first ions, a first doped region in the first well region, the first doped region having second ions, a second doped region in the first well region, the second doped region having third ions, and a metal plate electrically connected with the second doped region. When positive charges are accumulated in a device to be protected, a forward-biased PN junction is formed by the first well region and the first doped region to ensure that the accumulated positive charges can be quickly conducted out. When negative charges are accumulated in the device to be protected, a reverse-biased PN junction is formed by the first well region and the first doped region to ensure that the accumulated negative charges can be quickly conducted out. When the device to be protected is tested, a blocking voltage is applied to the metal plate, the blocking voltage being greater than a test voltage of the device to be protected, so that the conduction of the PN junction is blocked, and the test authenticity and accuracy of the device to be protected are ensured.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to an electrostatic discharge protection structure, its formation method, and its operating method. Background Technology

[0002] Integrated circuits are susceptible to damage from static electricity. Protection circuits are typically designed at the input / output terminals or power supply protection devices to prevent internal circuits from being damaged by static electricity.

[0003] In existing integrated circuit designs, electrostatic discharge (ESD) protection structures are often used to reduce electrostatic damage.

[0004] However, existing electrostatic discharge protection structures still have many problems. Summary of the Invention

[0005] The technical problem solved by this invention is to provide an electrostatic discharge protection structure, a method for forming it, and a method for operating it, so as to improve the electrostatic discharge effect.

[0006] To address the aforementioned problems, the present invention provides an electrostatic discharge protection structure, comprising: a substrate; a first well region located within the substrate, the first well region containing a first ion; a first doped region located within the first well region, the first doped region containing a second ion, the first well region exposing the top surface of the first doped region, and the second ion having a different electrical type from the first ion; a second doped region located within the first well region, the second doped region containing a third ion, the first well region exposing the top surface of the second doped region, and the third ion having the same electrical type as the first ion; and a metal plate electrically connected to the second doped region.

[0007] Optionally, the concentration of the second ion in the first doped region is higher than the concentration of the first ion in the first well region.

[0008] Optionally, the concentration of the second ion in the first doped region is greater than 1E15 atoms / cm². 3 .

[0009] Optionally, the concentration of the third ion in the second doped region is higher than the concentration of the first ion in the first well region.

[0010] Optionally, the concentration of the third ion in the second doped region is greater than 1E15 atoms / cm². 3 .

[0011] Optionally, the material of the metal plate includes aluminum.

[0012] Optionally, the first ion includes an N-type ion, the second ion includes a P-type ion, and the third ion includes an N-type ion; or the first ion includes a P-type ion, the second ion includes an N-type ion, and the third ion includes a P-type ion.

[0013] Accordingly, the present invention also provides a method for forming an electrostatic discharge protection structure, comprising: providing a substrate; forming a first well region in the substrate, the first well region containing a first ion; forming a first doped region in the first well region, the first doped region containing a second ion, the first well region exposing the top surface of the first doped region, and the second ion having a different electrical type from the first ion; forming a second doped region in the first well region, the second doped region containing a third ion, the first well region exposing the top surface of the second doped region, and the third ion having the same electrical type as the first ion; forming a metal plate, the metal plate being electrically connected to the second doped region.

[0014] Optionally, the concentration of the second ion in the first doped region is higher than the concentration of the first ion in the first well region.

[0015] Optionally, the concentration of the second ion in the first doped region is greater than 1E15 atoms / cm². 3 .

[0016] Optionally, the concentration of the third ion in the second doped region is higher than the concentration of the first ion in the first well region.

[0017] Optionally, the concentration of the third ion in the second doped region is greater than 1E15 atoms / cm². 3 .

[0018] Optionally, the material of the metal plate includes aluminum.

[0019] Optionally, the first ion includes an N-type ion, the second ion includes a P-type ion, and the third ion includes an N-type ion; or the first ion includes a P-type ion, the second ion includes an N-type ion, and the third ion includes a P-type ion.

[0020] Accordingly, the present invention also provides a method for operating an electrostatic discharge protection structure, comprising: providing a device to be protected, the device to be protected including a gate structure; providing an electrostatic discharge protection structure as described above; electrically connecting the gate structure to the first doped region; applying a test voltage to the gate structure and applying a blocking voltage to the metal plate to perform electrical detection on the device to be protected, wherein the blocking voltage is greater than the test voltage.

[0021] Optionally, when the device to be protected is an NMOS transistor and the charge accumulated in the gate structure is positive, the first ion is an N-type ion, the second ion is a P-type ion, and the third ion is an N-type ion.

[0022] Optionally, when the device to be protected is a PMOS transistor and the charge accumulated in the gate structure is positive, the first ion is an N-type ion, the second ion is a P-type ion, and the third ion is an N-type ion.

[0023] Optionally, when the device to be protected is an NMOS transistor and the charge accumulated in the gate structure is negative, the first ion is a P-type ion, the second ion is an N-type ion, and the third ion is a P-type ion.

[0024] Optionally, when the device to be protected is a PMOS transistor and the charge accumulated in the gate structure is negative, the first ion is a P-type ion, the second ion is an N-type ion, and the third ion is a P-type ion.

[0025] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0026] In the electrostatic discharge protection structure of this invention, when positive charge accumulates in the device to be protected, a forward-biased PN junction is formed through the first well region and the first doped region to ensure rapid discharge of the accumulated positive charge; when negative charge accumulates in the device to be protected, a reverse-biased PN junction is formed through the first well region and the first doped region to ensure rapid discharge of the accumulated negative charge. During testing of the device to be protected, a blocking voltage is applied to the metal plate, and this blocking voltage is greater than the test voltage of the device to be protected, to block the conduction of the PN junction, ensuring the accuracy of the test results.

[0027] Furthermore, the concentration of the second ions in the first doped region is higher than the concentration of the first ions in the first well region. The purpose of forming a high concentration of second ions in the first doped region is to prevent a Schottky contact between the metal connected to the first doped region and the first doped region during subsequent electrical connection with the device to be protected, and instead to form a resistive contact.

[0028] Furthermore, the concentration of the third ion in the second doped region is higher than the concentration of the first ion in the first well region. The purpose of forming a high concentration of third ions in the second doped region is to prevent a Schottky contact between the metal connected to the second doped region and the second doped region during subsequent electrical connection with the metal plate, and instead to form a resistive contact.

[0029] In the method for forming the electrostatic discharge protection structure of the present invention, when the device to be protected accumulates positive charge, a forward-biased PN junction is formed through the first well region and the first doped region to ensure that the accumulated positive charge can be quickly discharged; when the device to be protected accumulates negative charge, a reverse-biased PN junction is formed through the first well region and the first doped region to ensure that the accumulated negative charge can be quickly discharged. During the testing of the device to be protected, a blocking voltage is applied to the metal plate, and the blocking voltage is greater than the test voltage of the device to be protected, to block the conduction of the PN junction, ensuring the accuracy of the test results for the device to be protected.

[0030] Furthermore, the concentration of the second ions in the first doped region is higher than the concentration of the first ions in the first well region. The purpose of forming a high concentration of second ions in the first doped region is to prevent a Schottky contact between the metal connected to the first doped region and the first doped region during subsequent electrical connection with the device to be protected, and instead to form a resistive contact.

[0031] Furthermore, the concentration of the third ion in the second doped region is higher than the concentration of the first ion in the first well region. The purpose of forming a high concentration of third ions in the second doped region is to prevent a Schottky contact between the metal connected to the second doped region and the second doped region during subsequent electrical connection with the metal plate, and instead to form a resistive contact.

[0032] In the working method of the electrostatic discharge protection structure of the present invention, when the device to be protected accumulates positive charge, a forward-biased PN junction is formed through the first well region and the first doped region to ensure that the accumulated positive charge can be quickly discharged; when the device to be protected accumulates negative charge, a reverse-biased PN junction is formed through the first well region and the first doped region to ensure that the accumulated negative charge can be quickly discharged. During the testing of the device to be protected, a blocking voltage is applied to the metal plate, and the blocking voltage is greater than the test voltage of the device to be protected, to block the conduction of the PN junction, ensuring the accuracy of the test results for the device to be protected. Attached Figure Description

[0033] Figure 1 This is a schematic diagram showing the connection between the reverse bias diode protection circuit and the NMOS transistor;

[0034] Figure 2 This is a schematic diagram showing the connection between the forward bias diode protection circuit and the NMOS transistor;

[0035] Figure 3 This is a schematic diagram showing the connection between a gate-grounded N-type field-effect transistor protection circuit and an NMOS transistor;

[0036] Figures 4 to 8 This is a schematic diagram of the steps in the method for forming the electrostatic discharge protection structure according to an embodiment of the present invention;

[0037] Figure 9 This is a schematic diagram of the connection between the electrostatic discharge protection structure and the device to be protected in one embodiment of the present invention;

[0038] Figure 10 This is a schematic diagram of the connection between the electrostatic discharge protection structure and the device to be protected in another embodiment of the present invention;

[0039] Figure 11 This is a schematic diagram of the connection between the electrostatic discharge protection structure and the device to be protected in another embodiment of the present invention;

[0040] Figure 12 This is a schematic diagram showing the connection between the electrostatic discharge protection structure and the device to be protected in another embodiment of the present invention. Detailed Implementation

[0041] As described in the background section, existing electrostatic discharge protection structures still have many problems. These will be explained in detail below.

[0042] Existing electrostatic discharge protection structures include: reverse biased diode protection circuit, forward biased diode protection circuit, and gate grounded N-type field-effect transistor (GGNMOS) protection circuit.

[0043] Please refer to Figure 1 Taking an NMOS transistor as the device to be protected, and assuming that the gate structure of the NMOS transistor accumulates positive charge, a reverse-biased diode protection circuit is typically used as an electrostatic discharge (ESD) protection structure for NMOS transistors. When the voltage generated by the accumulated charge exceeds the reverse-bias breakdown voltage of the PN junction, the accumulated charge is discharged, providing protection. However, the current density per unit area is relatively small, and it cannot discharge quickly and effectively. Moreover, for NMOS transistors with low threshold voltages, if the PN junction is not reverse-biased, it cannot provide protection. If used to protect PMOS transistors, a negative voltage cannot be applied during testing.

[0044] Please refer to Figure 2Taking an NMOS transistor as the device to be protected, and assuming that the gate structure of the NMOS transistor accumulates positive charge, the forward and reverse bias diode protection circuit is typically used as the electrostatic discharge protection structure for PMOS transistors. As long as there is charge accumulated on the gate structure, it can be quickly discharged through the forward and reverse bias diode protection circuit. If a negative voltage cannot be applied to the PMOS transistor during testing, it can proceed normally as long as the negative voltage does not reverse-break down the PN junction. However, this cannot meet the testing requirements for a positive gate voltage on an NMOS transistor.

[0045] Please refer to Figure 3 Taking an NMOS transistor as the protected device, and assuming the gate structure of the NMOS transistor accumulates positive charge, the working mechanism of a gate-grounded N-type field-effect transistor protection circuit is as follows: Since the power dissipation on the MOS transistor is the product of the current and the voltage drop, under a certain ESD current, if the voltage drop on the MOS transistor can be reduced, the junction temperature of the MOS transistor can be reduced, thus achieving the purpose of protecting the MOS transistor. The gate-grounded N-type field-effect transistor protection circuit, as an ESD device, relies on a parasitic NPN BJT to discharge ESD current in the forward direction. The NPN consists of the N+ active region of the drain, a P-type substrate, and the N+ active region of the source. The reverse path for discharging ESD current consists of a PN diode and a gate-source connected NMOS diode. The PN diode consists of a P-type substrate and the N+ active region. In a full-chip ESD network, when an ESD event occurs, the gate-grounded N-type field-effect transistor protection circuit may conduct in both the forward and reverse directions, determined by the potential ESD path. The ESD current will always flow towards the low-resistance path. Therefore, the forward and reverse ESD performance of the gate-grounded N-type field-effect transistor (BJT) protection circuit must be considered during the design process to ensure the reliability of the integrated circuit. The gate-grounded N-type field-effect transistor protection circuit, as a BJT, operates on a breakdown device mechanism, relying on avalanche breakdown between the drain and substrate to form a low-resistance path to discharge ESD current. Compared to PN junctions, the gate-grounded N-type field-effect transistor protection circuit has the advantage of high on-state current density and a lower threshold voltage V0. t Lower, but for the threshold voltage V t Even with lower-end MOS transistors, their protection capabilities remain insufficient.

[0046] Based on this, the present invention provides an electrostatic discharge protection structure, a method for forming it, and a method for its operation. When positive charge accumulates in the device to be protected, a forward-biased PN junction is formed through the first well region and the first doped region to ensure rapid discharge of the accumulated positive charge. When negative charge accumulates in the device to be protected, a reverse-biased PN junction is formed through the first well region and the first doped region to ensure rapid discharge of the accumulated negative charge. During testing of the device to be protected, a blocking voltage is applied to the metal plate, and the blocking voltage is greater than the test voltage of the device to be protected to block the conduction of the PN junction, ensuring the accuracy of the test results.

[0047] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0048] Figures 4 to 8 This is a schematic diagram of the steps in the method for forming the electrostatic discharge protection structure according to an embodiment of the present invention.

[0049] Please refer to Figure 4 Substrate 100 is provided.

[0050] In this embodiment, the substrate 100 is made of silicon; in other embodiments, the substrate may also be made of single-crystal germanium, silicon germanium, silicon carbide, silicon-on-insulator (SOI), germanium-on-insulator (GOI); or the substrate may be made of other materials, such as gallium arsenide or other group III-V compounds.

[0051] The substrate 100 contains doped ions, which are N-type or P-type ions.

[0052] In this embodiment, the doped ions in the substrate 100 are P-type ions.

[0053] Please refer to Figure 5 A first well region 101 is formed within the substrate 100, and the first well region 101 contains a first ion.

[0054] In this embodiment, the first ion is an N-type ion; in other embodiments, the first ion may also be a P-type ion.

[0055] It should be noted that in this embodiment, the first well region 101 is formed by implanting the first ions. The photomask used in the process of implanting the first ions is the same photomask used in conventional semiconductor manufacturing processes, and there is no need to make a new photomask for the implantation of the first ions.

[0056] Please refer to Figure 6A first doped region 102 is formed within the first well region 101, the first doped region 102 contains a second ion, the first well region 101 exposes the top surface of the first doped region 102, and the second ion has a different electrical type than the first ion.

[0057] In this embodiment, the second ion is a P-type ion; in other embodiments, when the first ion is a P-type ion, the second ion is an N-type ion.

[0058] In this embodiment, the concentration of the second ions in the first doped region 102 is higher than the concentration of the first ions in the first well region 101. By forming a high concentration of second ions in the first doped region 102, the purpose is to avoid a Schottky contact between the metal connected to the first doped region 102 and the first doped region 102 during subsequent electrical connection with the device to be protected, and instead form a resistive contact.

[0059] In this embodiment, the concentration of the second ion within the first doped region 102 is greater than 1E15 atoms / cm². 3 .

[0060] It should be noted that in this embodiment, the first doped region 102 is formed by implanting the second ions. The photomask used in the implantation of the second ions is the same photomask used in conventional semiconductor processes, and there is no need to make a new photomask for the implantation of the second ions.

[0061] Please refer to Figure 7 A second doped region 103 is formed within the first well region 101, the second doped region 103 contains a third ion, the first well region 101 exposes the top surface of the second doped region 103, and the third ion has the same electrical type as the first ion.

[0062] In this embodiment, the third ion is an N-type ion; in other embodiments, when the first ion is a P-type ion, the third ion is a P-type ion.

[0063] In this embodiment, the concentration of the third ion in the second doped region 103 is higher than the concentration of the first ion in the first well region 101. By forming a high concentration of third ions in the second doped region 103, the purpose is to avoid a Schottky contact between the metal connected to the second doped region 103 and the second doped region during subsequent electrical connection with the metal plate, and instead form a resistive contact.

[0064] In this embodiment, the concentration of the third ion within the second doped region 103 is greater than 1E15 atoms / cm². 3 .

[0065] It should be noted that in this embodiment, the second doped region 103 is formed by implanting the third ion. The photomask used in the implantation of the third ion is the same photomask used in conventional semiconductor manufacturing processes, and there is no need to make a new photomask for the implantation of the third ion.

[0066] Please refer to Figure 8 A metal plate 104 is formed, which is electrically connected to the second doped region 103.

[0067] When positive charge accumulates in the device to be protected, a forward-biased PN junction is formed through the first well region 101 and the first doped region 102 to ensure rapid discharge of the accumulated positive charge. When negative charge accumulates in the device to be protected, a reverse-biased PN junction is formed through the first well region 101 and the first doped region 102 to ensure rapid discharge of the accumulated negative charge. During testing of the device to be protected, a blocking voltage is applied to the metal plate 104, and the blocking voltage is greater than the test voltage of the device to be protected, to block the conduction of the PN junction and ensure the accuracy of the test results.

[0068] It should be noted that, in this embodiment, the size S of the boundary area between the first doped region 102 and the first well region 101 is not limited, and is adjusted according to the required magnitude of the protection current. The magnitude of the protection current I is... protect =S×I 单位面积 .

[0069] In this embodiment, the metal plate 104 is made of aluminum.

[0070] It should be noted that, in this embodiment, the electrical connection between the metal plate 104 and the second doped region 103 is achieved through several conductive layers and several conductive plugs (not shown) formed in a conventional semiconductor process.

[0071] Accordingly, this invention also provides an electrostatic discharge protection structure, please refer to the following embodiments. Figure 8The system includes: a substrate 100; a first well region 101 located within the substrate 100, the first well region 101 containing a first ion; a first doped region 102 located within the first well region 101, the first doped region 102 containing a second ion, the first well region 101 exposing the top surface of the first doped region 102, and the second ion having a different electrical type from the first ion; a second doped region 103 located within the first well region 101, the second doped region 103 containing a third ion, the first well region 101 exposing the top surface of the second doped region 103, and the third ion having the same electrical type as the first ion; and a metal plate 104 electrically connected to the second doped region 103.

[0072] When positive charge accumulates in the device to be protected, a forward-biased PN junction is formed through the first well region 101 and the first doped region 102 to ensure rapid discharge of the accumulated positive charge. When negative charge accumulates in the device to be protected, a reverse-biased PN junction is formed through the first well region 101 and the first doped region 102 to ensure rapid discharge of the accumulated negative charge. During testing of the device to be protected, a blocking voltage is applied to the metal plate 104, and the blocking voltage is greater than the test voltage of the device to be protected, to block the conduction of the PN junction and ensure the accuracy of the test results.

[0073] It should be noted that, in this embodiment, the size S of the boundary area between the first doped region 102 and the first well region 101 is not limited, and is adjusted according to the required magnitude of the protection current. The magnitude of the protection current I is... protect =S×I 单位面积 .

[0074] In this embodiment, the concentration of the second ions in the first doped region 102 is higher than the concentration of the first ions in the first well region 101. By forming a high concentration of second ions in the first doped region 102, the purpose is to avoid a Schottky contact between the metal connected to the first doped region 102 and the first doped region 102 during subsequent electrical connection with the device to be protected, and instead form a resistive contact.

[0075] In this embodiment, the concentration of the second ion within the first doped region 102 is greater than 1E15 atoms / cm². 3 .

[0076] In this embodiment, the concentration of the third ion in the second doped region 103 is higher than the concentration of the first ion in the first well region 101. By forming a high concentration of the third ion in the second doped region 103, the purpose is to avoid a Schottky contact between the metal connected to the second doped region 103 and the second doped region 103 during subsequent electrical connection with the metal plate 104, and instead form a resistive contact.

[0077] In this embodiment, the concentration of the third ion within the second doped region 103 is greater than 1E15 atoms / cm². 3 .

[0078] In this embodiment, the metal plate 104 is made of aluminum.

[0079] In this embodiment, the first ion is an N-type ion, the second ion is a P-type ion, and the third ion is an N-type ion.

[0080] In other embodiments, the first ion may be a P-type ion, the second ion may be an N-type ion, and the third ion may be a P-type ion.

[0081] Figure 9 This is a schematic diagram of the connection between the electrostatic discharge protection structure and the device to be protected in one embodiment of the present invention; Figure 10 This is a schematic diagram of the connection between the electrostatic discharge protection structure and the device to be protected in another embodiment of the present invention; Figure 11 This is a schematic diagram of the connection between the electrostatic discharge protection structure and the device to be protected in another embodiment of the present invention; Figure 12 This is a schematic diagram showing the connection between the electrostatic discharge protection structure and the device to be protected in another embodiment of the present invention.

[0082] Accordingly, this embodiment of the invention also provides a method for operating an electrostatic discharge protection structure, comprising: providing a device to be protected 200, the device to be protected 200 including a gate structure 201; providing an electrostatic discharge protection structure as described above; electrically connecting the gate structure 201 to the first doped region 102; applying a test voltage to the gate structure 201 and applying a blocking voltage to the metal plate 104 to perform electrical detection on the device to be protected 200, wherein the blocking voltage is greater than the test voltage.

[0083] It should be noted that in this embodiment, no voltage is applied to the metal plate 104 during the semiconductor manufacturing process.

[0084] Please refer to Figure 9In one embodiment, when the device to be protected 200 is an NMOS transistor and the charge accumulated in the gate structure 201 is positive, the first ion is an N-type ion, the second ion is a P-type ion, and the third ion is an N-type ion.

[0085] Since the first ion is an N-type ion and the second ion is a P-type ion, a forward-biased PN junction is formed between the first well region 101 and the first doped region 102, thereby enabling rapid discharge of positive charges. When the NMOS transistor is subjected to a forward test, i.e., a positive test voltage is applied to the gate structure 201, a blocking voltage is applied to the metal plate 104, and the blocking voltage is greater than the test voltage, to block the conduction of the PN junction, ensuring the accuracy of the NMOS transistor test. When the NMOS transistor is subjected to a reverse test, i.e., a negative test voltage is applied to the gate structure 201, a 0-volt blocking voltage is applied to the metal plate 104 to block the conduction of the PN junction, ensuring the accuracy of the NMOS transistor test.

[0086] Please refer to Figure 10 In one embodiment, when the device to be protected 200 is a PMOS transistor and the charge accumulated in the gate structure 201 is positive, the first ion is an N-type ion, the second ion is a P-type ion, and the third ion is an N-type ion.

[0087] Since the first ion is an N-type ion and the second ion is a P-type ion, a forward-biased PN junction is formed between the first well region 101 and the first doped region 102, thereby enabling rapid discharge of positive charges. When a reverse test is applied to the PMOS transistor, i.e., a negative test voltage is applied to the gate structure 201, a 0-volt blocking voltage is applied to the metal plate 104 to block the conduction of the PN junction, ensuring the accuracy of the PMOS transistor test. When a forward test is applied to the PMOS transistor, i.e., a positive test voltage is applied to the gate structure 201, a blocking voltage is applied to the metal plate 104, and the blocking voltage is greater than the test voltage, to block the conduction of the PN junction, ensuring the accuracy of the NMOS transistor test.

[0088] Please refer to Figure 11 In one embodiment, when the device to be protected 200 is an NMOS transistor and the charge accumulated in the gate structure 201 is negative, the first ion is a P-type ion, the second ion is an N-type ion, and the third ion is a P-type ion.

[0089] Since the first ion is a P-type ion and the second ion is an N-type ion, a reverse-biased PN junction is formed between the first well region 101 and the first doped region 102, thereby enabling rapid discharge of negative charges. When the NMOS transistor is subjected to a forward test, i.e., a positive test voltage is applied to the gate structure 201, a blocking voltage is applied to the metal plate 104, and the blocking voltage is greater than the test voltage, to block the conduction of the PN junction, ensuring the accuracy of the NMOS transistor test. When the NMOS transistor is subjected to a reverse test, i.e., a negative test voltage is applied to the gate structure 201, a 0-volt blocking voltage is applied to the metal plate 104 to block the conduction of the PN junction, ensuring the accuracy of the NMOS transistor test.

[0090] Please refer to Figure 12 In one embodiment, when the device to be protected 200 is a PMOS transistor and the charge accumulated in the gate structure 201 is negative, the first ion is a P-type ion, the second ion is an N-type ion, and the third ion is a P-type ion.

[0091] Since the first ion is a P-type ion and the second ion is an N-type ion, a reverse-biased PN junction is formed between the first well region 101 and the first doped region 102, thereby enabling rapid discharge of negative charges. When a reverse test is applied to the PMOS transistor, i.e., a negative test voltage is applied to the gate structure 201, a 0-volt blocking voltage is applied to the metal plate 104 to block the conduction of the PN junction, ensuring the accuracy of the PMOS transistor test. When a forward test is applied to the PMOS transistor, i.e., a positive test voltage is applied to the gate structure 201, a blocking voltage is applied to the metal plate 104, and the blocking voltage is greater than the test voltage, to block the conduction of the PN junction, ensuring the accuracy of the NMOS transistor test.

[0092] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. An electrostatic discharge protection structure, characterized in that, include: Substrate; A first well region located within the substrate, wherein the first well region contains a first ion; A first doped region is located within the first well region, the first doped region contains a second ion, the first well region exposes the top surface of the first doped region, and the second ion has a different electrical type from the first ion; A second doped region is located within the first well region, the second doped region contains a third ion, the first well region exposes the top surface of the second doped region, and the third ion has the same electrical type as the first ion, the first doped region and the second doped region are separated from each other; A metal plate electrically connected to the second doped region; The gate structure of the device to be protected is electrically connected to the first doped region; During the testing of the device to be protected, a blocking voltage is applied to the metal plate to block the conduction of the PN junction formed by the first well region and the first doped region.

2. The electrostatic discharge protection structure as described in claim 1, characterized in that, The concentration of the second ion in the first doped region is higher than the concentration of the first ion in the first well region.

3. The electrostatic discharge protection structure as described in claim 2, characterized in that, The concentration of the second ion in the first doped region is greater than 1E15 atoms / cm 3 .

4. The electrostatic discharge protection structure as described in claim 1, characterized in that, The concentration of the third ion in the second doped region is higher than the concentration of the first ion in the first well region.

5. The electrostatic discharge protection structure as described in claim 4, characterized in that, The concentration of the third ion in the second doped region is greater than 1E15 atoms / cm 3 .

6. The electrostatic discharge protection structure as described in claim 1, characterized in that, The material of the metal plate includes aluminum.

7. The electrostatic discharge protection structure as described in claim 1, characterized in that, The first ion is an N-type ion, the second ion is a P-type ion, and the third ion is an N-type ion; or the first ion is a P-type ion, the second ion is an N-type ion, and the third ion is a P-type ion.

8. A method for forming an electrostatic discharge protection structure, characterized in that, include: Provide substrate; A first well region is formed within the substrate, and the first well region contains a first ion; A first doped region is formed within the first well region, the first doped region contains a second ion, the first well region exposes the top surface of the first doped region, and the second ion has a different electrical type from the first ion; A second doped region is formed within the first well region, the second doped region contains a third ion, the top surface of the second doped region is exposed in the first well region, and the third ion has the same electrical type as the first ion, the first doped region and the second doped region are separated from each other; A metal plate is formed, the metal plate being electrically connected to the second doped region; The gate structure of the device to be protected is electrically connected to the first doped region; During the testing of the device to be protected, a blocking voltage is applied to the metal plate to block the conduction of the PN junction formed by the first well region and the first doped region.

9. The method for forming the electrostatic discharge protection structure as described in claim 8, characterized in that, The concentration of the second ion in the first doped region is higher than the concentration of the first ion in the first well region.

10. The method for forming the electrostatic discharge protection structure as described in claim 9, characterized in that, The concentration of the second ion in the first doped region is greater than 1E15 atoms / cm 3 .

11. The method for forming the electrostatic discharge protection structure as described in claim 8, characterized in that, The concentration of the third ion in the second doped region is higher than the concentration of the first ion in the first well region.

12. The method for forming the electrostatic discharge protection structure as described in claim 10, characterized in that, The concentration of the third ion in the second doped region is greater than 1E15 atoms / cm 3 .

13. The method for forming the electrostatic discharge protection structure as described in claim 8, characterized in that, The material of the metal plate includes aluminum.

14. The method for forming the electrostatic discharge protection structure as described in claim 8, characterized in that, The first ion is an N-type ion, the second ion is a P-type ion, and the third ion is an N-type ion; or the first ion is a P-type ion, the second ion is an N-type ion, and the third ion is a P-type ion.

15. A method for operating an electrostatic discharge protection structure, characterized in that, include: A device to be protected is provided, the device to be protected including a gate structure; Provide an electrostatic discharge protection structure as described in any one of claims 1 to 7; When testing the device to be protected, a test voltage is applied to the gate structure and a blocking voltage is applied to the metal plate to perform electrical testing on the device to be protected. The blocking voltage is greater than the test voltage. When the device to be protected is an NMOS transistor, and the charge accumulated in the gate structure is positive, the first ion is an N-type ion, the second ion is a P-type ion, and the third ion is an N-type ion; or... When the device to be protected is a PMOS transistor, and the charge accumulated in the gate structure is positive, the first ion is an N-type ion, the second ion is a P-type ion, and the third ion is an N-type ion; or... When the device to be protected is an NMOS transistor, and the charge accumulated in the gate structure is negative, the first ion is a P-type ion, the second ion is an N-type ion, and the third ion is a P-type ion; or... When the device to be protected is a PMOS transistor and the charge accumulated in the gate structure is negative, the first ion is a P-type ion, the second ion is an N-type ion, and the third ion is a P-type ion.

Images