Electrostatic discharge protection structure and method of operation thereof

Abstract

An electrostatic discharge protection structure and a working method thereof, wherein the structure comprises: a device to be protected, comprising a first gate structure; a protection structure, comprising a substrate with a channel; a second gate structure on the substrate; a first source-drain doped region and a second source-drain doped region in the channel region, the first source-drain doped region being electrically connected with the first gate structure, and the second source-drain doped region being electrically connected with the substrate; and a metal plate electrically connected with the second gate structure. Since the electric charge accumulated on the second gate structure is used to open the channel region, the electric charge accumulated on the first gate structure can flow from the first source-drain doped region to the substrate through the second source-drain doped region, so that the accumulated electric charge is quickly discharged. When the device to be protected is tested, the off voltage of the channel region is applied to the metal plate, thereby preventing the device to be protected from leaking during the test and ensuring the authenticity and accuracy of the test of the device to be protected.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to an electrostatic discharge protection structure and its working method. Background Technology

[0002] Integrated circuits are susceptible to damage from static electricity. Protection circuits are typically designed at the input / output terminals or power supply protection devices to prevent internal circuits from being damaged by static electricity.

[0003] In existing integrated circuit designs, electrostatic discharge (ESD) protection structures are often used to reduce electrostatic damage.

[0004] However, existing electrostatic discharge protection structures still have many problems. Summary of the Invention

[0005] The technical problem solved by this invention is to provide an electrostatic discharge protection structure and its working method to improve the electrostatic discharge effect.

[0006] To address the aforementioned problems, this invention provides an electrostatic discharge protection structure, comprising: a device to be protected, the device including a first gate structure; a protection structure, the protection structure including: a substrate having a plurality of parallel channel regions; a second gate structure located on the substrate, the second gate structure spanning the channel regions and covering a portion of the surface of the channel regions; a first source / drain doped region and a second source / drain doped region located within the channel regions, the first source / drain doped region and the second source / drain doped region being located on opposite sides of the second gate structure, the first source / drain doped region being electrically connected to the first gate structure, the second source / drain doped region being electrically connected to the substrate, and the charge accumulated on the second gate structure being used to turn on the channel regions; and a metal plate electrically connected to the second gate structure.

[0007] Optionally, the device to be protected includes an NMOS transistor or a PMOS transistor.

[0008] Optionally, the first source / drain doped region and the second source / drain doped region contain source / drain ions, which include N-type ions or P-type ions.

[0009] Optionally, when the charge accumulated on the second gate structure is positive, the source / drain ions are N-type ions.

[0010] Optionally, when the charge accumulated on the second gate structure is negative, the source / drain ions are P-type ions.

[0011] Optionally, the number of the channel areas is 1 to 50.

[0012] Optionally, the material of the metal plate includes aluminum.

[0013] Accordingly, the present invention also provides a method for operating an electrostatic discharge protection structure, comprising: providing an electrostatic discharge protection structure as described above; and when a test voltage is applied to the first gate structure to perform electrical detection of the device to be protected, applying a turn-off voltage of the channel region to the metal plate to turn off the channel region.

[0014] Optionally, the device to be protected includes an NMOS transistor or a PMOS transistor.

[0015] Optionally, the first source / drain doped region and the second source / drain doped region contain source / drain ions, which include N-type ions or P-type ions.

[0016] Optionally, when the charge accumulated on the second gate structure is positive, the source / drain ions are N-type ions.

[0017] Optionally, when the charge accumulated on the second gate structure is negative, the source / drain ions are P-type ions.

[0018] Optionally, when the source / drain ions are N-type ions, the turn-off voltage is a negative voltage.

[0019] Optionally, when the source / drain ions are P-type ions, the turn-off voltage is a positive voltage.

[0020] Optionally, the number of the channel areas is 1 to 50.

[0021] Optionally, the material of the metal plate includes aluminum.

[0022] Compared with the prior art, the technical solution of the present invention has the following advantages: In the electrostatic discharge protection structure of this invention, a transistor structure is formed by the channel region, the first source / drain doped region, the second source / drain doped region, and the second gate structure. The transistor has a relatively high turn-on voltage, and the channel region can be turned on using the charge accumulated on the second gate structure. At this time, the charge (including positive and negative charges) accumulated on the first gate structure can flow from the first source / drain doped region to the second source / drain doped region. The second source / drain doped region is electrically connected to the substrate, thus allowing the charge accumulated on the first gate structure to be quickly discharged to the substrate, providing a protective function.

[0023] In the working method of the electrostatic discharge protection structure of the present invention, a transistor structure is formed by the channel region, the first source / drain doped region, the second source / drain doped region, and the second gate structure. The transistor has a relatively high turn-on voltage, and the channel region can be turned on using the charge accumulated on the second gate structure. At this time, the charge (including positive and negative charges) accumulated on the first gate structure can flow from the first source / drain doped region to the second source / drain doped region. The second source / drain doped region is electrically connected to the substrate, so the charge accumulated on the first gate structure can be quickly discharged to the substrate, thus playing a protective role. When testing the device to be protected, by applying a turn-off voltage to the channel region on the metal plate, the channel region is turned off, thereby preventing leakage from the protection structure during testing and ensuring the accuracy of the test results. Attached Figure Description

[0024] Figure 1 This is a schematic diagram showing the connection between the reverse bias diode protection circuit and the NMOS transistor; Figure 2 This is a schematic diagram showing the connection between the forward bias diode protection circuit and the NMOS transistor; Figure 3 This is a schematic diagram showing the connection between a gate-grounded N-type field-effect transistor protection circuit and an NMOS transistor; Figure 4 This is a schematic diagram of the electrostatic discharge protection structure according to an embodiment of the present invention. Detailed Implementation

[0025] As described in the background section, existing electrostatic discharge protection structures still have many problems. These will be explained in detail below.

[0026] Existing electrostatic discharge protection structures include: reverse biased diode protection circuit, forward biased diode protection circuit, and gate-grounded N-type field-effect transistor (GGNMOS) protection circuit.

[0027] Please refer to Figure 1Taking an NMOS transistor as the device to be protected, and assuming that the gate structure of the NMOS transistor accumulates positive charge, a reverse-biased diode protection circuit is typically used as an electrostatic discharge (ESD) protection structure for NMOS transistors. When the voltage generated by the accumulated charge exceeds the reverse-bias breakdown voltage of the PN junction, the accumulated charge is discharged, providing protection. However, the current density per unit area is relatively small, and it cannot discharge quickly and effectively. Moreover, for NMOS transistors with low threshold voltages, if the PN junction is not reverse-biased, it cannot provide protection. If used to protect PMOS transistors, a negative voltage cannot be applied during testing.

[0028] Please refer to Figure 2 Taking an NMOS transistor as the device to be protected, and assuming that the gate structure of the NMOS transistor accumulates positive charge, the forward and reverse bias diode protection circuit is typically used as the electrostatic discharge protection structure for PMOS transistors. As long as there is charge accumulated on the gate structure, it can be quickly discharged through the forward and reverse bias diode protection circuit. If a negative voltage cannot be applied to the PMOS transistor during testing, it can proceed normally as long as the negative voltage does not reverse-break down the PN junction. However, this cannot meet the testing requirements for a positive gate voltage on an NMOS transistor.

[0029] Please refer to Figure 3 Taking an NMOS transistor as the protected device, and assuming the gate structure of the NMOS transistor accumulates positive charge, the working mechanism of a gate-grounded N-type field-effect transistor protection circuit is as follows: Since the power dissipation on the MOS transistor is the product of the current and the voltage drop, under a certain ESD current, if the voltage drop on the MOS transistor can be reduced, the junction temperature of the MOS transistor can be reduced, thus achieving the purpose of protecting the MOS transistor. The gate-grounded N-type field-effect transistor protection circuit, as an ESD device, relies on a parasitic NPN BJT to discharge ESD current in the forward direction. The NPN consists of the N+ active region of the drain, a P-type substrate, and the N+ active region of the source. The reverse path for discharging ESD current consists of a PN diode and a gate-source connected NMOS diode. The PN diode consists of a P-type substrate and the N+ active region. In a full-chip ESD network, when an ESD event occurs, the gate-grounded N-type field-effect transistor protection circuit may conduct in both the forward and reverse directions, determined by the potential ESD path. The ESD current will always flow towards the low-resistance path. Therefore, the forward and reverse ESD performance of the gate-grounded N-type field-effect transistor (BJT) protection circuit must be considered during the design process to ensure the reliability of the integrated circuit. The gate-grounded N-type field-effect transistor protection circuit, as a BJT, operates on a breakdown device mechanism, relying on avalanche breakdown between the drain and substrate to form a low-resistance path to discharge ESD current. Compared to PN junctions, the gate-grounded N-type field-effect transistor protection circuit has the advantage of high on-state current density and a lower threshold voltage V0. t Lower, but for the threshold voltage Vt Even with lower-end MOS transistors, their protection capabilities remain insufficient.

[0030] Based on this, the present invention provides an electrostatic discharge protection structure and its operating method. Since the charge accumulated on the second gate structure is used to open the channel region, the charge accumulated on the first gate structure can flow from the first source / drain doped region to the second source / drain doped region. The second source / drain doped region is electrically connected to the substrate, thus allowing the charge accumulated on the first gate structure to be quickly discharged to the substrate, providing protection. During testing of the device to be protected, a turn-off voltage is applied to the channel region on the metal plate to close the channel region, thereby preventing leakage from the protection structure during testing and ensuring the accuracy of the testing of the device to be protected.

[0031] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0032] Figure 4 This is a schematic diagram of the electrostatic discharge protection structure according to an embodiment of the present invention.

[0033] Please refer to Figure 4 An electrostatic discharge protection structure includes: a device to be protected 100, the device to be protected 100 including a first gate structure 101; a protection structure 200, the protection structure 200 including: a substrate 201, the substrate 201 having a plurality of parallel channel regions 202; a second gate structure 203 located on the substrate 201, the second gate structure 203 spanning the channel regions 202 and covering a portion of the surface of the channel regions 202; a first source / drain doped region 204 and a second source / drain doped region 205 located within the channel regions 202, the first source / drain doped region 204 and the second source / drain doped region 205 being located on opposite sides of the second gate structure 203, the first source / drain doped region 204 being electrically connected to the first gate structure 205, the second source / drain doped region 205 being electrically connected to the substrate 201, and the charge accumulated on the second gate structure 203 being used to turn on the channel regions 202; and a metal plate 206 electrically connected to the second gate structure 203.

[0034] In this embodiment, a transistor structure is formed by the channel region 202, the first source / drain doped region 204, the second source / drain doped region 205, and the second gate structure 203. The transistor has a relatively high turn-on voltage, and the channel region 202 can be turned on using the charge accumulated on the second gate structure 203. At this time, the charge (including positive and negative charges) accumulated on the first gate structure 101 can flow from the first source / drain doped region 204 to the second source / drain doped region 205. The second source / drain doped region 205 is electrically connected to the substrate 201, thus it can quickly conduct the charge accumulated on the first gate structure 101 to the substrate 201, providing a protective function.

[0035] In this embodiment, the device to be protected 100 is an NMOS transistor; in other embodiments, the device to be protected may also be a PMOS transistor.

[0036] In this embodiment, the substrate 201 is made of silicon; in other embodiments, the substrate may also be made of single-crystal germanium, silicon germanium, silicon carbide, silicon-on-insulator (SOI), germanium-on-insulator (GOI); or the substrate may be made of other materials, such as gallium arsenide or other group III-V compounds.

[0037] The substrate 201 contains doped ions, which are N-type or P-type ions.

[0038] In this embodiment, the doped ions in the substrate 201 are P-type ions.

[0039] In this embodiment, the charge accumulated on the second gate structure 203 is positive charge. The first source / drain doped region 204 and the second source / drain doped region 205 contain source / drain ions, and these source / drain ions are N-type ions. Due to the positive charge accumulated on the second gate structure 203, the voltage on the second gate structure 203 is higher than the voltage of the substrate 201. When the voltage of the second gate structure 203 is higher than the voltage of the substrate 201, it is used to open the N-type channel. Therefore, in order to ensure that the charge accumulated on the second gate structure 203 can open the channel region 202, the source / drain ions need to be N-type ions.

[0040] In other embodiments, when the charge accumulated on the second gate structure is negative, source / drain ions are present in both the first and second source / drain doped regions, and these source / drain ions are P-type ions. Due to the negative charge accumulated on the second gate structure, the voltage on the second gate structure is lower than the voltage of the substrate. When the voltage of the second gate structure is lower than the voltage of the substrate, it is used to open the P-type channel. Therefore, in order to ensure that the charge accumulated on the second gate structure can open the channel region, the source / drain ions need to be P-type ions.

[0041] In this embodiment, the number of channel regions 202 is 1 to 50.

[0042] In this embodiment, the protective structure can allow a current I to pass through. protect =W×Idsat×finger; where W is the width of the second gate structure, which is 0.1μm to 100μm; Idsat is the current allowed to pass through a single transistor; and finger is the number of channel regions.

[0043] In other embodiments, if the chip size is limited and a greater number of channel regions cannot be formed, the allowable current Idsat of a single transistor can be increased by implanting ions of the opposite ion electrical type to the source / drain ions into the channel regions. The implantation energy is 30 keV to 200 keV, and the implantation dose is 1E11 atoms / cm. 3 ~5E15 atoms / cm 3 .

[0044] It should be noted that in this embodiment, the protective structure 200 is formed simultaneously according to the global process in the semiconductor manufacturing process, and the formation of the protective structure 200 does not require the additional fabrication of a new photomask.

[0045] In this embodiment, the metal plate 206 is made of aluminum.

[0046] It should be noted that, in this embodiment, the electrical connection between the metal plate 206 and the second gate structure 203 is achieved through several conductive layers and several conductive plugs (not shown) formed in a conventional semiconductor manufacturing process.

[0047] Accordingly, this embodiment of the invention also provides a method for operating an electrostatic discharge protection structure, including: providing an electrostatic discharge protection structure as described above; when a test voltage is applied to the first gate structure 101 to perform electrical detection of the device to be protected 100, applying a turn-off voltage of the channel region 202 to the metal plate 206 to turn off the channel region 202.

[0048] In this embodiment, a transistor structure is formed by the channel region 202, the first source / drain doped region 204, the second source / drain doped region 205, and the second gate structure 203. The transistor has a relatively high turn-on voltage, and the channel region 202 can be turned on using the charge accumulated on the second gate structure 203. At this time, the charge (including positive and negative charges) accumulated on the first gate structure 101 can flow from the first source / drain doped region 204 to the second source / drain doped region 205. The second source / drain doped region 205 is electrically connected to the substrate 201, so the charge accumulated on the first gate structure 101 can be quickly discharged to the substrate 201, thus providing protection. When testing the device to be protected 100, a turn-off voltage is applied to the metal plate 206 to turn off the channel region 202, thereby preventing leakage from the protection structure 200 during testing and ensuring the accuracy of the test results for the device to be protected 100.

[0049] In this embodiment, the device to be protected 100 is an NMOS transistor; in other embodiments, the device to be protected may also be a PMOS transistor.

[0050] In this embodiment, the substrate 201 is made of silicon; in other embodiments, the substrate may also be made of single-crystal germanium, silicon germanium, silicon carbide, silicon-on-insulator (SOI), germanium-on-insulator (GOI); or the substrate may be made of other materials, such as gallium arsenide or other group III-V compounds.

[0051] The substrate 201 contains doped ions, which are N-type or P-type ions.

[0052] In this embodiment, the doped ions in the substrate 201 are P-type ions.

[0053] In this embodiment, the charge accumulated on the second gate structure 203 is positive charge. The first source / drain doped region 204 and the second source / drain doped region 205 contain source / drain ions, and these source / drain ions are N-type ions. Due to the positive charge accumulated on the second gate structure 203, the voltage on the second gate structure 203 is higher than the voltage of the substrate 201. When the voltage of the second gate structure 203 is higher than the voltage of the substrate 201, it is used to open the N-type channel. Therefore, in order to ensure that the charge accumulated on the second gate structure 203 can open the channel region 202, the source / drain ions need to be N-type ions.

[0054] In other embodiments, when the charge accumulated on the second gate structure is negative, source / drain ions are present in both the first and second source / drain doped regions, and these source / drain ions are P-type ions. Due to the negative charge accumulated on the second gate structure, the voltage on the second gate structure is lower than the voltage of the substrate. When the voltage of the second gate structure is lower than the voltage of the substrate, it is used to open the P-type channel. Therefore, in order to ensure that the charge accumulated on the second gate structure can open the channel region, the source / drain ions need to be P-type ions.

[0055] In this embodiment, the number of channel regions 202 is 1 to 50.

[0056] In this embodiment, since the source and drain ions are N-type ions, the turn-off voltage is a negative voltage.

[0057] In other embodiments, when the source / drain ions are P-type ions, the turn-off voltage is a positive voltage.

[0058] It should be noted that in this embodiment, the protective structure 200 is formed simultaneously according to the global process in the semiconductor manufacturing process, and the formation of the protective structure 200 does not require the additional fabrication of a new photomask.

[0059] In this embodiment, the metal plate 206 is made of aluminum.

[0060] It should be noted that, in this embodiment, the electrical connection between the metal plate 206 and the second gate structure 203 is achieved through several conductive layers and several conductive plugs (not shown) formed in a conventional semiconductor manufacturing process.

[0061] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. An electrostatic discharge protection structure, characterized in that, include: The device to be protected includes a first gate structure; A protective structure includes: a substrate having a plurality of parallel channel regions; a second gate structure located on the substrate, the second gate structure spanning the channel regions and covering a portion of the surface of the channel regions; a first source / drain doped region and a second source / drain doped region located within the channel regions, the first source / drain doped region and the second source / drain doped region being located on opposite sides of the second gate structure, the first source / drain doped region being electrically connected to the first gate structure, the second source / drain doped region being electrically connected to the substrate, and the charge accumulated on the second gate structure being used to turn on the channel regions; A metal plate electrically connected to the second gate structure, the metal plate being used to turn off the channel region by applying a turn-off voltage to the metal plate during testing of the device to be protected, thereby preventing leakage of current from the protection structure during testing of the device to be protected.

2. The electrostatic discharge protection structure as described in claim 1, characterized in that, The device to be protected includes an NMOS transistor or a PMOS transistor.

3. The electrostatic discharge protection structure as described in claim 1, characterized in that, The first and second source / drain doped regions contain source / drain ions, which include N-type ions or P-type ions.

4. The electrostatic discharge protection structure as described in claim 3, characterized in that, When the charge accumulated on the second gate structure is positive, the source / drain ions are N-type ions.

5. The electrostatic discharge protection structure as described in claim 3, characterized in that, When the second gate structure accumulates negative charge, the source / drain ions are P-type ions.

6. The electrostatic discharge protection structure as described in claim 1, characterized in that, The number of the channel zones is 1 to 50.

7. The electrostatic discharge protection structure as described in claim 1, characterized in that, The material of the metal plate includes aluminum.

8. A method for operating an electrostatic discharge protection structure, characterized in that, include: Provide an electrostatic discharge protection structure as described in any one of claims 1 to 7; When a test voltage is applied to the first gate structure to perform electrical testing on the device to be protected, a turn-off voltage is applied to the channel region on the metal plate to turn off the channel region.

9. The working method of the electrostatic discharge protection structure as described in claim 8, characterized in that, The device to be protected includes an NMOS transistor or a PMOS transistor.

10. The method of operating the electrostatic discharge protection structure as described in claim 9, characterized in that, The first and second source / drain doped regions contain source / drain ions, which include N-type ions or P-type ions.

11. The method of operating the electrostatic discharge protection structure as described in claim 10, characterized in that, When the charge accumulated on the second gate structure is positive, the source / drain ions are N-type ions.

12. The method of operating the electrostatic discharge protection structure as described in claim 10, characterized in that, When the second gate structure accumulates negative charge, the source / drain ions are P-type ions.

13. The method of operating the electrostatic discharge protection structure as described in claim 10, characterized in that, When the source / drain ions are N-type ions, the turn-off voltage is a negative voltage.

14. The method of operating the electrostatic discharge protection structure as described in claim 10, characterized in that, When the source / drain ions are P-type ions, the turn-off voltage is a positive voltage.

15. The method of operating the electrostatic discharge protection structure as described in claim 8, characterized in that, The number of the channel zones is 1 to 50.

16. The method of operating the electrostatic discharge protection structure as described in claim 8, characterized in that, The material of the metal plate includes aluminum.

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