Programmable logic array with reliable timing

Abstract

The present disclosure relates to programmable logic arrays with reliable timing. An integrated circuit includes a programmable logic array. The programmable logic array includes a plurality of logic elements arranged in rows and columns. Each logic element includes a direct output and a synchronous output. The direct output of each logic element is coupled to all other logic elements of a higher order, but not to logic elements of a lower order.

Description

Technical Field

[0001] This disclosure relates to integrated circuits, and more specifically, to integrated circuits including programmable logic arrays (PLAs). Background Technology

[0002] Many integrated circuits include programmable logic arrays (PLAs). A PLA can include programmable logic elements interconnected with each other and connected to the PLA's input / output signals via programmable interconnects. The interconnects can include multiplexers controlled by configuration registers. Logic elements can be programmed to combine one or more of their inputs to generate a single output whose state is a Boolean function of the input states. The output state can be captured or not captured by flip-flops or latches.

[0003] In synchronous systems, specifically in systems comprising combinational logic paths connecting the output of one flip-flop to the input of another, where both flip-flops are timed by the same clock signal, it is desirable that the propagation delay of the logic path be less than the period of the clock signal. This allows for proper setup time at the input of the destination flip-flop. Without considering this constraint, the output state of the destination flip-flop could be unpredictable.

[0004] PLA programmers often struggle to ensure safe timing relationships between triggers. This is a consequence of the unpredictable combinational path delays inherent in programmable logic and interconnects. In many cases, PLA programmers can become frustrated if the PLA fails to perform programmed functions due to timing delays.

[0005] All topics discussed in the Background section are not necessarily prior art and should not be considered prior art merely as a result of their discussion in the Background section. Along these lines, the identification of any problems in the prior art discussed in the Background section or related to those topics should not be considered prior art unless explicitly stated otherwise. Instead, the discussion of any topic in the Background section should be considered as part of the inventor's method for addressing a particular problem, which itself may be inventive. Summary of the Invention

[0006] Embodiments of this disclosure provide a PLA that reduces timing errors by introducing constraints at the hardware level of the PLA, which ensure that any permissible configuration of the PLA will result in proper timing. Unlike logic elements that allow programmers to connect the PLA in any conceivable way, a PLA according to the principles of this disclosure includes only connection paths that result in proper timing. Connection paths that could lead to timing errors are not available at the hardware level.

[0007] In one embodiment, each logic element includes a direct output and a synchronous output. The synchronous output is synchronized with the PLA clock signal. The direct output is not synchronized with the PLA clock signal. Because the synchronous output is synchronized with the PLA clock signal, timing or set-and-hold errors typically do not occur when the synchronous output is passed to the input of another logic element. However, because the direct output is not synchronized with the PLA clock signal, timing errors may occur in certain situations. Therefore, the PLA implements a constraint to ensure that the direct output of a logic element cannot be passed to the input of certain logic elements that are more likely to cause timing errors.

[0008] In one embodiment, the PLA includes logic elements arranged in rows and columns. Each row extends between the inputs and outputs of the PLA. The column rank corresponds to its proximity to the input, with lower ranks being closer to the input. The PLA does not include signal paths that connect the direct outputs of logic elements in one column to the inputs of logic elements in lower ranks. This ensures that setup time between logic elements is met.

[0009] The constraints on direct outputs are implemented at the hardware level. Specifically, signal paths cannot be used to directly connect the direct outputs of logic elements to the inputs of lower-order logic elements. When the PLA is programmed by the user, direct output connections to lower-order logic elements are directly unavailable. The remaining possible programming schemes for the PLA will not result in timing errors. Therefore, embodiments of this disclosure produce a PLA that significantly reduces the likelihood of malfunctioning or non-functional layouts. Attached Figure Description

[0010] The accompanying drawings will now be referred to by way of example only. In the drawings, the same reference numerals denote similar elements or actions. However, in some drawings, different reference numerals may be used to indicate the same or similar elements. The dimensions and relative positions of elements in the drawings need not be drawn to scale. For example, the shapes and angles of various elements are not necessarily drawn to scale, and some of these elements may be enlarged and positioned to improve drawing clarity.

[0011] Figure 1 This is a block diagram of an integrated circuit including a PLA according to one embodiment.

[0012] Figure 2 This is a schematic diagram of a block of a PLA according to one embodiment.

[0013] Figure 3 This is a schematic diagram of the logic elements of a PLA according to one embodiment.

[0014] Figure 4 This is a schematic diagram of a PLA according to one embodiment.

[0015] Figure 5 This is a block diagram of multiple blocks of a PLA according to one embodiment.

[0016] Figure 6 This is a block diagram of multiple blocks of a PLA according to one embodiment.

[0017] Figure 7 This is a flowchart of a method for forming a PLA according to one embodiment.

[0018] Figure 8 This is a flowchart of a method for forming a PLA according to one embodiment. Detailed Implementation

[0019] In the following description, certain specific details are set forth in order to provide a thorough understanding of the various disclosed embodiments. However, those skilled in the art will recognize that the embodiments may be practiced without one or more of these specific details or with other methods, components, materials, etc. In other instances, well-known systems, components, and circuits associated with integrated circuits have not been shown or described in detail to avoid unnecessarily obscuring the description of the embodiments.

[0020] Unless the context otherwise requires, throughout the specification and the following claims, the word “comprising” and its variations, such as “including” and “comprising”, shall be interpreted in an open-ended, inclusive sense, meaning “including but not limited to”. Furthermore, the terms “first,” “second,” and similar sequence indicators shall be interpreted as interchangeable unless the context clearly indicates otherwise.

[0021] Throughout this specification, references to "an embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment. Therefore, the phrases "in one embodiment" or "in an embodiment" appearing throughout this specification do not necessarily refer to the same embodiment. Furthermore, particular features, structures, or characteristics may be combined in one or more embodiments in any suitable manner.

[0022] As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” include plural indicators unless otherwise clearly indicated. It should also be noted that the term “or” is generally used in its broadest sense, meaning “and / or,” unless otherwise clearly indicated.

[0023] Figure 1This is a block diagram of an integrated circuit 100 according to one embodiment. The integrated circuit 100 includes a PLA 102, a clock generator 104, and a controller 106. The PLA 102 includes a plurality of logic elements 108, a plurality of direct interconnects 110, and a plurality of synchronous interconnects 112. As will be described in more detail below, the components of the PLA 102 cooperate to ensure that timing errors do not occur after the PLA 102 is programmed.

[0024] PLA 102 includes an input side and an output side. The input side can receive one or more input signals from sources outside the PLA 102. The output side can provide one or more signals after processing the input signals according to the PLA 102's programming logic. As used herein, "input side" and "output side" correspond to the logical sides of the PLA 102 and are not necessarily physical locations. The input side can refer to the set of input signals of the PLA 102, and the output side can refer to the set of output signals of the PLA 102. The actual signals can be located anywhere in the physical implementation of the PLA.

[0025] Each logic element 108 includes multiple inputs 111, multiple direct outputs 107, and multiple synchronous outputs 109. The logic elements 108 can be arranged in rows and columns. The arrangement of the logic elements 108 may refer to a conceptual or logical arrangement rather than a physical arrangement, because the physical layout of integrated circuits can be highly complex, and the physical location or physical proximity of two circuit elements may not perfectly align with their positions in the circuit diagram, as the metal interconnects connecting the two circuit elements may involve complex wiring. Each row of logic elements 108 may be referred to as a block. Each column of logic elements 108 includes a rank. The rank corresponds to the proximity of the logic element to the input side of PLA 102. As used herein, the lower the rank of a column, the closer the column is to the input side of PLA 102. However, other ranking schemes may be used without departing from the scope of this disclosure.

[0026] As used herein, the terms "proximity," "distance," and "closeness" to the input side of a logic element can correspond to proximity in terms of logic flow or circuit flow, rather than absolute physical proximity. This is because, as stated above, the physical layout of integrated circuits can be highly complex, and the metal interconnect layout (including metal lines and conductive vias) can cause two circuit elements that are adjacent in terms of logic flow or circuit flow to be relatively far apart in terms of physical location. Similarly, two circuit elements that are physically close to each other may be relatively far apart in terms of logic flow or circuit flow. As used herein, "upstream" or "downstream" relationships refer to relationships according to logic flow or circuit flow.

[0027] Each logic element 108 includes multiple inputs 111. Each input can receive: one or more input signals from the inputs of PLA 102, a direct output signal from the direct output 107 of the logic element 108 of PLA 102, and a synchronous output signal from the synchronous output 109 of the logic element 108 of PLA 102.

[0028] Synchronous interconnect 112 is a signal line that electrically connects the synchronous output 109 of logic element 108 to the input 111 of logic element 108. In one embodiment, synchronous interconnect 112 may enable the synchronous output of a logic element to be connected to the input 111 of any logic element 108 (including low-order logic elements). Synchronous interconnect 112 may include conductive vias, metal lines, and other metal interconnects formed in the layers of integrated circuit 100. In some cases, synchronous interconnect 112 may include one or more switches capable of selectively connecting and disconnecting synchronous interconnect 112.

[0029] Direct interconnect 110 is a signal line that electrically connects the direct output 107 of logic element 108 to the input 111 of logic element 108. In one embodiment, direct interconnect 110 is constrained in a manner that does not constrain synchronous interconnect 112. While synchronous interconnect 112 allows synchronous outputs of logic element 108 to be connected to the inputs of any other logic element in or within a designated block or portion of PLA 102, direct interconnect 110 does not allow direct outputs 107 to be connected to the inputs 111 of some logic element 108.

[0030] In one embodiment, the direct interconnect 110 does not enable the direct output 107 of logic element 108 to be connected to the input 111 of a lower-ordered logic element 108. This can be achieved by physically forming the direct interconnect 110 such that there is no physical direct interconnect 110 available for connecting the direct output 107 of logic element 108 to the input 111 of a lower-ordered logic element 108.

[0031] The constraints on the direct interconnect 110 help ensure that there are no timing errors when processing signals within the PLA 102. As a result, the PLA programmer can be confident that any permissible programming configuration of the PLA 102 will be free of timing errors. This can be highly beneficial, as the PLA 102 will function correctly after programming.

[0032] Clock generator 104 generates a clock signal CLK for PLA 102. The clock signal CLK can be passed to logic element 108. Synchronization output 109 can be synchronized with the clock signal CLK provided by clock generator 104. Although clock generator 104 is shown as external to PLA 102, in some cases, clock generator 104 can be part of PLA 102.

[0033] Controller 106 can be used to program PLA 102. Controller 106 can receive programming inputs for configuring the logic elements 108 of PLA 102. Controller 106 enables the programmer of PLA 102 to specifically program each logic element 108 in a desired manner. Programming PLA 102 may include writing specific data values ​​into the memory 108 of the logic elements. The values ​​in memory 108 determine that the output provided by the logic element 108 is based in part on the inputs 111 of the logic element 108. Programming PLA 102 may also include determining which inputs 111 will be used to generate the output. The formation of the direct interconnects 110 as described above ensures that the direct outputs 107 of the logic elements will not be used as inputs 111 of lower-ordered logic elements 108.

[0034] Controller 106 provides an interface through which a user can program PLA 102. In some cases, the user can program PLA 102 via an interface provided by another circuit or system electrically connected to integrated circuit 100. External circuitry or systems enable the user to program PLA 102 within constraints implemented by controller 106. Controller 106 programs each logic element 108 according to programs and commands received via the interface and according to constraints implemented by direct interconnect 110.

[0035] Figure 2 This is a block diagram of a portion of PLA 102 according to one embodiment. More specifically, Figure 2 This is a block diagram of block 105 of PLA 102. Block 105 corresponds to a row of logic elements 108 in PLA 102. In practice, PLA 102 may include multiple parallel blocks 105. In this way, PLA 102 can be arranged as rows and columns of logic elements 108. To simplify the explanation of some principles of this disclosure, Figure 2 Only a single block 105 is shown in the image.

[0036] Block 102 includes an input side and an output side. The input side receives input from sources outside the PLA 102. Figure 2A single input signal is shown on the input side. However, in reality, several input signals or bit values ​​may be received on the input side of PLA 105. Multiple data signals are output from PLA 102 on the output side. The data values ​​provided on the output side are based on the data values ​​received on the input side and the programming of each logic element 108 of PLA 102.

[0037] Each logic element 108 in block 105 has a sequence between 1 and 4. The logic element 108 closest to the input side has sequence 1. The next logic element 108 closest to the input side has sequence 2. The next logic element 108 closest to the input side has sequence 3. The logic element 108 furthest from the input side has sequence 4. Therefore, in the scheme shown here, the lower sequence corresponds to being closer to the input side. In the example where there are multiple parallel blocks 105, each sequence will correspond to a column of logic elements 108.

[0038] Each logic element 108 includes multiple inputs 111, direct outputs 107, and synchronous outputs 109. Internal circuitry within the logic element 108 determines which input signals will be used to generate the output. Typically, the direct outputs 107 and synchronous outputs 109 have the same value, except that the synchronous output 109 is synchronized with the clock signal CLK.

[0039] The synchronous output 109 of each logic element 108 is coupled to a synchronous interconnect 112. As used herein, "synchronous interconnect" corresponds to a conductive interconnect connected to the synchronous output 109 of the logic element 108. The synchronous interconnect 112 of each logic element 108 is provided to the input of each logic element 108. For simplicity, Figure 2 It is shown that all synchronous interconnects 112 are joined to a single bus 113. Thus, line 113 corresponds to multiple separate synchronous interconnects 112, each synchronous interconnect 112 being individually connected to the input of each logic element 108, including the same logic element from which the synchronous interconnect 112 receives a direct output.

[0040] The direct output 107 of logic element 108 in sequence 1 is connected to the input of each logic element 108 in sequences 2, 3, and 4. The direct output 107 of logic element 108 in sequence 2 is connected to the input of each logic element in sequences 3 and 4. The direct output 107 of logic element 108 in sequence 3 is connected to the input of logic element 108 in sequence 4. The direct output 107 of logic element 108 in sequence 3 is not connected to the input of logic elements in sequences 1, 2, and 3. The direct output 107 of logic element 108 in sequence 4 is not connected to the input of any logic element 108 in block 105.

[0041] Direct interconnect 110 provides a connection to the aforementioned direct output 107. Each direct interconnect 110 is shown separately, in contrast to synchronous interconnect 112, to illustrate the principle that the direct output of logic element 108 is only connected to the input of the higher-order logic element 108.

[0042] Figure 3 This is a schematic diagram of logic element 108 of PLA 102 according to one embodiment. Figure 3 Logic element 108 is available for use Figure 1 - Figure 2 The logic element 108 and an embodiment of the logic element 108 in the following figures. Although Figure 3 A specific embodiment of logic element 108 is shown, but other configurations of logic element 108 may be utilized without departing from the scope of this disclosure.

[0043] Logic element 108 includes a multiplexer 114, a memory 116, and flip-flops 118. Multiplexer 114 corresponds to the input side of logic element 108. Specifically, multiplexer 114 may have multiple inputs 111. Inputs 111 may include synchronous outputs of all logic elements 108 in the block. Inputs 111 may include direct outputs of all low-order logic elements. Inputs 111 may include one or more inputs of PLA 102. In practice, there may be a large number of inputs.

[0044] Multiplexer 114 provides multiple outputs. Figure 3 In this example, multiplexer 114 has four outputs. In this case, a control signal (not shown) is provided to multiplexer 114 to determine which of the inputs 111 will be provided at the output of multiplexer 114. Because multiplexer 114 does not accept direct outputs of logic elements 108 in a higher or equal order, setup and hold errors or timing errors can be avoided in PLA 102. Multiplexer 114 can accept other numbers of inputs and provide... Figure 3 Other numbers of outputs shown do not depart from the scope of this disclosure.

[0045] In one embodiment, memory 116 is a register with 16 data values ​​d1-d16. Each data value can be a binary value of 0 or 1. The register outputs one of the data values ​​d1-d16 based on the combination of data values ​​received from multiplexer 114. In this case, the output of multiplexer 114 effectively corresponds to the address of register 116. If the multiplexer provides the value 0000 on all four outputs, register 116 outputs the value stored in d1. If the multiplexer provides the value 1111 on all four outputs, register 116 outputs the value stored in d16. Therefore, each four-bit value received from multiplexer 114 corresponds to one of the 16 data storage locations in register 116. Although Figure 3 Note that memory 116 is a register, but other types of memory may be used for logic element 108 without departing from the scope of this disclosure.

[0046] Programming logic element 108 includes selecting a value for each of the data values ​​d1-d16 and writing the selected data value to memory 116. Programming logic element 108 may also include selecting the value of a control signal provided to multiplexer 114. The value of the control signal determines which of the inputs 111 will be provided at the output of multiplexer 114.

[0047] Logic element 108 includes flip-flop 118. Flip-flop 118 receives the output of memory 116 at its data input. The data output of flip-flop 118 corresponds to the synchronous output 109 of logic element 108.

[0048] Logic element 108 also includes an AND gate 120. AND gate 120 includes a first input that receives an enable signal En and a second input that receives a clock signal CLK from PLA 102. If the enable signal is high, the clock signal CLK is passed to the clock input of flip-flop 118. Therefore, on the rising edge of the clock signal at clock input 118, the value data present at the data input is passed to the data output of flip-flop 118. Thus, the output of flip-flop 118 is synchronized with the clock signal CLK of PLA 102.

[0049] Logic element 108 also provides a direct output 107. Direct output 107 corresponds to the output of memory 116 and is therefore not passed through flip-flop 118. Direct output 107 of logic element 108 is not synchronized with clock signal CLK.

[0050] Figure 4 This is a schematic diagram of PLA 102 according to some embodiments. Figure 4 The PLA 102 comprises four blocks 105, A-D. Each block corresponds to a row of logic elements 108. Figure 4In the example, each block includes four logic elements 108. However, in practice, each block can have more than [a certain number of elements]. Figure 4 The diagram shows fewer or more logic elements 108.

[0051] Figure 4 The PLA 102 includes four columns 1-4 of logic elements 108. (Assigned to...) Figure 4 The numbers in each column correspond to the order in the column. Therefore, the logic element 108 of column 1 has order 1. The logic element 108 of column 2 has order 2. The logic element 108 of column 3 has order 3. The logic element 108 of column 4 has order 4.

[0052] Each logic element 108 can be substantially related to Figure 3 The logic element 108 shown is the same. In particular, each logic element may have a multiplexer 114, a memory 116, and a flip-flop 118. Figure 4 The flip-flop 118 that provides the synchronous output is not shown. However, in fact, the flip-flop 118 exists. Figure 4 In each logic element 108, such as Figure 3 As shown. Alternatively, different types of synchronizers may be present in logic element 108 to provide synchronous output 109.

[0053] Each logic element block is 108, such as Figure 2 The arrangement is shown. Specifically, the direct output of each logic element 108 in the block is coupled to the input of each logic element 108 in a higher order. The direct output 107 of each logic element is not provided to logic elements of equal or lower order. Direct interconnect 110 couples the direct output 109 to the input of each logic element 108.

[0054] The synchronous output 109 of each logic element 108 of the block is provided to the input of each logic element of the block, regardless of the order. Figure 4 For each block, a bus 113 corresponding to each of the various synchronous interconnects 112 of the block is shown. Thus, each synchronous interconnect 112 is individually provided to the input of each logic element 108 of the block.

[0055] The outputs of PLA 102 include the direct outputs of each logic element 108 in blocks A-D. Therefore, PLA 102 outputs 16 direct outputs. The outputs of PLA 102 also include the synchronous outputs 109 of each logic element 108 in blocks A-D. Therefore, PLA 102 outputs 16 synchronous outputs. The inputs of PLA are provided to the inputs of each logic element 108 in each block A-D.

[0056] Figure 5This is a block diagram of PLA 102 according to some embodiments. PLA 102 includes two blocks (rows) of logic elements 108. Each row includes three logic elements 108. Therefore, there are three columns of logic elements 1-3. Each logic element 108 can be substantially connected to... Figure 3 The logic element 108 is the same.

[0057] Figure 5 One embodiment is shown in which the direct output of each logic element 108 is provided to the input of each higher-order logic element 108, regardless of the block value. Thus, logic elements 108 of block A can be provided to the inputs of logic elements 108 of blocks A and B, and logic elements of one of blocks B can be provided to the inputs of logic elements 108 of blocks A and B, provided that the receiving logic element 108 has a higher order. Direct outputs 107 are connected to the inputs of other logic elements 108 via direct interconnects 110.

[0058] To simply illustrate the principle of logic elements that can provide direct input to other rows, Figure 5 Synchronous interconnect 112 is not shown. However, synchronous interconnect 112 exists and connects the synchronous output of each logic element 108 to the input of each logic element 108, regardless of row or order.

[0059] In fact, PLA 102 may include, for example: Figure 4 The four rows and four columns are shown. PLA 102 may include other numbers of rows and columns without departing from the scope of this disclosure.

[0060] Figure 6 This is a block diagram of a PLA 102 according to one embodiment. PLA 102 includes a plurality of blocks 105. Each block 105 corresponds to a row of logic elements 108, as previously shown. The synchronous output of each block 105 can be provided as input to any other block 105. The direct outputs of the logic elements 108 of each block 105 can be interconnected within the block 105 according to the previously described ordering constraints. Other numbers of blocks may be used without departing from the scope of this disclosure.

[0061] Figure 7 This is a flowchart of a method 700 for forming a PLA according to one embodiment. Method 700 can utilize information regarding... Figure 1 - Figure 6The system, components, and processes are described. At 702, method 700 includes blocks of logic elements forming a programmable logic array, each logic element having an ordering based on the position of the logic elements between the input side and the output side of the programmable logic array. Each logic element provides both a direct output and a synchronous output. At 704, method 700 includes forming one or more direct interconnects for each logic element, connecting the direct output of the logic element only to all logic elements in a higher-ordered block.

[0062] In 706, method 700 includes forming one or more synchronous interconnects for each logic element to connect the synchronous output of the logic element to all other logic elements in the block.

[0063] Figure 8 This is a flowchart of a method 800 for forming a PLA according to one embodiment. Method 800 can utilize information regarding... Figure 1 - Figure 6 The system, components, and processes are described. At 802, method 800 includes providing an interface for programming a programmable logic array, the programmable logic array including blocks of logic elements, direct outputs, and synchronous outputs, each block of logic elements having an ordering based on the positions of the logic elements between the input side and the output side of the programmable logic array. At 804, method 800 includes allowing selection via the interface of the direct output of each logic element as an input to any logic element of a higher ordering during programming of the programmable logic array. At 806, method 800 includes disallowing selection via the interface of the direct output of each logic element as an input to any logic element of equal or lower ordering during programming of the programmable logic array.

[0064] In one embodiment, the integrated circuit includes a PLA. The PLA includes an input side, an output side, and a row of logic elements. Each logic element includes multiple inputs, direct outputs, and synchronous outputs. The PLA includes multiple direct interconnects that connect the direct outputs of each logic element to the inputs of each logic element in a higher order, but not to logic elements in equal or lower orders, wherein the order indicates the relative distance of the logic elements from the input side.

[0065] In one embodiment, the integrated circuit includes a PLA. The PLA includes an array of logic elements arranged in rows and columns. Each logic element includes multiple inputs and direct outputs. The PLA includes multiple direct interconnects that couple the direct output of each logic element in each row to logic elements downstream of the logic elements in that row, without coupling the direct output of each logic element in each row to logic elements upstream of the logic elements in that row.

[0066] In one embodiment, a method includes forming a row of logic elements that form a programmable logic array, each logic element including a direct output and a synchronous output. The method includes forming a plurality of direct interconnects that couple the direct output of each logic element only to logic elements downstream of the logic element, and forming a plurality of synchronous interconnects that couple the synchronous output of each logic element to all other logic elements in the row.

[0067] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments based on the detailed description above. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be construed as including all possible embodiments and the full scope of the authorized equivalents of these claims. Therefore, the claims are not limited to this disclosure.

Claims

1. An integrated circuit, comprising a PLA, the PLA comprising: Input side; Output side; Logic element rows, each logic element includes: Multiple inputs; Direct output; and Synchronous output; and Multiple direct interconnects connect the direct output of each logic element to the input of each logic element in a higher-order sequence, but not to lower-order logic elements, wherein the order indicates the relative distance of the logic element from the input side.

2. The integrated circuit of claim 1, wherein the direct interconnect connects the direct output of each logic element to one of the inputs of that logic element.

3. The integrated circuit of claim 1, wherein the PLA includes a plurality of synchronous interconnects that connect the synchronous output of each logic element to the input of each of the logic elements in the row.

4. The integrated circuit of claim 1, wherein each logic element comprises: Multiplexers have the following features: Input, corresponding to the input of the logic element; as well as Multiple outputs; A programmable memory, coupled to the plurality of outputs of the multiplexer and including a plurality of data units and outputs; as well as A trigger having a data input coupled to the output of the programmable memory.

5. The integrated circuit of claim 4, wherein the output of the programmable memory is the direct output of the logic element.

6. The integrated circuit of claim 5, wherein the trigger comprises: Clock input that receives the clock signal from the PLA; as well as Data output, corresponding to the synchronous output of the logic element.

7. The integrated circuit of claim 6, further comprising a clock generator configured to provide the clock signal to the PLA.

8. The integrated circuit of claim 4, wherein the data value on the output of the multiplexer corresponds to the address of a data cell for the programmable memory.

9. The integrated circuit of claim 4, wherein the programmable memory includes a register.

10. The integrated circuit of claim 1, comprising a controller coupled to the PLA and configured to program the PLA.

11. An integrated circuit including a PLA, said PLA comprising: An array of logic elements arranged in rows and columns, each logic element comprising: Multiple inputs; and Direct output; and Multiple direct interconnects couple the direct output of each logic element in each row to a logic element downstream of the logic element in the row, but do not couple the direct output of each logic element in each row to a logic element upstream of the logic element in the row.

12. The integrated circuit of claim 11, wherein the direct interconnect couples the direct output of each logic element to the logic element in a column downstream of the logic element.

13. The integrated circuit of claim 11, wherein each logic element includes a synchronous output.

14. The integrated circuit of claim 13, wherein the PLA includes a plurality of synchronous interconnects that connect the synchronous output of each logic element to the input of each of the logic elements in the array.

15. The integrated circuit of claim 11, wherein each logic element comprises: Multiplexers have the following features: Input, corresponding to the input of the logic element; as well as Multiple outputs; A programmable memory, coupled to the plurality of outputs of the multiplexer and including a plurality of data units and outputs; as well as A trigger, coupled to the output of the programmable memory and having a data input coupled to the output of the programmable memory.

16. A method comprising: Rows of logic elements that form a programmable logic array, each logic element including direct outputs and synchronous outputs; Multiple direct interconnects are formed, wherein the direct output of each logic element is coupled only to logic elements downstream of the logic element; as well as Multiple synchronous interconnects are formed, which couple the synchronous output of each logic element to all other logic elements in the row.

17. The method of claim 16, wherein forming the row of logic elements comprises performing the following for each logic element: A multiplexer is formed, which has the following characteristics: Inputs, corresponding to the inputs of the logic element; and Multiple outputs; A programmable memory is formed, the programmable memory being coupled to the plurality of outputs of the multiplexer and including a plurality of data units and outputs; as well as A trigger is formed, the trigger being coupled to the output of the programmable memory and having a data input coupled to the output of the programmable memory.

18. The method of claim 17, wherein the output of the programmable memory is the direct output of the logic element.

19. The method of claim 17, wherein the trigger comprises: Clock input, receiving the clock signal from the PLA; as well as Data output, corresponding to the synchronous output of the logic element.

20. The method of claim 17, wherein the programmable memory includes a register.

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