Digital-to-analog conversion device and method with signal correction mechanism

Abstract

The present disclosure relates to a digital-to-analog conversion device and method with a signal correction mechanism. A digital-to-analog conversion device with a signal correction mechanism. The digital-to-analog conversion circuit includes a conversion circuit for generating an output analog signal and an echo cancellation analog signal. An echo transmission circuit down-samples an echo path to generate an echo signal. An echo correction circuit includes odd and even correction circuits for generating odd and even correction parts of the echo cancellation correction signal by mapping odd and even input parts of an input digital signal with a code word offset table and processing with response coefficients. A correction parameter operation circuit generates an offset amount based on an error signal of the echo signal relative to the echo cancellation correction signal and path information associated with the echo correction circuit. The echo correction circuit converges the response coefficients based on the error signal and pseudo noise transmission path information and updates the code word offset table based on the offset amount.

Description

Technical Field

[0001] This invention relates to digital-to-analog conversion technology, and more particularly to a digital-to-analog conversion apparatus and method with a signal correction mechanism. Background Technology

[0002] A digital-to-analog converter is a crucial component that converts signals from digital to analog form. A digital-to-analog converter can generate analog signals of varying magnitudes by multiplying different digital codes by corresponding conversion gain values.

[0003] However, digital-to-analog converters often suffer from errors due to the offset of the internal current source, and the mismatch between the signal itself and the signal in the transmission path can cause echo. Therefore, digital-to-analog converters require various correction techniques to correct the input and output signals in order to achieve the best conversion results. Summary of the Invention

[0004] In view of the problems of the prior art, one object of the present invention is to provide a digital-to-analog conversion apparatus and method with a signal correction mechanism to improve the prior art.

[0005] This invention includes a digital-to-analog converter with a signal correction mechanism, comprising: a digital-to-analog conversion circuit, an echo transmission circuit, an echo correction circuit, and a correction parameter calculation circuit. The digital-to-analog conversion circuit includes a complex conversion circuit operating at a first frequency to convert based on a signal feed associated with an input digital signal having an input codeword, generating an output analog signal and an echo-canceling analog signal, wherein the echo-canceling analog signal at least cancels the output analog signal's echo along the echo path. The echo transmission circuit processes the echo path to downsample and generate an echo signal with a second frequency, wherein the second frequency is half the first frequency. The echo correction circuit includes an odd correction circuit and an even correction circuit operating at the second frequency and corresponding to the conversion circuit used to generate the echo-canceling analog signal. These circuits are mapped by a complex codeword deviation table and processed by a complex array response coefficient based on signal feeds associated with the odd and even input portions of the input digital signal, respectively, to generate odd-corrected and even-corrected portions of the echo-canceling correction signal. The correction parameter calculation circuit operates at the second frequency to generate a complex offset based on the error signal of the echo signal relative to the echo cancellation correction signal and the path information related to the echo correction circuit. The echo correction circuit converges the response coefficient based on the error signal and the pseudo-noise transmission path information from the digital-to-analog conversion circuit to the echo transmission circuit, and updates the codeword deviation table based on the offset.

[0006] The present invention further includes a digital-to-analog conversion method with a signal correction mechanism, applied in a digital-to-analog conversion device, comprising: a digital-to-analog conversion circuit performing conversion based on a signal feed related to an input digital signal having an input codeword, generating an output analog signal and an echo-canceling analog signal, wherein the echo-canceling analog signal at least cancels the output analog signal's output echo on the echo path, wherein the digital-to-analog conversion circuit includes a complex conversion circuit operating at a first frequency; an echo transmission circuit performing signal processing on the echo path to downsample and generate an echo signal having a second frequency, wherein the second frequency is half of the first frequency; and an echo correction circuit performing conversion based on a signal feed related to the odd-numbered input portion and the even-numbered input portion of the input digital signal, respectively. The signal input is mapped by a complex codeword offset table and processed by a complex array of response coefficients to generate an odd-correction portion and an even-correction portion of the echo cancellation correction signal. The echo correction circuit includes an odd-correction circuit and an even-correction circuit operating at a second frequency and corresponding to the conversion circuit used to generate the echo cancellation analog signal. A correction parameter calculation circuit generates a complex offset based on the error signal of the echo signal relative to the echo cancellation correction signal and path information related to the echo correction circuit. The correction parameter calculation circuit operates at the second frequency. The echo correction circuit converges the response coefficients based on the error signal and the pseudo-noise transmission path information from the digital-to-analog conversion circuit to the echo transmission circuit, and updates the codeword offset table based on the offset.

[0007] Regarding the features, implementation, and effects of this case, the preferred embodiments are described in detail below with reference to the drawings. Attached Figure Description

[0008] Figure 1 This shows a block diagram of a digital-to-analog converter with a signal correction mechanism according to one embodiment of the present invention.

[0009] Figure 2 A more detailed block diagram of the signal input circuit is shown in one embodiment of the present invention;

[0010] Figure 3 A more detailed block diagram of a digital-to-analog conversion circuit is shown in one embodiment of the present invention;

[0011] Figure 4 A more detailed block diagram of the echo correction circuit is shown in one embodiment of the present invention;

[0012] Figure 5 A block diagram showing a digital-to-analog conversion device according to another embodiment of the present invention; and

[0013] Figure 6 This invention illustrates a flowchart of a digital-to-analog conversion method with a signal correction mechanism, according to one embodiment of the present invention. Detailed Implementation

[0014] One objective of this invention is to provide a digital-to-analog converter with a signal correction mechanism, which, when generating an output analog signal and an echo-cancelling analog signal with a first frequency, enables the internal circuitry to operate at a second frequency, half the first frequency, based on the echo signal through downsampling.

[0015] Please refer to Figure 1 . Figure 1 This diagram shows a block diagram of a digital-to-analog converter 100 with a signal correction mechanism according to one embodiment of the present invention. The digital-to-analog converter 100 includes: a signal input circuit 110, a digital-to-analog converter 120, an echo transmission circuit 130, an echo correction circuit 140, and a correction parameter calculation circuit 150.

[0016] Signal input circuit 110 feeds a signal into digital-to-analog converter circuit 120. Digital-to-analog converter circuit 120 includes a complex-to-digital converter operating at a first frequency, wherein the first frequency is, for example, but not limited to, 800 MHz. Digital-to-analog converter circuit 120 performs digital-to-analog conversion based on the signal feed associated with the input digital signal IS having an input codeword, generating an output analog signal OD and an echo-cancelling analog signal. The echo-cancelling analog signal at least cancels the output analog signal OD at the output echo path EP.

[0017] The following will be paired Figure 2 and Figure 3 The operation of the signal input circuit 110 and the digital-to-analog conversion circuit 120 will be explained.

[0018] Figure 2 This diagram shows a more detailed block diagram of the signal input circuit 110 according to one embodiment of the present invention. The signal input circuit 110 includes: an odd-numbered feed circuit 200, an even-numbered feed circuit 210, an odd-numbered pseudo-noise generation circuit 220, and an even-numbered pseudo-noise generation circuit 230.

[0019] Figure 3 This diagram shows a more detailed block diagram of a digital-to-analog conversion circuit 120 according to one embodiment of the present invention. The complex conversion circuit in the digital-to-analog conversion circuit 120 includes an output conversion circuit 300, an output echo cancellation conversion circuit 310, and a pseudo-noise conversion circuit 320.

[0020] The odd-numbered input circuit 200 extracts the odd-numbered input portion (ISO) of the input digital signal IS and outputs it. The even-numbered input circuit 210 extracts the even-numbered input portion (ISE) of the input digital signal IS and outputs it. Therefore, when the input digital signal IS has a first frequency, the odd-numbered input portion (ISO) and the even-numbered input portion (ISE) each have a second frequency, the value of which is approximately half of the first frequency. For example, when the first frequency is 800 MHz, the second frequency is 400 MHz.

[0021] In one embodiment, the odd-numbered feed circuit 200 and the even-numbered feed circuit 210 are self-contained. Figure 1 As shown, for example, the signal source SS of the transmitter (TX) in a communication system receives the input digital signal IS. Furthermore, the odd-numbered feed circuit 200 and the even-numbered feed circuit 210 can be implemented by a filter circuit to filter and output the odd-numbered input portion ISO and the even-numbered input portion ISE, respectively.

[0022] Output conversion circuit 300 receives the odd-numbered input portion (ISO) and the even-numbered input portion (ISE) and converts them to generate the output analog signal OD. Output echo cancellation conversion circuit 310 also receives the odd-numbered input portion (ISO) and the even-numbered input portion (ISE) and converts them to generate the output echo cancellation analog signal OEC in the echo cancellation analog signal. The output analog signal OD is the signal actually transmitted to the outside. However, the output analog signal OD may be transmitted via... Figure 1 The echo path EP shown leaks into, for example, but not limited to, the receiver circuit (RX, not shown). Therefore, the output echo cancellation analog signal OEC cancels the echo of the output analog signal OD leaking onto the echo path EP.

[0023] Odd-number pseudo-noise generation circuit 220 generates an odd-number pseudo-noise digital signal INO, which is fed into digital-to-analog converter circuit 120. Even-number pseudo-noise generation circuit 230 generates an even-number pseudo-noise digital signal INE, which is also fed into digital-to-analog converter circuit 120. In one embodiment, the odd-number pseudo-noise digital signal INO and the even-number pseudo-noise digital signal INE can be random 0 and 1 signals of analog noise.

[0024] The pseudo-noise conversion circuit 320 receives odd-numbered pseudo-noise digital signals INO and even-numbered pseudo-noise digital signals INE, converts them to generate a pseudo-noise analog signal ON, and sends it to the echo path EP. The generation of the odd-numbered pseudo-noise digital signals INO and INE, and the feedback of the pseudo-noise analog signal ON, can be used to measure the response of the digital-to-analog conversion circuit 120 to the echo path EP.

[0025] In one embodiment, the digital-to-analog converter 120 further includes an overlay circuit 330 to overlay the analog signal before transmitting it to... Figure 1 The echo path EP performs echo cancellation on the output analog signal OD that leaks out to the echo path EP.

[0026] Figure 1 The echo transmission circuit 130 performs signal processing on the echo path EP to downsample and generate an echo signal ES having a second frequency that is half the first frequency. The signal processing includes, for example, but not limited to, echo response processing and analog-to-digital conversion via downsampling to generate the echo signal ES.

[0027] Each conversion circuit in the aforementioned digital-to-analog conversion circuit 120 includes a complex current source (not shown in the figure), which generates an analog signal based on the control fed in the corresponding signal. The current source may include thermometer-type and binary-controlled current sources, each with a current deviation value, which causes a static mismatch error to the output analog signal.

[0028] The echo correction circuit 140 eliminates the static mismatch error of each conversion circuit. The echo correction circuit 140, through its included odd correction circuit and even correction circuit, which operate at a second frequency and correspond to the conversion circuit used to generate the echo cancellation analog signal, feeds in signals related to the odd input portion ISO and the even input portion ISE of the input digital signal IS, respectively. These signals are mapped by a complex digital character deviation table and processed by a complex array response coefficient to generate the odd correction portion and even correction portion of the echo cancellation correction signal.

[0029] Furthermore, the echo correction circuit 140 further uses a set of odd-numbered pseudo-noise digital signals INO and INE, respectively, a set of odd-numbered pseudo-noise response parameters CCNO and a set of even-numbered pseudo-noise response parameters CCNE (e.g., ... Figure 4 The signal (as shown) is processed to generate odd-numbered pseudo-noise correction signals ECNO and even-numbered pseudo-noise correction signals ECNE.

[0030] Figure 4 This diagram shows a more detailed block diagram of an echo correction circuit 140 according to one embodiment of the present invention. The echo correction circuit 140 includes an odd-output echo cancellation correction circuit 400, an even-output echo cancellation correction circuit 410, an odd-output pseudo-noise correction circuit 420, and an even-output pseudo-noise correction circuit 430.

[0031] The odd-output echo cancellation correction circuit 400 includes a first mapping circuit 440A and a first response circuit 440B. The first mapping circuit 440A receives the odd-input portion ISO of the input digital signal IS and maps it according to a first codeword offset table TB1 to generate a first mapped signal DS1. The first response circuit 440B receives the first mapped signal DS1 and processes it according to a set of first response coefficients CC1 to generate an odd-output echo cancellation correction signal ECS1.

[0032] The even-number output echo cancellation correction circuit 410 includes a second mapping circuit 450A and a second response circuit 450B. The second mapping circuit 450A receives the even-number input portion ISE of the input digital signal IS and maps it according to a second codeword offset table TB2 to generate a second mapping signal DS2. The second response circuit 450B receives the second mapping signal DS2 and processes it according to a set of second response coefficients CC2 to generate an even-number output echo cancellation correction signal ECS2.

[0033] In the above mapping circuit, each codeword offset table contains a one-to-one correspondence between complex digital characters and their offset values. The input codeword is one of the codewords in the first codeword offset table TB1 and the second codeword offset table TB2. In the initial state, the offset values ​​corresponding to all codewords are preset to 0.

[0034] Odd-number pseudo-noise correction circuit 420 receives the odd-number pseudo-noise digital signal INO and processes it according to the odd-number pseudo-noise response coefficient CCNO to generate the odd-number pseudo-noise correction signal ECNO. Even-number pseudo-noise correction circuit 430 receives the even-number pseudo-noise digital signal INE and processes it according to the even-number pseudo-noise response coefficient CCNE to generate the even-number pseudo-noise correction signal ECNE.

[0035] In one embodiment, Figure 1 The digital-to-analog converter 100 further includes an error calculation circuit 160 that calculates the error signal DIS of the echo signal ES relative to the aforementioned correction signals (i.e., ECS1 to ECS2 and ECNO, ECNE).

[0036] In one embodiment, Figure 1 The digital-to-analog converter 100 further includes a residual echo cancellation circuit 170 for further cancellation of residual echoes. The residual echo cancellation circuit 170 includes a residual echo response circuit 180 and a cancellation circuit 190.

[0037] The residual echo response circuit 180 receives the input digital signal IS and processes it according to a set of residual echo response coefficients CCR to generate a residual echo cancellation signal ECR. The cancellation circuit 190 subtracts the residual echo cancellation signal ECR from the error signal DIS to generate a final error signal FDIS. The residual echo response circuit 180 then converges based on the final error signal FDIS.

[0038] The correction parameter calculation circuit 150 generates a complex offset based on the error signal DIS of the echo signal ES relative to the aforementioned correction signals (i.e., ECS1-ECS2, ECNO, ECNE) and the path information associated with the echo correction circuit 140. In one embodiment, the correction parameter calculation circuit 150 actually generates the offset based on the final error signal FDIS processed by the residual echo cancellation circuit 170.

[0039] In one embodiment, the aforementioned path information refers to the path delays DL1 to DL2 between each response circuit (first response circuit 440B and second response circuit 450B) and the correction parameter calculation circuit 150. Since the processing of these circuits takes time, the correction parameter calculation circuit 150 needs to backtrack the calculated offset to the correct input codeword based on the path delays DL1 to DL2.

[0040] In one embodiment, the correction parameter calculation circuit 150 receives the first to second response coefficients CC1 to CC2 of the first to second response circuits 440B to 450B, performs one-dimensional inversion on each of these response coefficients, multiplies them by the value of the final error signal FDIS, and then accumulates them to generate corresponding inversion error values. The correction parameter calculation circuit 150 further sets each inversion error value as a first to second offset DA1 to DA2 corresponding to the first to second mapping circuits 440A to 450A, based on path delays DL1 to DL2.

[0041] It should be noted that the above-described method of generating offset is merely an example. In other embodiments, the correction parameter calculation circuit 150 may also generate offset in other ways.

[0042] The echo correction circuit 140 can be trained based on the final error signal FDIS and the pseudo-noise transmission path information from the digital-to-analog converter circuit 120 to the echo transmission circuit 130, so that the response coefficients of each group converge, thereby achieving the purpose of correcting the digital-to-analog converter circuit 120. The pseudo-noise transmission path information can be obtained by feeding in odd-numbered pseudo-noise digital signals INO and even-numbered pseudo-noise digital signals INE, and transmitting pseudo-noise analog signals ON.

[0043] To avoid interference between the training targets, the digital-to-analog converter 100 is trained in different stages.

[0044] During the first training phase, the output conversion circuit 300 and the pseudo-noise conversion circuit 320 are enabled so that the odd pseudo-noise correction circuit 420 and the even pseudo-noise correction circuit 430 converge the odd pseudo-noise response coefficient CCNO and the even pseudo-noise response coefficient CCNE according to the echo signal ES, so that the first response circuit 440B and the second response circuit 450B set the converged odd pseudo-noise response coefficient CCNO and the even pseudo-noise response coefficient CCNE as the first response coefficient CC1 and the second response coefficient CC2, respectively.

[0045] During the second training phase, the output echo cancellation conversion circuit 310 is further enabled to update the first codeword offset table TB1 and the second codeword offset table TB2 based on the first offset DA1 and the second offset DA2 associated with the odd-numbered output echo cancellation correction circuit 400 and the even-numbered output echo cancellation correction circuit 410 in the offset.

[0046] In one embodiment, the output echo cancellation conversion circuit 310 includes multiple permutations of the deviation values ​​of each current source corresponding to different input codewords, creating a mapping relationship between the deviation values ​​of the current sources and the offsets of the input codewords. The correction parameter calculation circuit 150 can, in the second training phase, first divide the offsets corresponding to different input codewords into complex groups based on the operating state of each current source, and set each current source as a target current source, to further set the corresponding current deviation value calculation formula. The current deviation value calculation formula is the result of subtracting two of these groups, so that the current deviation values ​​of current sources other than the target current source cancel each other out.

[0047] The correction parameter calculation circuit 150 substitutes the offset into the calculation formula of the current deviation value corresponding to each current source to calculate the current deviation value of the target current source, and then converts the current deviation value of the current source into the complex code word deviation value so as to update the corresponding first and second code word deviation tables TB1 to TB2.

[0048] In one embodiment, the correction parameter calculation circuit 150 may first set the current deviation value of two of the current sources to 0 as an anchor point for calculation, thereby avoiding system interaction.

[0049] In this manner, the correction parameter calculation circuit 150 can update the first and second codeword deviation tables TB1 to TB2 of the first and second mapping circuits 440A to 450A.

[0050] In one embodiment, the output echo cancellation conversion circuit 310 may further include a control circuit (not shown) to generate an activation sequence based on the current deviation values ​​corresponding to the current sources. Then, based on the input codeword, the thermometer-controlled current sources are activated in the activation sequence using a thermometer code control method, so that the linearity of the activation sequence of these current sources is greater than a preset value. The activation sequence can be set in different ways, which will not be elaborated here.

[0051] Because the output analog signal OD, during transmission, will generate an echo along the echo path EP due to transformer bounce or external impedance mismatch, it cannot be completely eliminated by the output echo cancellation analog signal OEC. Therefore, in some embodiments, the digital-to-analog converter 100 may be further equipped with circuitry for mismatch echo cancellation to eliminate the echoes caused by the mismatch.

[0052] Please refer to the following at the same time Figures 1 to 4 The circuitry related to mismatch echo cancellation described above is illustrated using dashed squares. Figures 1 to 4 middle.

[0053] like Figure 2 As shown, in some embodiments, the signal input circuit 110 further includes an odd-number filter circuit 240 and an even-number filter circuit 250, which respectively extract the odd-number input portion ISO and the even-number input portion ISE of the input digital signal IS, filter them, and output the odd-number filtered signal FSO and the even-number filtered signal FSE to the digital-to-analog converter circuit 120.

[0054] Furthermore, the signal input circuit 110 may optionally include a limiting circuit 260 configured to limit the maximum and minimum values ​​of the odd-numbered filtered signal FSO and the even-numbered filtered signal FSE to preset maximum and minimum values ​​respectively before transmitting them to the digital-to-analog converter circuit 120.

[0055] For example, when the common signal values ​​of odd-numbered filter signals FSO and even-numbered filter signals FSE are between -6 and +6, the appearance of infrequent extreme values ​​such as -7 and +7 can easily cause peak errors in the subsequent correction process of the relevant correction circuit. Therefore, the limiting circuit 260 can limit the extreme values ​​of -7 and +7 to the preset minimum and maximum values ​​of -6 and +6, thus avoiding the occurrence of peak errors.

[0056] like Figure 3 As shown, the digital-to-analog conversion circuit 120 further includes a mismatch echo cancellation conversion circuit 340, which receives odd-numbered filtered signals FSO and even-numbered filtered signals FSE and converts them to generate a mismatch echo cancellation analog signal MEC.

[0057] like Figure 4 As shown, the echo correction circuit 140 further includes an odd-number mismatch echo cancellation correction circuit 460 and an even-number mismatch echo cancellation correction circuit 470.

[0058] The odd-mismatch echo cancellation correction circuit 460 includes a third mapping circuit 480A and a third response circuit 480B. The third mapping circuit 480A receives the odd-number filtered signal FSO and maps it according to the third codeword offset table TB3 to generate a third-number mapped signal DS3. The third response circuit 480B receives the third-number mapped signal DS3 and processes it according to a set of third response coefficients CC3 to generate the odd-mismatch echo cancellation correction signal ECS3.

[0059] The odd-mismatch echo cancellation correction circuit 470 includes a fourth mapping circuit 490A and a fourth response circuit 490B. The fourth mapping circuit 490A receives the even-number filtered signal FSE and maps it according to the fourth codeword offset table TB4 to generate a fourth mapped signal DS4. The fourth response circuit 490B receives the fourth mapped signal DS4 and processes it according to a set of fourth response coefficients CC4 to generate an even-mismatch echo cancellation correction signal ECS4.

[0060] Similarly, the codeword deviation tables mentioned above also contain a one-to-one correspondence between complex codewords and their deviation values. This will not be elaborated upon further here.

[0061] The error calculation circuit 160 will further calculate the echo signal ES relative to the above-mentioned correction signal, odd mismatch echo cancellation correction signal ECS3 and even mismatch echo cancellation correction signal ECS4, and calculate the error signal DIS.

[0062] The correction parameter calculation circuit 150 calculates the path information related to the final error signal FDIS and the odd mismatch echo cancellation correction circuit 460 and the even mismatch echo cancellation correction circuit 470, i.e., the path delays DL3 to DL4 (as follows). Figure 5 As shown, an offset is generated to trace back to the correct input codeword. Furthermore, the correction parameter calculation circuit 150 receives the third and fourth response coefficients CC3 to CC4 from the third and fourth response circuits 480B to 490B, performs a one-dimensional inversion on each of these response coefficients, multiplies them by the value of the final error signal FDIS, and then accumulates them to generate the corresponding inversion error value. The correction parameter calculation circuit 150 further sets each inversion error value to the corresponding third and fourth offsets DA3 to DA4 of the third and fourth mapping circuits 480A to 490A based on the path delays DL3 to DL4.

[0063] It should be noted that the above-described method of generating offset is merely an example. In other embodiments, the correction parameter calculation circuit 150 may also generate offset in other ways.

[0064] The first training phase after adding the mismatch echo cancellation correlation circuit is roughly the same as described above, except that the third response circuit 480B and the fourth response circuit 490B also set the converged odd pseudo-noise response coefficient CCNO and even pseudo-noise response coefficient CCNE as the third response coefficient CC3 and the fourth response coefficient CC4, respectively.

[0065] In the second training phase following the addition of the mismatch echo cancellation related circuitry, the mismatch echo cancellation conversion circuit 340 will also enable the output of the mismatch echo cancellation analog signal MEC to update the third to fourth codeword offset tables TB3 to TB4 according to the respective associated third to fourth offsets DA3 to DA4. In one embodiment, the third to fourth codeword offset tables TB3 to TB4 can be selectively updated directly based on the feed of the third to fourth offsets DA3 to DA4 without setting any anchor points. However, the invention is not limited thereto.

[0066] Please refer to Figure 5 . Figure 5 A block diagram showing a digital-to-analog conversion device 500 according to another embodiment of the present invention. Figure 5 Digital-to-analog converter 500 and Figure 1 The digital-to-analog converter 100 has many identical parts, so the identical components will not be described in detail.

[0067] In this embodiment, Figure 5 The digital-to-analog converter 500 includes relevant circuitry for mismatch echo cancellation and is configured with... Figure 2 The mechanism for updating the odd filter coefficients FXO and even filter coefficients FXE in the odd filter circuit 240 and even filter circuit 250.

[0068] To be more detailed, Figure 5 The echo transmission circuit 130 may be equipped with two downsampling circuits (not shown in the figure) to generate an odd echo signal ESO and an even echo signal ESE, each with a second frequency. The odd echo signal ESO has an odd sign, and the even echo signal ESE has an even sign. Figure 5 In this embodiment, the error signal DIS generated by the operation with the echo cancellation correction signal is represented by the odd-numbered echo signal ESO. However, in other embodiments, the even-numbered echo signal ESE can also be selected to generate the error signal DIS by the operation with the echo cancellation correction signal.

[0069] Furthermore, the digital-to-analog converter 500 may further include an update circuit 510. The update circuit 510 includes an odd-response circuit 520, an even-response circuit 530, and an interactive operation circuit 540.

[0070] The odd response circuit 520 and the even response circuit 530 respectively capture the odd input portion ISO and the even input portion ISE of the input digital signal IS, respond to them, and output the odd response signal RSO and the even response signal RSE.

[0071] The interactive operation circuit 540 receives the odd response signal RSO, the even response signal RSE, the odd echo signal ESO, and the even echo signal ESE. The interactive operation circuit 540 then performs interactive operations based on the odd sign of the odd response signal RSO, the even response signal RSE, the odd echo signal ESO, and the even sign of the even echo signal ESE. Here, the odd and even signs can be represented by +1 and -1, respectively. The odd signs are operated with the odd response signal RSO and the even response signal RSE, and the even signs are also operated with the odd response signal RSO and the even response signal RSE, respectively. This interactive operation generates an interactive operation result MOR with a first frequency, which the odd filter circuit 240 and the even filter circuit 250 use to update the odd filter coefficient FXO and the even filter coefficient FXE.

[0072] Therefore, the digital-to-analog converter 100 of the present invention generates an output analog signal and an echo cancellation analog signal at a first frequency, and performs correction based on the echo signal by downsampling so that the internal circuitry can operate at a second frequency, which is half the first frequency.

[0073] Please refer to Figure 6 . Figure 6 This diagram shows a flowchart of a digital-to-analog conversion method 600 with a signal correction mechanism according to one embodiment of the present invention.

[0074] In addition to the aforementioned apparatus, the present invention also discloses a digital-to-analog conversion method 600, applicable to, for example, but not limited to, [various applications]. Figure 1 In the digital-to-analog conversion device 100. One of the digital-to-analog conversion methods 600 is implemented, for example... Figure 6 As shown, it includes the following steps.

[0075] In step S610: The digital-to-analog converter circuit 120 performs a conversion based on the signal feed-in associated with the input digital signal IS having the input codeword, generating an output analog signal OD and an echo-canceling analog signal. The echo-canceling analog signal cancels at least the output echo of the output analog signal OD on the echo path. The digital-to-analog converter circuit 120 includes a complex conversion circuit operating at a first frequency.

[0076] In step S620: The echo transmission circuit 130 performs signal processing on the echo path EP to generate an echo signal ES with a second frequency, wherein the second frequency is half of the first frequency.

[0077] In step S630: The echo correction circuit 140 feeds in signals related to the odd input portion ISO and the even input portion ISE of the input digital signal IS, respectively, which are mapped by a complex digital character deviation table and processed by a complex array response coefficient to generate the odd correction portion and even correction portion of the echo cancellation correction signal. The echo correction circuit includes an odd correction circuit and an even correction circuit that operate at a second frequency and correspond to the conversion circuit used to generate the echo cancellation analog signal.

[0078] In step S640: The correction parameter calculation circuit 150 generates a complex offset based on the error signal DIS of the echo signal ES relative to the output correction signal and the echo cancellation correction signal, and the path information related to the echo correction circuit 140, wherein the correction parameter calculation circuit 150 operates at the second frequency.

[0079] In step S650: The echo correction circuit 140 converges the response coefficients based on the error signal DIS and the pseudo-noise transmission path information from the digital-to-analog conversion circuit 120 to the echo transmission circuit 130, and updates the codeword deviation table based on the offset.

[0080] It should be noted that the above-described implementation is merely an example. In other embodiments, those skilled in the art can make modifications without departing from the spirit of the invention.

[0081] In summary, the digital-to-analog converter and method with a signal correction mechanism of the present invention can, when generating an output analog signal and an echo-cancelling analog signal at a first frequency, perform correction based on the echo signal by downsampling, enabling the internal circuit to operate at a second frequency, half the first frequency.

[0082] Although the embodiments of this case are described above, these embodiments are not intended to limit this case. Those skilled in the art can make changes to the technical features of this case based on the express or implied content of this case. All such changes may fall within the scope of patent protection sought in this case. In other words, the scope of patent protection in this case shall be determined by the scope of the patent application in this specification.

[0083] [Symbol Explanation]

[0084] 100: Digital-to-analog converter

[0085] 110: Signal Input Circuit

[0086] 120: Digital-to-Analog Conversion Circuit

[0087] 130: Echo transmission circuit

[0088] 140: Echo correction circuit

[0089] 150: Correction parameter calculation circuit

[0090] 160: Error Calculation Circuit

[0091] 170: Residual echo cancellation circuit

[0092] 180: Residual Echo Response Circuit

[0093] 190: Elimination circuit

[0094] 200: Odd-numbered feed circuit

[0095] 210: Even-numbered feed circuit

[0096] 220: Odd-number pseudo-noise generation circuit

[0097] 230: Even-number pseudo-noise generation circuit

[0098] 240: Odd-number filter circuit

[0099] 250: Even-number filter circuit

[0100] 260: Limiting circuit

[0101] 300: Output conversion circuit

[0102] 310: Output echo cancellation conversion circuit

[0103] 320: Pseudo-noise conversion circuit

[0104] 330: Superposition Circuit

[0105] 340: Mismatch Echo Cancellation Conversion Circuit

[0106] 400: Odd Output Echo Cancellation Correction Circuit

[0107] 410: Even-numbered output echo cancellation correction circuit

[0108] 420: Odd-number pseudo-noise correction circuit

[0109] 430: Even-number pseudo-noise correction circuit

[0110] 440A: First mapping circuit

[0111] 440B: First Response Circuit

[0112] 450A: Second mapping circuit

[0113] 450B: Second Response Circuit

[0114] 460: Odd-number mismatch echo cancellation correction circuit

[0115] 470: Even-number mismatch echo cancellation correction circuit

[0116] 480A: Third mapping circuit

[0117] 480B: Third Response Circuit

[0118] 490A: Fourth Mapping Circuit

[0119] 490B: Fourth Response Circuit

[0120] 500: Digital-to-Analog Converter

[0121] 510: Update the circuit

[0122] 520: Odd-response circuit

[0123] 530: Even-number response circuit

[0124] 540: Interactive Computing Circuit

[0125] 600: Digital-to-Analog Conversion Method

[0126] S610~S650: Steps

[0127] CC1: First Response Coefficient

[0128] CC2: Second Response Coefficient

[0129] CC3: Third Response Coefficient

[0130] CC4: Fourth Response Coefficient

[0131] CCNE: Even-numbered pseudo-noise response parameters

[0132] CCNO: Odd-numbered pseudo-noise response parameters

[0133] CCR: Residual Echo Response Coefficient

[0134] DA1: First offset

[0135] DA2: Second offset

[0136] DA3: Third Offset

[0137] DA4: Fourth Offset

[0138] DIS: Error Signal

[0139] DL1~DL4: Path Delay

[0140] DS1: First Mapping Signal

[0141] DS2: Second Mapping Signal

[0142] DS3: Third Mapping Signal

[0143] DS4: Fourth Mapping Signal

[0144] ECS1: Odd Output Echo Cancellation Correction Signal

[0145] ECS2: Even-numbered output echo cancellation correction signal

[0146] ECS3: Odd Mismatch Echo Cancellation Correction Signal

[0147] ECS4: Even-number mismatch echo cancellation correction signal

[0148] ECNE: Even-numbered pseudo-noise correction signal

[0149] ECNO: Odd-number pseudo-noise correction signal

[0150] ECR: Residual Echo Cancellation Signal

[0151] EP: Echo Path

[0152] ES: Echo Signal

[0153] ESE: Even Echo Signal

[0154] ESO: Odd Echo Signal

[0155] FDIS: Final Error Signal

[0156] FSE: Even-number filtered signal

[0157] FSO: Odd-number filtered signal

[0158] FXE: Even-numbered filter coefficients

[0159] FXO: Odd filter coefficients

[0160] INO: Odd-number pseudo-noise digital signal

[0161] INE: Even-numbered pseudo-noise digital signal

[0162] IS: Input digital signal

[0163] ISE: Even Input Section

[0164] ISO: Odd Input Section

[0165] MEC: Mismatch Echo Cancellation Analog Signal

[0166] MOR: Interactive computation result

[0167] OD: Output analog signal

[0168] OEC: Output echo cancellation analog signal

[0169] ON: Pseudo-noise analog signal

[0170] RSE: Even Response Signal

[0171] RSO: Odd Response Signal

[0172] SS: Signal Source

[0173] TB1: First Codeword Deviation Table

[0174] TB2: Second Codeword Deviation Table

[0175] TB3: Third Codeword Deviation Table

[0176] TB4: Fourth Codeword Deviation Table

Claims

1. A digital-to-analog converter with a signal correction mechanism, comprising: A digital-to-analog converter circuit includes a complex-to-digital converter circuit operating at a first frequency to perform conversion based on a signal feed associated with an input digital signal having an input codeword, generating an output analog signal and an echo-canceling analog signal, the echo-canceling analog signal performing at least one output echo cancellation on the output analog signal in an echo path; An echo transmission circuit processes the echo path to generate an echo signal with a second frequency, wherein the second frequency is half of the first frequency. An echo correction circuit includes an odd-number correction circuit and an even-number correction circuit operating at the second frequency and corresponding to the complex conversion circuit used to generate the echo cancellation analog signal. The circuit is fed with signals related to an odd-number input portion and an even-number input portion of the input digital signal, respectively mapped by a complex digital character deviation table and processed by a complex array of response coefficients to generate an odd-number correction portion and an even-number correction portion of an echo cancellation correction signal; and A calibration parameter calculation circuit, operating at the second frequency, generates a complex offset based on an error signal of the echo signal relative to the echo cancellation correction signal and path information associated with the echo correction circuit. The echo correction circuit causes the complex array response coefficients to converge based on the error signal and pseudo-noise transmission path information from the digital-to-analog converter circuit to the echo transmission circuit, and updates the complex digital character deviation table based on the complex offset.

2. The digital-to-analog converter according to claim 1, further comprising a signal input circuit configured to feed a signal into the digital-to-analog converter circuit, comprising: An odd-numbered feed circuit extracts the odd-numbered input portion of the input digital signal and outputs it. An even-numbered feed circuit extracts the even-numbered input portion of the input digital signal and outputs it. An odd-number pseudo-noise generation circuit generates an odd-number pseudo-noise digital signal which is then fed into the digital-to-analog converter circuit; and An even-number pseudo-noise generation circuit generates an even-number pseudo-noise digital signal which is fed into the digital-to-analog converter circuit.

3. The digital-to-analog converter according to claim 2, wherein the digital-to-analog converter circuit comprises: An output conversion circuit receives the odd-numbered input portion and the even-numbered input portion of the input digital signal and converts them to generate the output analog signal; An output echo cancellation conversion circuit receives the odd-numbered input portion and the even-numbered input portion of the input digital signal and converts them to generate an output echo cancellation analog signal from the echo cancellation analog signal to the echo path; and A pseudo-noise conversion circuit receives the odd-numbered pseudo-noise digital signal and the even-numbered pseudo-noise digital signal, converts them, and generates a pseudo-noise analog signal to the echo path.

4. The digital-to-analog converter of claim 3, wherein the echo correction circuit comprises: An odd-output echo cancellation correction circuit includes: A first mapping circuit, which receives the odd-numbered input portion of the input digital signal and maps it according to a first codeword deviation table in the complex digital character deviation table to generate a first mapping signal; and A first response circuit receives the first mapping signal, processes it according to a set of first response coefficients in the complex array of response coefficients, and generates an odd-numbered output echo cancellation correction signal in the echo cancellation correction signal; An even-output echo cancellation correction circuit includes: A second mapping circuit, which receives the even-numbered input portion of the input digital signal and maps it according to a second codeword deviation table in the complex codeword deviation table to generate a second mapping signal; and A second response circuit receives the second mapping signal, processes it according to a set of second response coefficients in the complex array of response coefficients, and generates an even number of echo cancellation correction signals in the echo cancellation correction signal output; An odd-number pseudo-noise correction circuit receives the odd-number pseudo-noise digital signal, processes it according to a set of odd-number pseudo-noise response coefficients, and generates an odd-number pseudo-noise correction signal; and An even-number pseudo-noise correction circuit receives the even-number pseudo-noise digital signal, processes it according to a set of even-number pseudo-noise response coefficients, and generates an even-number pseudo-noise correction signal.

5. The digital-to-analog converter of claim 4, wherein in a first training phase, the output conversion circuit and the pseudo-noise conversion circuit are enabled to cause the odd-number pseudo-noise correction circuit and the even-number pseudo-noise correction circuit to converge the set of odd-number pseudo-noise response coefficients and the set of even-number pseudo-noise response coefficients according to the echo signal, so that the first response circuit and the second response circuit respectively set the converged set of odd-number pseudo-noise response coefficients and the set of even-number pseudo-noise response coefficients as the first response coefficient and the second response coefficient; and In a second training phase, the output echo cancellation conversion circuit is further enabled to update the first codeword offset table and the second codeword offset table based on a first offset and a second offset associated with the odd-numbered output echo cancellation correction circuit and the even-numbered output echo cancellation correction circuit in the complex offset.

6. The digital-to-analog converter according to claim 4, wherein the signal input circuit further includes an odd-number filter circuit and an even-number filter circuit, which respectively extract the odd-number input portion and the even-number input portion of the input digital signal, filter them, and output them as an odd-number filter signal and an even-number filter signal to the digital-to-analog converter circuit. The digital-to-analog conversion circuit further includes a mismatch echo cancellation conversion circuit that receives the odd-numbered filtered signal and the even-numbered filtered signal, converts them to generate a mismatch echo cancellation analog signal from the echo cancellation analog signal, and sends it to the echo path. The echo correction circuit further includes: An odd-number mismatch echo cancellation correction circuit includes: A third mapping circuit receives the odd-numbered filtered signal and maps it according to a third codeword deviation table in the complex codeword deviation table to generate a third mapping signal; and A third response circuit receives the third mapping signal and processes it according to a set of third response coefficients in the complex array of response coefficients to generate an odd mismatch echo cancellation correction signal in the echo cancellation correction signal; An even-number mismatch echo cancellation correction circuit includes: A fourth mapping circuit receives the even-numbered filtered signal and maps it according to a fourth codeword deviation table in the complex codeword deviation table to generate a fourth mapping signal; and A fourth response circuit receives the fourth mapping signal and processes it according to a set of fourth response coefficients in the complex array of response coefficients to generate an even-number mismatch echo cancellation correction signal in the echo cancellation correction signal; In a first training phase, the third response circuit and the fourth response circuit respectively set the converged set of odd pseudo-noise response coefficients and the set of even pseudo-noise response coefficients as the set of third response coefficients and the set of fourth response coefficients. In a second training phase, the mismatch echo cancellation conversion circuit is further enabled to update the third codeword deviation table and the fourth codeword deviation table according to a third offset and a fourth offset related to the odd mismatch echo cancellation correction circuit and the even mismatch echo cancellation correction circuit in the complex offset.

7. The digital-to-analog converter of claim 6, wherein the echo transmission circuit downsamples to generate an odd echo signal and an even echo signal having the second frequency, and the odd echo signal has an odd sign and the even echo signal has an even sign, the digital-to-analog converter further comprising an update circuit comprising: An odd-response circuit extracts the odd-numbered input portion of the input digital signal, responds to it, and outputs an odd-numbered response signal. An even-response circuit, which captures the even-number input portion of the input digital signal, responds to it, and outputs an even-number response signal; and An interactive operation circuit updates a set of odd-number filtering parameters of the odd-number filtering circuit and a set of even-number filtering parameters of the even-number filtering circuit based on the interactive operation result between the odd-number response signal, the even-number response signal, the odd-number positive and negative sign, and the even-number positive and negative sign.

8. The digital-to-analog converter according to claim 6, wherein the signal input circuit further includes a limiting circuit configured to limit a maximum value and a minimum value of the odd-numbered filtered signal and the even-numbered filtered signal to a preset maximum value and a minimum value respectively before transmitting them to the digital-to-analog converter circuit.

9. The digital-to-analog converter according to claim 1, further comprising a residual echo cancellation circuit, including: A residual echo response circuit receives the input digital signal, processes it according to a set of residual echo response coefficients, and generates a residual echo cancellation signal; and An echo cancellation circuit subtracts the residual echo cancellation signal from the error signal to generate a final error signal; The residual echo response circuit converges based on the final error signal, and the correction parameter calculation circuit actually generates the complex offset based on the final error signal and the path information related to the echo correction circuit.

10. A digital-to-analog conversion method with a signal correction mechanism, applied in a digital-to-analog conversion device, comprising: A digital-to-analog converter circuit converts an input digital signal based on a signal feed-in associated with an input digital signal having an input codeword, generating an output analog signal and an echo-canceling analog signal, the echo-canceling analog signal performing at least one output echo cancellation on the output analog signal in an echo path, wherein the digital-to-analog converter circuit includes a complex conversion circuit operating at a first frequency. An echo transmission circuit processes the echo path to generate an echo signal with a second frequency, wherein the second frequency is half of the first frequency. An echo correction circuit is fed with signals related to an odd-numbered input portion and an even-numbered input portion of the input digital signal, respectively. The signals are mapped by a complex digital character deviation table and processed by a complex array response coefficient to generate an odd-numbered correction portion and an even-numbered correction portion of an echo cancellation correction signal. The echo correction circuit includes an odd-numbered correction circuit and an even-numbered correction circuit that operate at the second frequency and correspond to the complex number conversion circuit used to generate the echo cancellation analog signal. A correction parameter calculation circuit generates a complex offset based on an error signal of the echo signal relative to the echo cancellation correction signal and path information associated with the echo correction circuit, wherein the correction parameter calculation circuit operates at the second frequency; and The echo correction circuit causes the complex array response coefficients to converge based on the error signal and a pseudo-noise transmission path information from the digital-to-analog converter to the echo transmission circuit, and updates the complex digital character deviation table based on the complex number offset.

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