semiconductor element

Abstract

A semiconductor element is provided. The semiconductor element includes a substrate, a dielectric layer, a first metallization layer, a first via layer, a second metallization layer, and a second via layer. The dielectric layer is disposed on the substrate, the first metallization layer is disposed within the dielectric layer and extends along a first direction, the first via layer is surrounded by the first metallization layer, the second metallization layer is disposed within the dielectric layer and extends along the first direction, and the second via layer is surrounded by the second metallization layer, wherein the first metallization layer includes a first protrusion protruding toward the second metallization layer.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Applications Nos. 17 / 824,010 and 17 / 824,487 (i.e., priority date "May 25, 2022"), the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a semiconductor element, and more particularly to a semiconductor element comprising a character line having protrusions. Background Technology

[0003] With the rapid growth of the electronics industry, the development of integrated circuits (ICs) has achieved high performance and miniaturization. Technological advancements in IC materials and design have resulted in several generations of ICs, each generation of circuits being smaller and more complex than the previous one.

[0004] Dynamic Random Access Memory (DRAM) devices are a type of random access memory that stores each bit of data in a separate capacitor within an integrated circuit. Typically, DRAM is arranged in a square array with one capacitor and one transistor per cell. A vertical transistor has been developed for a 4F2 DRAM cell, where F represents the minimum feature width or critical dimension (CD) of the photolithography process. However, recently, with the continuous reduction of word line pitch, DRAM manufacturers face a significant challenge in shrinking the area of ​​memory cells. For example, the path of the bit line can easily come into contact with the word line, leading to short circuits due to coverage errors in the photolithography process.

[0005] The above description of "prior art" is merely to provide background information and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the above "prior art" should be considered part of the "prior art" of this case, nor does it constitute prior art of this disclosure. Summary of the Invention

[0006] One aspect of this disclosure provides a semiconductor device comprising a substrate, a dielectric layer, a first metallization layer, a first channel layer, a second metallization layer, and a second channel layer. The dielectric layer is disposed on the substrate, the first metallization layer is disposed within the dielectric layer and extends along a first direction, the first channel layer is surrounded by the first metallization layer, the second metallization layer is disposed within the dielectric layer and extends along the first direction, and the second channel layer is surrounded by the second metallization layer, wherein the first metallization layer includes a first protrusion projecting toward the second metallization layer.

[0007] Another aspect of this disclosure provides another semiconductor device, the semiconductor device comprising a bottom substrate, a first bottom cell, a top substrate, a first top cell, and a shared bit line. The first bottom cell includes a first bottom capacitor disposed within the bottom substrate, and also includes a first bottom word line disposed on the bottom substrate and extending along a first direction, and further includes a first bottom channel layer surrounded by the first bottom word line. The first top cell includes a first top capacitor disposed within the top substrate, and also includes a first top word line disposed on the top substrate and extending along the first direction, and further includes a first top channel layer surrounded by the first top word line. The shared bit line is disposed between the first bottom cell and the first top cell and extends along a second direction substantially perpendicular to the first direction.

[0008] Another aspect of this disclosure provides a method for manufacturing a semiconductor device, the method comprising providing a substrate. The method also includes forming a conductive layer on the substrate. The method further includes patterning the conductive layer to form a first metallization layer and a second metallization layer extending along a first direction, wherein the first metallization layer includes a first protrusion projecting toward the second metallization layer. Additionally, the method includes forming a first channel layer within the first metallization layer and forming a second channel layer within the second metallization layer.

[0009] In some embodiments, the formation of the first channel layer and the second channel layer includes: forming a first opening in the first metallization layer and forming a second opening in the second metallization layer, wherein the first opening overlaps with the first protrusion along a second direction substantially perpendicular to the first direction; and forming the first channel layer in the first opening and forming the second channel layer in the second opening.

[0010] In some embodiments, the first opening is offset from the second opening along the second direction.

[0011] In some embodiments, the patterning of the conductive layer further includes forming a second protrusion of the second metallization layer, and the second protrusion protrudes toward the first metallization layer.

[0012] In some embodiments, the first channel layer overlaps with the first protrusion along a second direction that is generally perpendicular to the first direction.

[0013] In some embodiments, the second channel layer overlaps with the second protrusion along the second direction.

[0014] In some embodiments, the first channel layer is misaligned with the second channel layer along the second direction.

[0015] In some embodiments, the first metallization layer has a first sidewall and a second sidewall opposite to the first sidewall, the second sidewall facing the second metallization layer, and a first distance between the first sidewall and the first channel layer is different from a second distance between the second sidewall and the first channel layer.

[0016] In some embodiments, the second distance is greater than the first distance.

[0017] In some embodiments, the second metallization layer has a third sidewall and a fourth sidewall, the third sidewall facing the first metallization layer, and a third distance between the third sidewall and the second channel layer is different from a fourth distance between the fourth sidewall and the second channel layer.

[0018] In some embodiments, the third distance is greater than the fourth distance.

[0019] In some embodiments, a fifth distance between the first sidewall of the first metallization layer and the fourth sidewall of the second metallization layer is consistent along the first direction.

[0020] In some embodiments, a sixth distance between the second sidewall of the first metallization layer and the third sidewall of the second metallization layer varies along the first direction.

[0021] Embodiments of this disclosure provide a semiconductor device that may include word lines with protrusions. The protrusions allow for relatively large overlap errors when the word lines are patterned to form openings in the channel layer, preventing leakage current between the word lines and the channel layer.

[0022] The foregoing has provided a fairly broad overview of the features and technical advantages of this disclosure, enabling a better understanding of the detailed description that follows. Other features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to modify or design other structures or processes to achieve the same purpose as this disclosure. Those skilled in the art will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0023] This disclosure can be more fully understood by considering the drawings and referring to the embodiments and claims, wherein similar reference numerals denote similar elements in all the drawings and:

[0024] Figure 1A A plan view of a semiconductor element illustrating some embodiments of the present disclosure is shown.

[0025] Figure 1B Semiconductor elements illustrating some embodiments of this disclosure along Figure 1A A schematic cross-sectional view of section line A-A' shown in the figure.

[0026] Figure 2A A plan view of a semiconductor element illustrating some embodiments of the present disclosure is shown.

[0027] Figure 2B Semiconductor elements illustrating some embodiments of this disclosure along Figure 2A A schematic cross-sectional view of section line B-B' shown in the figure.

[0028] Figure 3 This is a flowchart illustrating a method for manufacturing a semiconductor element according to some embodiments of this disclosure.

[0029] Figure 4A This disclosure illustrates one or more stages of a method for manufacturing a semiconductor element according to some embodiments of the present disclosure.

[0030] Figure 4B Some embodiments of this disclosure are illustrated along the lines of Figure 4A A schematic diagram of the cross section along line A-A'.

[0031] Figure 5A This disclosure illustrates one or more stages of a method for manufacturing a semiconductor element according to some embodiments of the present disclosure.

[0032] Figure 5B Some embodiments of this disclosure are illustrated along the lines of Figure 5A A schematic diagram of the cross section along line A-A'.

[0033] Figure 6A This disclosure illustrates one or more stages of a method for manufacturing a semiconductor element according to some embodiments of the present disclosure.

[0034] Figure 6B Some embodiments of this disclosure are illustrated along the lines of Figure 6A A schematic diagram of the cross section along line A-A'.

[0035] Figure 7A This disclosure illustrates one or more stages of a method for manufacturing a semiconductor element according to some embodiments of the present disclosure.

[0036] Figure 7B Some embodiments of this disclosure are illustrated along the lines of Figure 7A A schematic diagram of the cross section along line A-A'.

[0037] Figure 8A This disclosure illustrates one or more stages of a method for manufacturing a semiconductor element according to some embodiments of the present disclosure.

[0038] Figure 8B Some embodiments of this disclosure are illustrated along the lines of Figure 8A A schematic diagram of the cross section along line A-A'.

[0039] Figure 9A This disclosure illustrates one or more stages of a method for manufacturing a semiconductor element according to some embodiments of the present disclosure.

[0040] Figure 9B Some embodiments of this disclosure are illustrated along the lines of Figure 9A A schematic diagram of the cross section along line A-A'.

[0041] The reference numerals in the attached figures are explained as follows:

[0042] 100: Semiconductor components

[0043] 102: Substrate

[0044] 104-1: Gate Dielectric

[0045] 104-2: Gate Dielectric

[0046] 106-1: Channel Layer

[0047] 106-2: Channel Layer

[0048] 108-1: Capacitor

[0049] 108-2: Capacitor

[0050] 110: Dielectric layer

[0051] 112: Dielectric layer

[0052] 114: Dielectric layer

[0053] 116-1: Metallization layer

[0054] 116-1p: Prominent part

[0055] 116-2: Metallization layer

[0056] 116-2p: Prominent part

[0057] 116s1: Sidewall

[0058] 116s2: Sidewall

[0059] 116s3: Sidewall

[0060] 116s4: Sidewall

[0061] 116r1: Opening

[0062] 116r2-1: Opening

[0063] 116r2-2: Opening

[0064] 118: Contact plug

[0065] 118-1: Contact plug

[0066] 118-2: Contact plug

[0067] 120-1: Metallization layer

[0068] 120-2: Metallization layer

[0069] 140-1: Unit

[0070] 140-2: Unit

[0071] 150: Dielectric layer

[0072] 200: Semiconductor components

[0073] 202: Substrate

[0074] 204-1: Gate Dielectric

[0075] 204-2: Gate Dielectric

[0076] 206-1: Channel Layer

[0077] 206-2: Channel Layer

[0078] 208-1: Capacitor

[0079] 208-2: Capacitor

[0080] 216-1: Metallization layer

[0081] 216-2: Metallization layer

[0082] 216s1: Sidewall

[0083] 216s2: Sidewall

[0084] 216-1p: Prominent part

[0085] 216s3: Sidewall

[0086] 216s4: Sidewall

[0087] 216-2p: Prominent part

[0088] 218-1: Contact plug

[0089] 218-2: Contact plug

[0090] 212: Dielectric layer

[0091] 240-1: Unit

[0092] 240-2: Unit

[0093] 300: Method

[0094] 302: Operation

[0095] 304: Operation

[0096] 306: Operation

[0097] 308: Operation

[0098] 310: Operation

[0099] 312: Operation

[0100] D1: Distance

[0101] D2: Distance

[0102] D3: Distance

[0103] D4: Distance

[0104] D5: Distance

[0105] D6: Distance

[0106] D7: Distance

[0107] D8: Distance

[0108] D9: Distance

[0109] D10: Distance

[0110] D11: Distance

[0111] D12: Distance Detailed Implementation

[0112] The embodiments or examples of this disclosure illustrated in the drawings are described below using specific language. It should be understood that this is not intended to limit the scope of this disclosure. Any changes or modifications to the described embodiments and any further application of the principles described herein will be considered common practice to those skilled in the art related to this disclosure. Reference numerals may be repeated in all embodiments; however, sharing the same reference numerals does not necessarily mean that a feature of one embodiment is applicable to another.

[0113] It should be understood that when a component is referred to as being "connected to" or "coupled to" another component, it can be a direct connection or coupling to the other component, or there may be an intermediate component.

[0114] It should be understood that although terms such as first, second, third, etc., may be used herein to describe various components, parts, regions, layers, or portions, these components, parts, regions, layers, or portions are not limited by these terms, but are only used to distinguish one component, part, region, layer, or portion from another region, layer, or portion. Therefore, the first component, part, region, layer, or portion discussed below may also be referred to as the second component, part, region, layer, or portion without departing from the teachings of the concept of the present invention.

[0115] The terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to limit the concept of the invention. Unless otherwise expressly stated herein, the singular forms “a” and “the” as used herein are also used to include the plural forms. It should be further understood that the term “comprising” as used in the specification means the presence of the stated features, complete individuals, steps, operations, components, or parts, but does not exclude the presence or addition of one or more other features, complete individuals, steps, operations, components, parts, or groups thereof.

[0116] It should be noted that the term "approximately" used to describe the quantity of ingredients, components, or reactants in this disclosure refers to numerical variations that may occur, for example, through typical measurements and liquid handling processes used to prepare concentrates or solutions. Furthermore, variations may arise from negligence in the measurement process, differences in the manufacture, source, or purity of the ingredients used to manufacture the composition or carry out the method. On one hand, the term "approximately" indicates a value within 10% of the reported value. On the other hand, the term "approximately" indicates a value within 5% of the reported value. Still on the other hand, the term "approximately" indicates a value within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported value.

[0117] Figure 1A A plan view of a semiconductor element 100 illustrating some embodiments of the present disclosure is shown.

[0118] In some embodiments, the semiconductor element 100 may include a cell region in which a memory element is formed, for example... Figure 1A and Figure 1B The structure is shown. Memory elements may include, for example, dynamic random access memory (DRAM) elements, one-time programmable (OTP) memory elements, static random access memory (SRAM) elements, or other suitable memory elements. In some embodiments, DRAM may include, for example, transistors, capacitors, and other components.

[0119] During a read operation, the word line can be asserted, turning on the transistor. The enabled transistor allows the sense amplifier to read the voltage across the capacitor via the bit line. During a write operation, data to be written can be provided on the bit line when the word line is asserted.

[0120] In some embodiments, semiconductor element 100 may include a peripheral region (not shown) for forming logic elements (e.g., system-on-a-chip (SoC), central processing unit (CPU), graphics processing unit (GPU), application processor (AP), microcontroller, etc.), radio frequency (RF) elements, sensing elements, microelectromechanical system (MEMS) elements, signal processing elements (e.g., digital signal processing (DSP) elements), front-end elements (e.g., analog front-end (AFE) elements) or other elements.

[0121] like Figure 1A As shown, the semiconductor device 100 may include a substrate 102, a plurality of metallization layers 116-1 and 116-2, a plurality of metallization layers 120-1 and 120-2, a plurality of gate dielectrics 104-1 and 104-2, a plurality of channel layers 106-1 and 106-2, and a dielectric layer 112.

[0122] Substrate 102 may be a semiconductor substrate, such as a semiconductor bulk, a semiconductor-on-insulator (SOI) substrate, or a similar substrate. Substrate 102 may include elemental semiconductors comprising silicon or germanium in single-crystal, polycrystalline, or amorphous forms; compound semiconductor materials comprising at least one of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; alloy semiconductor materials comprising at least one of SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; any other suitable materials or combinations thereof. In some embodiments, the alloy semiconductor substrate may comprise a SiGe alloy having a gradient Ge characteristic, wherein the Si and Ge composition changes from one ratio at one location to another as the characteristic is positioned. In another embodiment, the SiGe alloy is formed on a silicon substrate. In some embodiments, the SiGe alloy may be mechanically strained by another material in contact with it. In some embodiments, substrate 102 may have a multilayer structure, or substrate 102 may comprise a multilayer compound semiconductor structure.

[0123] The substrate 102 may have multiple doped regions (not shown). In some embodiments, p-type and / or n-type dopants may be doped within the substrate 102. In some embodiments, the p-type dopant comprises boron (B), other group III elements, or any combination thereof. In some embodiments, the n-type dopant comprises arsenic (As), phosphorus (P), other group V elements, or any combination thereof.

[0124] Each metallization layer 116-1 and metallization layer 116-2 may extend along the Y-axis, and each metallization layer 116-1 and metallization layer 116-2 may be parallel. In some embodiments, each metallization layer 116-1 and metallization layer 116-2 may be physically separated. Metallization layers 116-1 and metallization layer 116-2 may contain conductive materials, such as tungsten (W), copper (Cu), aluminum (Al), tantalum (Ta), molybdenum (Mo), tantalum nitride (TaN), titanium, titanium nitride (TiN), similar materials, and / or combinations thereof. In some embodiments, metallization layers 116-1 and metallization layer 116-2 may be referred to as character lines.

[0125] Metallization layer 116-1 may include a sidewall 116s1 and an opposite sidewall 116s2, wherein the sidewall 116s2 of metallization layer 116-1 may face metallization layer 116-2. In some embodiments, metallization layer 116-1 may have a protrusion 116-1p. In some embodiments, the protrusion 116-1p of metallization layer 116-1 may face metallization layer 116-2. In some embodiments, the sidewall 116s2 of metallization layer 116-1 may protrude toward metallization layer 116-2, thereby defining the protrusion 116-1p.

[0126] Metallization layer 116-2 may include a sidewall 116s3 and a sidewall 116s4 opposite to the sidewall 116s3, wherein the sidewall 116s3 of metallization layer 116-2 may face metallization layer 116-1. In some embodiments, metallization layer 116-2 may have a protrusion 116-2p. In some embodiments, the protrusion 116-2p of metallization layer 116-2 may face metallization layer 116-1. In some embodiments, the sidewall 116s3 of metallization layer 116-2 may protrude toward metallization layer 116-1, thereby defining the protrusion 116-2p.

[0127] In some embodiments, the protrusions 116-1p of metallization layer 116-1 and 116-2p of metallization layer 116-2 may be staggered. In some embodiments, the protrusions 116-1p of metallization layer 116-1 and 116-2p of metallization layer 116-2 are misaligned along the X-axis. In some embodiments, the protrusions 116-1p of metallization layer 116-1 may not overlap with the protrusions 116-2p of metallization layer 116-2 along the X-axis. In other embodiments, the protrusions 116-1p of metallization layer 116-1 may partially overlap with the protrusions 116-2p of metallization layer 116-2 along the X-axis. In some embodiments, from a plan view, the protrusions 116-1p and / or 116-2p may have a semi-circular or semi-elliptical outline. However, this disclosure is not intended to be limiting.

[0128] Metallization layers 120-1 and 120-2 may be disposed above metallization layers 116-1 and 116-2, each metallization layer 120-1 and 120-2 extending along the X-axis, and each metallization layer 120-1 and 120-2 may be parallel. Each metallization layer 120-1 and 120-2 may be physically separated. In some embodiments, the horizontal plane where metallization layers 120-1 and 120-2 are located is higher than that of metallization layers 116-1 and 116-2. Metallization layers 120-1 and 120-2 may contain conductive materials, such as tungsten, copper, aluminum, tantalum, tantalum nitride, titanium, titanium nitride, similar materials, and / or combinations thereof. In some embodiments, metallization layers 120-1 and 120-2 may be referred to as bit lines.

[0129] In some embodiments, gate dielectric 104-1 and gate dielectric 104-2 may be disposed on a sidewall (not shown) of a word line (e.g., 116-1 and 116-2). In some embodiments, gate dielectric 104-1 may be embedded in metallization layer 116-1. In some embodiments, gate dielectric 104-2 may be embedded in metallization layer 116-2. In some embodiments, gate dielectric 104-1 may be surrounded by metallization layer 116-1. In some embodiments, gate dielectric 104-2 may be surrounded by metallization layer 116-2. In some embodiments, each gate dielectric 104-1 and gate dielectric 104-2 may overlap with metallization layer 120-1 or metallization layer 120-2 along the Z-axis.

[0130] In some embodiments, gate dielectric 104-1 and gate dielectric 104-2 may comprise silicon oxide (SiO2). x ), silicon nitride (Si x N y The gate dielectric layer may comprise a dielectric material, such as a high-k dielectric material, or a combination thereof. In some embodiments, the gate dielectric layer may comprise a dielectric material, such as a high-k dielectric material. The high-k dielectric material may have a dielectric constant (k value) greater than 4. The high-k material may comprise hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), yttrium oxide (Y2O3), aluminum oxide (Al2O3), titanium dioxide (TiO2), or other suitable materials. Other suitable materials are within the scope of this disclosure. In some embodiments, gate dielectric 104-1 and gate dielectric 104-2 may comprise rings having circular, elliptical, or other contours.

[0131] In some embodiments, each channel layer 106-1 and channel layer 106-2 may be disposed on a sidewall (not shown) of the gate dielectric 104-1 or the gate dielectric 104-2. In some embodiments, each channel layer 106-1 and channel layer 106-2 may be embedded within the gate dielectric 104-1 or the gate dielectric 104-2. In some embodiments, each channel layer 106-1 and channel layer 106-2 may be surrounded by the gate dielectric 104-1 or the gate dielectric 104-2. In some embodiments, each channel layer 106-1 and channel layer 106-2 may be in contact with the gate dielectric 104-1 or the gate dielectric 104-2. In some embodiments, each channel layer 106-1 and channel layer 106-2 may overlap with the metallization layer 120-1 or the metallization layer 120-2 along the Z-axis. In some embodiments, as seen in a plan view, each channel layer 106-1 and channel layer 106-2 may be completely surrounded by gate dielectric 104-1 or gate dielectric 104-2.

[0132] In some embodiments, each channel layer 106-1 and channel layer 106-2 may be disposed on one sidewall (not shown) of metallization layer 116-1 or metallization layer 116-2. In some embodiments, each channel layer 106-1 and channel layer 106-2 may be embedded within metallization layer 116-1 or metallization layer 116-2. In some embodiments, each channel layer 106-1 and channel layer 106-2 may be surrounded by metallization layer 116-1 or metallization layer 116-2.

[0133] In some embodiments, channel layers 106-1 and 106-2 may be staggered. In some embodiments, channel layer 106-1 may be misaligned with channel layer 106-2 along the X-axis. In some embodiments, channel layer 106-1 may overlap with the protrusion 116-1p of metallization layer 116-1 along the X-axis. In some embodiments, channel layer 106-2 may overlap with the protrusion 116-2p of metallization layer 116-2 along the X-axis.

[0134] The sidewall 116s1 of the metallization layer 116-1 and the channel layer 106-1 have a distance D1 along the X-axis, and the sidewall 116s2 of the metallization layer 116-1 and the channel layer 106-1 have a distance D2 along the X-axis. In some embodiments, the distance D1 may be different from the distance D2. In some embodiments, the distance D2 may be greater than the distance D1.

[0135] The sidewall 116s3 of the metallization layer 116-2 has a distance D3 along the X-axis between it and the channel layer 106-2, and the sidewall 116s4 of the metallization layer 116-2 has a distance D4 along the X-axis between it and the channel layer 106-2. In some embodiments, the distance D3 may be different from the distance D4. In some embodiments, the distance D3 may be greater than the distance D4.

[0136] In some embodiments, the sidewalls 116s1 of metallization layer 116-1 may have relatively straight edges. In some embodiments, the sidewalls 116s4 of metallization layer 116-2 may have relatively straight edges. A distance D5 is provided along the X-axis between the sidewalls 116s1 and 116s4 of metallization layer 116-1. In some embodiments, the distance D5 may be substantially consistent or remain unchanged along the Y-axis.

[0137] There is a distance D6 along the X-axis between the sidewall 116-2s of metallization layer 116-1 and the sidewall 116s3 of metallization layer 116-2. In some embodiments, the distance D6 may vary along the Y-axis.

[0138] The materials of channel layers 106-1 and 106-2 may include amorphous semiconductors, polycrystalline semiconductors, and / or metal oxides. Semiconductors may include, but are not limited to, germanium (Ge), silicon (Si), tin (Sn), and antimony (Sb). Metal oxides may include, but are not limited to, indium oxide; tin oxide; zinc oxide; binary metal oxides such as In-Zn-based oxides, Sn-Zn-based oxides, Al-Zn-based oxides, Zn-Mg-based oxides, Sn-Mg-based oxides, or In-Mg-based oxides, or In-Ga-based oxides; such as In-Ga-Zn-based oxides (also referred to as IGZO), In-Al-Zn-based oxides, In-S-based oxides (also referred to as ITO), In-Sn-Zn-based oxides, Sn-Ga-Zn-based oxides, Al-Ga-Zn-based oxides, Sn-Al-Zn-based oxides, In-Hf-Zn-based oxides, In-La-Zn-based oxides, In-Ce-Zn-based oxides, In-Pr-Zn-based oxides, In... Ternary metal oxides, such as In-Nd-Zn-based oxides, In-Sm-Zn-based oxides, In-Eu-Zn-based oxides, In-Gd-Zn-based oxides, In-Tb-Zn-based oxides, In-Dy-Zn-based oxides, In-Ho-Zn-based oxides, In-Er-Zn-based oxides, In-Tm-Zn-based oxides, In-Yb-Zn-based oxides, or In-Lu-Zn-based oxides; and quaternary metal oxides, such as In-Sn-Ga-Zn-based oxides, In-Hf-Ga-Zn-based oxides, In-Al-Ga-Zn-based oxides, In-Sn-Al-Zn-based oxides, In-Sn-Hf-Zn-based oxides, or In-Hf-Al-Zn-based oxides, but the invention is not limited thereto.

[0139] In some embodiments, dielectric layer 112 may be disposed on a sidewall (not shown) of metallization layer 116-1 or metallization layer 116-2. In some embodiments, dielectric layer 112 may be disposed between metallization layer 116-1 and metallization layer 116-2. In some embodiments, each gate dielectric 104-1 and gate dielectric 104-2 may be physically separated from dielectric layer 112. In some embodiments, each gate dielectric 104-1 and gate dielectric 104-2 may be physically separated from dielectric layer 112 by metallization layer 116-1 or metallization layer 116-2.

[0140] In some embodiments, each channel layer 106-1 or channel layer 106-2 may be physically separated from the dielectric layer 112. In some embodiments, each channel layer 106-1 or channel layer 106-2 may be physically separated from the dielectric layer 112 by gate dielectric 104-1 and gate dielectric 104-2 and metallization layer 116-1 or metallization layer 116-2.

[0141] Dielectric layer 112 may contain silicon oxide (SiO2). x ), silicon nitride (Si x N y The dielectric layer 112 may be made of silicon oxynitride (SiON) or other suitable materials. In some embodiments, the material of the dielectric layer 112 may be different from the materials of the gate dielectric layer 104-1 and the gate dielectric layer 104-2. In some embodiments, the material of the dielectric layer 112 may be the same as the material of the gate dielectric layer 104-1 and the gate dielectric layer 104-2, but with different qualities or film densities.

[0142] Figure 1B Semiconductor element 100 illustrating some embodiments of this disclosure along Figure 1A A schematic cross-sectional view of section line A-A' shown in the figure.

[0143] like Figure 1B As shown, the semiconductor element 100 may also include a plurality of capacitors 108-1 and 108-2, a dielectric layer 110, a dielectric layer 114, and a plurality of contact plugs 118.

[0144] In some embodiments, capacitor 108-1 may be electrically connected to metallization layer 120-1 via contact plug 118 and channel layer 106-1. In some embodiments, capacitor 108-2 may be electrically connected to metallization layer 120-2 via contact plug 118 and channel layer 106-2.

[0145] In some embodiments, capacitors 108-1 and 108-2 may be embedded within substrate 102. In some embodiments, each capacitor 108-1 and 108-2 may include a first electrode, a capacitor dielectric, and a second electrode (not shown in the figure). In some embodiments, from a plan view, each capacitor 108-1 and 108-2 may have a circular, oval, elliptical, or similar outline. In some embodiments, the capacitor dielectric may surround the first electrode. In some embodiments, the second electrode may surround the first electrode. In some embodiments, the second electrode may surround the capacitor dielectric. In some embodiments, the capacitor dielectric may be disposed between the first electrode and the second electrode.

[0146] The first electrode and / or the second electrode may contain semiconductor materials or conductive materials. Semiconductor materials may contain polycrystalline silicon or other suitable materials, and conductive materials may contain tungsten, copper, aluminum, tantalum or other suitable materials.

[0147] The capacitor dielectric may contain dielectric materials such as silicon oxide, tungsten oxide, zirconium oxide, copper oxide, aluminum oxide, hafnium oxide, or similar materials.

[0148] In some embodiments, the contact plug 118 may be disposed between the capacitor 108-1 and the channel layer 106-1. The contact plug 118 may comprise a semiconductor material or a conductive material.

[0149] Dielectric layer 110 may be disposed on substrate 102, and dielectric layer 110 may contain silicon oxide (SiO2). x ), silicon nitride (Si x N y Materials that can be silicon oxynitride (SiON), silicon phosphosilicate glass (PSG), borosilicate phosphosilicate glass (BPSG), low-k dielectric materials (k<4), or other suitable materials. Dielectric layer 110 can also be called the lower dielectric layer.

[0150] Dielectric layer 114 may be disposed on metallization layer 116-1 and metallization layer 116-2, and dielectric layer 114 may contain silicon oxide (SiO2). x ), silicon nitride (Si x N y Materials used include silicon oxynitride (SiON), silicon phosphosilicate glass (PSG), borosilicate phosphosilicate glass (BPSG), low-k dielectric materials (k<4), or other suitable materials. In some embodiments, metallization layers 120-1 and 120-2 may be disposed on dielectric layer 114. Dielectric layer 115 may also be referred to as the upper dielectric layer.

[0151] In some embodiments, each gate dielectric 104-1 and gate dielectric 104-2 may penetrate the dielectric layer 114. In some embodiments, each gate dielectric 104-1 and gate dielectric 104-2 may penetrate the dielectric layer 110. In some embodiments, each gate dielectric 104-1 and gate dielectric 104-2 may penetrate the metallization layer 116-1 or the metallization layer 116-2.

[0152] In some embodiments, each channel layer 106-1 and channel layer 106-2 may penetrate the dielectric layer 114. In some embodiments, each channel layer 106-1 and channel layer 106-2 may penetrate the dielectric layer 110. In some embodiments, each channel layer 106-1 and channel layer 106-2 may penetrate the metallization layer 116-1 or the metallization layer 116-2.

[0153] In some embodiments, a transistor may include a word line (e.g., metallization layer 116-1 or metallization layer 116-2), a gate dielectric 104-1 or gate dielectric 104-2, and a channel layer 106-1 or channel layer 106-2. During a read operation, the word line (e.g., metallization layer 116-1 or metallization layer 116-2) can be asserted, turning on a transistor that may be formed in a peripheral region. The enabled transistor allows a sense amplifier to read the voltage across a capacitor (e.g., capacitor 108-1 or capacitor 108-2) via the bit line (e.g., metallization layer 120-1 or metallization layer 120-2). During a write operation, data to be written can be provided on the bit line (e.g., metallization layer 120-1 or metallization layer 120-2) when the word line (e.g., metallization layer 116-1 or metallization layer 116-2) is asserted.

[0154] In this embodiment, the metallization layer 116-1 may have a protrusion 116-1p, and the channel layer 106-1 may be partially surrounded by the protrusion 116-1p. The protrusion 116-1p allows for a relatively large overlap error when patterning the metallization layer 116-1, which can prevent leakage current between the metallization layer 116-1 and the channel layer 106-1.

[0155] In this embodiment, the protrusion 116-1p of the metallization layer 116-1 can face the metallization layer 116-2, and the protrusion 116-2p of the metallization layer 116-2 can face the metallization layer 116-1, thereby reducing the size of the semiconductor device 100.

[0156] Figure 2A and Figure 2B Semiconductor element 200 is illustrated in some embodiments of this disclosure, wherein Figure 2A It is a two-dimensional schematic diagram and Figure 2B It is along Figure 2A The diagram shows a cross-sectional view along section B-B'. It should be noted that, for clarity, Figure 2A Some components or features are omitted. Semiconductor element 200 is similar to... Figure 1A and Figure 1B The semiconductor element 100 shown has the following differences.

[0157] like Figure 2A As shown, the semiconductor device 200 may include a substrate 202, a plurality of metallization layers 216-1 and 216-2, a plurality of gate dielectrics 204-1 and 204-2, a plurality of channel layers 206-1 and 206-2, and a dielectric layer 212.

[0158] Each metallization layer 216-1 and metallization layer 216-2 may extend along the Y-axis, and each metallization layer 216-1 and metallization layer 216-2 may be parallel. In some embodiments, each metallization layer 216-1 and metallization layer 216-2 may be physically separated. The material of metallization layers 216-1 and metallization layer 216-2 may be the same as or similar to the material of metallization layer 116-1. In some embodiments, metallization layers 216-1 and metallization layer 216-2 may be referred to as top character lines. In some embodiments, metallization layers 116-1 and metallization layer 116-2 (e.g., Figure 2B (As shown) can be called the bottom character line.

[0159] In some embodiments, the material of substrate 202 may be the same as or similar to the material of substrate 102. In some embodiments, substrate 202 may also be referred to as a top substrate. In some embodiments, substrate 102 (e.g. Figure 2B (As shown) can also be called the bottom substrate.

[0160] Metallization layer 216-1 may include a sidewall 216s1 and an opposite sidewall 216s2, the sidewall 216s2 of metallization layer 216-1 facing metallization layer 216-2. In some embodiments, metallization layer 216-1 may have a protrusion 216-1p. In some embodiments, the protrusion 216-1p of metallization layer 216-1 may face metallization layer 216-2. In some embodiments, the sidewall 216s2 of metallization layer 216-1 may protrude toward metallization layer 216-2, thereby defining the protrusion 216-1p.

[0161] Metallization layer 216-2 may include a sidewall 216s3 and an opposite sidewall 216s4, wherein the sidewall 216s3 of metallization layer 216-2 may face metallization layer 216-1. In some embodiments, metallization layer 216-2 may have a protrusion 216-2p. In some embodiments, the protrusion 216-2p of metallization layer 216-2 may face metallization layer 216-1. In some embodiments, the sidewall 216s3 of metallization layer 216-2 may protrude toward metallization layer 216-1, thereby defining the protrusion 216-2p.

[0162] In some embodiments, the protrusions 216-1p of metallization layer 216-1 and 216-2p of metallization layer 216-2 may be staggered. In some embodiments, the protrusions 216-1p of metallization layer 216-1 and 216-2p of metallization layer 216-2 are misaligned along the X-axis. In some embodiments, the protrusions 216-1p of metallization layer 216-1 may not overlap with the protrusions 216-2p of metallization layer 216-2 along the X-axis. In other embodiments, the protrusions 216-1p of metallization layer 216-1 may partially overlap with the protrusions 216-2p of metallization layer 216-2 along the X-axis. In some embodiments, from a planar schematic view, the protrusions 216-1p and / or 216-2p may have a semi-circular or semi-elliptical profile; however, this disclosure is not intended to be limiting.

[0163] In some embodiments, metallization layer 216-1 may be disposed on metallization layer 120-1. In some embodiments, metallization layer 216-2 may be disposed on metallization layer 120-2. In some embodiments, the horizontal plane where each metallization layer 216-1 and metallization layer 216-2 is located is higher than metallization layer 120-1 and metallization layer 120-2.

[0164] In some embodiments, gate dielectric 204-1 and gate dielectric 204-2 may be disposed on a sidewall of the word line (not shown in the figure). In some embodiments, gate dielectric 204-1 may be embedded in metallization layer 216-1. In some embodiments, gate dielectric 204-2 may be embedded in metallization layer 216-2. In some embodiments, gate dielectric 204-1 may be surrounded by metallization layer 216-1. In some embodiments, gate dielectric 204-2 may be surrounded by metallization layer 216-2. In some embodiments, each gate dielectric 204-1 and gate dielectric 204-2 may overlap with metallization layer 120-1 or metallization layer 120-2 along the Z-axis.

[0165] In some embodiments, the materials of gate dielectric 204-1 and gate dielectric 204-2 may be the same as or similar to the material of gate dielectric 104-1. In some embodiments, gate dielectric 204-1 and gate dielectric 204-2 may be referred to as the top gate dielectric layer, and gate dielectric 104-1 and gate dielectric 104-2 (as...) Figure 2B (As shown) can be referred to as the bottom gate dielectric layer.

[0166] In some embodiments, each channel layer 206-1 and channel layer 206-2 may be disposed on a sidewall (not shown) of the gate dielectric 204-1 or the gate dielectric 204-2. In some embodiments, each channel layer 206-1 and channel layer 206-2 may be embedded within the gate dielectric 204-1 or the gate dielectric 204-2. In some embodiments, each channel layer 206-1 and channel layer 206-2 may be surrounded by the gate dielectric 204-1 or the gate dielectric 204-2. In some embodiments, each channel layer 206-1 and channel layer 206-2 may be in contact with the gate dielectric 204-1 or the gate dielectric 204-2.

[0167] In some embodiments, each channel layer 206-1 and channel layer 206-2 may be disposed on one sidewall (not shown) of metallization layer 216-1 or metallization layer 216-2. In some embodiments, each channel layer 206-1 and channel layer 206-2 may be embedded within metallization layer 216-1 or metallization layer 216-2. In some embodiments, each channel layer 206-1 and channel layer 206-2 may be surrounded by metallization layer 216-1 or metallization layer 216-2.

[0168] In some embodiments, the materials of channel layers 206-1 and 206-2 may be the same as or similar to the material of channel layer 106-1. In some embodiments, channel layers 206-1 and 206-2 may be referred to as top channel layers, and channel layers 106-1 and 106-2 (e.g., Figure 2B (As shown) can be called the bottom channel layer.

[0169] In some embodiments, channel layers 206-1 and 206-2 may be staggered. In some embodiments, channel layer 206-1 may be offset from channel layer 206-2 along the X-axis. In some embodiments, channel layer 206-1 may not overlap with channel layer 206-2 along the X-axis. In some embodiments, channel layer 206-1 may overlap with protrusion 216-1p along the X-axis. In some embodiments, channel layer 206-2 may overlap with protrusion 216-2p along the X-axis.

[0170] In some embodiments, each channel layer 206-1 and channel layer 206-2 may overlap with metallization layer 120-1 or metallization layer 120-2 along the Z-axis. In some embodiments, as viewed in a plan view, each channel layer 206-1 and channel layer 206-2 may be completely surrounded by gate dielectric 204-1 or gate dielectric 204-2.

[0171] The sidewall 216s1 of the metallization layer 216-1 and the channel layer 206-1 have a distance D7 along the X-axis, and the sidewall 216s2 of the metallization layer 216-1 and the channel layer 206-1 have a distance D8 along the X-axis. In some embodiments, the distance D7 may be different from the distance D8. In some embodiments, the distance D8 may be greater than the distance D7.

[0172] The sidewall 216s3 of the metallization layer 216-2 and the channel layer 206-2 have a distance D9 along the X-axis, and the sidewall 216s4 of the metallization layer 216-2 and the channel layer 206-2 have a distance D10 along the X-axis. In some embodiments, the distance D9 may be different from the distance D10. In some embodiments, the distance D9 may be greater than the distance D10.

[0173] In some embodiments, the sidewalls 216s1 of metallization layer 216-1 may have relatively straight edges. In some embodiments, the sidewalls 216s4 of metallization layer 216-2 may have relatively straight edges. A distance D11 is provided along the X-axis between the sidewalls 216s1 and 216s4 of metallization layer 216-1. In some embodiments, the distance D11 may be substantially consistent or remain unchanged along the Y-axis.

[0174] There is a distance D12 along the X-axis between the sidewall 216-2s of metallization layer 216-1 and the sidewall 216s3 of metallization layer 216-2. In some embodiments, the distance D12 may vary along the Y-axis.

[0175] In some embodiments, dielectric layer 212 may be disposed on the sidewall of metallization layer 216-1 or metallization layer 216-2. In some embodiments, dielectric layer 212 may be disposed between metallization layer 216-1 and metallization layer 216-2. In some embodiments, each gate dielectric 204-1 and gate dielectric 204-2 may be physically separated from dielectric layer 212. In some embodiments, each gate dielectric 204-1 and gate dielectric 204-2 may be physically separated from dielectric layer 212 by metallization layer 216-1 or metallization layer 216-2. In some embodiments, the material of dielectric layer 212 may be the same as or similar to the material of dielectric layer 112.

[0176] In some embodiments, each channel layer 206-1 or channel layer 206-2 may be physically separated from the dielectric layer 212. In some embodiments, each channel layer 206-1 or channel layer 206-2 may be physically separated from the dielectric layer 212 by gate dielectric 204-1 and gate dielectric 204-2 and metallization layer 216-1 or metallization layer 216-2.

[0177] like Figure 2BAs shown, semiconductor element 200 may include unit 140-1, unit 140-2, unit 240-1, and unit 240-2. Each unit 240-1 and unit 240-2 is located at a horizontal plane higher than unit 140-1 and unit 140-2. In some embodiments, each unit 140-1 and unit 140-2 may also be referred to as a bottom unit. In some embodiments, each unit 240-1 and unit 240-2 may also be referred to as a top unit.

[0178] Unit 140-1 may include capacitor 108-1, channel layer 106-1, metallization layer 116-1, contact plug 118-1 and metallization layer 120-1.

[0179] Unit 140-2 may include capacitor 108-2, channel layer 106-2, metallization layer 116-2, contact plug 118-2 and metallization layer 120-2.

[0180] Unit 240-1 may include capacitor 208-1, channel layer 206-1, metallization layer 216-1, contact plug 218-1 and metallization layer 120-1.

[0181] Unit 240-2 may include capacitor 208-2, channel layer 206-2, metallization layer 216-2, contact plug 218-2 and metallization layer 120-2.

[0182] In some embodiments, the protrusion 216-1p of metallization layer 216-1 may partially or completely overlap with the protrusion 116-1p of metallization layer 116-1 along the Z-axis. In some embodiments, the protrusion 216-2p of metallization layer 216-2 may partially or completely overlap with the protrusion 116-2p of metallization layer 116-2 along the Z-axis.

[0183] In some embodiments, metallization layer 120-1 and metallization layer 120-2 may be disposed within a dielectric layer 150. In some embodiments, metallization layer 120-1 may be disposed between unit 140-1 and unit 240-1. In some embodiments, metallization layer 120-1 may be disposed between channel layer 106-1 and channel layer 206-1.

[0184] In some embodiments, metallization layer 120-1 may be disposed between channel layer 106-1 and channel layer 206-1. In some embodiments, metallization layer 120-1 may be disposed between metallization layer 116-1 and metallization layer 216-1. In some embodiments, metallization layer 120-1 may be disposed between capacitor 108-1 and capacitor 208-1. In some embodiments, metallization layer 120-1 may be disposed between channel layer 106-1 and capacitor 208-1. In some embodiments, metallization layer 120-1 may serve as a shared bit line between unit 140-1 and unit 240-1. In some embodiments, metallization layer 120-2 may serve as a shared bit line between unit 140-2 and unit 240-2.

[0185] In some embodiments, the metallization layer 120-1 can serve as a shared bit line, thereby reducing the size of the semiconductor element 200. Furthermore, the capacitance of the semiconductor element 200 can be increased.

[0186] Figure 3 This is a flowchart illustrating a method 300 for manufacturing a semiconductor element according to some embodiments of this disclosure.

[0187] Method 300 begins at operation 302, wherein a substrate is provided. In some embodiments, a first capacitor and a second capacitor may be formed within the substrate. In some embodiments, contact plugs may be formed within the substrate and above the first capacitor and the second capacitor. In some embodiments, a first dielectric layer may be formed on the substrate. In some embodiments, a conductive layer may be formed on the first dielectric layer. In some embodiments, a second dielectric layer may be formed on the conductive layer.

[0188] Method 300 continues to operation 304, wherein a patterning process may be performed to remove a portion of the first dielectric layer, the second dielectric layer, and the conductive layer. As a result, a first character line and a second character line are formed. Multiple openings may be formed to expose an upper surface of the substrate.

[0189] In some embodiments, the conductive layer may be patterned to form a first protrusion of the first character line. In some embodiments, the conductive layer may be patterned to form a second protrusion of the second character line. In some embodiments, the first protrusion may face the second character line. In some embodiments, the second protrusion may face the first character line.

[0190] Method 300 continues with operation 306, in which a third dielectric layer may be formed to fill the opening.

[0191] Method 300 continues with operation 308, wherein the second dielectric layer, the first word line, the second word line and a portion of the first dielectric layer may be removed, an opening may be formed in the first word line, and an opening may be formed in the second word line.

[0192] Method 300 continues with operation 310, wherein a first gate dielectric and a first channel layer may be formed in the opening of the first word line, and a second gate dielectric and a second channel layer may be formed in the opening of the second word line.

[0193] Method 300 continues with operation 312, wherein a first bit line and a second bit line can be formed on the first channel layer and the second channel layer respectively, thereby forming a semiconductor device.

[0194] Method 300 is merely exemplary and is not intended to limit this disclosure beyond what is expressly recited in the claims. Additional operations may be provided before, during, or after each operation of method 300, and for additional embodiments of this method, some of the described operations may be replaced, deleted, or reordered. In some embodiments, method 300 may include... Figure 3 Further operations not described herein. In some embodiments, method 300 may include Figure 3 One or more operations described in the document.

[0195] Figures 4A to 9A and Figures 4B to 9B This illustration describes one or more stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure, wherein... Figures 4A to 9A This is a planar schematic diagram, and Figures 4B to 9B respectively along Figures 4A to 9A A cross-sectional view along section line A-A'. It should be noted that, for clarity, some components illustrated in the cross-sectional view are not shown in the plan view.

[0196] like Figure 4A and Figure 4B As shown, a substrate 102 may be provided. In some embodiments, capacitors 108-1 and 108-2 may be formed within the substrate 102. In some embodiments, contact plugs 118 may be formed within the substrate 102 and above capacitors 108-1 and 108-2. In some embodiments, a dielectric layer 110 may be formed on the substrate 102. In some embodiments, a conductive layer 116 may be formed on the dielectric layer 110. In some embodiments, a dielectric layer 114 may be formed on the conductive layer 116. The dielectric layer 110 and dielectric layer 114 may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), low-pressure chemical vapor deposition (LPCVD), or other suitable processes. The conductive layer 116 may be formed by sputtering, PVD, or other suitable processes.

[0197] like Figure 5A and Figure 5B A patterning process can be performed to remove a portion of dielectric layer 110, dielectric layer 114, and conductive layer 116. As a result, metallization layers 116-1 and 116-2 are formed. Multiple openings 116r1 can be formed to expose the upper surface of substrate 102. The patterning process may include photolithography, etching, or other suitable processes. The photolithography process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, and drying (e.g., hard baking). The etching process may include, for example, dry or wet etching.

[0198] In some embodiments, the conductive layer 116 may be patterned to form a protrusion 116-1p of the metallization layer 116-1. In some embodiments, the conductive layer 116 may be patterned to form a protrusion 116-2p of the metallization layer 116-2. In some embodiments, the protrusion 116-1p may face the metallization layer 116-2. In some embodiments, the protrusion 116-2p may face the metallization layer 116-1.

[0199] like Figure 6A and Figure 6B As shown, a dielectric layer 112 can be formed to fill the opening 116r1. The dielectric layer 112 can be formed by CVD, ALD, PVD, LPCVD or other suitable processes.

[0200] like Figure 7A and Figure 7B As shown, dielectric layer 114, metallization layers 116-1 and 116-2, and a portion of dielectric layer 110 can be removed to form an opening 116r2-1 in metallization layer 116-1 and an opening 116r2-2 in metallization layer 116-2. In some embodiments, openings 116r2-1 and 116r2-2 may be staggered. In some embodiments, opening 116r2-1 may not overlap with opening 116r2-2 along the X-axis. In other embodiments, opening 116r2-1 may partially overlap with opening 116r2-2 along the X-axis.

[0201] like Figure 8A and Figure 8B As shown, a gate dielectric 104-1 and a channel layer 106-1 can be formed within opening 116r2-1, and a gate dielectric 104-2 and a channel layer 106-2 can be formed within opening 116r2-2. The gate dielectric 104-1 and gate dielectric 104-2, as well as the channel layers 106-1 and 106-2, can be formed by CVD, ALD, PVD, LPCVD, or other suitable processes.

[0202] like Figure 9A and Figure 9B As shown, metallization layers 120-1 and 120-2 can be formed on dielectric layer 112, thereby forming semiconductor device 100. Metallization layers 120-1 and 120-2 can be formed by sputtering, PVD or other suitable processes.

[0203] In this embodiment, the character lines (e.g., 116-1 and / or 116-2) have protrusions (e.g., 116-1p and 116-2p). These protrusions allow for relatively large overlap errors when the character lines are patterned to form openings (e.g., 116r2-1 and / or 116r2-2) in which the channel layer (e.g., 106-1 and / or 106-2) is formed. Therefore, leakage current between the character lines and the channel layer can be prevented.

[0204] One aspect of this disclosure provides a semiconductor device comprising a substrate, a dielectric layer, a first metallization layer, a first channel layer, a second metallization layer, and a second channel layer. The dielectric layer is disposed on the substrate, the first metallization layer is disposed within the dielectric layer and extends along a first direction, the first channel layer is surrounded by the first metallization layer, the second metallization layer is disposed within the dielectric layer and extends along the first direction, and the second channel layer is surrounded by the second metallization layer, wherein the first metallization layer includes a first protrusion projecting toward the second metallization layer.

[0205] Another aspect of this disclosure provides a semiconductor device comprising a bottom substrate, a first bottom cell, a top substrate, a first top cell, and a shared bit line. The first bottom cell includes a first bottom capacitor disposed within the bottom substrate, and also includes a first bottom word line disposed on the bottom substrate and extending along a first direction. The first bottom cell further includes a first bottom channel layer surrounded by the first bottom word line. The first top cell includes a first top capacitor disposed within the top substrate, and also includes a first top word line disposed on the top substrate and extending along the first direction. The first top cell further includes a first top channel layer surrounded by the first top word line. The shared bit line is disposed between the first bottom cell and the first top cell and extends along a second direction substantially perpendicular to the first direction.

[0206] Another aspect of this disclosure provides a method for manufacturing a semiconductor device, the method comprising providing a substrate. The method also includes forming a conductive layer on the substrate. The method further includes patterning the conductive layer to form a first metallization layer and a second metallization layer extending along a first direction, wherein the first metallization layer includes a first protrusion projecting toward the second metallization layer. Additionally, the method includes forming a first channel layer within the first metallization layer and forming a second channel layer within the second metallization layer.

[0207] Embodiments of this disclosure provide a semiconductor device that may include word lines with protrusions. The protrusions allow for relatively large overlap errors when the word lines are patterned to form openings in the channel layer, preventing leakage current between the word lines and the channel layer.

[0208] While this disclosure and its advantages have been detailed, it should be understood that various changes, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes discussed above can be implemented in different ways and can be replaced by other processes or combinations thereof.

[0209] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A semiconductor element, comprising: One substrate; A dielectric layer is disposed on the substrate; A first metallization layer is disposed within the dielectric layer and extends along a first direction; A first channel layer, surrounded by the first metallization layer; A second metallization layer is disposed within the dielectric layer and extends along the first direction; as well as A second channel layer, surrounded by the second metallization layer. The first metallization layer includes a first protrusion that protrudes toward the second metallization layer; The first metallization layer has a first sidewall and a second sidewall opposite to the first sidewall. The second sidewall faces the second metallization layer, and a first distance between the first sidewall and the first channel layer is different from a second distance between the second sidewall and the first channel layer.

2. The semiconductor device of claim 1, wherein the second metallization layer includes a second protrusion projecting toward the first metallization layer.

3. The semiconductor element of claim 2, wherein the first protrusion is misaligned with the second protrusion along a second direction substantially perpendicular to the first direction.

4. The semiconductor element of claim 2, wherein the first channel layer overlaps the first protrusion along a second direction substantially perpendicular to the first direction.

5. The semiconductor element of claim 4, wherein the second channel layer overlaps with the second protrusion along the second direction.

6. The semiconductor device of claim 5, wherein the first channel layer is misaligned with the second channel layer along the second direction.

7. The semiconductor element of claim 1, wherein the second distance is greater than the first distance.

8. The semiconductor device of claim 1, wherein the second metallization layer has a third sidewall and a fourth sidewall, the third sidewall facing the first metallization layer, and a third distance between the third sidewall and the second channel layer is different from a fourth distance between the fourth sidewall and the second channel layer.

9. The semiconductor element of claim 8, wherein the third distance is greater than the fourth distance.

10. The semiconductor device of claim 8, wherein a fifth distance between the first sidewall of the first metallization layer and the fourth sidewall of the second metallization layer is aligned along the first direction.

11. The semiconductor device of claim 8, wherein a sixth distance between the second sidewall of the first metallization layer and the third sidewall of the second metallization layer varies along the first direction.

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