A quantum bit structure and a method of manufacturing the same, a quantum circuit, a quantum device

Abstract

The application provides a quantum bit structure and a manufacturing method thereof, a quantum circuit and a quantum device. The manufacturing method of the quantum bit structure comprises the following steps: providing a substrate with a through hole, and the through hole is filled with a filling material; forming a quantum bit structure on the surface of the substrate, and a part of the quantum bit structure is located on the through hole; removing the filling material in the through hole to obtain the quantum bit structure. By manufacturing a part of the quantum bit structure above the through hole, the radio frequency field distribution associated with the capacitance can be changed, and then the resonance frequency of the quantum bit and the participation rate of the radio frequency current and the loss source can be changed, so that the amount of total radio frequency loss can be reduced, and the effect of prolonging the coherence time and the life of the quantum bit is achieved.

Description

Technical Field

[0001] This application relates to the field of quantum chip technology, and in particular to a quantum bit structure and its manufacturing method, quantum circuits, and quantum devices. Background Technology

[0002] Currently, when manufacturing superconducting quantum bits (qubits or qbits), the main parameters for evaluating their performance include the quantum bit's lifetime and coherence time. A longer coherence time allows the quantum bit more time to perform computational operations, thus providing more time to execute quantum algorithms. Coherence time is affected by various factors such as system noise, environmental interference, and hardware limitations. Summary of the Invention

[0003] The purpose of this application is to provide a method for manufacturing a quantum bit structure to extend the coherence time and lifetime of the quantum bit. The technical solution is as follows:

[0004] In a first aspect, this application provides a method for manufacturing a quantum bit structure, comprising the steps of:

[0005] A substrate having through holes and the through holes being filled with a filling material;

[0006] A quantum bit structure is formed on the surface of the substrate, with a portion of the quantum bit structure located on the via.

[0007] The filling material inside the through-hole is removed to obtain the quantum bit structure.

[0008] In one embodiment of this application, the via formation method includes: forming a hard mask layer on the front side of a substrate and forming an etching stop layer on the back side of the substrate; making an opening in the hard mask layer and etching through the substrate to form a via; and removing the etching stop layer and the hard mask layer.

[0009] In one embodiment of this application, the substrate is selected from silicon; the material of the hard mask layer is selected from silicon dioxide; and the material of the etching stop layer is selected from aluminum.

[0010] In one embodiment of this application, the thickness ratio of the substrate to the hard mask layer is 100:(1-2); the thickness of the etching stop layer is 20nm-200nm.

[0011] In one embodiment of this application, the method of filling the through hole with a filling material includes: forming a seed layer of filling material on the inner surface of the through hole; and filling the through hole with the filling material.

[0012] In one embodiment of this application, the thickness of the seed layer is 5nm-30nm.

[0013] In one embodiment of this application, the diameter of the through hole minus the length of the electrode in the quantum bit structure is 5 μm - 30 μm.

[0014] In one embodiment of this application, the material of the quantum bit structure is selected from aluminum, tantalum, titanium nitride, niobium, or niobium titanium nitride.

[0015] In one embodiment of this application, the material of the quantum bit structure is selected from aluminum, the filling material is selected from copper, and the removal of the filling material inside the through-hole includes removal using a copper sulfate solution.

[0016] In one embodiment of this application, the material of the quantum bit structure is selected from tantalum, titanium nitride, niobium, or niobium titanium nitride, and the filling material is selected from copper or tin; wherein, when the filling material is selected from copper, removing the filling material inside the through-hole includes removal with copper sulfate solution; when the filling material is selected from tin, removing the filling material inside the through-hole includes removal with sodium hydroxide solution or hydrochloric acid solution.

[0017] Secondly, this application provides a quantum bit structure manufactured according to the method described in the first aspect of this application.

[0018] Thirdly, this application provides a quantum bit structure located on the surface of a substrate, wherein a through-hole is provided on the substrate, and a portion of the quantum bit structure is located on the through-hole of the substrate.

[0019] In one embodiment of this application, the diameter of the through hole minus the length of the electrode in the quantum bit structure is 5 μm - 30 μm.

[0020] In one embodiment of this application, the substrate is selected from silicon; the material of the quantum bit structure is selected from aluminum, tantalum, titanium nitride, niobium, or niobium titanium nitride.

[0021] Fourthly, this application provides a quantum circuit comprising a quantum bit structure manufactured by the manufacturing method described in the first aspect of this application or a quantum bit structure described in the third aspect of this application.

[0022] Fifthly, this application provides a quantum device comprising a quantum bit structure manufactured by the manufacturing method described in the first aspect of this application, a quantum bit structure described in the third aspect of this application, or a quantum circuit described in the fourth aspect of this application.

[0023] The beneficial effects of this application are:

[0024] This application provides a method for manufacturing a quantum bit structure. By forming a quantum bit structure on the surface of a substrate with through-holes filled with a filling material, and fabricating a portion of the quantum bit structure on the filling material, and then removing the filling material inside the through-holes, a portion of the quantum bit structure can be suspended above the through-holes, forming a suspended quantum bit structure. This can change the radio frequency field distribution associated with the capacitance, thereby changing the resonant frequency of the quantum bit and the participation rate of the radio frequency current and loss sources, reducing the total radio frequency loss, and extending the coherence time and lifetime of the quantum bit. This fabrication method does not damage the quantum bit structure and is easy to implement in terms of technology. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other embodiments can be obtained based on these drawings.

[0026] Figure 1 This is a schematic diagram of a method for manufacturing a quantum bit structure according to one embodiment of this application;

[0027] Figure 2 This is a schematic diagram of a method for forming a via on a substrate according to one embodiment of this application;

[0028] Figure 3 This is a schematic diagram of a method for filling a through hole in one embodiment of this application;

[0029] Figure 4 This is a schematic diagram (top view) of a quantum bit structure according to one embodiment of this application;

[0030] Figure 5 This is a schematic diagram (front view) of a quantum bit structure according to one embodiment of this application;

[0031] Figure 6 A test diagram of T1, representing a quantum bit structure according to one embodiment of this application;

[0032] Figure 7 P0 test diagram of T2, a qubit structure according to one embodiment of this application;

[0033] Figure 8 The P1 test diagram shows the T2 qubit structure of one embodiment of this application.

[0034] In the figure, 1-substrate; 2-via; 21-hole; 3-seed layer; 4-filling material; 5-qubit structure; 6-hard mask layer; 7-etch stop layer; 81-first electrode; 82-second electrode; 9-capacitor pad. Detailed Implementation

[0035] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on this application are within the scope of protection of this application.

[0036] In the description of the embodiments of this application, the technical terms "width", "thickness", "upper", "lower", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. They are only for the convenience of describing the embodiments of this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.

[0037] The inventors discovered that when a qubit structure is located on the surface of a silicon substrate, interfaces such as silicon-air (SA), metal-air (MA), or silicon-metal (SM) exist, which can easily cause radio frequency (RF) current loss, leading to a shortened coherence time and lifetime of the qubit. A levitated qubit structure can reduce the total RF loss, thus extending the coherence time and lifetime of the qubit. However, when fabricating a levitated qubit structure, if the qubit structure is first fabricated on the surface of the silicon substrate, and then vias are etched on the back side of the silicon substrate using deep silicon etching, the accuracy of the etching endpoints must be precise, requiring advanced front and back side etching techniques; otherwise, the final levitated qubit structure can easily be destroyed. Conversely, directly fabricating the qubit structure on the vias is technically difficult to achieve.

[0038] Through in-depth research, the inventors discovered that by first forming vias filled with a filler material on a substrate, then fabricating a portion of the qubit structure on the vias, and finally removing the filler material from the vias, a suspended qubit structure can be obtained, thus extending the coherence time and lifetime of the qubits. This method neither damages the qubit structure nor is it easily implemented in the manufacturing process.

[0039] Firstly, such as Figure 1 As shown in the figure, this application provides a method for manufacturing a quantum bit structure, including the following steps:

[0040] A substrate 1 is provided with a through hole 2 and the through hole 2 is filled with a filler material 4;

[0041] A quantum bit structure 5 is formed on the surface of substrate 1, and a portion of the quantum bit structure 5 is located on the through hole 2;

[0042] The filling material 4 inside the through-hole 2 is removed to obtain the quantum bit structure.

[0043] This application also provides a method for manufacturing a quantum bit structure, comprising the steps of: providing a substrate with a blind hole on the front side and the blind hole filled with a filling material; forming a quantum bit structure on the surface of the front side of the substrate, with a portion of the quantum bit structure located on the blind hole; etching the back side of the substrate at a position corresponding to the filling material until reaching the depth of the filling material; and then removing the filling material to form a through hole between the front and back sides of the substrate, thereby obtaining a suspended quantum bit structure. The blind hole described in this application refers to a hole on the front side of the substrate, while the back side of the substrate at the corresponding position remains the substrate.

[0044] The qubit structure 5 described in this application includes electrodes, and may also include qubits, capacitor regions, quantum gates, control units, and other structures required for quantum chips. The electrodes are located above the via 2. Other specific parts of the qubit structure 5 located above the via 2 can be adjusted according to actual needs; for example, the capacitor region and qubits can be located above the via 2. The qubit structure 5 may include two gapped capacitor pads, with a portion of each capacitor pad located above the via 2 and the other portion located on the surface of the substrate 1. The electrode between the capacitor pads (not shown in the figure) is located above the via 2.

[0045] The via 2 described in this application is filled with a filling material 4, which can fill the entire interior of the via 2. When a quantum bit structure 5 is formed on the surface of the substrate 1, the electrodes, Josephson junctions and other parts can be fabricated on the filling material 4 of the via 2. After removing the filling material 4 inside the via 2, the electrodes, Josephson junctions and other parts can be suspended above the via 2 of the substrate 1.

[0046] This application places a portion of the qubit structure 5 on the through-hole 2 and another portion on the surface of the substrate 1, thereby suspending a portion of the qubit structure 5 over the through-hole 2 of the substrate 1, forming a suspended qubit structure. Since the substrate 1 can be made of silicon and the qubit structure 5 can contain metals, this arrangement can reduce RF current loss caused by at least one of the silicon substrate-air interface, the metal-air interface in the qubit structure, or the metal interface in the silicon substrate-qubit structure, thereby reducing the total RF loss and extending the coherence time and lifetime of the qubit. This manufacturing method is simple, highly operable and repeatable, and does not damage the qubit structure 5 during the manufacturing process.

[0047] In one embodiment of this application, such as Figure 2 As shown, the method for forming the via 2 includes: forming a hard mask layer 6 on the front side of the substrate 1 and forming an etching stop layer 7 on the back side of the substrate 1; making an opening 21 in the hard mask layer 6 and etching through the substrate 1 to form the via 2; and removing the etching stop layer 7 and the hard mask layer 6. This method can efficiently fabricate the via 2 on the substrate 1 without damaging other parts of the substrate 1.

[0048] This application does not specifically limit the method used to etch through the substrate 1 to form the via 2, as long as the purpose of forming the via 2 in the substrate 1 can be achieved. For example, the Bosch process can be used for etching through. The Bosch process is a process used in integrated circuit manufacturing to deposit an etched thin film on the lateral edge of the etched area in order to prevent or reduce lateral etching. It is a commonly used silicon etching method to obtain a high aspect ratio. It uses multiple alternating deposition and etching processes. For example, C4F8 gas is used for deposition and SF6 is used for etching. C4F8 forms a fluorine carbide polymer in the dissociation plasma, which is deposited on the silicon surface to form a barrier that can prevent fluorine ions from reacting chemically with silicon and improve the etching selectivity. SF6 is used as the etching gas, which generates SxFy ions and F- active free radicals in the plasma. These ions are bombarded towards the substrate in a near-vertical direction under the action of an electric field.

[0049] In one embodiment of this application, the substrate 1 is made of silicon; the hard mask layer 6 is made of silicon dioxide and / or silicon oxynitride; and the etching stop layer 7 is made of aluminum. The hard mask layer 6 described in this application can be a single-layer structure or a stacked structure. A single-layer hard mask layer can be a silicon oxynitride layer or a silicon dioxide layer. A stacked structure can be a silicon oxynitride layer and a silicon dioxide layer stacked sequentially along the substrate thickness direction, or a silicon dioxide layer and a silicon oxynitride layer stacked sequentially along the substrate thickness direction. The etching stop layer 7 described in this application can be a single-layer aluminum layer, which can achieve the etching stop effect while minimizing costs.

[0050] In one embodiment of this application, the method for creating an opening 21 in the hard mask layer 6 can be etching, and the etching gas can be trifluoromethane. To create the opening 21 in the hard mask layer 6, this application can use S1813 photoresist for front-side photolithography, and then use trifluoromethane gas to etch the opening in the hard mask layer.

[0051] In one embodiment of this application, the etching stop layer 7 can be removed using an etching solution. The type of etching solution can be determined based on the material of the etching stop layer. For example, if the material of the etching stop layer 7 is aluminum, an aluminum etching solution can be used to remove the etching stop layer 7.

[0052] In one embodiment of this application, the method for removing the hard mask layer 6 may be immersion in a BOE solution (buffered oxide etchant). The immersion time can be adjusted according to actual needs, aiming to completely remove the hard mask layer 6, for example, immersion for 30 minutes. The BOE solution described in this application may be a mixture of 49wt% HF aqueous solution and 40wt% NH4F aqueous solution in a volume ratio of 1:6.

[0053] In one embodiment of this application, the thickness ratio of the substrate 1 to the hard mask layer 6 is 100:(1-2). In another embodiment of this application, the thickness ratio of the substrate 1 to the hard mask layer 6 can be 100:(1-1.5), 100:(1.5-2), 100:(1.2-1.5), 100:(1.2-1.8), or 100:(1.5-1.8), or it can be 100:1, 100:1.1, 100:1.2, 100:1.3, 100:1.4, 100:1.5, 100:1.6, 100:1.7, 100:1.8, 100:1.8, 100:2.0, or any two of the above numerical ratios within a range formed by using them as endpoints. For substrates of different thicknesses, the thickness of the hard mask layer can be adjusted accordingly. When the thickness ratio of substrate 1 to hard mask layer 6 is controlled within the above range, a good etching effect can be obtained.

[0054] In one embodiment of this application, the thickness of the etching stop layer 7 is 20nm-200nm. In another embodiment, the thickness of the etching stop layer 7 can be 20nm-50nm, 20nm-100nm, 50nm-100nm, 50nm-150nm, 100nm-200nm, 100nm-150nm, 150nm-200nm, or 50nm-200nm, or it can be 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 110nm, 120nm, 130nm, 140nm, 150nm, 160nm, 170nm, 180nm, 190nm, 200nm, or any two of the above values ​​as endpoints. By controlling the thickness of the etching stop layer 7 within the above range, the etching stop effect can be achieved while minimizing costs.

[0055] In one embodiment of this application, such as Figure 3As shown, the method for filling the through-hole 2 with filler material 4 includes: forming a seed layer 3 of filler material 4 on the inner surface of the through-hole 2; and filling the through-hole 2 with filler material 4. The seed layer 3 of filler material 4 mentioned in this application refers to the seed layer 3 corresponding to filler material 4. For example, if filler material 4 is selected from copper, then the seed layer 3 of filler material 4 can be a copper seed layer. Forming a seed layer 3 of filler material 4 on the inner surface of the through-hole 2 is not a necessary step in this application; filler material 4 can be directly filled into the through-hole 2. Forming a seed layer 3 of filler material on the inner surface of the through-hole 2 first facilitates subsequent filling of the through-hole 2 with filler material 4. The type of material used in the seed layer 3 can be the same as or different from the type of material used in the filler material 4, as long as it facilitates subsequent filling of the through-hole 2 with filler material 4.

[0056] In one embodiment of this application, the thickness of the seed layer 3 is 5nm-30nm. In another embodiment of this application, the thickness of the seed layer 3 can be 5nm-10nm, 5nm-15nm, 5nm-20nm, 5nm-25nm, 10nm-15nm, 10nm-20nm, 10nm-25nm, 15nm-20nm, 15nm-25nm, or 20nm-25nm, or it can be 5nm, 6nm, 7nm, 8nm, 9nm, 10nm, 11nm, 12nm, 13nm, 14nm, 15nm, 16nm, 17nm, 18nm, 19nm, 20nm, 21nm, 22nm, 23nm, 24nm, 25nm, 26nm, 27nm, 28nm, 29nm, 30nm, or any two of the above values ​​as endpoints within a range. The thickness of the seed layer 3 in this application is controlled within the above-mentioned range, which allows for better filling of the through-hole 2 with the filler material 4 in subsequent steps.

[0057] In one embodiment of this application, the process for forming the seed layer 3 can be selected from magnetron sputtering, thermal evaporation, or chemical vapor deposition. The seed layer 3 formed by the above processes can serve as the anode for subsequent electroplating processes, better filling the via 2 with the filler material 4 in subsequent steps. This application does not particularly limit the specific method of magnetron sputtering, thermal evaporation, or chemical vapor deposition, as long as a seed layer 3 of filler material can be formed on the inner surface of the via 2. For example: the magnetron sputtering coating process described in this application may include: using the coating material as the target cathode, bombarding the target material with argon ions to generate cathode sputtering, and sputtering the target material atoms onto the inner surface of the through hole 2 to form a seed layer 3; the thermal evaporation method described in this application may include: placing the substrate 1 with the through hole 2 to be coated in a vacuum chamber, heating the coating material to evaporate and vaporize it to deposit it on the inner surface of the through hole 2 and form a seed layer 3; the chemical vapor deposition method described in this application may include: the reactive gas diffuses into the inner surface of the through hole 2, the reactive gas is adsorbed on the inner surface of the through hole 2, and a chemical reaction occurs on the inner surface of the through hole 2 to form a solid deposit.

[0058] like Figure 3 As shown, when a seed layer 3 of filling material 4 is formed on the inner surface of the through hole 2, a seed layer 3 is also formed on the surface of the substrate 1; before filling the through hole 2, the seed layer 3 on the surface of the substrate 1 is removed. Removing the seed layer 3 on the surface of the substrate 1 allows the filling material 4 to be filled only inside the through hole 2 in subsequent steps.

[0059] This application does not impose any particular limitation on the method used to remove the seed layer 3 formed on the surface of the substrate 1. For example, a grinding and polishing method can be used. The grinding and polishing method can easily remove the seed layer 3 formed on the surface of the substrate 1 without damaging the substrate 1. This application does not impose any particular limitation on the specific method of grinding and polishing, as long as it can remove the seed layer 3 formed on the surface of the substrate 1; for example, a grinding fluid can be used to grind the seed layer 3 formed on the surface of the substrate 1.

[0060] In one embodiment of this application, the process of filling the through-hole 2 with filler material 4 can be selected from electroplating or 3D filling. Using the above-mentioned process to fill the filler material 4 results in good filling effect and low cost. This application does not particularly limit the specific method of electroplating or 3D filling, as long as the through-hole 2 is filled with filler material 4; for example, the electroplating process may include: using the filler material (e.g., copper) as the anode, the substrate with through-holes to be plated as the cathode, and metal ions (e.g., copper ions) in the plating solution being reduced to metal atoms (e.g., copper atoms) through an electrode reaction under the action of an external electric field, and then depositing the metal (e.g., copper) on the cathode, thereby achieving the effect of filling the through-hole with metal (e.g., copper).

[0061] In this application, when filling the via 2, a filling material layer may be formed on the surface of the substrate 1; before forming the qubit structure 5 on the surface of the substrate 1, the filling material layer on the surface of the substrate 1 is removed. Since the electroplating process is not directional, a small amount of filling material layer may be deposited on the surface of the substrate 1 after electroplating, which will affect the subsequent surface homogenization and fabrication of the qubit structure 5. Therefore, the filling material layer on the surface of the substrate 1 can be removed.

[0062] This application does not impose any particular limitation on the method for removing the filler material layer on the surface of substrate 1; for example, a grinding and polishing method can be used. The grinding and polishing method easily removes the filler material layer formed on the surface of substrate 1. This application does not impose any particular limitation on the specific method of grinding and polishing, as long as it can remove the filler material layer formed on the surface of substrate 1; for example, a grinding fluid can be used to grind the filler material layer formed on the surface of substrate 1.

[0063] In one embodiment of this application, the diameter of the through-hole 2 is equal to the length of the electrode in the qubit structure 5, which is between 5 μm and 30 μm. In one embodiment of this application, the diameter of the through-hole 2 and the length of the electrode in the quantum bit structure 5 can be 5μm-10μm, 5μm-15μm, 5μm-20μm, 10μm-15μm, 10μm-20μm, 10μm-30μm, 15μm-20μm, 15μm-30μm or 20μm-30μm, or it can be 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, 11μm, 12μm, 13μm, 14μm, 15μm, 16μm, 17μm, 18μm, 19μm, 20μm, 21μm, 22μm, 23μm, 24μm, 25μm, 26μm, 27μm, 28μm, 29μm, 30μm or any two of the above values ​​as the endpoints within the range.

[0064] In this application, the diameter of the via 2 can be determined based on the length of the electrode in the qubit structure 5. For example, if the length of the electrode in the qubit structure 5 is 20 μm, the diameter of the via 2 can be set to 25 μm-50 μm, preferably 25 μm-35 μm, and more preferably 30 μm. The qubit structure described in this application includes one electrode, or multiple electrodes with the same or different orientations. If multiple electrodes exist, the length of the electrode in the qubit structure refers to the length of the longest electrode, so that all electrodes are completely suspended above the via. The electrodes can be connected to the substrate surface via capacitor pads. This application does not limit the specific structure of the qubit structure; for example, such as... Figure 4As shown, the qubit structure 5 includes a capacitor pad 9, a first electrode 81 and a second electrode 82 in different orientations. Both the first electrode 81 and the second electrode 82 are completely suspended above the via 2. The first electrode 81 and the second electrode 82 are respectively connected to the surface of the substrate 1 through the capacitor pad 9. This application controls the diameter of the via 2 and the length of the electrodes in the qubit structure 5 within the aforementioned range, which can better reduce the total radio frequency loss, thereby extending the coherence time and lifetime of the qubit.

[0065] In one embodiment of this application, the material of the quantum bit structure 5 is selected from aluminum, tantalum, titanium nitride, niobium, or niobium-titanium nitride. The quantum bit structure 5 described in this application may include electrodes, quantum bits, capacitor regions, quantum gates, control units, and other structures required for quantum chips, and its materials are selected from the above-mentioned range of materials, which enables the quantum bit structure to have the required performance.

[0066] In one embodiment of this application, the material of the quantum bit structure 5 is selected from aluminum, and the filling material 4 is selected from copper. Removing the filling material 4 inside the through-hole 2 includes removal using a copper sulfate solution. In another embodiment of this application, the material of the seed layer 3 is selected from copper. When removing the metallic copper (including the filling material 4 and the seed layer 3, which can be the same or different materials) inside the through-hole 2 using a copper sulfate solution, copper sulfate has high selectivity for copper metal and will not react with aluminum, silicon, etc., thus not damaging the aluminum-made quantum bit structure 5 and the silicon substrate 1.

[0067] In one embodiment of this application, the material of the qubit structure 5 is selected from tantalum, titanium nitride, niobium, or niobium titanium nitride, and the filling material 4 is selected from copper. Removal of the filling material inside the through-hole 2 includes removal using a copper sulfate solution. In another embodiment of this application, the material of the seed layer 3 is selected from copper. When removing the metallic copper inside the through-hole 2 (including the filling material 4 and the seed layer 3, the types of materials used for the seed layer 3 and the filling material 4 can be the same or different) using a copper sulfate solution, copper sulfate has high selectivity for copper metal and will not react with aluminum, silicon, etc., thus not damaging the qubit structure 5 made of tantalum, titanium nitride, niobium, or niobium titanium nitride and the silicon substrate 1.

[0068] In one embodiment of this application, the material of the quantum bit structure 5 is selected from tantalum, titanium nitride, niobium, or niobium titanium nitride, and the filling material 4 is selected from tin. Removing the filling material 4 inside the through-hole 2 includes removal using a sodium hydroxide solution or a hydrochloric acid solution. In one embodiment of this application, the material of the seed layer 3 is selected from tin. When removing the metallic tin inside the through-hole 2 (including the filling material 4 and the seed layer 3, the seed layer 3 and the filling material 4 can be the same or different types of materials) using a sodium hydroxide solution or a hydrochloric acid solution, since the sodium hydroxide solution or hydrochloric acid solution has high selectivity for tin metal, the sodium hydroxide solution or hydrochloric acid solution will not react with tantalum, titanium nitride, niobium, niobium titanium nitride, silicon, etc., and therefore will not damage the quantum bit structure 5 and the silicon substrate 1 made of tantalum, titanium nitride, niobium, or niobium titanium nitride.

[0069] Figure 6 This is a test graph of the T1 time of a qubit structure according to one embodiment of this application. T1 refers to the longitudinal relaxation time, also known as the energy relaxation time, which represents the time scale of the qubit decaying from a high-energy state to a low-energy state. In quantum computing, when a qubit is in a high-energy state, its energy gradually decays due to its interaction with the environment, causing the qubit to gradually lose coherence and eventually transition to a low-energy state. T1 characterizes this decay time scale. The T1 curve is a graph describing the process of the qubit decaying from a high-energy state to a low-energy state, representing the initial relaxation process of the qubit in the high-energy state. The slope of the curve is related to the decay rate, and the T1 time represents the decay time scale of the qubit. The longer the T1 time, the longer the storage time of the qubit in the high-energy state, and therefore the lower the error rate in quantum computing. This application performs a series of measurements on the qubit structure and then fits the T1 curve based on the measurement data, as shown in the figure below. Figure 6 As shown. From Figure 6 As can be seen, T1 is 4619 ns.

[0070] Figure 7 P0 test diagram of T2, a qubit structure according to one embodiment of this application; Figure 8This is a P1 test plot of the T2 of a qubit structure according to one embodiment of this application. T2 refers to the transverse relaxation time, also known as the coherence time, which represents the timescale by which the qubit maintains coherence between coherent superposition states. In quantum computing, a specific relative phase exists between qubits in coherent superposition states, which allows the special properties of quantum computing to function. However, due to interactions with the environment, the relative phase between qubits gradually accumulates errors, leading to a decay in coherence. T2 characterizes the time it takes for the qubits to maintain coherence. The T2 curve describes the relative phase maintenance time between coherent superposition states of a qubit, and the T2 time represents the coherence maintenance timescale of the qubit. The longer the T2 time, the longer the relative phase maintenance time between qubits, allowing for more complex quantum computing operations. When a qubit is measured, it collapses into either the ground state or an excited state. The P0 curve describes how the probability of the qubit being in the ground state gradually increases over time. The P1 curve represents the evolution of the probability of the qubit being in an excited state over time, describing how the probability of the qubit being in an excited state gradually increases over time. This application performs a series of measurements on the qubit structure, and then fits the measurement data to obtain the P0 and P1 curves of T2, as detailed below. Figure 7 and Figure 8 As shown. From Figure 7 and Figure 8 As can be seen, T2 is 1395ns.

[0071] Secondly, such as Figure 5 As shown, this application embodiment provides a quantum bit structure, the quantum bit structure 5 is located on the surface of a substrate 1, the substrate 1 is provided with a through hole 2, and a part of the quantum bit structure 5 is located on the through hole 2 of the substrate 1.

[0072] The qubit structure 5 described in this application includes electrodes, and may also include qubits, capacitor regions, quantum gates, control units, and other structures required for quantum chips. The electrodes are located above the via 2. Other specific parts of the qubit structure 5 located above the via 2 can be adjusted according to actual needs; for example, the capacitor region and qubits can be located above the via 2. The qubit structure 5 may include two gapped capacitor pads, with a portion of each capacitor pad located above the via 2 and the other portion located on the surface of the substrate 1. The electrode between the capacitor pads (not shown in the figure) is located above the via 2.

[0073] This application places a portion of the qubit structure 5 on the through-hole 2 and another portion on the surface of the substrate 1, thereby suspending the qubit structure 5 over the through-hole 2 of the substrate 1 to form a suspended qubit structure. Since the substrate 1 can be made of silicon and the qubit structure 5 can contain metals, this arrangement can reduce RF current loss caused by at least one of the silicon substrate-air interface, the metal-air interface in the qubit structure, or the metal interface in the silicon substrate-qubit structure, thereby reducing the total RF loss and extending the coherence time and lifetime of the qubit. This manufacturing method is simple, highly operable and repeatable, and does not damage the qubit structure 5 during the manufacturing process.

[0074] In one embodiment of this application, the diameter of the through hole 2 minus the length of the electrode in the quantum bit structure 5 is 5 μm - 30 μm. In one embodiment of this application, the diameter of the through-hole 2 and the length of the electrode in the quantum bit structure 5 can be 5μm-10μm, 5μm-15μm, 5μm-20μm, 10μm-15μm, 10μm-20μm, 10μm-30μm, 15μm-20μm, 15μm-30μm or 20μm-30μm, or it can be 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, 11μm, 12μm, 13μm, 14μm, 15μm, 16μm, 17μm, 18μm, 19μm, 20μm, 21μm, 22μm, 23μm, 24μm, 25μm, 26μm, 27μm, 28μm, 29μm, 30μm or any two of the above values ​​as the endpoints within the range.

[0075] In this application, the diameter of the via 2 can be determined based on the length of the electrode in the qubit structure 5. For example, if the length of the electrode in the qubit structure 5 is 20 μm, the diameter of the via 2 can be set to 25 μm-50 μm, preferably 25 μm-35 μm, and more preferably 30 μm. The qubit structure described in this application includes one electrode, or multiple electrodes with the same or different orientations. If multiple electrodes exist, the length of the electrode in the qubit structure refers to the length of the longest electrode, so that all electrodes are completely suspended above the via. The electrodes can be connected to the substrate surface via capacitor pads. This application does not limit the specific structure of the qubit structure; for example, such as... Figure 4As shown, the quantum bit structure 5 includes a capacitor pad 9, a first electrode 81 and a second electrode 82 in different orientations. Both the first electrode 81 and the second electrode 82 are completely suspended above the via 2. The first electrode 81 and the second electrode 82 are respectively connected to the surface of the substrate 1 through the capacitor pad 9. This application controls the diameter of the via 2 and the length of the electrodes in the quantum bit structure 5 within the aforementioned range, and can better reduce the total radio frequency loss, thereby achieving the effect of extending the coherence time and lifetime of the quantum bit.

[0076] In one embodiment of this application, the substrate 1 is selected from silicon; the material of the qubit structure 5 is selected from aluminum, tantalum, titanium nitride, niobium, or niobium titanium nitride. The qubit structure 5 described in this application may include electrodes, qubits, capacitor regions, quantum gates, control units, and other structures required for quantum chips, and its materials are selected from the above-mentioned range, which can enable the qubit structure to have the required performance.

[0077] Thirdly, embodiments of this application provide a quantum circuit comprising a quantum bit structure manufactured using the method described in the first aspect of this application or the quantum bit structure described in the second aspect of this application. The quantum circuit described in this application may comprise one or more quantum bit structures. Therefore, by changing the resonant frequency of the quantum bits and the participation rate of the radio frequency current and loss sources, the total radio frequency loss can be reduced, thereby extending the coherence time and lifetime of the quantum bits, better performing complex quantum computing operations, and improving computing power.

[0078] Fourthly, embodiments of this application provide a quantum device comprising a qubit structure fabricated using the methods described in the first aspect of this application, a qubit structure described in the second aspect of this application, or a quantum circuit described in the third aspect of this application. The quantum circuit described in this application may comprise one or more qubit structures. Therefore, by changing the resonant frequency of the qubits and the participation rate of the radio frequency current and loss sources, the total radio frequency loss can be reduced, thereby extending the coherence time and lifetime of the qubits, better performing complex quantum computing operations, and improving computing power.

[0079] The above description is only a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for manufacturing a quantum bit structure, characterized in that, Including the following steps: A substrate having through holes and the through holes being filled with a filling material; A quantum bit structure is formed on the surface of the substrate, with a portion of the quantum bit structure located on the via. The filling material inside the through-hole is removed to obtain the quantum bit structure; The diameter of the through hole minus the length of the electrode in the quantum bit structure is 5 μm - 30 μm; The material of the quantum bit structure is selected from aluminum, the filling material is selected from copper, and the removal of the filling material inside the through-hole includes removal using a copper sulfate solution; or The material of the quantum bit structure is selected from tantalum, titanium nitride, niobium, or niobium titanium nitride, and the filling material is selected from copper or tin; wherein, when the filling material is selected from copper, the removal of the filling material inside the through-hole includes removal with copper sulfate solution; when the filling material is selected from tin, the removal of the filling material inside the through-hole includes removal with sodium hydroxide solution or hydrochloric acid solution.

2. The manufacturing method according to claim 1, characterized in that, The method for forming the via includes: forming a hard mask layer on the front side of the substrate and forming an etching stop layer on the back side of the substrate; making an opening in the hard mask layer and etching through the substrate to form a via; and removing the etching stop layer and the hard mask layer.

3. The manufacturing method according to claim 2, characterized in that, The substrate is selected from silicon; the material of the hard mask layer is selected from silicon dioxide; and the material of the etching stop layer is selected from aluminum.

4. The manufacturing method according to claim 2, characterized in that, The thickness ratio of the substrate to the hard mask layer is 100:(1-2); the thickness of the etching stop layer is 20nm-200nm.

5. The manufacturing method according to claim 1, characterized in that, The method of filling the through hole with a filling material includes: forming a seed layer of filling material on the inner surface of the through hole; and filling the through hole with the filling material.

6. The manufacturing method according to claim 5, characterized in that, The thickness of the seed layer is 5nm-30nm.

7. A quantum bit structure manufactured by the manufacturing method according to any one of claims 1-6.

8. A quantum circuit comprising a quantum bit structure manufactured by any one of claims 1-6.

9. A quantum device comprising a qubit structure manufactured by any one of claims 1-6 or a quantum circuit as described in claim 8.

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