Reconfigurable hetero-junction memristor, regulation method, preparation method and application thereof

Abstract

The application discloses a reconfigurable heterojunction memristor, a regulation method, a preparation method and application thereof, and belongs to the field of micro-nano electronic devices. The functional layer of the application is composed of a PN heterojunction of n-AgO and p-Ag2O or a PN heterojunction of n-CuO2 and p-CuO. In the analog type, the application exhibits multi-value resistance change performance based on charge capture and release and exhibits self rectification characteristics, and a gate tube is not needed, which is conducive to large-scale integration. In the digital type, the existence of Ag / Cu ions in the layer helps the formation of Ag / Cu conductive wires, the conversion threshold voltage is small, and the application has the advantages of fast switching speed and low switching power consumption. The application realizes the PN heterojunction device of the N-type oxide layer and the P-type oxide layer through the electrochemical principle, realizes the analog-digital reconfiguration between the self-rectification analog device and the digital device, has a simple device structure, is suitable for various forms of in-memory computing, and has a wide application prospect.

Description

Technical Field

[0001] This invention belongs to the field of micro- and nano-electronic devices, and more specifically, relates to reconfigurable heterojunction memristors, their control methods, fabrication methods, and applications. Background Technology

[0002] Memristors can be classified into analog memristors and digital memristors based on how their conductance changes. Digital memristors have a significant threshold voltage and a large on / off ratio, as well as good state retention capabilities, and can be used as memory or selectors. Analog memristors, on the other hand, can have their resistance continuously increased and decreased in response to an applied signal, simulating the plasticity of neural synapses and storing synaptic weights, and can be used in computing units.

[0003] In memristor neural network structures, the hybrid use of analog and digital devices enables continuously adjustable image recognition processes in terms of both accuracy and speed. The simultaneous presence of analog and digital memristors in a single device provides a feasible solution for achieving tunable neuromorphic learning, thus promoting the development of brain-like morphological computing.

[0004] However, in the current research on heterojunction memristors, there is still no coexistence of analog and digital memristors with multi-resistivity characteristics. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the present invention aims to provide a reconfigurable heterojunction memristor, its control method, its fabrication method, and its applications, with the goal of achieving the coexistence of analog and digital memristors with multi-resistivity characteristics of heterojunction memristors.

[0006] To achieve the above objectives, in a first aspect, the present invention provides a reconfigurable heterojunction memristor, comprising a substrate, a lower electrode, a heterojunction intermediate layer, and an upper electrode stacked sequentially from bottom to top;

[0007] The heterojunction intermediate layer includes: an N-type oxide layer in contact with the lower electrode and a P-type oxide layer in contact with the upper electrode;

[0008] The N-type oxide layer is silver peroxide, and the P-type oxide layer is silver oxide;

[0009] Alternatively, the N-type oxide layer may be copper peroxide, and the P-type oxide layer may be copper oxide.

[0010] Preferably, the thickness of the N-type oxide layer is 3nm-200nm.

[0011] Preferably, the thickness of the P-type oxide layer is 3nm-200nm.

[0012] Preferably, both the lower electrode and the upper electrode are inert electrodes with a thickness of 2nm-200nm.

[0013] To achieve the above objectives, in a second aspect, the present invention provides a method for controlling a reconfigurable heterojunction memristor as described in the first aspect, comprising:

[0014] Analog to digital reconfiguration: The lower electrode is grounded, and a positive bias voltage is applied to the upper electrode that is in contact with the P-type oxide layer for a certain period of time, which causes the silver oxide layer / copper oxide layer to undergo an oxidation-reduction reaction and forms an Ag conductive wire / Cu conductive wire between the N-type oxide layer and the upper electrode. The two digital states of the device, on or off, are realized by the on and off of the conductive wire.

[0015] Digital to analog reconstruction: The lower electrode is grounded, and a negative bias voltage is applied to the upper electrode that is in contact with the P-type oxide layer for a certain period of time, which causes the Ag / Cu conductive wire between the N-type oxide layer and the upper electrode to break and return to the analog type. Based on charge trapping and release, it exhibits the analog characteristics of multi-value resistive switching.

[0016] Preferably, the analog memristor operates in a voltage range of -1V to 1V, and the digital memristor operates in a voltage range of -0.5V to 0.5V.

[0017] Preferably, the voltage applied to the memristor during the analog-to-digital conversion is greater than 1.2V, and the application time is greater than 1s.

[0018] Preferably, the voltage applied to the memristor during the digital-to-analog conversion is less than -0.8V, and the application time is greater than 1s.

[0019] To achieve the above objectives, in a third aspect, the present invention provides a method for fabricating a reconfigurable heterojunction memristor as described in the first aspect, comprising:

[0020] (1) The substrate material was ultrasonically cleaned in acetone, anhydrous ethanol and deionized water respectively, and then dried with nitrogen.

[0021] (2) Using magnetron sputtering, molecular beam epitaxy, atomic layer deposition, pulsed laser deposition or electrochemical methods, the lower electrode, the heterojunction intermediate layer and the upper electrode are sequentially prepared on the substrate;

[0022] (3) Dry the sample in acetone, anhydrous ethanol and deionized water respectively, and then dry the sample with nitrogen.

[0023] To achieve the above objectives, in a fourth aspect, the present invention provides an application of a reconfigurable heterojunction memristor as described in the first aspect, wherein the heterojunction memristor is used in neuromorphic neuron computing or threshold switching.

[0024] In summary, the technical solutions conceived by this invention have the following beneficial effects compared with the prior art:

[0025] (1) This invention discloses a reconfigurable heterojunction memristor, wherein the heterojunction intermediate layer includes: an N-type oxide layer in contact with the lower electrode and a P-type oxide layer in contact with the upper electrode; wherein the N-type oxide layer is silver peroxide and the P-type oxide layer is silver oxide; or, the N-type oxide layer is copper peroxide and the P-type oxide layer is copper oxide. The functional layer designed in this invention is composed of a PN heterojunction of n-AgO and p-Ag2O or a PN heterojunction of n-CuO2 and p-CuO. In analog mode, it exhibits multi-value resistive switching performance based on charge trapping and release, and shows self-rectification characteristics, eliminating the need for a selector transistor, which is beneficial for large-scale integration; in digital mode, due to the presence of Ag / Cu ions in the layer, it helps to form Ag / Cu conductive wires, resulting in a smaller switching threshold voltage and advantages of fast switching speed and low switching power consumption.

[0026] (2) This invention discloses a method for controlling an analog-to-digital reconfigurable heterojunction memristor. Under low bias, the heterojunction memristor exhibits analog-type IV characteristics during scanning. However, when a large positive bias is applied for a certain period, Ag / Cu ions in the P-type oxide layer migrate towards the cathode under the influence of the electric field, are reduced near the cathode, and form Ag / Cu conductive wires, thus transforming the device into a digital memristor dominated by these wires. Conversely, when a large negative bias is applied for a certain period, a reverse reaction occurs, causing the Ag / Cu conductive wires to break, and the device is reconfigured from digital to analog-type memristor again. This invention achieves analog-to-digital reconfigurability between self-rectified analog and digital devices using electrochemical principles for PN heterojunction devices with N-type and P-type oxide layers. The device structure is simple and suitable for various forms of in-memory computing, showing broad application prospects. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of a reconfigurable heterojunction memristor film structure provided by the present invention.

[0028] Figure 2 This is a schematic diagram illustrating the analog-to-digital reconfiguration principle of the analog-to-digital reconfigurable memristor provided in Embodiment 1 of the present invention.

[0029] Figure 3 This is a schematic diagram of the digital-to-analog reconfiguration principle of the analog-to-digital reconfigurable memristor provided in Embodiment 1 of the present invention.

[0030] Figure 4 The figure shows the linear IV curve of the memristor under continuous voltage scanning when it behaves as an analog memristor, as provided in Embodiment 2 of the present invention. The inset is the logarithmic IV curve of the current.

[0031] Figure 5This is a single double logarithmic IV curve under continuous voltage scanning when the memristor behaves as an analog memristor, as provided in Embodiment 2 of the present invention.

[0032] Figure 6 This is a linear IV curve under continuous voltage scanning after the memristor provided in Embodiment 2 of the present invention is reconstructed into a digital memristor through positive bias processing.

[0033] Figure 7 This is a full-band curve of the memristor provided in Embodiment 2 of the present invention under 50 consecutive pulse scans with an amplitude of 2V, a pulse width of 0.5μs, and a frequency of 1kHz.

[0034] Figure 8 This is a full-band curve of the memristor provided in Embodiment 2 of the present invention under 50 consecutive pulse scans with an amplitude of -2V, a pulse width of 0.5μs, and a frequency of 1kHz.

[0035] In all the accompanying drawings, the same reference numerals are used to denote the same elements or structures, wherein:

[0036] 1-Substrate, 2-Lower electrode, 3-N-type oxide layer, 4-P-type oxide layer, 5-Upper electrode. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0038] like Figure 1 As shown, the present invention provides a reconfigurable heterojunction memristor, comprising a substrate 1, a lower electrode 2, a heterojunction intermediate layer, and an upper electrode 5 stacked sequentially from bottom to top; the heterojunction intermediate layer includes: an N-type oxide layer 3 in contact with the lower electrode and a P-type oxide layer 4 in contact with the upper electrode; the N-type oxide layer is silver peroxide and the P-type oxide layer is silver oxide; or, the N-type oxide layer is copper peroxide and the P-type oxide layer is copper oxide.

[0039] Preferably, the thickness of the N-type oxide layer is 3nm-200nm.

[0040] Preferably, the thickness of the P-type oxide layer is 3nm-200nm.

[0041] Preferably, both the lower and upper electrodes are inert electrodes with a thickness of 2nm-200nm. The inert electrodes are Pt, ITO, Ti, W, Au, Pd, n-Si, or p-Si.

[0042] This invention provides a method for controlling the above-mentioned reconfigurable heterojunction memristor, comprising:

[0043] Analog to digital reconfiguration: The lower electrode is grounded, and a positive bias voltage is applied to the upper electrode that is in contact with the P-type oxide layer for a certain period of time, which causes the silver oxide layer / copper oxide layer to undergo an oxidation-reduction reaction and forms an Ag conductive wire / Cu conductive wire between the N-type oxide layer and the upper electrode. The two digital states of the device, on or off, are realized by the on and off of the conductive wire.

[0044] Digital to analog reconstruction: The lower electrode is grounded, and a negative bias voltage is applied to the upper electrode that is in contact with the P-type oxide layer for a certain period of time, which causes the Ag / Cu conductive wire between the N-type oxide layer and the upper electrode to break and return to the analog type. Based on charge trapping and release, it exhibits the analog characteristics of multi-value resistive switching.

[0045] Preferably, the analog memristor operates in a voltage range of -1V to 1V, and the digital memristor operates in a voltage range of -0.5V to 0.5V.

[0046] Preferably, the voltage applied to the memristor during the analog-to-digital conversion is greater than 1.2V, and the application time is greater than 1s.

[0047] Preferably, the voltage applied to the memristor during the digital-to-analog conversion is less than -0.8V, and the application time is greater than 1s.

[0048] This invention provides a method for fabricating the above-mentioned reconfigurable heterojunction memristor, comprising:

[0049] (1) The substrate material was ultrasonically cleaned in acetone, anhydrous ethanol and deionized water respectively, and then dried with nitrogen.

[0050] (2) Using magnetron sputtering, molecular beam epitaxy, atomic layer deposition, pulsed laser deposition or electrochemical methods, the lower electrode, the heterojunction intermediate layer and the upper electrode are sequentially prepared on the substrate;

[0051] (3) Dry the sample in acetone, anhydrous ethanol and deionized water respectively, and then dry the sample with nitrogen.

[0052] This invention provides an application of the above-mentioned reconfigurable heterojunction memristor, which is used in neuromorphic neuron computing or threshold switching.

[0053] Example 1

[0054] This embodiment is a five-layer planar memristor unit, with both the upper and lower electrodes made of Pt. The specific fabrication process is as follows:

[0055] (1) Select a silicon wafer with a crystal plane index of (100) and a thickness of 500 μm, and thermally grow a 1 μm thick SiO2 thin film layer on its surface as a substrate. Cut it into 1×1 cm samples, immerse them in acetone, clean them in an ultrasonic environment for 10-15 minutes, then immerse them in anhydrous ethanol and clean them in an ultrasonic environment for 5 minutes. The ultrasonic power is 40W. Finally, clean them with deionized water and dry them with a nitrogen gun.

[0056] (2) Take a clean sample and grow a Pt bottom electrode layer of about 100 nm on its surface using magnetron sputtering. To increase the adhesion between the Pt electrode layer and the substrate, a Ti adhesion layer of about 10 nm can be sputtered first using DC sputtering, and then the Pt target material can be sputtered using DC sputtering with a sputtering power of 200 W, an Ar atmosphere of 0.5 Pa, and a sputtering time of 1000 s.

[0057] (3) AgO / Ag2O layers were prepared by magnetron sputtering using an Ag target. AC sputtering was performed, and the thickness of the two dielectric layers was controlled by adjusting the sputtering time during the sputtering process to obtain the AgO and Ag2O dielectric layers respectively. In this embodiment, the AgO layer was grown using an O2:Ar ratio of 40:40, and the Ag2O layer was grown using an O2:Ar ratio of 24:40. The thicknesses of the AgO and Ag2O layers were 10 nm and 30 nm, respectively.

[0058] (4) A square photolithographic pattern is prepared on the dielectric layer Ag2O by photolithography. The size of the upper electrode is 100μm×100μm. The steps of the photolithography process are: homogenization, pre-baking, pre-exposure, post-baking, post-exposure (to make the photoresist inverted), and development.

[0059] (5) A 100 nm Pt layer is grown on the photolithographically processed sample by magnetron sputtering with a sputtering power of 200 W, an Ar atmosphere of 0.5 Pa, and a sputtering time of 1000 s to obtain the upper electrode.

[0060] (6) The thin film sample prepared in step (5) is soaked in acetone for 30-50 minutes, then washed with anhydrous ethanol and deionized water, and dried with nitrogen.

[0061] After completing the above steps, the Pt / AgO / Ag2O / Pt memristor unit is prepared.

[0062] like Figure 2As shown, when scanning under a small bias voltage, the Pt / AgO / Ag2O / Pt memristor unit IV characteristics exhibit analog memristor behavior. However, when a large positive bias voltage is applied for a certain period of time, Ag ions in the Ag2O dielectric layer will migrate towards the cathode under the action of the electric field, be reduced near the cathode, and form Ag conductive filaments. Thus, the device is transformed into a digital memristor dominated by Ag conductive filaments.

[0063] like Figure 3 As shown, when a large negative bias voltage is applied for a certain period of time, a reverse reaction will occur, causing the Ag conductive wire to break, and thus the Pt / AgO / Ag2O / Pt memristor unit will be reconstructed from a digital type to an analog type memristor again.

[0064] Example 2

[0065] In this embodiment, a semiconductor device analyzer B1500 was used to perform DC I / V scanning and high-speed switching characteristic tests on the memristor unit prepared in Example 1.

[0066] Figure 4 This is a linear I / V curve of the Pt / AgO / Ag2O / Pt memristor under continuous voltage scanning after fabrication without bias reconstruction, as provided in this embodiment of the invention. The inset is a logarithmic I / V curve of the current. Multiple consecutive positive DC I / V voltage scans and multiple consecutive negative scans are performed on the device unit. The positive voltage scan range is controlled between 0V and 1V, and the negative voltage scan range is controlled between -0.5V and 0V. The current limit is set to 100μA. Figure 4 It can be seen that during continuous unidirectional scanning, the hysteresis curve changes steadily in one direction, which is consistent with the characteristics of analog memristors, indicating that the device conductance can be continuously and directionally changed during repeated excitation. Furthermore, the current ratio between the forward and negative scans is extremely large. Compared to previous memristors that required a selector transistor, this analog memristor has self-rectification capabilities, thus eliminating the need for a selector transistor structure during large-scale integration and significantly improving integration density.

[0067] Figure 5This is a double logarithmic IV curve obtained from a single scan of the Pt / AgO / Ag2O / Pt memristor provided in this embodiment of the invention, before bias reconstruction processing. Multiple forward DC I / V voltage scans were performed on the device unit, and one scan was selected for double logarithmic processing. The forward voltage scan range was controlled between 0V and 1V, and the limiting current was set to 100μA. Fitting the double logarithmic IV curve reveals that the device's IV characteristics exhibit a clear two-segment power-law characteristic, consistent with the space charge-limited current effect based on charge trapping and releasing, indicating that the physical mechanism of its simulated characteristics is a charge trapping and releasing mechanism. In the low-voltage region, the curve slope is close to 1, representing the ohmic characteristic region; in the medium-to-high voltage region, the curve slope is greater than 2, representing the region of steep current increase.

[0068] Figure 6 This is an I / V curve of a Pt / AgO / Ag2O / Pt memristor provided in this embodiment of the invention, after being positively biased for a certain period of time and subjected to continuous voltage scanning. The lower electrode is grounded, and a scanning voltage is applied to the upper electrode. Multiple bidirectional DC I / V voltage scans are performed on the unit, with the voltage scanning range controlled between -0.5V and 0.5V, and the current limit set to 100μA. Figure 6 It can be seen that there is a resistance window during the forward scan and a stable resistance change occurs, which is consistent with the characteristics of a digital memristor. This indicates that the device has been reconstructed into a digital memristor. Furthermore, the presence of Ag ions in the dielectric layer itself helps to form Ag conductive wires. The resistance threshold of this device is only about 0.2V.

[0069] Figure 7 This is a full-band waveform of the Pt / AgO / Ag2O / Pt memristor provided in this embodiment of the invention, under 50 consecutive positive pulse scans, where the pulse amplitude is 2V, the pulse width is 0.5μs, and the frequency is 1kHz. Figure 7 It can be seen that the conductivity of the device increases steadily under continuous positive pulse excitation, exhibiting LTP (long-term potentiation) characteristics consistent with simulated synapses.

[0070] Figure 8 This is a full-band waveform of the Pt / AgO / Ag2O / Pt memristor provided in this embodiment of the invention, under 50 consecutive negative pulse scans, where the pulse amplitude is -2V, the pulse width is 0.5μs, and the frequency is 1kHz. Figure 8 It can be seen that the conductivity of this device decreases slowly under continuous negative pulse excitation, although it is similar to... Figure 7 The linearity of the LTP characteristic is generally lower than that of the simulated synapse, but it still demonstrates that it has the LTD (long term depression) characteristic that is consistent with the simulated synapse.

[0071] Based on the above electrical measurements, it can be found that (1) when the memristor is in analog mode, it can realize the analog synaptic function by performing multi-value resistance switching based on charge capture and release; (2) under the action of a bias voltage applied for a certain period of time, Ag2O can undergo redox reaction, thereby forming Ag conductive wires between the dielectric layer and the upper electrode, and thus transforming from analog to digital, realizing analog-digital reconfigurability of the device; (3) in the memristor, due to the existence of asymmetric potential barriers between AgO and Ag2O and Pt electrode, when the device is an analog memristor, it has self-rectification characteristics; (4) in the memristor, due to the presence of Ag ions in the dielectric layer itself, it helps to form Ag conductive wires. Therefore, when the device is reconfigured into a digital memristor, the switching threshold voltage is small, and it has the advantages of fast switching speed and low switching power consumption.

[0072] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A reconfigurable heterojunction memristor, characterized in that, It includes, from bottom to top, a substrate, a lower electrode, a heterojunction intermediate layer, and a upper electrode; The heterojunction intermediate layer includes: an N-type oxide layer in contact with the lower electrode and a P-type oxide layer in contact with the upper electrode; The N-type oxide layer is silver peroxide, and the P-type oxide layer is silver oxide; Alternatively, the N-type oxide layer may be copper peroxide, and the P-type oxide layer may be copper oxide.

2. The memristor as claimed in claim 1, characterized in that, The thickness of the N-type oxide layer is 3nm-200nm.

3. The memristor as described in claim 1, characterized in that, The thickness of the P-type oxide layer is 3nm-200nm.

4. The memristor as described in any one of claims 1 to 3, characterized in that, Both the lower and upper electrodes are inert electrodes with a thickness of 2nm-200nm.

5. A method for controlling a reconfigurable heterojunction memristor as described in any one of claims 1 to 4, characterized in that, include: Analog to digital reconfiguration: The lower electrode is grounded, and a positive bias voltage is applied to the upper electrode that is in contact with the P-type oxide layer for a certain period of time, which causes the silver oxide layer / copper oxide layer to undergo an oxidation-reduction reaction and forms an Ag conductive wire / Cu conductive wire between the N-type oxide layer and the upper electrode. The two digital states of the device, on or off, are realized by the on and off of the conductive wire. Digital to analog reconstruction: The lower electrode is grounded, and a negative bias voltage is applied to the upper electrode that is in contact with the P-type oxide layer for a certain period of time, which causes the Ag / Cu conductive wire between the N-type oxide layer and the upper electrode to break and return to the analog type. Based on charge trapping and release, it exhibits the analog characteristics of multi-value resistive switching.

6. The method as described in claim 5, characterized in that, The analog memristor operates in a voltage range of -1V to 1V, while the digital memristor operates in a voltage range of -0.5V to 0.5V.

7. The method as described in claim 6, characterized in that, The memristor is switched from analog to digital by applying a voltage greater than 1.2V for a duration greater than 1s.

8. The method as described in claim 6, characterized in that, The memristor is switched from digital to analog by applying a voltage of less than -0.8V for a duration of more than 1s.

9. A method for fabricating a reconfigurable heterojunction memristor as described in any one of claims 1 to 4, characterized in that, include: (1) The substrate material was ultrasonically cleaned in acetone, anhydrous ethanol and deionized water respectively, and then dried with nitrogen. (2) Using magnetron sputtering, molecular beam epitaxy, atomic layer deposition, pulsed laser deposition or electrochemical methods, the lower electrode, the heterojunction intermediate layer and the upper electrode are sequentially prepared on the substrate; (3) Dry the sample in acetone, anhydrous ethanol and deionized water respectively, and then dry the sample with nitrogen.

10. An application of the reconfigurable heterojunction memristor as described in any one of claims 1 to 4, characterized in that, The heterojunction memristor is used for neuromorphic neuron computation or threshold switching.

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