inverter

Abstract

An inverter continuously generates three-phase alternating currents in a case where a prohibition potential is either a high potential or a low potential. In an abnormal operation, a control circuit changes a potential of a limited output wiring between two potentials out of a high potential, a neutral point potential, and a low potential, excluding the prohibition potential, and changes potentials of respective normal output wirings among the three potentials. In the abnormal operation, the control device outputs a coordinate of an origin, a first coordinate which is a coordinate of a first intermediate coordinate point, and a second coordinate which is a coordinate of a second intermediate coordinate point, in time offset in a limited state where an instruction value vector belongs to a first limited triangular region. The second coordinate is a lower side coordinate of the second intermediate coordinate point when the first coordinate is the upper side coordinate, and is an upper side coordinate of the second intermediate coordinate point when the first coordinate is the lower side coordinate.

Description

Technical Field

[0001] (Cited from relevant applications)

[0002] This application is an associated application of Japanese Patent Application No. 2021-55374, filed on March 29, 2021, and claims priority based on that Japanese patent application, and incorporates all the contents of that Japanese patent application as part of this specification.

[0003] The technology disclosed in this specification relates to an inverter.

[0004] Japanese Patent Application Publication No. 2016-220325 (hereinafter referred to as Patent Document 1) discloses an inverter capable of varying the output potential between three levels. This inverter has an upper capacitor connected between the high-potential line and the neutral point, and a lower capacitor connected between the neutral point and the low-potential line. Therefore, the potential of the neutral point becomes the potential between the high-potential line and the low-potential line. The inverter has switching circuits for each of the three output lines (U-phase, V-phase, and W-phase). Each switching circuit has multiple semiconductor elements. Each switching circuit changes the potential of the corresponding output line between a high potential, a neutral point potential, and a low potential by activating each semiconductor element. By varying the potential of each output line between the three levels, a three-phase alternating current is generated between the output lines. Summary of the Invention

[0005] The technical problem that the invention aims to solve

[0006] Semiconductor components within switching circuits may sometimes experience short-circuit faults. In such cases, a specific potential cannot always be applied to the output wiring in a switching circuit with a short-circuit faulty component. For example, if a short-circuit faulty component occurs, a line-to-line short circuit may sometimes occur between the high-potential wiring, the neutral point, and the low-potential wiring when other semiconductor components connected to that short-circuit faulty component (hereinafter referred to as the specific component) are turned on. In this situation, the specific component cannot be turned on, and a high-potential, neutral-point potential, or low-potential cannot be applied to the output wiring. Hereinafter, the potential that cannot be applied to the output wiring will be referred to as the prohibition potential.

[0007] Even when a short-circuit fault occurs, it is sometimes desirable to generate three-phase AC current using an inverter. In such cases, it is conceivable to change the potential of each output wiring between two potentials other than the disabled potential.

[0008] With the neutral point potential set to an inactive value, the inverter can change the potential of the three output wirings between high and low potentials to generate three-phase alternating current. In this condition, the inverter can continuously generate three-phase alternating current.

[0009] When the low potential is the disabled potential, the potential of the three output wirings can be varied between the high potential and the neutral point potential to generate three-phase alternating current. However, in this case, the inverter cannot continuously generate three-phase alternating current. That is, during this operation, due to the continuous use of the charge stored in the upper capacitor, after a certain period of time, the charge in the upper capacitor becomes extremely low, causing the neutral point potential to become extremely high. Thus, if the neutral point potential becomes extremely high, three-phase alternating current cannot be generated properly.

[0010] When the high potential is the disabled potential, the potential of the three output wirings can be varied between the neutral point potential and the low potential to generate three-phase alternating current. However, in this case, the inverter cannot continuously generate three-phase alternating current. That is, during this operation, due to the continuous use of the charge stored in the lower capacitor, after a certain period of time, the charge in the lower capacitor becomes extremely low, and the neutral point potential becomes extremely low. Thus, if the neutral point potential becomes extremely low, three-phase alternating current cannot be properly generated.

[0011] As explained above, in the aforementioned technologies, three-phase alternating current cannot be continuously generated when the prohibited potential is high or low. This specification presents an inverter capable of continuously generating three-phase alternating current under these conditions.

[0012] Technical solutions adopted to solve technical problems

[0013] The inverter disclosed in this specification includes: a high-potential wiring; a low-potential wiring; a neutral point; an upper capacitor connected between the high-potential wiring and the neutral point; a lower capacitor connected between the neutral point and the low-potential wiring; three switching circuits, each having a U-phase switching circuit, a V-phase switching circuit, and a W-phase switching circuit; a command circuit; and a control circuit. Each of the three switching circuits has multiple semiconductor elements and an output wiring. The control circuit controls the three switching circuits such that the potentials of the output wirings of the U-phase switching circuit (U-phase output wiring), the V-phase switching circuit (V-phase output wiring), and the W-phase switching circuit (W-phase output wiring) vary between the high-potential wiring (high potential), the neutral point (neutral point potential), and the low-potential wiring (low potential). The command circuit generates a command value vector composed of voltage vectors, which are represented by a spatial vector coordinate system defined by parameters Vu, Vv, and Vw. The parameter Vu represents the value of the potential of the U-phase output wiring, which is either the high potential, the neutral point potential, or the low potential. The parameter Vv represents the value of the potential of the V-phase output wiring, which is either the high potential, the neutral point potential, or the low potential. The parameter Vw represents the value of the potential of the W-phase output wiring, which is either the high potential, the neutral point potential, or the low potential. The control circuit controls the three switching circuits based on the command value vector. The spatial vector coordinate system has multiple intermediate coordinate points located between the origin and the outermost coordinate point. Each intermediate coordinate point has an upper coordinate representing the voltage vector that changes the voltage of the upper capacitor and a lower coordinate representing the voltage vector that changes the voltage of the lower capacitor. The spatial vector coordinate system has multiple triangular regions with the origin and two adjacent intermediate coordinate points as vertices. The control circuit described above can perform an abnormal operation when a short-circuit fault occurs in any of the semiconductor elements, preventing the application of either a high or low potential (a prohibition potential) to the corresponding output line in one of the three switching circuits. The semiconductor element experiencing the short-circuit fault is referred to as the short-circuit fault element. The output line of the switching circuit containing the short-circuit fault element is referred to as the restricted output line. The output lines of the two switching circuits not containing the short-circuit fault element are respectively referred to as normal output lines. In the abnormal operation, the control circuit causes the potential of the restricted output line to vary between two potentials other than the prohibition potential (high potential, neutral point potential, and low potential), and causes the potential of each of the normal output lines to vary between the high potential, neutral point potential, and low potential.In the aforementioned abnormal operation, the plurality of intermediate coordinate points include: a plurality of normal intermediate coordinate points in which neither the upper coordinate nor the lower coordinate contains the prohibition parameter representing the prohibition potential; and a plurality of restricted intermediate coordinate points in which one of the upper coordinate and the lower coordinate contains the prohibition parameter while the other does not. In the aforementioned abnormal operation, the plurality of triangular regions include: a first restricted triangular region where both intermediate coordinate points constituting the vertex are restricted intermediate coordinate points; a second restricted triangular region where one of the two intermediate coordinate points constituting the vertex is a normal intermediate coordinate point while the other is a restricted intermediate coordinate point; and a normal triangular region where both intermediate coordinate points constituting the vertex are normal intermediate coordinate points. In the aforementioned abnormal operation, when the command value vector belongs to the first restricted triangular region, the control device outputs the coordinates of the origin, the coordinates of the first intermediate coordinate point (i.e., the first coordinate), and the coordinates of the second intermediate coordinate point (i.e., the second coordinate) in a time-staggered manner. Under the aforementioned restrictions, the intermediate coordinate point within the specific first restricted triangle region (i.e., the specific first restricted triangle region) and the adjacent second restricted triangle region (i.e., the adjacent second restricted triangle region) of the quadrilateral formed by the first restricted triangle region to which the aforementioned instruction value vector belongs is the first intermediate coordinate point, and the intermediate coordinate point within the adjacent second restricted triangle region is the second intermediate coordinate point. The first coordinate is the coordinate of the upper and lower coordinates of the first intermediate coordinate point that does not contain the prohibited parameter. The second coordinate is the lower coordinate of the second intermediate coordinate point when the first coordinate is the upper coordinate, and the upper coordinate of the second intermediate coordinate point when the first coordinate is the lower coordinate.

[0014] Furthermore, "the command value vector belongs to the first restricted triangle region" means that at least a portion of the command value vector is located within the first restricted triangle region. This includes both cases where the entire command value vector is contained within the first restricted triangle region and cases where the command value vector passes through the first restricted triangle region.

[0015] In the first restricted triangle region, both intermediate coordinate points are restricted intermediate coordinate points. At these two restricted intermediate coordinate points, neither the upper nor lower coordinate can be output. Therefore, if the coordinates of the two restricted coordinate points are to be output out of time, either the upper or lower coordinate will be output in a biased manner. This can easily cause fluctuations in the neutral point's potential. In contrast, in the inverter described above, under the restricted state where the command value vector belongs to the first restricted triangle region, the coordinates of the first intermediate coordinate point (i.e., the first coordinate) and the coordinates of the second intermediate coordinate point (i.e., the second coordinate) are output out of time. Here, the second intermediate coordinate point is an intermediate coordinate point within the second restricted triangle region adjacent to the first restricted triangle region. Since the second intermediate coordinate point is a normal intermediate coordinate point, neither the upper nor lower coordinate at the second intermediate coordinate point contains the prohibited parameter. Therefore, both the upper and lower coordinates can be output as the second intermediate coordinate point. This inverter outputs the upper coordinate as the coordinate of the first intermediate coordinate point (first coordinate) and the lower coordinate as the coordinate of the second intermediate coordinate point (second coordinate). Furthermore, when the inverter outputs the lower coordinate as the coordinate of the first intermediate coordinate point (first coordinate), it also outputs the lower coordinate as the coordinate of the second intermediate coordinate point (second coordinate). This allows it to suppress fluctuations in the neutral point's potential. Attached Figure Description

[0016] Figure 1 This is the circuit diagram of the inverter in Example 1.

[0017] Figure 2 This is a table showing the first to third states of Embodiment 1.

[0018] Figure 3 It is a diagram showing a spatial vector coordinate system.

[0019] Figure 4 It is a graph showing the angle of the output voltage vector versus the three-phase AC current.

[0020] Figure 5 This is a circuit diagram showing the current path when the output is (0, 0, 2).

[0021] Figure 6 This is a circuit diagram showing the current path when the output is (1, 1, 2) and the current is in the positive direction.

[0022] Figure 7 This is a circuit diagram showing the current path when the output is (1, 1, 2) and the current is reversed.

[0023] Figure 8 This is a circuit diagram showing the current path when the output is (0, 0, 1) and the current is in the positive direction.

[0024] Figure 9 This is a circuit diagram showing the current path when the output is (0, 0, 1) and the current is reversed.

[0025] Figure 10 This is a table that shows the prohibited potentials.

[0026] Figure 11 This is a circuit diagram showing the path of the short-circuit current when the first diode has a short-circuit fault and when the third switching element has a short-circuit fault.

[0027] Figure 12 This is a circuit diagram showing the path of the short-circuit current when the first switching element has a short-circuit fault and when the fourth switching element has a short-circuit fault.

[0028] Figure 13 This is a circuit diagram showing the path of the short-circuit current when the second diode has a short-circuit fault and the second switching element has a short-circuit fault.

[0029] Figure 14 This is a diagram showing the spatial vector coordinate system when the command value vector belongs to the inner triangle region T5, which is a normal triangle region (when the prohibition parameter is Vw = 0).

[0030] Figure 15 This is a diagram showing the spatial vector coordinate system when a single command value vector belongs to the inner triangle region T1, which is the first restricted triangle region (when the prohibition parameter is Vw = 0).

[0031] Figure 16 This is a diagram showing the spatial vector coordinate system when the command value vector belongs to the inner triangle region T2, which is the first restricted triangle region (when the prohibition parameter is Vw = 0).

[0032] Figure 17 This is a diagram showing the spatial vector coordinate system when the command value vector belongs to the inner triangle region T6, which is the second restriction triangle region (when the prohibition parameter is Vw = 0).

[0033] Figure 18 This is a diagram showing the spatial vector coordinate system when the command value vector belongs to the inner triangle region T3, which is the second restriction triangle region (when the prohibition parameter is Vw = 0).

[0034] Figure 19 This is a diagram showing the spatial vector coordinate system when the command value vector belongs to the inner triangle region T5, which is the first restricted triangle region (when the prohibition parameter is Vw = 2).

[0035] Figure 20 This is a diagram showing the spatial vector coordinate system when the command value vector belongs to the inner triangle region T6, which is the second restriction triangle region (when the prohibition parameter is Vw = 2).

[0036] Figure 21 This is the circuit diagram of the inverter in Example 2.

[0037] Figure 22 This is a table showing the first to third states of Embodiment 2.

[0038] Figure 23 This is a circuit diagram showing the current path when the output is (0, 0, 2).

[0039] Figure 24 This is a circuit diagram showing the current path when the output is (1, 1, 2).

[0040] Figure 25 This is a circuit diagram showing the current path when the output is (0, 0, 1). Detailed Implementation

[0041] In an inverter of one example disclosed in this specification, under the aforementioned limiting conditions, the instruction circuit may also generate the instruction value vector not exceeding the line segment connecting the first intermediate coordinate point and the second intermediate coordinate point.

[0042] Based on this structure, the control circuit can easily output a voltage vector according to the command value vector.

[0043] In an inverter of one example disclosed in this specification, during the aforementioned abnormal operation, the control device may, in a preparatory state where the command value vector belongs to the second restricted triangle region, output the coordinates of the origin, the coordinates of the third intermediate coordinate point (i.e., the third coordinate), and the coordinates of the fourth intermediate coordinate point (i.e., the fourth coordinate) in a time-staggered manner. In the preparatory state, among the two intermediate coordinate points forming a quadrilateral (excluding the origin) in which the command value vector belongs (i.e., the specific second restricted triangle region) and the first restricted triangle region adjacent to the specific second restricted triangle region (i.e., the adjacent first restricted triangle region), the intermediate coordinate point within the adjacent first restricted triangle region may be the third intermediate coordinate point, and the intermediate coordinate point within the specific second restricted triangle region may be the fourth intermediate coordinate point. The third coordinate may also be the coordinate between the upper and lower coordinates of the third intermediate coordinate point that does not contain the prohibited parameter. The fourth coordinate may also be the lower coordinate of the fourth intermediate coordinate point when the third coordinate is the upper coordinate, and the upper coordinate of the fourth intermediate coordinate point when the third coordinate is the lower coordinate.

[0044] Furthermore, "the command value vector belongs to the second restriction triangle region" means that at least a portion of the command value vector is located within the second restriction triangle region. This includes both cases where the entire command value vector is contained within the second restriction triangle region and cases where the command value vector passes through the second restriction triangle region.

[0045] According to this structure, when the output time of the upper coordinate in the restricted state increases, the output time of the lower coordinate in the ready state also increases; conversely, when the output time of the lower coordinate in the restricted state increases, the output time of the upper coordinate in the ready state also increases. Therefore, the output time of the upper coordinate and the output time of the lower coordinate are easily balanced throughout the entire period from the restricted state to the ready state. This further suppresses fluctuations in the neutral point's potential.

[0046] In one example of an inverter disclosed in this specification, in the aforementioned preparatory state, the instruction circuit may also generate the instruction value vector not exceeding the line segment connecting the third intermediate coordinate point and the fourth intermediate coordinate point.

[0047] Based on this structure, the control circuit can easily output a voltage vector according to the command value vector.

[0048] In an inverter of one example disclosed in this specification, each of the three aforementioned switching circuits includes: a first switching element, the positive terminal of which is connected to the high-potential wiring; a second switching element, the positive terminal of which is connected to the negative terminal of the first switching element, and the negative terminal of which is connected to the corresponding output wiring; a third switching element, the positive terminal of which is connected to the corresponding output wiring; a fourth switching element, the positive terminal of which is connected to the negative terminal of the third switching element, and the negative terminal of which is connected to the low-potential wiring; a first diode, the anode of which is connected to the neutral point, and the cathode of which is connected to the negative terminal of the first switching element; and a second diode, the anode of which is connected to the negative terminal of the third switching element, and the cathode of which is connected to the neutral point. When the short-circuit fault element is the second switching element or the second diode, the inhibit potential may also be the low potential. When the short-circuit fault element is the third switching element or the first diode, the inhibit potential may also be the high potential.

[0049] In another example of the inverter disclosed in this specification, each of the three aforementioned switching circuits includes: a first switching element connected between the high-potential wiring and the corresponding output wiring; a second switching element connected between the neutral point and the corresponding output wiring; a third switching element connected in series with the second switching element between the neutral point and the corresponding output wiring; a fourth switching element connected between the corresponding output wiring and the low-potential wiring; a first intermediate diode, the cathode of which is connected in parallel with the second switching element in a direction toward the neutral point; and a second intermediate diode, the cathode of which is connected in parallel with the third switching element in a direction toward the output wiring. When the short-circuit fault element is the second switching element, the inhibit potential can also be the low potential. When the short-circuit fault element is the third switching element, the inhibit potential can also be the high potential.

[0050] [Example 1]

[0051] (Inverter structure)

[0052] Figure 1 This is a circuit diagram showing the inverter 10 of Embodiment 1. The inverter 10 is installed in a vehicle. Additionally, a battery 18 and a motor 90 are installed in the vehicle. The motor 90 is a motor used to drive the vehicle. The motor 90 is a three-phase motor. The inverter 10 is connected to the battery 18 and the motor 90. The inverter 10 converts the DC power supplied from the battery 18 into three-phase AC power and supplies the three-phase AC power to the motor 90. Thus, the motor 90 drives and propels the vehicle.

[0053] Inverter 10 has a high-potential wiring 12, a neutral point 14, a low-potential wiring 16, an upper capacitor 20, and a lower capacitor 22. The high-potential wiring 12 is connected to the positive terminal of battery 18. The low-potential wiring 16 is connected to the negative terminal of battery 18. The potential of the low-potential wiring 16 is set as a reference potential (0V). A DC voltage is applied between the high-potential wiring 12 and the low-potential wiring 16 through battery 18. Therefore, the high-potential wiring 12 has a potential VH that is higher than the potential (0V) of the low-potential wiring 16. The upper capacitor 20 is connected between the high-potential wiring 12 and the neutral point 14. The lower capacitor 22 is connected between the neutral point 14 and the low-potential wiring 16. Therefore, the potential VM of the neutral point 14 (hereinafter referred to as the neutral point potential VM) is higher than the potential (0V) of the low-potential wiring 16 and lower than the potential VH of the high-potential wiring 12. The neutral point potential VM varies according to the amount of charge stored in the upper capacitor 20 and the amount of charge stored in the lower capacitor 22. The neutral point potential VM rises when the upper capacitor 20 discharges or the lower capacitor 22 charges. The neutral point potential VM falls when the upper capacitor 20 charges or the lower capacitor 22 discharges.

[0054] The inverter 10 has three switching circuits 30: a U-phase switching circuit 30u, a V-phase switching circuit 30v, and a W-phase switching circuit 30w. Each of the switching circuits 30 is connected between the high-potential wiring 12, the low-potential wiring 16, and the neutral point 14. Each of the switching circuits 30 has a first switching element 41, a second switching element 42, a third switching element 43, a fourth switching element 44, a first diode 51, a second diode 52, and an output wiring 60. Since the structures of the three switching circuits 30 are identical, the structure of one switching circuit 30 will be described below.

[0055] Switching elements 41-44 are constructed from IGBTs (insulated gate bipolar transistors). However, switching elements 41-44 can also be constructed from other elements (e.g., FETs). A return-flow diode is connected in parallel with each of the switching elements 41-44. The anode of the return-flow diode is connected to the emitter of the corresponding switching element, and the cathode of the return-flow diode is connected to the collector of the corresponding switching element. Switching elements 41-44 are connected in series between the high-potential wiring 12 and the low-potential wiring 16. That is, the collector of the first switching element 41 is connected to the high-potential wiring 12. The collector of the second switching element 42 is connected to the emitter of the first switching element 41. The collector of the third switching element 43 is connected to the emitter of the second switching element 42. The collector of the fourth switching element 44 is connected to the emitter of the third switching element 43. The emitter of the fourth switching element 44 is connected to the low-potential wiring 16. The anode of the first diode 51 is connected to the neutral point 14. The cathode of the first diode 51 is connected to the emitter of the first switching element 41 and the collector of the second switching element 42. The anode of the second diode 52 is connected to the emitter of the third switching element 43 and the collector of the fourth switching element 44. The cathode of the second diode 52 is connected to the neutral point 14. One end of the output wiring 60 is connected to the emitter of the second switching element 42 and the collector of the third switching element 43. The other end of the output wiring 60 is connected to the motor 90.

[0056] Furthermore, the output wiring 60 of the U-phase switching circuit 30u will be referred to as the U-phase output wiring 60u, the output wiring 60 of the V-phase switching circuit 30v will be referred to as the V-phase output wiring 60v, and the output wiring 60 of the W-phase switching circuit 30w will be referred to as the W-phase output wiring 60w. The U-phase output wiring 60u, V-phase output wiring 60v, and W-phase output wiring 60w are each connected to the motor 90.

[0057] The inverter 10 includes a control circuit 70 and a command circuit 72. The command circuit 72 generates command values ​​based on the operating state of the motor 90 and inputs these command values ​​to the control circuit 70. Although not shown in the diagram, the control circuit 70 is connected to the gates of the switching elements 41-44 of each of the U-phase switching circuit 30u, the V-phase switching circuit 30v, and the W-phase switching circuit 30w. That is, the control circuit 70 is connected to... Figure 1 The gates of the twelve switching elements shown are connected. The control circuit 70, based on the command value input from the command circuit 72, turns each switching element on / off. This generates a three-phase alternating current between the three output lines 60. By supplying the three-phase alternating current to the motor 90, the motor 90 is driven, and the vehicle is moved.

[0058] (Potential of output wiring)

[0059] Next, the potentials applied to each output wiring 60 will be explained. The control circuit 70 controls each switching circuit 30 to... Figure 2 Any one of the first, second, and third states shown.

[0060] In the first state, the control is set so that the first switching element 41 is turned on, the second switching element 42 is turned on, the third switching element 43 is turned off, and the fourth switching element 44 is turned off. In the first state, the output wiring 60 is connected to the high-potential wiring 12 via the first switching element 41 and the second switching element 42. Therefore, in the first state, the potential of the output wiring 60 becomes the same as the potential VH of the high-potential wiring 12.

[0061] In the second state, the control is configured such that the first switching element 41 is off, the second switching element 42 is on, the third switching element 43 is on, and the fourth switching element 44 is off. In the second state, the output wiring 60 is connected to the neutral point 14 via the second switching element 42 and the first diode 51 or via the third switching element 43 and the second diode 52. Therefore, in the second state, the potential of the output wiring 60 becomes the neutral point potential VM.

[0062] In the third state, the control is set so that the first switching element 41 is off, the second switching element 42 is off, the third switching element 43 is on, and the fourth switching element 44 is on. In the third state, the output wiring 60 is connected to the low-potential wiring 16 via the third switching element 43 and the fourth switching element 44. Therefore, in the third state, the potential of the output wiring 60 becomes 0V, the same as that of the low-potential wiring 16.

[0063] The states of each switching circuit 30 change between the first, second, and third states, and the potentials of each output wiring 60 change between potential VH, neutral point potential VM, and potential 0V. The control circuit 70 controls the potentials of each output wiring 60 to generate three-phase alternating current in the output wiring 60.

[0064] (Voltage Vector)

[0065] Figure 3 This is a spatial vector coordinate system that shows the potential applied to each of the output wirings 60. Figure 3The voltage vector A1 is illustrated in the diagram. The spatial vector coordinate system has nineteen coordinate points. Each coordinate point is represented by a coordinate (Vu, Vv, Vw) composed of three parameters Vu, Vv, and Vw. Parameter Vu represents the potential value of the U-phase output wiring 60u. Parameter Vv represents the potential value of the V-phase output wiring 60v. Parameter Vw represents the potential value of the W-phase output wiring 60w. Parameters Vu, Vv, and Vw are values ​​between 0 and 2. A value "0" indicates that 0V is applied to the corresponding output wiring 60, a value "1" indicates that a neutral point potential VM is applied to the corresponding output wiring 60, and a value "2" indicates that a potential VH is applied to the corresponding output wiring 60. For example, (2, 2, 0) means that a potential VH is applied to the U-phase output wiring 60u, a potential VH is applied to the V-phase output wiring 60v, and 0V is applied to the W-phase output wiring 60w.

[0066] The spatial vector coordinate system has nineteen coordinate points, including an origin O, twelve outermost coordinate points, and six intermediate coordinate points M1 to M6. The origin O is located at the center of the spatial vector coordinate system. The origin O is represented by the coordinates (0, 0, 0), (1, 1, 1), and (2, 2, 2). That is, the origin O indicates that the U-phase output wiring 60u, V-phase output wiring 60v, and W-phase output wiring 60w are set to the same potential. The outermost coordinate points are located on the outermost perimeter of the spatial vector coordinate system. That is, the outermost coordinate points are located on the hexagons that form the outermost perimeter of the spatial vector coordinate system. Each outermost coordinate point is represented by one coordinate. The intermediate coordinate points M1 to M6 are located between the origin O and the outermost coordinate points. That is, the intermediate coordinate points are located on the hexagons that are further inward than the outermost perimeter of the spatial vector coordinate system. Each intermediate coordinate point is represented by two coordinates. The intermediate coordinate point is represented by the upper coordinate of parameters Vu, Vv, and Vw, where part of Vu, Vv, and Vw is 2 and the remainder is 1, and the lower coordinate of parameters Vu, Vv, and Vw, where part of Vu, Vv, and Vw is 1 and the remainder is 0.

[0067] In the spatial vector coordinate system, there exist multiple triangular regions with three of the aforementioned nineteen coordinate points as vertices. Six triangular regions T1 to T6 exist adjacent to the origin O. Hereinafter, the triangular regions T1 to T6 adjacent to the origin O will be referred to as the inner triangular regions. The inner triangular regions T1 to T6 have two of the intermediate coordinate points M1 to M6 and the origin O as vertices. Eighteen triangular regions exist further outward than the inner triangular regions T1 to T6.

[0068] (Instruction value vector)

[0069] Command circuit 72 generates command values ​​for the potentials to be applied to the three output wirings 60. Command circuit 72 generates command values ​​using a voltage vector represented by coordinates (Vu, Vv, Vw) in a spatial vector coordinate system. Hereinafter, the voltage vector generated by command circuit 72 as the command value will be referred to as the command value vector. Command circuit 72 generates the command value vector based on the rotational speed of motor 90, the current flowing through motor 90, the amount of throttle input by the driver, etc. For example, it can... Figure 3 The voltage vector A1 is output as the command value vector. Additionally, as follows... Figure 3 As shown, the angle θ relative to the Vu axis represents the angle of the voltage vector. The instruction circuit 72 generates the instruction value vector sequentially by gradually increasing the angle θ of the instruction value vector. That is, as... Figure 3 As indicated by arrow 102, the instruction circuit 72 sequentially generates the instruction value vector by rotating it. The instruction value vector is then input to the control circuit 70. Furthermore, as will be explained in detail later, the instruction circuit 72 sometimes modifies the instruction value vector. Hereinafter, the instruction value vector before modification will be referred to as the primary instruction value vector, and the instruction value vector after modification will be referred to as the secondary instruction value vector.

[0070] (Normal action)

[0071] Control circuit 70 controls inverter 10 based on command value vector. In the absence of short-circuit faulty components, control circuit 70 performs normal operation. During normal operation, control circuit 70 controls inverter 10 according to a primary command value vector. For example, when the parameter Vu of the primary command value vector is "0", control circuit 70 controls the U-phase switching circuit 30u to the third state and applies 0V to the U-phase output wiring 60u. When the parameter Vu of the primary command value vector is "1", control circuit 70 controls the U-phase switching circuit 30u to the second state and applies a neutral point potential VM to the U-phase output wiring 60u. When the parameter Vu of the primary command value vector is "2", control circuit 70 controls the U-phase switching circuit 30u to the first state and applies a potential VH to the U-phase output wiring 60u. When the parameter Vv of the primary command value vector is "0", control circuit 70 controls the V-phase switching circuit 30v to the third state and applies 0V to the V-phase output wiring 60v. When the parameter Vv of the first command value vector is "1", the control circuit 70 controls the V-phase switching circuit 30V to the second state and applies a neutral point potential VM to the V-phase output wiring 60V. When the parameter Vv of the first command value vector is "2", the control circuit 70 controls the V-phase switching circuit 30V to the first state and applies a potential VH to the V-phase output wiring 60V. When the parameter Vw of the first command value vector is "0", the control circuit 70 controls the W-phase switching circuit 30w to the third state and applies 0V to the W-phase output wiring 60w. When the parameter Vw of the first command value vector is "1", the control circuit 70 controls the W-phase switching circuit 30w to the second state and applies a neutral point potential VM to the W-phase output wiring 60w. When the parameter Vw of the first command value vector is "2", the control circuit 70 controls the W-phase switching circuit 30w to the first state and applies a potential VH to the W-phase output wiring 60w.

[0072] Furthermore, the parameters of the voltage vector are sometimes represented by decimals. For example, Figure 3The coordinates of voltage vector A1 are (0.75, 0.5, 0). Thus, when the voltage vector, whose parameters are expressed as decimals, is a command value vector, the control circuit 70 outputs a voltage vector equivalent to the command value vector by outputting the coordinates of each vertex of the triangular region containing the coordinates of the command value vector (i.e., the leading edge of the command value vector) in a time-staggered manner. For example, when the command circuit 72 generates voltage vector A1 as the command value vector, the control circuit 70 outputs the three vertices of the triangular region T1 containing the coordinates of voltage vector A1 (i.e., the coordinates of the middle coordinate points M1 and M2 and the origin O) in a time-staggered manner. Therefore, (0.75, 0.5, 0) is output. Furthermore, the coordinates of the middle coordinate point M1 can be output as either (2, 1, 1) or (1, 0, 0). Similarly, the coordinates of the middle coordinate point M2 can be output as either (2, 2, 1) or (1, 1, 0). Additionally, the coordinates of the origin can be output as (0, 0, 0), (1, 1, 1), and (2, 2, 2). When (0.75, 0.5, 0) is output, the time ratio for outputting the coordinates of each point is shown in Equation 1 below.

[0073] [Formula 1]

[0074]

[0075] Furthermore, in Equation 1 above, T1 is the time ratio of the output intermediate coordinate point M1, T2 is the time ratio of the output intermediate coordinate point M2, and T3 is the time ratio of the output origin O. Also, in Equation 1 above, θ is the angle of the quadratic command value vector relative to the Vu axis, Vmag is the voltage value converted from the length of the quadratic command value vector, and VH is the potential of the high-potential wiring 12.

[0076] As described above, as indicated by arrow 102, the instruction circuit 72 sequentially generates a primary instruction value vector by rotating it, and inputs this vector to the control circuit 70. The control circuit 70 outputs a voltage vector according to the input primary instruction value vector. Therefore, the output voltage vector rotates as indicated by arrow 102. Consequently, a three-phase alternating current is generated between the three output wirings 60. Figure 4 The diagram illustrates the relationship between the currents Iu, Iv, and Iw flowing through the three output wirings 60u, 60v, and 60w and the angle θ of the output voltage vector. (For example...) Figure 4 As shown, the phase of the voltage vector angle θ is offset by approximately 90° relative to the phase of the current Iu. However, due to the parasitic resistance of the circuit, the phase difference between angle θ and current Iu can sometimes vary. Figure 4 Further variations are possible. Additionally, when the frequency of the three-phase alternating current is changed, the phase difference between the angle θ and the current Iu can sometimes change. For example... Figure 4As shown, the three-phase alternating current flowing through the output wiring 60u, 60v, and 60w causes the magnetic field generated inside the motor 90 to rotate. As a result, the rotor of the motor 90 rotates.

[0077] (Changes in neutral point potential VM)

[0078] Next, the variation of the neutral point potential VM will be explained. (In the output...) Figure 3 In the coordinates shown, where the coordinates do not include the value "1" as a parameter, no neutral point potential VM is applied to any of the three output wirings 60. In this case, no change in the neutral point potential VM occurs. For example, in the case of output (0, 0, 2), as... Figure 5 As shown, output wiring 60u and 60v are connected to low-potential wiring 16, and output wiring 60w is connected to high-potential wiring 12. Furthermore, depending on the operating state of the motor 90, there are cases where the current flows in the same direction as the voltage applied to the motor 90 (hereinafter referred to as forward) and cases where the current flows in the opposite direction to the voltage applied to the motor 90 (hereinafter referred to as reverse). In the case where the current flows in the forward direction, as... Figure 5 As indicated by arrow 200, current flows from the high-potential wiring 12 to the motor 90 via output wiring 60w. The current flowing into the motor 90 flows to the low-potential wiring 16 via output wirings 60u and 60v. Furthermore, in the case of reverse current flow, the current flows in the opposite direction of arrow 200. In either of these cases, no charge flows into or out of the neutral point 14. Therefore, no change in the neutral point potential VM occurs in this situation. Similarly, no change in the neutral point potential VM occurs when outputting (2,0,0), (2,2,0), (0,2,0), (0,2,2), or (2,0,2).

[0079] In output Figure 3 In the case of coordinates containing the value "1" as a parameter, the neutral point potential VM changes because the neutral point 14 is connected to at least one of the three output wirings 60.

[0080] For example, in the case of output (1, 1, 2), such as Figure 6 As shown, output wiring 60u and 60v are connected to neutral point 14, and output wiring 60w is connected to high-potential wiring 12. When the current flows in the forward direction, as... Figure 6As indicated by arrow 202, current flows from the high-potential wiring 12 to the motor 90 via output wiring 60w. The current flowing into the motor 90 flows to the neutral point 14 via output wirings 60u and 60v. In this case, due to the discharge of the upper capacitor 20, the neutral point potential VM rises. Furthermore, in the case of current flowing in the reverse direction, as... Figure 7 As indicated by arrow 204, current flows from neutral point 14 to motor 90 via output wiring 60u, 60v. The current flowing into motor 90 flows to high-potential wiring 12 via output wiring 60w. In this case, the neutral point potential VM decreases due to the charging of the upper capacitor 20. Thus, in the case of output (1, 1, 2), the neutral point potential VM rises when the current is in the positive direction and falls when the current is in the reverse direction. Similarly, in the cases of outputs (2, 1, 1), (2, 2, 1), (1, 2, 1), (1, 2, 2), (2, 1, 2), the neutral point potential VM rises when the current is in the positive direction and falls when the current is in the reverse direction.

[0081] Additionally, for example, in the case of output (0, 0, 1), such as Figure 8 As shown, output wiring 60u and 60v are connected to low-potential wiring 16, and output wiring 60w is connected to neutral point 14. When the current flows in the forward direction, as... Figure 8 As indicated by arrow 206, current flows from neutral point 14 to motor 90 via output wiring 60w. The current flowing into motor 90 flows to low-potential wiring 16 via output wiring 60u, 60v. In this case, the neutral point potential VM decreases due to the discharge of the lower capacitor 22. Furthermore, in the case of reverse current flow, as... Figure 9 As indicated by arrow 208, current flows from the low-potential wiring 16 to the motor 90 via output wirings 60u and 60v. The current flowing into the motor 90 flows to the neutral point 14 via output wiring 60w. In this case, the neutral point potential VM rises because the lower capacitor 22 is charging. Thus, in the case of output (0, 0, 1), the neutral point potential VM decreases when the current is in the positive direction and increases when the current is in the reverse direction. Similarly, in the cases of outputs (1, 0, 0), (1, 1, 0), (0, 1, 0), (0, 1, 1), and (1, 0, 1), the neutral point potential VM decreases when the current is in the positive direction and increases when the current is in the reverse direction.

[0082] Furthermore, even in the output Figure 3In the coordinates shown (2, 1, 0), (1, 2, 0), (0, 2, 1), (0, 1, 2), (1, 0, 2), (2, 0, 1), the neutral point potential VM changes due to the inflow or outflow of charge into or out of the neutral point 14.

[0083] During normal operation, the command circuit 72 and the control circuit 70 change the output voltage vector according to the neutral point potential VM. For example, if the neutral point potential VM is lower than the control target value, a voltage vector that raises the neutral point potential VM is preferentially output. Conversely, if the neutral point potential VM is higher than the control target value, a voltage vector that lowers the neutral point potential VM is preferentially output. Therefore, it is possible to supply three-phase AC current to the motor 90 while controlling the neutral point potential VM to a value close to the target value.

[0084] (Short-circuit component detection action)

[0085] When the vehicle is not in motion, the control circuit 70 periodically performs a short-circuit element determination operation. During this operation, for the switching circuits 30u, 30v, and 30w, it determines whether switching elements 41-44 and diodes 51-52 have short-circuit faults. A short-circuit fault in a switching element refers to a fault mode where the switching element is switched on regardless of the potential of its gate. A short-circuit fault in a diode refers to a fault mode where current flows through the diode in both directions. The control circuit 70 selects any one of the three switching circuits 30u, 30v, and 30w and performs a short-circuit element determination operation on the selected switching circuit. During this operation, the control circuit 70 switches on each element in various combinations and measures the current flowing through them. Thus, the control circuit 70 determines whether a short-circuit faulty element exists, and if so, determines which of the switching elements 41-44 and diodes 51-52 is the short-circuit faulty element.

[0086] (A. Unusual action)

[0087] Next, the abnormal operation will be explained. When a short-circuit faulty element is present, the command circuit 72 and control circuit 70 perform an abnormal operation when the motor 90 needs to be driven. Furthermore, the switching circuit 30 with the short-circuit faulty element will be referred to below as the limiting switching circuit 30x. Furthermore, the output wiring 60 of the limiting switching circuit 30x will be referred to as the limiting output wiring 60x. Furthermore, the switching circuit 30 other than the limiting switching circuit 30x will be referred to as the normal switching circuit 30y. Furthermore, the output wiring 60 of the normal switching circuit 30y will be referred to as the normal output wiring 60y. The abnormal operation is performed when there is only one limiting switching circuit 30x and only one short-circuit faulty element. In the abnormal operation, the limiting switching circuit 30x is controlled so that a prohibition potential is not applied to the limiting output wiring 60x. First, the prohibition potential will be explained.

[0088] (A-1. Prohibited Potential)

[0089] The prohibited potential refers to the voltage that cannot be applied to the limiting output wiring 60x due to a short circuit between lines within the limiting switching circuit 30x. Figure 10 The relationship between short-circuit fault components and the inhibit potential is shown. The inhibit potential varies depending on the type of short-circuit fault component within the limiting switch circuit 30x.

[0090] like Figure 12 As indicated by arrow 304, in the event of a short-circuit fault in the first switching element 41, a line-to-line short circuit occurs between the high-potential wiring 12 and the neutral point 14 in the second state. Therefore, in the event of a short-circuit fault in the first switching element 41, the limiting switching circuit 30x cannot be set to the second state, and the neutral point potential VM cannot be applied to the limiting output wiring 60x. Therefore, as Figure 10 As shown, in the event of a short circuit fault in the first switching element 41, the prohibited potential is the neutral point potential VM.

[0091] like Figure 13 As indicated by arrow 310, in the event of a short-circuit fault in the second switching element 42, a line-to-line short circuit occurs between the neutral point 14 and the low-potential wiring 16 in the third state. Therefore, in the event of a short-circuit fault in the second switching element 42, the limiting switching circuit 30x cannot be set to the third state, and 0V cannot be applied to the limiting output wiring 60x. Therefore, as Figure 10 As shown, in the event of a short circuit fault in the second switching element 42, the prohibition potential is 0V.

[0092] like Figure 11As indicated by arrow 302, in the event of a short-circuit fault in the third switching element 43, a line-to-line short circuit occurs between the high-potential wiring 12 and the neutral point 14 in the first state. Therefore, in the event of a short-circuit fault in the third switching element 43, the limiting switching circuit 30x cannot be set to the first state, and a potential VH cannot be applied to the limiting output wiring 60x. Therefore, as Figure 10 As shown, in the event of a short circuit fault in the third switching element 43, the prohibited potential is potential VH.

[0093] like Figure 12 As indicated by arrow 306, in the event of a short-circuit fault in the fourth switching element 44, a line-to-line short circuit occurs between the neutral point 14 and the low-potential wiring 16 in the second state. Therefore, in the event of a short-circuit fault in the fourth switching element 44, the limiting switching circuit 30x cannot be set to the second state, and the neutral point potential VM cannot be applied to the limiting output wiring 60x. Therefore, as Figure 10 As shown, in the event of a short circuit fault in the fourth switching element 44, the prohibited potential is the neutral point potential VM.

[0094] like Figure 11 As indicated by arrow 300, in the event of a short-circuit fault in the first diode 51, a line-to-line short circuit occurs between the high-potential wiring 12 and the neutral point 14 in the first state. Therefore, in the event of a short-circuit fault in the first diode 51, the limiting switch circuit 30x cannot be set to the first state, and a potential VH cannot be applied to the limiting output wiring 60x. Therefore, as... Figure 10 As shown, in the event of a short circuit fault in the first diode 51, the prohibited potential is potential VH.

[0095] like Figure 13 As indicated by arrow 308, in the case of a short-circuit fault in the second diode 52, a line-to-line short circuit occurs between the neutral point 14 and the low-potential wiring 16 in the third state. Therefore, in the case of a short-circuit fault in the second diode 52, the limiting switch circuit 30x cannot be set to the third state, and 0V cannot be applied to the limiting output wiring 60x. Therefore, as Figure 10 As shown, in the event of a short circuit fault in the second diode 52, the prohibition potential is 0V.

[0096] As explained above, depending on the short-circuit fault element, the prohibition potential that cannot be applied to the output wiring 60x will change. As stated above, during abnormal operation, the control method changes according to the change in the prohibition potential.

[0097] (A-2. Prohibition of abnormal operation when the potential is the neutral point potential VM)

[0098] When the neutral point potential VM is disabled (i.e., the short-circuit fault element is the first switching element 41 or the fourth switching element 44), the control circuit 70 controls the potentials of the output lines 60u, 60v, and 60w between the high potential VH and 0V. In this operation, since the neutral point potential VM is not applied to any of the three output lines 60, the three-phase AC current can continue to be supplied to the motor 90 regardless of the neutral point potential VM. Therefore, the vehicle can continue to operate.

[0099] (A-3. Prohibits abnormal operation when the potential is 0V or a high potential VH)

[0100] When the prohibition potential is 0V or the high potential is VH, the instruction circuit 72 generates a primary instruction value vector in the same way as normal operation, and then generates a secondary instruction value vector after correcting the primary instruction value vector.

[0101] As described above, there are six inner triangular regions T1 to T6 located adjacent to the origin O. During abnormal operation, the instruction circuit 72 classifies the six inner triangular regions T1 to T6 into a first restricted triangular region, a second restricted triangular region, and a normal triangular region, and determines which of these regions the primary instruction value vector belongs to. The instruction circuit 72 generates a secondary instruction value vector based on the determination result. Therefore, the first restricted triangular region, the second restricted triangular region, and the normal triangular region will be described below. As described above, during abnormal operation, since a prohibition potential cannot be applied to the restricted output wiring 60x, a portion of the coordinates cannot be output. That is, coordinates containing parameters indicating the application of a prohibition potential to the restricted output wiring 60x (hereinafter referred to as prohibition parameters) cannot be output. Hereinafter, coordinates containing prohibition parameters will be referred to as prohibited coordinates, and coordinates not containing prohibition parameters will be referred to as normal coordinates. Figure 14 This example illustrates the case where output wiring 60x is limited to output wiring 60w and the disable potential is 0V. (Including...) Figure 14 In the spatial vector diagrams, strikethrough lines are added to prohibit coordinate annotations. Figure 14In the diagram, since the prohibition parameter Vw = 0, (2, 0, 0), (2, 1, 0), (2, 2, 0), (1, 2, 0), (0, 2, 0), (1, 0, 0), (1, 1, 0), (0, 1, 0), and (0, 0, 0) are prohibited coordinates, while the other coordinates are normal coordinates. As mentioned above, the intermediate coordinate points M1 to M6 have both upper and lower coordinates. When there is only one short-circuit fault element, one of the upper or lower coordinates of the three intermediate coordinate points is a prohibited coordinate. Below, the intermediate coordinate point where either the upper or lower coordinate is a prohibited coordinate is called a restricted intermediate coordinate point, and the intermediate coordinate point where both the upper and lower coordinates are normal coordinates is called a normal intermediate coordinate point. For example, in... Figure 14 In the case of M1 to M3, the lower coordinates (i.e., (1, 0, 0), (1, 1, 0), (0, 1, 0)) are forbidden coordinates, while the upper coordinates (i.e., (2, 1, 1), (2, 2, 1), (1, 2, 1)) are normal coordinates. Therefore, in Figure 14 In this case, the intermediate coordinate points M1 to M3 are the restricted intermediate coordinate points. Additionally, in... Figure 14 In this case, intermediate coordinate points M4 to M6 are normal intermediate coordinate points. The first restricted triangle region is the inner triangle region T1 to T6, where the two intermediate coordinate points constituting vertices other than the origin O are both within the restricted intermediate coordinate point inner triangle region. For example, in... Figure 14 In the diagram, the inner triangular regions T1 and T2 are the first restricted triangular regions. The second restricted triangular region is an inner triangular region within the inner triangular regions T1 to T6 where one of the intermediate coordinate points constituting the vertices other than the origin O is a restricted intermediate coordinate point, and the other is a normal intermediate coordinate point. For example, in... Figure 14 In the diagram, the inner triangular regions T3 and T6 are the second restricted triangular regions. A normal triangular region is an inner triangular region within the inner triangular regions T1–T6 where the two intermediate coordinate points of the vertices other than the origin O are both normal intermediate coordinate points. For example, in… Figure 14 In the diagram, the inner triangular regions T4 and T5 are normal triangular regions. Two first-restricted triangular regions are adjacent to each other, and two normal triangular regions are adjacent to each other. Two second-restricted triangular regions are positioned on opposite sides, sandwiching the origin O. Each second-restricted triangular region is positioned between a first-restricted triangular region and a normal triangular region.

[0102] The instruction circuit 72 determines which of the inner triangle regions T1 to T6 the inner triangle region to which the primary instruction value vector belongs. Furthermore, the inner triangle region to which the primary instruction value vector belongs refers to the inner triangle region among the inner triangle regions T1 to T6 that contains at least a portion of the primary instruction value vector. In other words, the inner triangle region to which the primary instruction value vector belongs refers to the inner triangle region containing the base portion of the primary instruction value vector. For example, Figure 14 The command value vector B1 shown belongs to the inner triangular region T5. Additionally, for example... Figure 15 The command value vector B2 shown belongs to the inner triangle region T1. The command circuit 72 determines whether the inner triangle region to which the command value vector belongs is the first restricted triangle region, the second restricted triangle region, or the normal triangle region. Based on the determination result, the command circuit 72 and the control circuit 70 operate in the following manner.

[0103] (A-3-1. When the command value vector belongs to a normal triangular region)

[0104] When the command value vector falls within the normal triangular region, the command circuit 72 directly inputs the command value vector to the control circuit 70. For example, in Figure 14 In this case, the primary command value vector B1 belongs to the inner triangle region T5, which is a normal triangle region. The control circuit 70 outputs a voltage vector based on the primary command value vector, just as in normal operation. Since there are no prohibited coordinates within the angular range of the normal triangle region, there is no problem even if the voltage vector is output as in normal operation when the primary command value vector belongs to the normal triangle region. For example, the control circuit 70 can also detect the neutral point potential VM and select either the upper or lower coordinate based on the neutral point potential VM and output it. That is, if the neutral point potential VM is higher than the target value (e.g., VH / 2), the coordinate that causes the neutral point potential VM to decrease can be selected from the upper and lower coordinates and output. Conversely, if the neutral point potential VM is lower than the target value (e.g., VH / 2), the coordinate that causes the neutral point potential VM to increase can be selected from the upper and lower coordinates and output.

[0105] (A-3-2. When the command value vector belongs to the first restricted triangle region)

[0106] When a single instruction value vector belongs to a first restricted triangle region, the instruction circuit 72 determines a second restricted triangle region adjacent to the first restricted triangle region to which the single instruction value vector belongs (hereinafter referred to as the specific first restricted triangle region). Hereinafter, the second restricted triangle region adjacent to the specific first restricted triangle region is referred to as the adjacent second restricted triangle region. For example, in... Figure 15 In the instruction circuit 72, the instruction value vector B2 belongs to the inner triangle region T1 (i.e., the first restricted triangle region). Therefore, the specific first restricted triangle region is the inner triangle region T1. In this case, the instruction circuit 72 determines the second restricted triangle region adjacent to the inner triangle region T1, namely the inner triangle region T6, as the adjacent second restricted triangle region. Next, the instruction circuit 72 determines two intermediate coordinate points that do not contain the origin O and form opposite corners in the quadrilateral formed by the specific first restricted triangle region and the adjacent second restricted triangle region. Below, among the two determined intermediate coordinate points (i.e., the two intermediate coordinate points that do not contain the origin O and form opposite corners), the intermediate coordinate point within the specific first restricted triangle region is called the first intermediate coordinate point, and the intermediate coordinate point within the adjacent second restricted triangle region is called the second intermediate coordinate point. The first intermediate coordinate point is a restricted intermediate coordinate point, and the second intermediate coordinate point is a normal intermediate coordinate point. For example, in... Figure 15 In the quadrilateral formed by the two inner triangular regions T1 and T6, the two intermediate coordinate points that do not contain the origin O and form opposite corners are intermediate coordinate points M2 and M6. Since intermediate coordinate point M2 is the coordinate point of the vertex forming the specific first restricted triangular region (i.e., the inner triangular region T1), it is also the first intermediate coordinate point. Since intermediate coordinate point M6 is the coordinate point of the vertex forming the adjacent second restricted triangular region (i.e., the inner triangular region T6), it is also the second intermediate coordinate point. Intermediate coordinate point M2 (i.e., the first intermediate coordinate point) is a restricted intermediate coordinate point, and intermediate coordinate point M6 (i.e., the second intermediate coordinate point) is a normal intermediate coordinate point. Next, the instruction circuit 72 calculates the line segment (hereinafter referred to as line segment L1) connecting the first and second intermediate coordinate points. For example, in... Figure 15 In this process, the line segment L1 connecting intermediate coordinate point M2 (i.e., the first intermediate coordinate point) and intermediate coordinate point M6 (i.e., the second intermediate coordinate point) is calculated. Next, the instruction circuit 72 determines whether the primary instruction value vector exceeds line segment L1. If the primary instruction value vector exceeds line segment L1, the instruction circuit 72 calculates a voltage vector with an angle θ equal to the primary instruction value vector and having a length not exceeding that of line segment L1 as the secondary instruction value vector. That is, the instruction circuit 72 calculates the secondary instruction value vector by shortening the primary instruction value vector. For example, in... Figure 15 In the first command value vector B2, the line segment L1 extends beyond it (i.e., it extends to a position further outward than the outer periphery of line segment L1). Therefore, the command circuit 72 calculates a secondary command value vector C2 whose angle θ is equal to the primary command value vector B2 and does not exceed the line segment L1. Alternatively, if the primary command value vector does not exceed the line segment L1, the command circuit 72 directly sets the primary command value vector as the secondary command value vector. The generated secondary command value vector is input to the control circuit 70.

[0107] The control circuit 70 outputs a voltage vector based on the secondary command value vector. Here, the control circuit 70 outputs a voltage vector that is approximately consistent with the secondary command value vector by staggering the outputs of the coordinates of the first intermediate coordinate point, the second intermediate coordinate point, and the origin O in time. Since the first intermediate coordinate point is a restricted intermediate coordinate point, either the upper or lower coordinate of the first intermediate coordinate point is a prohibited coordinate. Therefore, the control circuit 70 outputs the upper or lower coordinate, which is a normal coordinate, as the coordinate of the first intermediate coordinate point. Furthermore, since the second intermediate coordinate point is a normal intermediate coordinate point, both the upper and lower coordinates of the second intermediate coordinate point are normal coordinates. The control circuit 70 outputs the coordinates opposite to those output as the first intermediate coordinate point as the coordinates of the second intermediate coordinate point. That is, when the control circuit 70 outputs the upper coordinate as the first intermediate coordinate point, it outputs the lower coordinate as the second intermediate coordinate point. Conversely, when the control circuit 70 outputs the lower coordinate as the first intermediate coordinate point, it outputs the upper coordinate as the second intermediate coordinate point. Furthermore, the control circuit 70 outputs any coordinate that is not a prohibited coordinate as the coordinate of the origin O. For example, in the output... Figure 15 In the case of the quadratic instruction value vector C2, the output (2, 2, 1) is used as the first intermediate coordinate point, the output (1, 0, 1) is used as the second intermediate coordinate point, and the output (2, 2, 2) or (1, 1, 1) is used as the origin O. In this case, the time ratio of the output coordinates of each coordinate point is shown in Equation 2 below.

[0108] [Formula 2]

[0109]

[0110] Furthermore, in Equation 2 above, Ta is the output ratio of the first intermediate coordinate point, Tb is the output ratio of the second intermediate coordinate point, and Tc is the output ratio of the origin O. Also, in Equation 2 above, ω is the angle of the quadratic command value vector relative to the direction of (2, 0, 2), Vmag is the voltage value converted from the length of the quadratic command value vector, and VH is the potential of the high-potential wiring 12.

[0111] As explained above, when the inverter 10 outputs a voltage vector belonging to the first restricted triangle region, it determines a quadrilateral formed by the specific first restricted triangle region and the adjacent second restricted triangle region, and determines a first intermediate coordinate point and a second intermediate coordinate point that do not include the origin O and form opposite corners of the quadrilateral. Then, by outputting the first intermediate coordinate point, the second intermediate coordinate point, and the origin O in a time-staggered manner, the voltage vector belonging to the first restricted triangle region is output. According to this method, since the second intermediate coordinate point is a normal intermediate coordinate point, the coordinate on the opposite side of the first intermediate coordinate point can be selected as the second intermediate coordinate point. Therefore, when the upper coordinate is output as the first intermediate coordinate point, the lower coordinate can be output as the second intermediate coordinate point, and when the lower coordinate is output as the first intermediate coordinate point, the upper coordinate can be output as the second intermediate coordinate point. Thus, continuous output of the upper or lower coordinate can be prevented. Therefore, the inverter 10 according to Embodiment 1 can suppress fluctuations in the neutral point potential VM during abnormal operation.

[0112] To be more specific, in normal movement, in situations such as Figure 15 When the command value vector C2 outputs a voltage vector with coordinates within the inner triangular region T1, the three coordinate points constituting the three vertices of the inner triangular region T1 (i.e., the middle coordinate point M1, the middle coordinate point M2, and the origin O) are output in staggered time. If the same control as the normal operation is implemented during an abnormal operation, a change in the neutral point potential VM will occur. That is, as... Figure 15 As shown, when the lower coordinates of intermediate coordinate points M1 and M2 are prohibited coordinates, only the upper coordinates can be output as intermediate coordinate points M1 and M2. As mentioned above, if the upper coordinates are output, the neutral point potential VM will rise or fall. Therefore, if the upper coordinates of intermediate coordinate point M1, the upper coordinates of intermediate coordinate point M2, and the coordinates of the origin O are output at different times, the upper coordinates will be output biased, causing the neutral point potential VM to fluctuate significantly. For example, if the upper coordinates are output biased at the timing when the neutral point potential VM rises during the output of the upper coordinates, the neutral point potential VM will rise significantly. Similarly, if the upper coordinates are output biased at the timing when the neutral point potential VM falls during the output of the upper coordinates, the neutral point potential VM will fall significantly. In contrast, in the control method of the above embodiment, intermediate coordinate point M6, which is the normal intermediate coordinate point, is selected instead of intermediate coordinate point M1, and the lower coordinates are output as the coordinates of intermediate coordinate point M6. That is, the upper coordinates of intermediate coordinate point M1, the lower coordinates of intermediate coordinate point M6, and the coordinates of the origin O are output in a staggered manner in time. Therefore, the upper coordinates are not output in a biased manner. Thus, the variation of the neutral point potential VM can be suppressed.

[0113] Furthermore, when the control circuit 70 outputs the first intermediate coordinate point, the second intermediate coordinate point, and the origin O in a time-staggered manner, it cannot output a voltage vector exceeding line segment L1. In this inverter 10, when the primary command value vector exceeds line segment L1, the command circuit 72 calculates a secondary command value vector that does not exceed line segment L1. Therefore, the control circuit 70 outputs a voltage vector based on the secondary command value vector, thereby enabling the output of a voltage vector at an appropriate angle.

[0114] in addition, Figure 16 An example of a primary instruction value vector B3 belonging to the inner triangle region T2 (i.e., the first restricted triangle region) is shown. In this case, the specific first restricted triangle region is the inner triangle region T2, the adjacent second restricted triangle region is the inner triangle region T3, the first intermediate coordinate point is the intermediate coordinate point M2, and the second intermediate point is the intermediate coordinate point M4. The instruction circuit 72 generates a secondary instruction value vector C3. The control circuit 70 outputs the upper coordinate of the intermediate coordinate point M2, the lower coordinate of the intermediate coordinate point M4, and the coordinate of the origin O in a time-staggered manner. Figure 16 In, also with Figure 15 Similarly, it can suppress variations in the neutral point potential VM.

[0115] (A-3-3. When the command value vector belongs to the second restricted triangle region)

[0116] When a single instruction value vector belongs to the second restricted triangle region, the instruction circuit 72 determines a first restricted triangle region adjacent to the second restricted triangle region to which the single instruction value vector belongs (hereinafter referred to as the specific second restricted triangle region). Hereinafter, the first restricted triangle region adjacent to the specific second restricted triangle region is referred to as the adjacent first restricted triangle region. For example, in... Figure 17 In this context, the instruction value vector B4 belongs to the inner triangle region T6 (i.e., the second restricted triangle region). Therefore, the specific second restricted triangle region is the inner triangle region T6. In this case, the instruction circuit 72 determines the first restricted triangle region adjacent to the inner triangle region T6, i.e., the inner triangle region T1, as the adjacent first restricted triangle region. Next, the instruction circuit 72 determines two intermediate coordinate points that do not contain the origin O and form opposite corners in the quadrilateral formed by the specific second restricted triangle region and the adjacent first restricted triangle region. Hereinafter, among the two determined intermediate coordinate points (i.e., the two intermediate coordinate points that do not contain the origin O and form opposite corners), the intermediate coordinate point in the adjacent first restricted triangle region is called the third intermediate coordinate point, and the intermediate coordinate point in the specific second restricted triangle region is called the fourth intermediate coordinate point. The third intermediate coordinate point is a restricted intermediate coordinate point, and the fourth intermediate coordinate point is a normal intermediate coordinate point. For example, in Figure 17In the quadrilateral formed by the two inner triangular regions T1 and T6, the two intermediate coordinate points that do not contain the origin O and form opposite corners are intermediate coordinate points M2 and M6. Since intermediate coordinate point M2 is the coordinate point of the vertex forming the adjacent first restricted triangular region (i.e., the inner triangular region T1), it is also the third intermediate coordinate point. Since intermediate coordinate point M6 is the coordinate point of the vertex forming the specific second restricted triangular region (i.e., the inner triangular region T6), it is also the fourth intermediate coordinate point. Intermediate coordinate point M2 (i.e., the third intermediate coordinate point) is a restricted intermediate coordinate point. Intermediate coordinate point M6 (i.e., the fourth intermediate coordinate point) is a normal intermediate coordinate point. Next, the instruction circuit 72 calculates the line segment (hereinafter referred to as line segment L2) connecting the third and fourth intermediate coordinate points. For example, in Figure 17 In this process, the line segment L2 connecting intermediate coordinate point M2 (i.e., the third intermediate coordinate point) and intermediate coordinate point M6 (i.e., the fourth intermediate coordinate point) is calculated. Next, the instruction circuit 72 determines whether the primary instruction value vector exceeds line segment L2. If the primary instruction value vector exceeds line segment L2, the instruction circuit 72 calculates a voltage vector with an angle θ equal to the primary instruction value vector and a length not exceeding that of line segment L2 as the secondary instruction value vector. That is, the instruction circuit 72 calculates the secondary instruction value vector by shortening the primary instruction value vector. For example, in... Figure 17 In the first command value vector B4, the line segment L2 extends beyond the line segment L2 (i.e., it extends to a position further outward than the line segment L2). Therefore, the command circuit 72 calculates a secondary command value vector C4 whose angle θ is equal to the primary command value vector B4 and does not exceed the line segment L2. Alternatively, if the primary command value vector does not exceed the line segment L2, the command circuit 72 directly sets the primary command value vector as the secondary command value vector. The generated secondary command value vector is input to the control circuit 70.

[0117] The control circuit 70 outputs a voltage vector based on the secondary command value vector. Here, the control circuit 70 outputs a voltage vector that is approximately consistent with the secondary command value vector by staggering the outputs of the coordinates of the third intermediate coordinate point, the fourth intermediate coordinate point, and the origin O in time. Since the third intermediate coordinate point is a restricted intermediate coordinate point, one of the upper or lower coordinates representing the third intermediate coordinate point is a prohibited coordinate. Therefore, the control circuit 70 outputs the upper or lower coordinate that is a normal coordinate as the coordinate of the third intermediate coordinate point. Furthermore, since the fourth intermediate coordinate point is a normal intermediate coordinate point, both the upper and lower coordinates representing the fourth intermediate coordinate point are normal coordinates. The control circuit 70 outputs the coordinates opposite to those output as the third intermediate coordinate point as the coordinates of the fourth intermediate coordinate point. That is, when the control circuit 70 outputs the upper coordinate as the third intermediate coordinate point, it outputs the lower coordinate as the fourth intermediate coordinate point. Conversely, when the control circuit 70 outputs the lower coordinate as the third intermediate coordinate point, it outputs the upper coordinate as the fourth intermediate coordinate point. Furthermore, the control circuit 70 outputs any coordinate that is not a prohibited coordinate as the coordinate of the origin O. For example, in the output... Figure 17 In the case of the quadratic instruction value vector C4, the output (2, 2, 1) is used as the third intermediate coordinate point, the output (1, 0, 1) is used as the fourth intermediate coordinate point, and the output (2, 2, 2) or (1, 1, 1) is used as the origin O. In this case, the time ratio of the output coordinates of each coordinate point is shown in Equation 3 below.

[0118] [Formula 3]

[0119]

[0120] Furthermore, in Equation 3 above, Td is the output ratio of the third intermediate coordinate point, Te is the output ratio of the fourth intermediate coordinate point, and Tf is the output ratio of the origin O. Also, in Equation 3 above, ω is the angle of the secondary command value vector relative to the direction of (2, 0, 2), Vmag is the voltage value converted from the length of the secondary command value vector, and VH is the potential of the high-potential wiring 12.

[0121] As explained above, when the inverter 10 outputs a voltage vector belonging to the second restricted triangle region, it determines a quadrilateral formed by the specific second restricted triangle region and the adjacent first restricted triangle region, and determines the third and fourth intermediate coordinate points of this quadrilateral, which do not include the origin O and form diagonals. Then, by outputting the third intermediate coordinate point, the fourth intermediate coordinate point, and the origin O in a time-staggered manner, the voltage vector belonging to the second restricted triangle region is output. According to this method, when the control period when the primary command value vector belongs to the first restricted triangle region is added to the control period when the primary command value vector belongs to the second restricted triangle region, the time ratio of outputting the upper coordinate and the time ratio of outputting the lower coordinate are easily balanced. That is, during the control period when the primary command value vector belongs to the first restricted triangle region, the time ratio of outputting the first intermediate coordinate point is longer than the time ratio of outputting the second intermediate coordinate point. This is because the coordinates of the secondary command value vector are closer to the first intermediate coordinate point than the second intermediate coordinate point. Furthermore, during the control period when the primary command value vector belongs to the second restricted triangle region, the time ratio of outputting the fourth intermediate coordinate point is longer than the time ratio of outputting the third intermediate coordinate point. This is because the coordinates of the secondary command value vector are closer to the fourth intermediate coordinate point than the third intermediate coordinate point. Furthermore, the coordinates of the first intermediate coordinate point are equal to the coordinates of the third intermediate coordinate point, and the coordinates of the second intermediate coordinate point are equal to the coordinates of the fourth intermediate coordinate point. Therefore, when the control period when the primary command value vector belongs to the first restriction triangle region is added to the control period when the primary command value vector belongs to the second restriction triangle region, the time ratio of the upper output coordinate and the time ratio of the lower output coordinate are easily balanced. For example, it is conceivable that in... Figure 17 After control, execute Figure 15 The situation under control. In this case, Figure 17 In the control, a longer output (1, 0, 1) and a shorter output (2, 2, 1) are used. Figure 15 In the control, a longer output (2, 2, 1) and a shorter output (1, 0, 1) are used. Therefore, in Figure 17 Control period and Figure 15 When the control periods are summed, the time ratios of output (1, 0, 1) and output (2, 2, 1) are easily balanced. That is, the time ratios of the upper output coordinate and the lower output coordinate are easily balanced. Therefore, it is possible to further suppress the variation of the neutral point potential VM.

[0122] in addition, Figure 18An example of a primary instruction value vector B5 belonging to the inner triangle region T3 (i.e., the second restricted triangle region) is shown. In this case, the specific second restricted triangle region is the inner triangle region T3, the adjacent first restricted triangle region is the inner triangle region T2, the third intermediate coordinate point is the intermediate coordinate point M2, and the fourth intermediate coordinate point is the intermediate coordinate point M4. The instruction circuit 72 generates a secondary instruction value vector C5. The control circuit 70 outputs the upper coordinate of the intermediate coordinate point M2, the lower coordinate of the intermediate coordinate point M4, and the coordinate of the origin O in a time-staggered manner. Figure 16 After control, execute Figure 18 The control enables Figure 16 Control period and Figure 18 The time ratio of the upper and lower coordinates during the summation of the control periods is balanced. Therefore, it is possible to further suppress variations in the neutral point potential VM.

[0123] The inverter 10 of Embodiment 1 has been described above. Furthermore, in Figures 14-18 In the example, the case where the prohibited coordinate is the lower coordinate is used is illustrated. Figures 19-21 This example illustrates the case where the prohibited coordinates are the upper coordinates (more specifically, the prohibited parameter is Vw = 2). In this case, the first restricted triangle region is the inner triangle regions T4 and T5, the second restricted triangle region is the inner triangle regions T3 and T6, and the normal triangle region is the inner triangle regions T1 and T2. In this case, the lower coordinates are chosen as the first and third intermediate coordinate points, and the upper coordinates are chosen as the second and fourth intermediate coordinate points. For example, in... Figure 19 In this process, since the instruction value vector B6 belongs to the inner triangle region T5 (i.e., the first restricted triangle region), the first intermediate coordinate point (i.e., intermediate coordinate point M5), the second intermediate coordinate point (i.e., intermediate coordinate point M1), and the origin O are continuously output. At this time, (0, 0, 1) is output as the coordinates of intermediate coordinate point M5, and (2, 1, 1) is output as the coordinates of intermediate coordinate point M1. Additionally, for example, in... Figure 20 In this process, since the instruction value vector B7 belongs to the inner triangle region T6 (i.e., the second restricted triangle region), the third intermediate coordinate point (i.e., intermediate coordinate point M5), the fourth intermediate coordinate point (i.e., intermediate coordinate point M1), and the origin O are continuously output. At this time, (0, 0, 1) is output as the coordinates of intermediate coordinate point M5, and (2, 1, 1) is output as the coordinates of intermediate coordinate point M1. Therefore, the time ratios of the upper and lower coordinates are easily balanced, which can suppress fluctuations in the neutral point potential VM.

[0124] As explained above, in the inverter 10 of Embodiment 1, the neutral point potential VM does not easily change during abnormal operation. Therefore, it is possible to continue abnormal operation for a long time.

[0125] [Example 2]

[0126] Figure 21 Inverter 400 of Embodiment 2 is shown. Furthermore, parts of inverter 400 of Embodiment 2 that have the same functions as those in Embodiment 1 are labeled with the same reference numerals as those in Embodiment 1.

[0127] (Inverter structure)

[0128] An inverter 400 is installed in the vehicle. Additionally, a battery 18 and a motor 90 are installed in the vehicle. The motor 90 is a three-phase motor used to propel the vehicle. The inverter 400 is connected to the battery 18 and the motor 90. The inverter 400 converts the DC power supplied from the battery 18 into three-phase AC power and supplies the three-phase AC power to the motor 90. Thus, the motor 90 drives and propels the vehicle.

[0129] Inverter 400 has a high-potential wiring 12, a neutral point 14, a low-potential wiring 16, an upper capacitor 20, and a lower capacitor 22. The high-potential wiring 12 is connected to the positive terminal of battery 18. The low-potential wiring 16 is connected to the negative terminal of battery 18. The potential of the low-potential wiring 16 is set as a reference potential (0V). A DC voltage is applied between the high-potential wiring 12 and the low-potential wiring 16 through battery 18. Therefore, the high-potential wiring 12 has a higher potential VH than the potential (0V) of the low-potential wiring 16. The upper capacitor 20 is connected between the high-potential wiring 12 and the neutral point 14. The lower capacitor 22 is connected between the neutral point 14 and the low-potential wiring 16. Therefore, the potential VM of the neutral point 14 (hereinafter referred to as the neutral point potential VM) is higher than the potential (0V) of the low-potential wiring 16 and lower than the potential VH of the high-potential wiring 12. The neutral point potential VM varies depending on the amount of charge stored in the upper capacitor 20 and the amount of charge stored in the lower capacitor 22. The neutral point potential VM rises when the upper capacitor 20 discharges or the lower capacitor 22 charges. The neutral point potential VM falls when the upper capacitor 20 charges or the lower capacitor 22 discharges.

[0130] The inverter 400 has three switching circuits 30: a U-phase switching circuit 30u, a V-phase switching circuit 30v, and a W-phase switching circuit 30w. The switching circuits 30 are connected between the high-potential wiring 12, the low-potential wiring 16, and the neutral point 14, respectively. Each switching circuit 30 includes a first switching element 441, a second switching element 442, a third switching element 443, a fourth switching element 444, a first diode 451, a second diode 452, a third diode 453, a fourth diode 454, and an output wiring 60. Since the structures of the three switching circuits 30 are identical, the structure of one switching circuit 30 will be described below.

[0131] Switching elements 441 to 444 are composed of IGBTs. However, switching elements 441 to 444 can also be composed of other elements (such as FETs).

[0132] The first switching element 441 is connected between the high-potential wiring 12 and the output wiring 60. The collector of the first switching element 441 is connected to the high-potential wiring 12, and the emitter of the first switching element 441 is connected to the output wiring 60.

[0133] The first diode 451 is connected in parallel with the first switching element 441. The anode of the first diode 451 is connected to the emitter of the first switching element 441, and the cathode of the first diode 451 is connected to the collector of the first switching element 441.

[0134] The fourth switching element 444 is connected between the output wiring 60 and the low-potential wiring 16. The collector of the fourth switching element 444 is connected to the output wiring 60, and the emitter of the fourth switching element 444 is connected to the low-potential wiring 16.

[0135] The fourth diode 454 is connected in parallel with the fourth switching element 444. The anode of the fourth diode 454 is connected to the emitter of the fourth switching element 444, and the cathode of the fourth diode 454 is connected to the collector of the fourth switching element 444.

[0136] The second switching element 442 and the third switching element 443 are connected in series between the output wiring 60 and the neutral point 14. The drain of the second switching element 442 is connected to the neutral point 14. The source of the second switching element 442 is connected to the source of the third switching element 443. The drain of the third switching element 443 is connected to the output wiring 60.

[0137] The second diode 452 is connected in parallel with the second switching element 442. The anode of the second diode 452 is connected to the source of the second switching element 442, and the cathode of the second diode 452 is connected to the drain of the second switching element 442. That is, the second diode 452 is connected in parallel with the second switching element 442 with its cathode facing the neutral point 14.

[0138] The third diode 453 is connected in parallel with the third switching element 443. The anode of the third diode 453 is connected to the source of the third switching element 443, and the cathode of the third diode 453 is connected to the drain of the third switching element 443. That is, the third diode 453 is connected in parallel with the third switching element 443 with the cathode facing the output wiring 60 side.

[0139] Hereinafter, the output wiring 60 of the U-phase switching circuit 30u will be referred to as the U-phase output wiring 60u, the output wiring 60 of the V-phase switching circuit 30v will be referred to as the V-phase output wiring 60v, and the output wiring 60 of the W-phase switching circuit 30w will be referred to as the W-phase output wiring 60w. The U-phase output wiring 60u, V-phase output wiring 60v, and W-phase output wiring 60w are each connected to the motor 90.

[0140] The inverter 400 includes a control circuit 70 and a command circuit 72. The command circuit 72 generates command values ​​based on the operating state of the motor 90 and inputs these command values ​​to the control circuit 70. Although not shown in the diagram, the control circuit 70 is connected to the gates of the switching elements 441 to 444 of each of the U-phase switching circuit 30u, the V-phase switching circuit 30v, and the W-phase switching circuit 30w. That is, the control circuit 70 is connected to... Figure 21 The gates of the twelve switching elements shown are connected. The control circuit 70, based on the command value input from the command circuit 72, turns each switching element on / off. This generates a three-phase alternating current between the three output lines 60. By supplying the three-phase alternating current to the motor 90, the motor 90 is driven, and the vehicle is moved.

[0141] (Potential of output wiring)

[0142] Next, the potentials applied to each output wiring 60 will be explained. The control circuit 70 controls each switching circuit 30 to... Figure 22 Any one of the first, second, and third states shown.

[0143] In the first state, the control is set so that the first switching element 441 is turned on, the second switching element 442 is turned off, the third switching element 443 is turned off, and the fourth switching element 444 is turned off. In the first state, the output wiring 60 is connected to the high-potential wiring 12 via the first switching element 441. Therefore, in the first state, the potential of the output wiring 60 is at the same potential VH as that of the high-potential wiring 12.

[0144] In the second state, the control is set so that the first switching element 441 is off, the second switching element 442 is on, the third switching element 443 is on, and the fourth switching element 444 is off. In the second state, the output wiring 60 is connected to the neutral point 14 via the third switching element 443 and the second switching element 442. Therefore, in the second state, the potential of the output wiring 60 is at the same neutral point potential VM as that of the neutral point 14.

[0145] In the third state, the control is set so that the first switching element 441 is off, the second switching element 442 is off, the third switching element 443 is off, and the fourth switching element 444 is on. In the third state, the output wiring 60 is connected to the low-potential wiring 16 via the fourth switching element 444. Therefore, in the third state, the potential of the output wiring 60 is 0V, the same as that of the low-potential wiring 16.

[0146] The states of each switching circuit 30 change between the first, second, and third states, causing the potential of each output line 60 to vary between a high potential VH, a neutral point potential VM, and 0V. The control circuit 70 controls the potential of each output line 60 to generate a three-phase alternating current in the output lines 60.

[0147] (Normal action)

[0148] The instruction circuit 72, similar to that in Embodiment 1, generates an instruction value vector represented by coordinates in a spatial vector coordinate system. In the absence of a short-circuit faulty element, the control circuit 70 performs normal operation. During normal operation, the control circuit 70 controls the inverter 10 based on the instruction value vector. The normal operation of Embodiment 2 is the same as that of Embodiment 1.

[0149] (Changes in neutral point potential VM)

[0150] Next, the variation of the neutral point potential VM will be explained. Figure 3 In the voltage vectors shown in the coordinates that do not contain the value "1", no neutral point potential VM is applied to any of the three output wirings 60. In this case, no change in the neutral point potential VM occurs. For example, in the case of output (0, 0, 2), as... Figure 23 As shown, output wiring 60u and 60v are connected to low-potential wiring 16, and output wiring 60w is connected to high-potential wiring 12. Furthermore, depending on the operating state of the motor 90, there are cases where the current flows in the same direction as the voltage applied to the motor 90 (hereinafter referred to as forward) and cases where the current flows in the opposite direction to the voltage applied to the motor 90 (hereinafter referred to as reverse). In the case where the current flows in the forward direction, as... Figure 23As indicated by arrow 401, current flows from the high-potential wiring 12 to the motor 90 via output wiring 60w. The current flowing into the motor 90 flows to the low-potential wiring 16 via output wirings 60u and 60v. Furthermore, in the case of reverse current flow, the current flows in the opposite direction of arrow 401. In either of these cases, no charge flows into or out of the neutral point 14. Therefore, no change in the neutral point potential VM occurs under these conditions. Similarly, no change in the neutral point potential VM occurs when the outputs (2,0,0), (2,2,0), (0,2,0), (0,2,2), and (2,0,2) are used as voltage vectors.

[0151] In output Figure 3 In the case of a voltage vector containing the value "1" in the coordinates shown, the neutral point potential VM changes because the neutral point 14 is connected to at least one of the three output wirings 60.

[0152] For example, in the case of output (1, 1, 2), such as Figure 24 As shown, output wiring 60u and 60v are connected to neutral point 14, and output wiring 60w is connected to high-potential wiring 12. When the current flows in the forward direction, as... Figure 24 As indicated by arrow 402, current flows from the high-potential wiring 12 to the motor 90 via output wiring 60w. The current flowing into the motor 90 flows to the neutral point 14 via output wirings 60u and 60v. In this case, the neutral point potential VM rises due to the discharge of the upper capacitor 20. Conversely, when the current flows in the reverse direction, it flows in the opposite direction of arrow 402. In this case, the neutral point potential VM decreases due to the charging of the upper capacitor 20. Thus, with output (1, 1, 2), the neutral point potential VM rises when the current is in the positive direction and falls when the current is in the reverse direction. Similarly, with outputs (2, 1, 1), (2, 2, 1), (1, 2, 1), (1, 2, 2), and (2, 1, 2) as voltage vectors, the neutral point potential VM rises when the current is in the positive direction and falls when the current is in the reverse direction.

[0153] Additionally, for example, in the case of output (0, 0, 1), such as Figure 25 As shown, output wiring 60u and 60v are connected to low-potential wiring 16, and output wiring 60w is connected to neutral point 14. When the current flows in the forward direction, as... Figure 25As indicated by arrow 404, current flows from neutral point 14 to motor 90 via output wiring 60w. The current flowing into motor 90 flows to low-potential wiring 16 via output wiring 60u, 60v. In this case, the neutral point potential VM decreases due to the discharge of the lower capacitor 22. Conversely, when the current flows in the reverse direction, it flows in the opposite direction of arrow 404. In this case, the neutral point potential VM increases due to the charging of the lower capacitor 22. Thus, with an output of (0, 0, 1), the neutral point potential VM decreases when the current is in the positive direction and increases when the current is in the reverse direction. Similarly, with outputs (1, 0, 0), (1, 1, 0), (0, 1, 0), (0, 1, 1), (1, 0, 1) as voltage vectors, the neutral point potential VM decreases when the current is in the positive direction and increases when the current is in the reverse direction.

[0154] Furthermore, even in the output Figure 3 In the cases of (2, 1, 0), (1, 2, 0), (0, 2, 1), (0, 1, 2), (1, 0, 2), and (2, 0, 1) shown in the voltage vector, the neutral point potential VM will change due to the inflow or outflow of charge into or out of the neutral point 14.

[0155] During normal operation, the command circuit 72 and the control circuit 70 change the output voltage vector according to the neutral point potential VM. For example, if the neutral point potential VM is lower than the control target value, a voltage vector that raises the neutral point potential VM is preferentially output. Conversely, if the neutral point potential VM is higher than the control target value, a voltage vector that lowers the neutral point potential VM is preferentially output. Therefore, it is possible to supply three-phase AC current to the motor 90 while controlling the neutral point potential VM to a value close to the target value.

[0156] (Short-circuit component detection action)

[0157] When the vehicle is not in motion, the control circuit 70 periodically performs a short-circuit element determination operation. During this operation, for each of the switching circuits 30u, 30v, and 30w, the control circuit 70 determines whether a short-circuit fault has occurred in switching elements 441 to 444. The control circuit 70 determines whether a short-circuit faulty element exists, and if so, determines which of the switching elements 441 to 444 is the faulty element.

[0158] (A. Unusual action)

[0159] Next, the abnormal operation will be explained. When a short-circuit fault occurs in the second switching element 442 or the third switching element 443, the command circuit 72 and the control circuit 70 can perform the abnormal operation. However, in the event of a short-circuit fault in the first switching element 441 or the fourth switching element 444, the inverter 400 cannot perform the abnormal operation. In the abnormal operation, the limiting switching circuit 30x is controlled to prevent the application of an inhibit potential to the limiting output wiring 60x. First, the inhibit potential will be explained.

[0160] (A-1. Prohibited Potential)

[0161] The prohibition potential refers to the voltage that cannot be applied to the limiting output wiring 60x due to a short circuit between lines within the limiting switch circuit 30x. The prohibition potential varies depending on the type of short-circuit fault component within the limiting switch circuit 30x.

[0162] In the event of a short-circuit fault in the second switching element 442, when the fourth switching element 444 is turned on, the short-circuit current flows from the neutral point 14 through the second switching element 442, the third diode 453, and the fourth switching element 444 to the low-potential wiring 16. Therefore, in the event of a short-circuit fault in the second switching element 442, the fourth switching element 444 cannot be turned on. Therefore, in the event of a short-circuit fault in the second switching element 442, a potential of 0V is prohibited.

[0163] In the event of a short-circuit fault in the third switching element 443, when the first switching element 441 is turned on, the short-circuit current flows from the high-potential wiring 12 through the first switching element 441, the third switching element 443, and the second diode 452 to the neutral point 14. Therefore, in the event of a short-circuit fault in the third switching element 443, the first switching element 441 cannot be turned on. Therefore, in the event of a short-circuit fault in the third switching element 443, the high potential VH is prohibited.

[0164] (A-2. Prohibits abnormal operation when the potential is 0V or a high potential VH)

[0165] The prohibition of abnormal operation at a potential of 0V or a high potential VH is the same in both Example 2 and Example 1. That is, as in Example 1. Figure 14 As shown, when the command value vector belongs to the normal triangular region, the output voltage vector is the same as in normal operation. Figure 15 , Figure 16 , Figure 19As shown, when the primary instruction value vector belongs to the first restricted triangle region, the instruction circuit 72 calculates line segment L1 in the same manner as in Embodiment 1, and calculates a secondary instruction value vector not exceeding line segment L1. Furthermore, the control circuit 70, in the same manner as in Embodiment 1, outputs the normal coordinates of the first intermediate coordinate point, the coordinates of the second intermediate coordinate point (coordinates opposite to those of the first intermediate coordinate point), and the coordinates of the origin in a time-staggered manner. Figure 17 , Figure 18 , Figure 20 As shown, when the primary instruction value vector belongs to the second restricted triangle region, the instruction circuit 72 calculates line segment L2 in the same manner as in Embodiment 1, and calculates a secondary instruction value vector not exceeding line segment L2. Furthermore, the control circuit 70, in the same manner as in Embodiment 1, outputs the normal coordinates of the third intermediate coordinate point, the coordinates of the fourth intermediate coordinate point (the coordinates opposite to the third intermediate coordinate point), and the coordinates of the origin in a time-staggered manner. Therefore, in the abnormal operation of Embodiment 2, the fluctuation of the neutral point potential VM can be suppressed, just as in Embodiment 1.

[0166] As explained above, in the inverter 400 of Embodiment 2, the neutral point potential VM does not easily change during abnormal operation. Therefore, it is possible to continue abnormal operation for a long time.

[0167] Diode 452 in Embodiment 2 is an example of a first intermediate diode. Diode 453 in Embodiment 2 is an example of a second intermediate diode.

[0168] Additionally, in Examples 1 and 2, as Figure 15 , Figure 16 , Figure 19 As shown, a state where a single instruction value vector belongs to the first restricted triangle region is an example of a restricted state. Furthermore, in embodiments 1 and 2, as... Figure 17 , Figure 18 , Figure 20 As shown, the state in which a single instruction value vector belongs to the second restricted triangle region is an example of a preparatory state.

[0169] In addition, during abnormal operations, the control methods of Embodiments 1 and 2 described above can be executed in combination with other control methods. For example, other control methods can be executed when the neutral point potential VM is within the allowable range, and the control methods of Embodiments 1 and 2 can be executed to suppress further changes in the neutral point potential VM when the neutral point potential VM is outside the allowable range.

[0170] The embodiments have been described in detail above, but these are merely illustrative and not intended to limit the scope of the claims. The technology described in the claims includes various modifications and alterations to the specific examples described above. The technical elements described in this specification or drawings exert their technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of application. Furthermore, the technology illustrated in this specification or drawings can achieve multiple objectives simultaneously, and achieving one of these objectives is itself technically useful.

Claims

1. An inverter, comprising: High-potential wiring; Low-potential wiring; Neutral point; An upper capacitor connected between the high-potential wiring and the neutral point; A lower capacitor connected between the neutral point and the low-potential wiring; Three switching circuits with U-phase switching circuit, V-phase switching circuit and W-phase switching circuit; Instruction circuit; as well as Control circuit, Each of the three switching circuits described has multiple semiconductor elements and output wiring. The control circuit controls the three switching circuits by causing the potentials of the output wiring of the U-phase switching circuit (U-phase output wiring), the output wiring of the V-phase switching circuit (V-phase output wiring), and the output wiring of the W-phase switching circuit (W-phase output wiring) to vary between the potential of the high-potential wiring (high potential), the potential of the neutral point (neutral point potential), and the potential of the low-potential wiring (low potential). The instruction circuit generates an instruction value vector composed of voltage vectors, which are represented by a spatial vector coordinate system defined by parameters Vu, Vv, and Vw. The parameter Vu represents the value of the U-phase output wiring at either the high potential, the neutral point potential, or the low potential. The parameter Vv indicates which of the following potentials the V-phase output wiring represents: the high potential, the neutral point potential, or the low potential. The parameter Vw represents the value of the W-phase output wiring at either the high potential, the neutral point potential, or the low potential. The control circuit controls the three switching circuits based on the command value vector. The spatial vector coordinate system has multiple intermediate coordinate points located between the origin and the outermost coordinate point. Each of the intermediate coordinate points has an upper coordinate representing the voltage vector that causes the voltage change of the upper capacitor and a lower coordinate representing the voltage vector that causes the voltage change of the lower capacitor. The spatial vector coordinate system has multiple triangular regions with the origin and two adjacent intermediate coordinate points as vertices. The control circuit is capable of performing abnormal operations when a short-circuit fault occurs in any of the three switching circuits, preventing the application of either the high or low potential as a disable potential to the corresponding output wiring. The semiconductor element that experiences a short-circuit fault is called a short-circuit fault element. The output wiring of one of the three switching circuits that includes the short-circuit fault element is referred to as the limiting output wiring. The output wiring of the two switching circuits that do not contain the short-circuit fault element are respectively referred to as normal output wiring. During the abnormal operation, the control circuit causes the potential of the limiting output wiring to vary between two of the following three potentials: the high potential, the neutral point potential, and the low potential, excluding the disable potential. Simultaneously, the potential of each normal output wiring varies between these three potentials. In the aforementioned abnormal operation, the plurality of intermediate coordinate points include: a plurality of normal intermediate coordinate points in which neither the upper coordinate nor the lower coordinate contains the prohibition parameter representing the prohibition potential; and a plurality of restricted intermediate coordinate points in which one of the upper coordinate and the lower coordinate contains the prohibition parameter while the other does not. In the aforementioned abnormal action, the plurality of triangular regions include: a first restricted triangular region where both intermediate coordinate points constituting the vertex are the restricted intermediate coordinate points; a second restricted triangular region where one of the two intermediate coordinate points constituting the vertex is the normal intermediate coordinate point and the other is the restricted intermediate coordinate point; and a normal triangular region where both intermediate coordinate points constituting the vertex are the normal intermediate coordinate points. During the abnormal operation, when the command value vector belongs to the restricted area of ​​the first restricted triangle, the control device outputs the coordinates of the origin, the coordinates of the first intermediate coordinate point (i.e., the first coordinate), and the coordinates of the second intermediate point (i.e., the second coordinate) in a staggered manner in time. Under the restricted state, in the quadrilateral formed by the first restricted triangle region (i.e., the specific first restricted triangle region) to which the instruction value vector belongs and the second restricted triangle region adjacent to the specific first restricted triangle region (i.e., the adjacent second restricted triangle region), the intermediate point within the specific first restricted triangle region that does not contain the origin and forms a diagonal is the first intermediate point, and the intermediate point within the adjacent second restricted triangle region is the second intermediate point. The first coordinate is the coordinate of the upper and lower sides of the first intermediate coordinate point that does not contain the prohibition parameter. The second coordinate is the lower coordinate of the second intermediate coordinate point when the first coordinate is the upper coordinate, and the upper coordinate of the second intermediate coordinate point when the first coordinate is the lower coordinate.

2. The inverter as described in claim 1, characterized in that, Under the restricted state, the instruction circuit generates an instruction value vector that does not exceed the length of the line segment connecting the first intermediate coordinate point and the second intermediate coordinate point.

3. The inverter as described in claim 1, characterized in that, In the aforementioned abnormal action, in the preparatory state where the command value vector belongs to the second restricted triangle region, the control device outputs the coordinates of the origin, the coordinates of the third intermediate coordinate point (i.e., the third coordinate), and the coordinates of the fourth intermediate point (i.e., the fourth coordinate) in a staggered manner in time. In the preparatory state, the intermediate point within the adjacent first restricted triangle region of the quadrilateral formed by the second restricted triangle region (specific second restricted triangle region) to which the command value vector belongs and the first restricted triangle region (adjacent first restricted triangle region) adjacent to the specific second restricted triangle region (adjacent first restricted triangle region), which does not contain the origin and forms a diagonal, is the third intermediate point. The intermediate point within the specific second restricted triangle region is the fourth intermediate point. The third coordinate is the coordinate of the upper and lower sides of the third intermediate coordinate point that does not contain the prohibited parameter. The fourth coordinate is the lower coordinate of the fourth intermediate coordinate point when the third coordinate is the upper coordinate, and the upper coordinate of the fourth intermediate coordinate point when the third coordinate is the lower coordinate.

4. The inverter as described in claim 2, characterized in that, In the aforementioned abnormal action, in the preparatory state where the command value vector belongs to the second restricted triangle region, the control device outputs the coordinates of the origin, the coordinates of the third intermediate coordinate point (i.e., the third coordinate), and the coordinates of the fourth intermediate point (i.e., the fourth coordinate) in a staggered manner in time. In the preparatory state, the intermediate point within the adjacent first restricted triangle region of the quadrilateral formed by the second restricted triangle region (specific second restricted triangle region) to which the command value vector belongs and the first restricted triangle region (adjacent first restricted triangle region) adjacent to the specific second restricted triangle region (adjacent first restricted triangle region), which does not contain the origin and forms a diagonal, is the third intermediate point. The intermediate point within the specific second restricted triangle region is the fourth intermediate point. The third coordinate is the coordinate of the upper and lower sides of the third intermediate coordinate point that does not contain the prohibited parameter. The fourth coordinate is the lower coordinate of the fourth intermediate coordinate point when the third coordinate is the upper coordinate, and the upper coordinate of the fourth intermediate coordinate point when the third coordinate is the lower coordinate.

5. The inverter as described in claim 3, characterized in that, In the preparatory state, the instruction circuit generates an instruction value vector that does not exceed the line segment connecting the third intermediate coordinate point and the fourth intermediate coordinate point.

6. The inverter as described in claim 4, characterized in that, In the preparatory state, the instruction circuit generates an instruction value vector that does not exceed the line segment connecting the third intermediate coordinate point and the fourth intermediate coordinate point.

7. The inverter as described in any one of claims 1 to 6, characterized in that, Each of the three said switching circuits has: A first switching element, the positive terminal of which is connected to the high-potential wiring; A second switching element, the positive terminal of which is connected to the negative terminal of the first switching element, and the negative terminal is connected to the corresponding output wiring; The third switching element, the positive terminal of which is connected to the corresponding output wiring; A fourth switching element, the positive terminal of which is connected to the negative terminal of the third switching element, and the negative terminal is connected to the low-potential wiring. A first diode, wherein the anode of the first diode is connected to the neutral point and the cathode is connected to the negative terminal of the first switching element; as well as The second diode has its anode connected to the cathode of the third switching element, and its cathode connected to the neutral point. When the short-circuit fault element is the second switching element or the second diode, the inhibit potential is the low potential. When the short-circuit fault element is the third switching element or the first diode, the inhibit potential is the high potential.

8. The inverter as described in any one of claims 1 to 6, characterized in that, Each of the three said switching circuits has: A first switching element is connected between the high-potential wiring and the corresponding output wiring; A second switching element is connected between the neutral point and the corresponding output wiring; A third switching element is connected in series with the second switching element between the neutral point and the corresponding output wiring; A fourth switching element is connected between the corresponding output wiring and the low-potential wiring; A first intermediate diode is connected in parallel with the second switching element with its cathode facing the neutral point side; as well as The second intermediate diode is connected in parallel with the third switching element with its cathode facing the output wiring side. When the short-circuit fault element is the second switching element, the inhibit potential is the low potential. When the short-circuit fault element is the third switching element, the inhibit potential is the high potential.

Images